K8D1716UBC-PC09 - Samsung Electronics

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Document Title

16M Bit (2M x8/1M x16) Dual Bank NOR Flash Memory

Revision History

Revision No.

0.0

0.1

0.2

1.0

Remark

Advance

Preliminary

History

Initial Draft

Support 48TSOP1 Lead Free Package

Support 48FBGA Leaded/Lead Free Package

Specification finalized

Draft Date

July 25, 2004

Sep 16, 2004

Nov 29, 2004

Dec 16, 2004

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

16M Bit (2M x8/1M x16) Dual Bank NOR Flash Memory

The K8D1716U featuring single 3.0V power supply, is a 16Mbit

NOR-type Flash Memory organized as 2Mx8 or 1M x16. The

memory architecture of the device is designed to divide its

memory arrays into 39 blocks to be protected by the block

group. This block architecture provides highly flexible erase and

program capability. The K8D1716U NOR Flash consists of two

banks. This device is capable of reading data from one bank

while programming or erasing in the other bank. Access times

of 70ns, 80ns and 90ns are available for the device. The

device′s fast access times allow high speed microprocessors to

operate without wait states. The device performs a program

operation in units of 8 bits (Byte) or 16 bit s (W ord) and erases in

units of a block. Single or multiple blocks can be erased. The

block erase operation is completed within typically 0.7 sec. The

device requires 15mA as program/erase current in the standard

and industrial temperature ranges.

The K8D1716U NOR Flash Memory is created by using Sam-

sung's advanced CMOS process technology. This device is

available in 48 pin TSOP1 and 48 ball FBGA package. The

device is compatible with EPROM applications to require high-

density and cost-effective nonvolatile read/write storage solu-

tions.

FEATURES

• Single Voltage, 2.7V to 3.6V for Read and Write operations

• Organization

1,048,576 x 16 bit (Word mode)

• Fast Read Access Time : 70ns

• Read While Program/Erase Operation

• Dual Bank architectures

Bank 1 / Bank 2 : 8Mb / 8Mb

• Secode(Security Code) Block : Extra 64K Byte block

• Power Consumption (typical value @5MHz)

- Read Current : 14mA

- Program/Erase Current : 15mA

- Read While Program or Read While Erase Current : 25mA

- Standby Mode/Auto Sleep Mode : 5µA

• WP/ACC input pin

- Allows special protection of two outermost boot blocks at VIL,

regardless of block protect status

- Removes special protection of two outermost boot block at VIH,

the two blocks return to normal block protect status

- Program time at VHH : 9µs/word

• Erase Suspend/Resume

• Unlock Bypass Program

• Hardware RESET Pin

• Command Register Operation

• Block Group Protection / Unprotection

• Supports Common Flash Memory Interface

• Industrial Temperature : -40°C to 85°C

• Endurance : 100,000 Program/Erase Cycles Minimum

• Data Retention : 10 years

• Package : 48 Pin TSOP1 : 12 x 20 mm / 0.5 mm Pin pitch

48 Ball FBGA : 6 x 8.5 mm / 0.8 mm Ball pitch

GENERAL DESCRIPTION

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

PIN DESCRIPTION

Pin Name Pin Function

A0 - A19 Address Inputs

DQ0 - DQ14 Data Inputs / Outputs

DQ15/A-1 DQ15 Data Input / Output

A-1 LSB Address

BYTE Word / Byte Selection

CE Chip Enable

OE Output Enable

RESET Hardware Reset Pin

RY/BY Ready/Busy Output

WE Write Enable

WP/ACC Hardware Write Protection/Program

Acceleration

Vcc Power Supply

VSS Ground

N.C No Connection

PIN CONFIGURATION

48-pin TSOP1

Standard Type

12mm x 20mm

A15

A14

A13

A12

A11

A10

A19

N.C

RESET

N.C

WP/ACC

RY/BY

A18

A17

A16

BYTE

Vss

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

Vcc

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

Vss

Note :

Please refer to the package dimension.

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

FUNCTIONAL BLOCK DIAGRAM

Vcc

Vss

BYTE

RESET

RY/BY

A0~A19

DQ0~DQ14

I/O

Interface

Bank

Control

Dec

Y Dec Latch &

Control

Latch &

Control

Dec

Y Dec

Erase

Control

Program

Control

High

Voltage

Gen.

Bank2

Cell Array

Bank1

Address

Bank2

Address

Bank1 Da ta-In/Out

Bank2 Da ta-In/Out

Bank1

Cell Array

WP/ACC

DQ15/A-1

A3 A7 A9 A13

A4 A17 RESET

RY/BY

A8 A12

A2 A6 A18 N.C A10 A14

DQ15/

A5 N.C A19 A11

A0 DQ0 DQ2 DQ5 DQ7 A16

CE DQ8 DQ10 DQ12 DQ14 BYTE

DQ9 DQ11 VCC DQ13

VSS DQ1 DQ3 DQ4 DQ6 VSS

A-1

2 3456

WP/

A1 A15

ACC

48 Ball FBGA TOP VIEW (BALL DOWN)

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

ORDERING INFORMATION

K 8 D 17 1 6 U T C - Y I 0 7

Samsung

NOR Flash Memory

Device Type

Dual Bank Boot Block Operating Temperature Range

C = Commercial Temp. (0 °C to 70 °C)

I = Industrial Temp. (-40 °C to 85 °C)

Block Architecture

T = Top Boot Block

B = Bottom Boot Block

Version

ion

Access Time

07 = 70 ns

08 = 80 ns

09 = 90 ns

Operating Voltage Range

2.7V to 3.6V

Organization

x16

Table 1. PRODUCT LINE-UP

Part No. - 7 -8 -9

Vcc 2.7V~3.6V

Max. Address Access Time (ns) 70ns 80ns 90ns

Max. CE Access Time (ns) 70ns 80ns 90ns

Max. OE Access Time (ns) 25ns 25ns 35ns

Table 2. K8D1716U DEVICE BANK DIVISIONS

Device

Part Number Bank 1 Bank 2

Mbit Block Sizes Mbit Block Sizes

K8D1716U 8 Mbit Eight 8 Kbyte/4 Kword,

fifteen 64 Kbyte/32 Kword 8 Mbit Sixteen

64 Kbyte/32 Kword

Bank Division

17 = 8Mbits + 8Mbits Package

P = 48TSOP1(Lead-Free) Y = 48 TSOP1

D : FBGA(Lead Free) F : FBGA

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Table 3. Top Boot Block Ad dress (K8D1716UT)

K8D1716UT Block A19 A18 A17 A16 A15 A14 A13 A12 Block Size

(KW/KB) Address Range

Word Mode Byte Mode

Bank1

BA3811111111 4 / 8 FF000H-FFFFFH 1FE000H-1FFFFFH

BA3711111110 4 / 8 FE000H-FEFFFH 1FC000H-1FDFFFH

BA3611111101 4 / 8 FD000H-FDFFFH 1FA000H-1FBFFFH

BA3511111100 4 / 8 FC000H-FCFFFH 1F8000H-1F9FFFH

BA3411111011 4 / 8 FB000H-FBFFFH 1F6000H-1F7FFFH

BA3311111010 4 / 8 FA000H-FAFFFH 1F4000H-1F5FFFH

BA3211111001 4 / 8 F9000H-F9FFFH 1F2000H-1F3FFFH

BA3111111000 4 / 8 F8000H-F8FFFH 1F0000H-1F1FFFH

BA30 1 1 1 1 0 X X X 32 / 64 F0000H-F7FFFH 1E0000H-1EFFFFH

BA29 1 1 1 0 1 X X X 32 / 64 E8000H-EFFFFH 1D0000H-1DFFFFH

BA28 1 1 1 0 0 X X X 32 / 64 E0000H-E7FFFH 1C0000H-1CFFFFH

BA27 1 1 0 1 1 X X X 32 / 64 D8000H-DFFFFH 1B0000H-1BFFFFH

BA26 1 1 0 1 0 X X X 32 / 64 D0000H-D7FFFH 1A0000H-1AFFFFH

BA25 1 1 0 0 1 X X X 32 / 64 C8000H-CFFFFH 190000H-19FFFFH

BA24 1 1 0 0 0 X X X 32 / 64 C0000H-C7FFFH 180000H-18FFFFH

BA23 1 0 1 1 1 X X X 32 / 64 B8000H-BFFFFH 170000H-17FFFFH

BA22 1 0 1 1 0 X X X 32 / 64 B0000H-B7FFFH 160000H-16FFFFH

BA21 1 0 1 0 1 X X X 32 / 64 A8000H-AFFFFH 150000H-15FFFFH

BA20 1 0 1 0 0 X X X 32 / 64 A0000H-A7FFFH 140000H-14FFFFH

BA19 1 0 0 1 1 X X X 32 / 64 98000H-9FFFFH 130000H-13FFFFH

BA18 1 0 0 1 0 X X X 32 / 64 90000H-97FFFH 120000H-12FFFFH

BA17 1 0 0 0 1 X X X 32 / 64 88000H-8FFFFH 110000H-11FFFFH

BA16 1 0 0 0 0 X X X 32 / 64 80000H-87FFFH 100000H-10FFFFH

Bank2

BA15 0 1 1 1 1 X X X 32 / 64 78000H-7FFFFH 0F0000H-0FFFFFH

BA14 0 1 1 1 0 X X X 32 / 64 70000H-77FFFH 0E0000H-0EFFFFH

BA13 0 1 1 0 1 X X X 32 / 64 68000H-6FFFFH 0D0000H-0DFFFFH

BA12 0 1 1 0 0 X X X 32 / 64 60000H-67FFFH 0C0000H-0CFFFFH

BA11 0 1 0 1 1 X X X 32 / 64 58000H-5FFFFH 0B0000H-0BFFFFH

BA10 0 1 0 1 0 X X X 32 / 64 50000H-57FFFH 0A0000H-0AFFFFH

BA9 0 1 0 0 1 X X X 32 / 64 48000H-4FFFFH 090000H-09FFFFH

BA8 0 1 0 0 0 X X X 32 / 64 40000H-47FFFH 080000H-08FFFFH

BA7 0 0 1 1 1 X X X 32 / 64 38000H-3FFFFH 070000H-07FFFFH

BA6 0 0 1 1 0 X X X 32 / 64 30000H-37FFFH 060000H-06FFFFH

BA5 0 0 1 0 1 X X X 32 / 64 28000H-2FFFFH 050000H-05FFFFH

BA4 0 0 1 0 0 X X X 32 / 64 20000H-27FFFH 040000H-04FFFFH

BA3 0 0 0 1 1 X X X 32 / 64 18000H-1FFFFH 030000H-03FFFFH

BA2 0 0 0 1 0 X X X 32 / 64 10000H-17FFFH 020000H-02FFFFH

BA1 0 0 0 0 1 X X X 32 / 64 08000H-0FFFFH 010000H-01FFFFH

BA0 0 0 0 0 0 X X X 32 / 64 00000H-07FFFH 000000H-00FFFFH

Device Block Address

A19-A12 Block

Size (X8)

Address Range (X16)

Address Range

K8D1716UT 11111xxx 64/32 1F0000H-1FFFFFH F8000H-FFFFFH

Table 4. Secode Block Addresses for Top Boot Device s

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Table 5. Bottom Boot Bloc k Address (K8D1716UB)

K8D1716UT Block A19 A18 A17 A16 A15 A14 A13 A12 Block Size

(KW/KB) Address Range

Word Mode Byte Mode

Bank2

BA3811111XXX 32 / 64F8000H-FFFFFH1F0000H-1FFFFFH

BA3711110XXX 32 / 64F0000H-F7FFFH 1E0000H-1EFFFFH

BA3611101XXX 32 / 64E8000H-EFFFFH 1D0000H-1DFFFFH

BA3511100XXX 32 / 64E0000H-E7FFFH 1C0000H-1CFFFFH

BA3411011XXX 32 / 64D8000H-DFFFFH1B0000H-1BFFFFH

BA3311010XXX 32 / 64 D0000H-D7FFFH 1A0000H-1AFFFFH

BA3211001XXX 32 / 64C8000H-CFFFFH190000H-19FFFFH

BA3111000XXX 32 / 64 C0000H-C7FFFH 180000H-18FFFFH

BA3010111XXX 32 / 64B8000H-BFFFFH 170000H-17FFFFH

BA2910110XXX 32 / 64B0000H-B7FFFH 160000H-16FFFFH

BA2810101XXX 32 / 64A8000H-AFFFFH 150000H-15FFFFH

BA2710100XXX 32 / 64A0000H-A7FFFH 140000H-14FFFFH

BA2610011XXX 32 / 6498000H-9FFFFH 130000H-13FFFFH

BA2510010XXX 32 / 6490000H-97FFFH 120000H-12FFFFH

BA2410001XXX 32 / 6488000H-8FFFFH 110000H-11FFFFH

BA2310000XXX 32 / 6480000H-87FFFH 100000H-10FFFFH

Bank1

BA2201111XXX 32 / 6478000H-7FFFFH 0F0000H-0FFFFFH

BA2101110XXX 32 / 6470000H-77FFFH 0E0000H-0EFFFFH

BA2001101XXX 32 / 6468000H-6FFFFH 0D0000H-0DFFFFH

BA1901100XXX 32 / 6460000H-67FFFH 0C0000H-0CFFFFH

BA1801011XXX 32 / 6458000H-5FFFFH 0B0000H-0BFFFFH

BA1701010XXX 32 / 6450000H-57FFFH 0A0000H-0AFFFFH

BA1601001XXX 32 / 6448000H-4FFFFH 090000H-09FFFFH

BA1501000XXX 32 / 6440000H-47FFFH 080000H-08FFFFH

BA1400111XXX 32 / 6438000H-3FFFFH 070000H-07FFFFH

BA1300110XXX 32 / 6430000H-37FFFH 060000H-06FFFFH

BA1200101XXX 32 / 6428000H-2FFFFH 050000H-05FFFFH

BA1100100XXX 32 / 6420000H-27FFFH 040000H-04FFFFH

BA1000011XXX 32 / 6418000H-1FFFFH 030000H-03FFFFH

BA900010XXX 32 / 64 10000H-17FFFH 020000H-02FFFFH

BA800001XXX 32 / 6408000H-0FFFFH 010000H-01FFFFH

BA700000111 4 / 8 07000H-07FFFH 00E000H-00FFFFH

BA600000110 4 / 8 06000H-06FFFH 00C000H-00DFFFH

BA500000101 4 / 8 05000H-05FFFH 00A000H-00BFFFH

BA400000100 4 / 8 04000H-04FFFH 008000H-009FFFH

BA300000011 4 / 8 03000H-03FFFH 006000H-007FFFH

BA200000010 4 / 8 02000H-02FFFH 004000H-005FFFH

BA100000001 4 / 8 01000H-01FFFH 002000H-003FFFH

BA000000000 4 / 8 00000H-00FFFH 000000H-001FFFH

Device Block Address

A19-A12 Block

Size (X8)

Address Range (X16)

Address Range

K8D1716UB 00000xxx 64/32 000000H-00FFFFH 00000H-07FFFH

Table 6. Secode Block Address es for Bottom Boot Devices

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

PRODUCT INTRODUCTION

Table 7. Opera tions Table

Operation CE OE WE BYTE WP/

ACC A9 A6 A1 A0 DQ15/

A-1 DQ8/

DQ14 DQ0/

DQ7 RESET

Read word L L H H L/H A9 A6 A1 A0 DQ15 DOUT DOUT H

byte L L H L A9 A6 A1 A0 A-1 High-Z DOUT H

Stand-by Vcc ±

0.3V X X X (2) X X X X High-Z High-Z High-Z (2)

Output Disable L H H X L/H X X X X High-Z High-Z High-Z H

Reset X X X X L/H X X X X High-Z High-Z High-Z L

Write word L H L H (4) A9 A6 A1 A0 DIN DIN DIN H

byte L H L L A9 A6 A1 A0 A-1 High-Z DIN H

Enable Block Group

Protect (3) LHLXL/HXLHL X X D

IN VID

Enable Block Group

Unprotect (3) LHLX(4)XHHL X X DIN VID

Temporary Block

Group XXXX(4)XXXX X X X V

Auto Select

Manufacturer ID (5) LLHXL/HV

ID LLL X X Code(See

Ta ble 9) H

Auto Select

Device Code (5) LLHXL/HV

ID LLH X X Code(See

Ta ble 9) H

Notes :

1. L = VIL (Low), H = VIH (High), VID = 8.5V~12.5V, DIN = Data in, DOUT = Data out, X = Don't care.

2. WP/ACC and RESET pin are asserted at Vcc±0.3 V or Vss±0.3 V in the Stand-by mode.

3. Addresses must be composed of the Block address (A12 - A19).

The Block Protect and Unprotect operations may be implemented via programming equipment too.

Refer to the "Block Group Protection and Unpro tection".

4. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protectio n depends on whether those

blocks were last protected or unprotected using the method described in "Block Group Protection and Unprotection". If WP/ACC=VHH, all blocks

will be temporarily unprotected.

5. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 9.

The K8D1716U is a 16Mbit (16,777,216 bits) NOR-type Flash memory. The de vice features single voltage power supply operating

within the range of 2.7V to 3.6V. The device is pr ogrammed by using the Channel Hot Electro n (C HE) injection mechanism which is

used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flex-

ible erase and program capability, the device adapts a block memory architecture that divides its memory array into 39 blocks (64-

Kbyte x 31 , 8-Kbyte x 8). Programming is done in units of 8 bit s (Byte) or 16 bit s (Word). All bits of data in one or multiple blocks can

be erased simultaneously when the device executes the erase operation. To prevent the device from accidental erasing or over-writ-

ing the programmed data, 39 memory blocks can be hardware protected by the block group. Byte/Word modes are available for read

operation. These modes can be selected via BYTE pin. The device provides read access times of 70ns, 80ns and 90ns supporting

high speed microprocessors to operate without any wait states.

The command set of K8D1716U is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), output

enable (OE) and write enable (WE). Device operations are executed by selective command codes. The command codes to be com-

bined wih addresses and data are sequentially written to the command registers using microprocessor w rite timing. The command

codes serve as inputs to an internal state machine which contro ls the program/erase ci rcuitry. Register contents also internally latch

addresses and data necessary to execute the program and erase operations. The K8D1716U is implemented with Internal Program/

Erase Algorithms to execute the program/erase operations. The Internal Program/Erase Algorithms are invoked by program/erase

command sequences. The Internal Program Algorithm automatically programs and verifies data at specified addresses. The Internal

Erase Algorithm automatically pre-programs the memory cell which is not pr ogrammed and then executes the erase operation . The

K8D1716U has means to indicate the status of completion of p rogram/erase ope rations. The status can be indicated via the RY/BY

pin, Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to

the read mode. The device requires only 14 mA as active read current and 15 mA for program/erase operations.

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

COMMAND DEFINITIONS

The K8D1716U operates by selecting and executing its operational modes. Each operational mode has its own command set. In

order to select a certain mode, a proper command with specific address and data sequences must be written into the command reg-

ister. Writing incorrect information w hich include address and data or writing an improper command will reset the device to the read

mode. The defined valid register command sequences are stated in Table 8. Note that Erase Suspend (B0H) and Erase Resume

(30H) commands are valid only w h ile the Block Erase Operation is in progress.

Table 8. Command Sequences

Command Sequence Cycle 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle

Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte

Read Addr 1RA

Data RD

Reset Addr 1XXXH

Data F0H

Autoselect

Manufacturer

ID (2,3)

Addr 4555H AAAH 2AAH 555H DA/

555H DA/

AAAH DA/

X00H DA/

X00H

Data AAH 55H 90H ECH

Autoselect

Device Code

(2,3)

Addr 4555H AAAH 2AAH 555H DA/

555H DA/

AAAH DA/

X01H DA/

X02H

Data AAH 55H 90H (See Table 9)

Autoselect

Block Group

Protect Verify

(2,3)

Addr 4555H AAAH 2AAH 555H DA/

555H DA/

AAAH BA /

X02H BA/

X04H

Data AAH 55H 90H (See Table 9)

Auto Select

Secode Block

Factory Protect

Verify (2,3)

Addr 4555H AAAH 2AAH 555H DA/

555H DA/

AAAH DA /

X03H DA/

X06H

Data AAH 55H 90H (See Table 9)

Enter Secode

Block Region Addr 3555H AAAH 2AAH 555H 555H AAAH

Data AAH 55H 88H

Exit Secode

Block Region Addr 4555H AAAH 2AAH 555H 555H AAAH XXXH

Data AAH 55H 90H 00H

Program Addr 4555H AAAH 2AAH 555H 555H AAAH PA

Data AAH 55H A0H PD

Unlock Bypass Addr 3555H AAAH 2AAH 555H 555H AAAH

Data AAH 55H 20H

Unlock Bypass

Program Addr 2XXXH PA

Data A0H PD

Unlock Bypass

Reset Addr 2XXXH XXXH

Data 90H 00H

Chip Erase Addr 6555H AAAH 2AAH 555H 555H AAAH 555H AAAH 2AAH 555H 555H AAAH

Data AAH 55H 80H AAH 55H 10H

Block Erase Addr 6555H AAAH 2AAH 555H 555H AAAH 555H AAAH 2AAH 555H BA

Data AAH 55H 80H AAH 55H 30H

Block Erase

Suspend (4, 5) Addr 1XXXH

Data B0H

Block Erase

Resume Addr 1XXXH

Data 30H

CFI Query (6) Addr 155H AAH

Data 98H

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Notes : 1. RA : Read Address, PA : Program Address, RD : Read Data, PD : Pro gram Data

DA : Dual Bank Address, BA : Block Address (A12 - A19), X = Don’t care .

2. To terminate the Autoselect Mode, it is necessary to write Reset command to the register.

3. The 4th cycle data of Autoselect mode is output data.

The 3rd and 4th cycle bank addresses of Autoselect mode must be same .

4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode.

5. The Erase Suspend command is applicable only to the Block Erase operation.

6. Command is valid when the device is in read mode or Autoselect mode.

7. DQ8 - DQ15 are don’t care in command sequence, but RD and PD is excluded.

8. A11 - A19 are also don’t care, except for the case of special notice.

Description CE OE WE A19

A12

A11

A10 A9 A8

A7 A6 A5

A2 A1 A0

DQ8 to DQ15 DQ7

DQ0

BYTE

=VIH BYTE

=VIL

Manufacturer ID L L H DA X VID XLXLL X X ECH

Device Code K8D1716UT

(Top Boot Block) LLHDAXV

ID XLXLH 22H X 75H

Device Code K8D1716UB

(Bottom Boot Block) LLHDAXV

ID XLXLH 22H X 77H

Block Protection

Verification LLHBAXV

ID XLXHL X X 01H (Protected),

00H (Unprotected)

Secode Block (2)

Indicator Bit (DQ7) LLHDAXV

ID XLXHH X X 80H (Factory locked),

00H (Not factory locked)

Table 9. K8D1716U Autoselect Codes, (High Voltage Method)

Notes : 1. L=Logic Low=VIL, H=Logic High=VIH, DA=Dual Bank Addr ess, BA=Block Address, X=Don’t care.

2. Secode Block : Security Code Block.

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

DEVICE OPERATION

Byte/Word Mode

If the BYTE pin is set at logical "1" , the device is in word mode, DQ0-DQ15 are active. Otherwise the BYTE pin is set at logical "0" ,

the device is in byte mode, DQ0-DQ7 are a ctive. DQ8-DQ14 are in the High-Z state and DQ15 pin is used as an input for the LSB

(A-1) address pin.

Read Mode

The K8D1716U is controlled by Chip Enable (C E) , Output Enable (OE) and Write Enable (W E). When CE and OE are low and WE

is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state

whenever CE or OE is high.

Standby Mode

The K8D1716U features St and-by Mode to reduce power consumption. This mode puts the device on hold when the device is dese-

lected by making CE high (CE = VIH). Refer to the DC characteristics for more details on stand-by modes.

Output Disable

The device outputs are disabled when OE is High (OE = VIH). The ou tput pins are in high impedance state.

Automatic Sleep Mode

K8D1716U features Automatic Sleep Mode to minimize the device power consumption. Since the device typically draws 5µA of the

current in Automatic Sleep Mode, this feature plays an extremely important role in battery-powered applications. When addresses

remain steady for tAA+50ns, the device automatically activates the Automatic Sleep Mod e. In th e sleep mode, ou tput data is latched

and always available to the system. When addresses are changed, the device provides new data without wait time.

Data

Outputs

tAA + 50ns

Data

Auto Sleep Mode

Address

Data Data Data Data

Figure 1. Auto Sleep Mode Operation

Autoselect Mode

The K8D1716U offers the Autoselect Mode to identify manufacture r and device type by reading a binary code. The Autoselect Mode

allows programming equipment to automatically match t he device t o be progra mmed with its corresponding progr amming algorithm.

In addition, this mode allows the verification of the status of write protected blocks. This mode is used by two method. The one is high

voltage method to be required VID (8.5V~12.5V) on address pin A9. When A9 is held at VID and the bank address or block address is

asserted, the device outputs the valid data via DQ pins(see Table 9 and Figure 2). The re st of addresses except A0, A1 a nd A6 are

Don′t Care. The other is autoselect command method that the autoselect code is accessible by the commamd sequence without VID.

The manufacturer and device code may also be read via the command register. The Command Sequence is shown in Table 8 and

Figure 3. The autoselect operation of block protect verification is initiated by first writing two unlock cycle. The third cycle must con-

tain the bank address and autoselect command (90H). If Block address while (A6, A1, A0) = (0,1,0) is finally asserted on the address

pin, it will produce a logical "1" at the device output DQ0 to indicate a write protected block or a logical "0" at the device output DQ0

to indicate a write unprotected block. To terminate the autoselect operation, write Reset command (F0H) into the command register.

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Figure 3. Autoselect Operat ion ( by command sequence method )

555H/

AAAH 2AAH/

555H 555H/

AAAH

AAH 55H 90H

00H/ 01H/

ECH

Manufacturer

Code Device Code

A19∼A0(x16)/*

DQ15∼DQ0 F0H

Return to

Read Mode

Write (Program/Erase) Mode

The K8D1716U executes its program/erase operations by writing commands in to the command register. In order to write the com-

mands to the register, CE and WE must be low and OE must be high. Addresses are latched on the falling edge of CE or WE (which-

ever occurs last) and the data are latched on the rising edge of CE or WE (whichever occurs first). The device uses standard

microprocessor write timing.

Program

The K8D1716U can be programmed in units of a word or a byte. Programming is writing 0's into the memory array by executing the

Internal Program Routine. In ord er to p erfor m the Internal Progr am Routine, a four-cycle command seq uence is necessary. The fir st

two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the mem-

ory location and the data to be programmed at that location are written. The device automatically generates adequate program

pulses and verifies the programmed cell margin by the Inter nal Program R outine . During the execution of the Routine, the system is

not required to provide further controls or timings.

During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program

operation will cause data corruption at the corresponding location.

Figure 4. Progra m Command Sequence

555H/

AAAH 2AAH/

555H 555H/

AAAH

AAH 55H A0H

Program

Start

DQ15-DQ0

Address

Data

RY/BY

VID

00H 01H

ECH 2275H

2277H

Manufacturer

Code Device Code

A6,A1,A0*

DQ15-DQ0

Figure 2. Autoselect Operation ( by high voltage method )

Return to

Read Mode

V = VIH or VIL

2275H

2277H

Note : The addresses other than A0 , A1 and A6 are Don′t care. Please refer to Table 9 for device code.

Note : The 3rd Cycle and 4th Cycle address must include the same bank address. Please refe r to Table 9 for device code.

(K8D1716U)

A19∼A-1(x8)

A19∼A0(x16)/

A19∼A-1(x8)

00H 02H

FLASH MEMORYK8D1716UTC / K8D1716UBC

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Unlock Bypass

The K8D1716U provides the unlock bypass mode to save it s program time for program operation. The mode is invoked by the unlock

bypass command sequence. Then, the unlock bypass program command sequence is required to program the device.

Unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command sequence

comprises only two bus cycles.

The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writ-

ing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock

bypass mode, the unlock bypass program command sequence is necessary to program in this mode. The unlock bypass program

command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the pro-

gram address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode.

The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock

bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains

only the data (00H). Then, the device returns to the read mode.

Chip Erase

To erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus

cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two

more write cycles prior to writing the chip erase command. The Inter nal Erase Routine automatically pre-programs and verifies the

entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CE pulse

in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.

Figure 5. Chip Erase Command Seque nce

555H/

AAAH 2AAH/

555H 555H/

AAAH

AAH 55H 80H

555H

Chip Erase

Start

DQ15-DQ0

AAAH 2AAH/

555H

AAH 55H 10H

RY/BY

555H/

AAAH

A19∼A0(x16)/

A19∼A-1(x8)

Block Erase

To erase a block is to write 1′s into the desired memory block by executing the Internal Era se Routine. Th e Block Erase requires six

bus cycles to write the command sequence shown in Table 8. After the first two "unlock" cycles, the erase setup command (80H) is

written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine

automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE

or CE, while the Block Erase command is latched on the rising edge of WE or CE.

Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Figure 6. Upon completion of the last cycle for the

Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50µs

(typical) "time window" is require d betw een t he Block Erase command writes. The Block Erase comman d must b e writte n within th e

50µs "time window", otherwise the Block Erase command will be ignored. The 50 µs "time window" is reset w hen the falling edge of

the WE occurs within the 50µs of "time window" to latch the Block Erase command. During the 50µs of "time window", any command

other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50µs of

"time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase

address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized

except the Erase Suspend command during Block Erase operation.

FLASH MEMORYK8D1716UTC / K8D1716UBC

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555H/

AAAH 2AAH/

555H 555H/

AAAH

AAH 55H 80H

555H/

Block Erase

Start

DQ15-DQ0

AAAH 2AAH/

555H Block

Address

AAH 55H 30H

RY/BY

DQ15-DQ0

Figure 7. Erase Suspend/Resume Comman d Seq uence

Erase Suspend / Resume

The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Sus-

pend command is only valid during the Block Erase operation including the time window of 50µs. The Erase Suspend command is

not valid while the Chip Erase or the Internal Program Routine sequence is running.

When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20µs to suspend

the erase operation. But, when the Erase Suspend command is written during the block erase time window (50µs) , the device imme-

diately terminates the block erase time window and suspends the erase operation.

After the erase operation has been suspended, the device is availble for reading or programming data in a block that is not being

erased. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode.

When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume

command is executed, the addresses are in Don't Care state.

Figure 6. Block Erase Command Sequence

A19∼A0(x16)/

A19∼A-1(x8)

A19∼A0(x16)/

A19∼A-1(x8)

555H/

AAAH Block

Address

AAH 30H

XXXH

Erase

Resume

XXXH

B0H 30H

Erase

Suspend

Block Erase

Start

Block Erase

Command Sequence

FLASH MEMORYK8D1716UTC / K8D1716UBC

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Read While Write

The K8D1716U provides dual bank memory architecture that divides the memory array into two banks. The device is capable of

reading data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with

dual bank architecture; this feature provides the capability of executing the read operation during Program/Erase or Erase-Suspend-

Program operation.

The Read While Write operation is prohibited during the chip erase operation. It is also allowed during erase operation when either

single block or multiple blocks from same bank ar e loaded to be erased. It means that the Read While Write operation is prohibited

when blocks from Bank1 and another blocks from Bank2 are loaded all together for the multi-block erase operation.

Block Group Protection & Unprotection

The K8D1716U feature hardware block group protection. This featur e will disable both program and erase operations in any combi-

nation of twenty five block groups of memory. Please refer to Tables 10 and 11. The block group p rotection feat ure is e nabled using

programming equipment at the user’s site. The device is shipped with all block groups unprotected.

This feature can be hardware protected or unprotected. If a block is protected, program or erase command in the protected block will

be ignored by the device. The protected block can only be read. This is useful method to preserve an important program data. The

block group unprotection allows the protected blocks to be erased or programed. All blocks must be protected before unprotect oper-

ation is executing. The block group protection and unprotection can be implemented by two methods.

The first method needs the following conditions.

Operation CE OE WE BYTE A9 A6 A1 A0 DQ15/

A-1 DQ8/

DQ14 DQ0/

DQ7 RESET

Block Group Protect L H L X X L H L X X DIN VID

Block Group Unprotect L H L X X H H L X X DIN VID

The K8D1716U needs the recovery time (20µs) from the rising edge of WE in order to execute its program, erase and read opera-

tions.

Operation CE OE WE BYTE A9 A6 A1 A0 DQ15/

A-1 DQ8/

DQ14 DQ0/

DQ7 RESET

Block Group Protect L VID XVID LHL X X X H

Block Group Unprotect L VID XVID HHL X X X H

Don't Care

Address

Don't Care

500ns

Block Group Address*

Figure 8. Block Group Protect Sequence (The second method)

Block Group Protect:150µs

Block Group Unprotect:500ms

Notes : * Block Group Address is Don't Care during Block Group Unprotection.

Address must be inputted to the block group address (A12~A19) during block group protection operation. Please refer to Figure 9

(Algorithm) and Switching Waveforms of Block Group Protect & Unprotect Operations.

The second method needs the following conditions in order to keep backward compatibility. Please refer to Figure 8.

Low

VID

FLASH MEMORYK8D1716UTC / K8D1716UBC

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Figure 9. Block Group Protection & Unprotection Algorithms

Block Protect

Algorithm Set up Block Group

address

Block Group Protect:

Write 60H to Block

Group address with

A6=0,A1=1

A0=0

Wait 150µs

Verify Block Group

Protect:Write 40H to

Block Group address

with A6=0,

A1=1,A0=0

Read from

Block Group address

with A6=0,

A1=1,A0=0

Data=01h?

Protect another

Block Group?

Remove VID

from RESET

Write RESET

command

END

Wait 1µs

First Write

Cycle=60h? Temporary Block Group

Unprotect Mode

Block Group Unprotect

Write 60H

with

A6=1,A1=1

A0=0

Wait 15ms

Verify Block Group

Unprotect:Write 40H to

Block Group address

with A6=1,

A1=1,A0=0

Read from

Block Group address

with A6=1,

A1=1,A0=0

Data=00h?

Last Block Group

Remove VID

from RESET

Wri te RESE T

command

END

Increment

COUNT

=1000?

Device failed

Yes Yes

Yes

Algorithm

Increment

COUNT

=25?

Device failed

Yes

All Block Groups

Protected ?

No Block Group <i>, i= 0

START

COUNT = 1

RESET=VID

Yes

Note : All blocks must be protected before unprotect operation is executing.

verified ?

Block Group

Protection ?

Yes

Set up next Block

Reset

COUNT=1

Block Unprotect

Group address

FLASH MEMORYK8D1716UTC / K8D1716UBC

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Table 10. Block Group Address (Top Boot Block)

Block Group Block Address Block

A19 A18 A17 A16 A15 A14 A13 A12

BGA0 0 0 0 0 0 X X X BA0

BGA1 0 0 0

X X X BA1 to BA310

BGA2 0 0 1 X X X X X BA4 to BA7

BGA3 0 1 0 X X X X X BA8 to BA11

BGA4 0 1 1 X X X X X BA12 to BA15

BGA5 1 0 0 X X X X X BA16 to BA19

BGA6 1 0 1 X X X X X BA20 to BA23

BGA7 1 1 0 X X X X X BA24 to BA27

BGA8

11100XXX

BA28 to BA3011101XXX

11110XXX

BGA9 11111000 BA31

BGA10 1 1 1 1 1 0 0 1 BA32

BGA11 1 1 1 1 1 0 1 0 BA33

BGA12 1 1 1 1 1 0 1 1 BA34

BGA13 1 1 1 1 1 1 0 0 BA35

BGA14 1 1 1 1 1 1 0 1 BA36

BGA15 1 1 1 1 1 1 1 0 BA37

BGA16 1 1 1 1 1 1 1 1 BA38

FLASH MEMORYK8D1716UTC / K8D1716UBC

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Table 11. Block Group Address (Bottom Boot Block)

Block Group Block Address Block

A19 A18 A17 A16 A15 A14 A13 A12

BGA0 00000000 BA0

BGA1 00000001 BA1

BGA2 00000010 BA2

BGA3 00000011 BA3

BGA4 00000100 BA4

BGA5 00000101 BA5

BGA6 00000110 BA6

BGA7 00000111 BA7

BGA8 0 0 0

X X X BA8 to BA1010

BGA9 0 0 1 X X X X X BA11 to BA14

BGA10 0 1 0 X X X X X BA15 to BA18

BGA11 0 1 1 X X X X X BA19 to BA22

BGA12 1 0 0 X X X X X BA23 to BA26

BGA13 1 0 1 X X X X X BA27 to BA30

BGA14 1 1 0 X X X X X BA31 to BA34

BGA15 1 1 1

X X X BA35 to BA3701

BGA16 1 1 1 1 1 X X X BA38

FLASH MEMORYK8D1716UTC / K8D1716UBC

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Temporary Block Group Unprotect

The protected blocks of the K8D1716U can be temporarily unprotected by applying high voltage (VID = 8.5V~12.5V) to the RESET

pin. In this mode, previously protected blocks can be programmed or erased with the program or erase command routines. When the

RESET pin goes high (RESET = VIH), all the previously protected blocks will be protected again. If the WP/ACC pin is asserted at VIL

, the two outermost boot blocks remain protected.

RESET

Program & Erase Operation

VID

V = VIH or VIL

at Protected Block

Figure 10. Temporary Block Group Unpro tec t Sequ en c e

Secode(Security Code) Block Region

The Secode Block feature provides a Flash memory region to be stored unique and permanent identification code, that is, Electronic

Serial Number (ESN), customer code and so on. This is primarily intended for customers who wish to use an Electronic Serial Num-

ber (ESN) in the device with the ESN prote cted against modificatio n. Once the Secode Block region is protected, any further modifi-

cation of that region is impossible. This ensures the security of the ESN once the product is shipped to the field.

The Secode Block is factory locked or customer lockable. Before the device is shipped, the factory locked Secode Block is written on

the special code and it is protected. The Secode Indicator bit (DQ7) is permanently fixed at "1" and it is not changed. The customer

lockable Secode Block is unprotected, therefore it is programmed and erased. The Secode Indicator bit (DQ7) of it is permanentl y

fixed at "0" and it is not changed. But once it is protected, there is no procedure to unprotect and modify the Secode Block.

The Secode Block region is 64K bytes in length and is accessed through a new command sequence ( see Table 8). After the system

has written the Enter Secode Block command sequence, the system may read the Secode Block region by using the same

addresses of the boot blocks (8KBx8). The K8D1716UT occupies the addr ess of the byte mode 3F000 0H to 3FFFFFH (word mod e

1F8000H to 1FFFFFH) and the K8D1716UB type occupies the address of the byte mode 000000H to 00FFFFH (word mode

000000H to 007FFFH). This mode of operation continues until the system issues the Exit Secode Block command sequence, or until

power is removed from the device. On power-up, or following a hardware reset, the device reverts to read mode.

Write Protect (WP)

The WP/ACC pin has two useful functions. The one is that certain boot block is protected by the hardw are method not to use VID.

The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph).

When the WP/ACC pin is asserted at VIL, the device can not perform program an d erase operation in the two "outermost" 8K byte

boot blocks independently of whether those blocks wer e protected or unpro tected using the method described in "Block Grou p pro-

tection/Unprotection".

The write protected blocks can only be read. This is useful method to preserve an important program data.

The two outermost 8K byte boot blocks are the two blocks containing the lowest addresses in a bottom-boot-configured device, or

the two blocks containing the highest addresses in a top-boot-congfigured device.

(K8D1716UT : BA37 and BA38, K8D1716UB : BA0 and BA1)

When the WP/ACC pin is asserted at VIH, the device reverts to whether the two outermost 8K byte boot blocks were last set to be

protected or unprotected. That is, block protection or unprotection for these two blocks depends o n whether they were last protected

or unprotected using the method described in "Block Group protection/unprotection".

Recommend that the WP/ACC pin must not be in the state of floating or unconnected, or the device may be led to malfun ction.

FLASH MEMORYK8D1716UTC / K8D1716UBC

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Accelerated Program Operation

Accelerated program operation reduces the program time. Th is is one of two functions provided by the WP/ACC pin. When the WP/

ACC pin is asserted as VHH, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotecting any

protected blocks, and reduces the program operation time. The system would use a two-cycle program command sequence as

required by the Unlock Bypass mode. Removing VHH from the WP/ACC pin returns the device to normal operation. Recommend

that the WP/ACC pin must not be asserted at VHH except accelerated program operation, or the device may be damaged. In

addition, the WP/ACC pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunc-

tion.

Software Reset

The reset command provides that the ban k is reseted t o read mode or erase- suspend- read mode. The addr esses are in Don't Care

state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a pro-

gram command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be

erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the

sequence cycles in an autoselect command sequence. In the autoselect mode, the reset comman d returns the bank to read mode.

If a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read

mode. If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode

if the bank was in the Erase Suspend state.

Hardware Reset

The K8D1716U offers a reset feature by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500ns.

When the RESET pin is driven low, any operatio n in progress will be terminated and the internal state machine will be reset to the

standby mode after 20µs. If a hardware reset occurs during a program operation, the data at that particular location will be lost.

Once the RESET pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that

all the data output pins are tri-stated for the duration of the RESET pulse.

The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program and Erase Routine, the

device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up fir mware from

the Flash memory.

Power-up Protection

To avoid initiation of a write cycle during Vcc Power-up, RESET low must be asserted during power-up. After RESET goes high, the

device is reset to the read mode.

Low Vcc Wr ite Inhibit

To avoid in itiation of a write cycle during Vcc power-up and power- down, a write cycle is locked out for Vcc less than 1.8V. If Vcc <

VLKO ( Lock-Out Vo ltage), the command registe r and all internal pr ogram /erase circuits are disabled. Under this condition the device

will reset itself to the read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user′s responsi-

bility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 1.8V.

Write Pulse Glitch Protection

Noise pulses of less than 5ns(typical) on CE, OE, or WE will not initiate a write cycle.

Logical In hibit

Writing is inhibited under any one of the following conditions : OE = VIL, CE = VIH or WE = VIH. To initiate a write, CE and WE must

be "0", while OE is "1".

Commom Flash Memory Interface

Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific informa-

tion of the device, such as memory size, byte/word configuration, and electrical features. Once this information has been obtained,

the system software will know which command sets to use to enable flash writes, block erases, and control the flash component.

When the system writes the CFI command(98H) to address 55H in word mode(or address AAH in byte mode), the device enters the

CFI mode. And then if the system writes the address shown in Table 12, the system can read the CFI data. Query data are always

presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate

this operation, the system must write the reset command.

FLASH MEMORYK8D1716UTC / K8D1716UBC

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Table 12. Common Flash Memory Interface Code

Description Addresses

(Word Mode) Addresses

(Byte Mode) Data

Query Unique ASCII string "QRY" 10H

11H

12H

20H

22H

24H

0051H

0052H

0059H

Primary OEM Command Set 13H

14H 26H

28H 0002H

0000H

Address for Primary Extended Table 15H

16H 2AH

2CH 0040H

0000H

Alternate OEM Command Set (00h = none exists) 17H

18H 2EH

30H 0000H

0000H

Address for Alternate OEM Extended Table (00h = none exists) 19H

1AH 32H

34H 0000H

0000H

Vcc Min. (write/erase)

D7-D4: volt, D3-D0: 100 millivolt 1BH 36H 0027H

Vcc Max. (write/erase)

D7-D4: volt, D3-D0: 100 millivolt 1CH 38H 0036H

Vpp Min. voltage(00H = no Vpp pin present) 1DH 3AH 0000H

Vpp Max. voltage(00H = no Vpp pin present) 1EH 3CH 0000H

Typical timeout per single byte/word write 2N us 1FH 3EH 0004H

Typical timeout for Min. size buffer write 2N us(00H = not supported) 20H 40H 0000H

Typical timeout per individual block erase 2N ms 21H 42H 000AH

Typical timeout for full chip erase 2N ms(00H = not supported) 22H 44H 0000H

Max. timeout for byte/word write 2N times typical 23H 46H 0005H

Max. timeout for buffer write 2N times typical 24H 48H 0000H

Max. timeout per individual block erase 2N times typical 25H 4AH 0004H

Max. timeout for full chip erase 2N times typical(00H = not supported) 26H 4CH 0000H

Device Size = 2N byte 27H 4EH 0015H

Flash Device Interface description 28H

29H 50H

52H 0002H

0000H

Max. number of byte in multi-byte write = 2N2AH

2BH 54H

56H 0000H

0000H

Number of Erase Block Regions within device 2CH 58H 0002H

Erase Block Region 1 Information

2DH

2EH

2FH

30H

5AH

5CH

5EH

60H

0007H

0000H

0020H

0000H

Erase Block Region 2 Information

31H

32H

33H

34H

62H

64H

66H

68H

001EH

0000H

0001H

Erase Block Region 3 Information

35H

36H

37H

38H

6AH

6CH

6EH

70H

0000H

Erase Block Region 4 Information

39H

3AH

3BH

3CH

72H

74H

76H

78H

0000H

FLASH MEMORYK8D1716UTC / K8D1716UBC

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Table 12. Common Flash Memory Interface Code

Note :

1. The number of blocks in Bank2 is device dependent.

K8D1716U(8Mb/8Mb) = 10h (16blocks)

Description Addresses

(Word Mode) Addresses

(Byte Mode) Data

Query-unique ASCII string "PRI" 40H

41H

42H

80H

82H

84H

0050H

0052H

0049H

Major version number, ASCII 43H 86H 0031H

Minor version number, ASCII 44H 88H 0032H

Address Sensitive Unlock(Bits 1-0)

0 = Required, 1= Not Required

Silcon Revision Number(Bits 7-2) 45H 8AH 0000H

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 46H 8CH 0002H

Block Protect

0 = Not Supported, 1 = Number of blocks in per group 47H 8EH 0001H

Block Temporary Unprotect 00 = Not Supported, 01 = Supported 48H 90H 0001H

Block Protect/Unprotect scheme 04=K8D1x16U mode 49H 92H 0004H

Simultaneous Operation (1)

00 = Not Supported, XX = Number of Blocks in Bank2 4AH 94H 00XXH

Burst Mode Type 00 = Not Supported, 01 = Supported 4BH 96H 0000H

Page Mode Type

00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page 4CH 98H 0000H

ACC(Acceleration) Supply Minimum

00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV 4DH 9AH 0085H

ACC(Acceleration) Supply Maximum

00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV 4EH 9CH 00C5H

Top/Bottom Boot Block Flag

02H = Bottom Boot Device, 03H = Top Boot Device 4FH 9EH 000XH

FLASH MEMORYK8D1716UTC / K8D1716UBC

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DEVICE STATUS FLAGS

The K8D1716U has means to indicate its status of operation in the bank where a program or erase operation is in processes.

Address must include bank address being excuted internal routine operation. The status is indicated by raising the device status flag

via corresponding DQ pins or the RY/ BY pin. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2. T he statuses are as

follows :

Table 13. Hardware Sequence Flags

Notes :

1. DQ2 will toggle when the device perf orms successive read operations from the erase suspended block.

2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.

Status DQ7 DQ6 DQ5 DQ3 DQ2 RY/BY

In Progress

Programming DQ7 Toggle 0 0 1 0

Block Erase or Chip Erase 0 Toggle 0 1 Toggle 0

Erase Suspend Read Erase Suspended

Block 1100

Toggle

(Note 1) 1

Erase Suspend Read Non-Erase Sus-

pended Block Data Data Data Data Data 1

Erase Suspend

Program Non-Erase Sus-

pended Block DQ7 Toggle 0 0 1 0

Exceeded

T ime Limits

Programming DQ7 Toggle 1 0 No

Toggle 0

Block Erase or Chip Erase 0 Toggle 1 1 (Note 2) 0

Erase Suspend Program DQ7 Toggle 1 0 No

Toggle 0

DQ7 : Data Polling

When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as

an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data

written to DQ7. When a user attempts to rea d the device during the Erase op eration, DQ7 will be low. If the device is placed in the

Erase Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block

that is being erased, DQ7 will be high. If a non-erased block address is read, the device will produce the true data to DQ7. If an

attempt is made to program a protected block, DQ7 outputs complements the data for approximately 1µs and the device then returns

to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement

data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block.

DQ6 : Toggle Bit

Toggle bit is another option to detect whether an Internal Routine is in prog ress or completed. Once the device is at a busy state,

DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routi ne. If the device is in the Erase Suspend Mode,

an attempt to read an address that belongs to a block that is being erased will produce a high output of DQ6. If an addre ss belongs

to a block that is not being erased, toggling is halted and valid data is produced at DQ6.

If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read

Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100µs

and the device then returns to the Read Mode without erasing the data in the block.

DQ5 : Exceed Timing Limits

If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

RY/BY : Ready/Busy

The K8D1716U has a Ready / Busy output that in dicates eithe r the complet ion of an operation or the status of Internal Algorithms. If

the output is Low, the device is busy with either a program or an erase operation. If the outpu t is High, the device is ready to accept

any read/write or erase operation. When the RY/ BY pin is low, the device will not accept any additional program or erase commands

with the exception of the Erase Suspend command. If the K8D1716U is placed in an Erase Suspend mode, the RY/ BY output will be

High. For programming, the RY/ BY is valid (RY/ BY = 0) after the rising edge of the fourth WE pulse in the four write pulse

sequence. For Chip Erase, RY/ BY is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block Erase,

RY/ BY is also valid after the rising edge of the sixth WE pulse.

The pin is an open drain output, allow ing two or more Ready/ Busy outputs to be OR-tied. An appro priate pull-up r esistor is requ ired

for proper operation.

DQ3 : Block Erase Timer

The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50µs of the block erase time win-

dow expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write

commands until the erase operation is completed. DQ3 is Low if the b lock erase time window is not expired. Within the b lock erase

time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been

accepted, the software may check the status of DQ3 following each block erase command.

DQ2 : Toggle Bit 2

The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase Suspend is in progress. When the device

executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is in the

Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase

Suspend mode, DQ2 toggles only if an address in t he er asing bl ock is read. If a non-erasing block address is read during the Erase

Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the

device is in the Erase Suspend mode. Combination of the status in DQ6 and DQ2 can be used to distinguish the erase operation

from the program operation.

VccF

Ready / Busy

open drain output

Device

Vss

where Σ IL is the sum of the input currents of all devices tied to the

Ready / Busy ball.

Rp = VccF (Max.) - VOL (Max.)

IOL + Σ IL = 3.2V

2.1mA + Σ IL

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Figure 13. Temporary Block Group Unprotect Routine

Start

RESET=VID

Notes :

1. All protected block groups are unprotected.

( If WP/ACC = VIL , the two outermost boot blocks remain protected )

2. All previously protected block groups are protected once again.

(Note 1)

Perform Erase or

Program Operations

Temporary Block

Unprotect Completed

(Note 2)

RESET=VIH

Start

DQ7 = Data ?

DQ5 = 1 ?

Fail Pass

Yes

Figure 11. Data Polling Algorithms Figure 12. To ggle Bit Algorith ms

DQ7 = Data ?

Yes

Read(DQ0~DQ7)

Valid Address

Read(DQ0~DQ7)

Valid Address

Start

DQ6 = Toggle ?

DQ5 = 1 ?

Fail Pass

DQ6 = Toggle ?

Yes

Read twice(DQ0~DQ7)

Valid Address

Read(DQ0~DQ7)

Valid Address

Yes Yes

Read(DQ0~DQ7)

Valid Address

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

DC CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS ( Voltage reference to Vss )

Parameter Symbol Min Typ. Max Unit

Supply Voltage VCC 2.7 3.0 3.6 V

Supply Voltage VSS 000V

ABSOLUTE MAXIMUM RATINGS

Notes :

1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on

input / output pins is Vcc+0.5V which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.

2. Minimum DC voltage is -0.5V on A9, OE, RESET and WP/ACC pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC

voltage on A9, OE, RESET pins is 12.5V which, during transitions, may overshoot to 14.0V for periods <20ns.

3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricte d to the condi tio ns

detailed in the operat ional sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter Symbol Rating Unit

Voltage on any pin relative to VSS

Vcc Vcc -0.5 to +4.0

A9, OE , RESET

VIN

-0.5 to +12.5

WP/ACC -0.5 to +12.5

All Other Pins -0.5 to +4.0

Temperature Under Bias Commercial Tbias -10 to +125 °C

Industrial -40 to +125

Storage Temperature Tstg -65 to +150 °C

Short Circuit Output Current IOS 5mA

Operating Temperature TA (Commercial Temp.) 0 to +70 °C

TA (Industrial Temp.) -40 to + 85 °C

Parameter Symbol Test Conditions Min Typ Max Unit

Input Leakage Current ILI VIN=VSS to VCC, VCC=VCCmax − 1.0 - + 1.0 µA

A9,OE,RESET Input Leakage

Current ILIT VCC=VCCmax, A9,OE,RESET=12.5V - - 35 µA

WP/ACC Input Leakage Current ILIW VCC=VCCmax, WP/ACC=12.5V - - 35 µA

Output Leakage Current ILO VOUT=VSS to VCC,VCC=VCCmax,OE=VIH − 1.0 - + 1.0 µA

Active Read Current (1) ICC1CE=VIL, OE=VIH 5MHz - 14 20 mA

1MHz - 3 6

Active Write Current (2) ICC2CE=VIL, OE=VIH, WE=VIL -1530mA

Read While Program Current (3) ICC3CE=VIL, OE=VIH -2550mA

Read While Erase Current (3) ICC4CE=VIL, OE=VIH -2550mA

Program While Erase Suspend

Current ICC5CE=VIL, OE=VIH -1535mA

ACC Accelerated Program

Current IACC CE=VIL, OE=VIH ACC Pin -510

Vcc Pin -1530

Standby Current ISB1VCC=VCCmax,CE, RESET=VCC±0.3V

WP/ACC= VCC± 0.3V or Vss±0.3V -518µA

Standby Current During Reset ISB2VCC=VCCmax, RESET=Vss± 0.3V,

WP/ACC=VCC± 0.3V or Vss±0.3V -518µA

Automatic Sleep Mode ISB3VIH=VCC±0.3V, VIL=VSS±0.3V,

OE=VIL, IOL=IOH=0 -518µA

Input Low Level VIL -0.5 - 0.8 V

Input High Level VIH 0.7xVcc -VCC+0.3 V

Voltage for WP/ACC Block Tempo-

rarily Unprotect and Program Accel-

eration (4) VHH VCC = 3.0V ± 0.3V 8.5 - 12.5 V

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

AC CHARACTERISTICS

AC TEST CONDITION

Parameter Value

Input Pulse Levels 0V to Vcc

Input Rise and Fall Times 5ns

Input and Output Timing Levels Vcc/2

Output Load CL = 30pF

Read Operations

Note : 1. Not 100% tested.

Parameter Symbol

VCC=2.7V~3.6V

Unit

-7 -8 -9

Min Max Min Max Min Max

Read Cycle Time (1) tRC 70 - 80 - 90 - ns

Address Access Time tAA -70-80-90ns

Chip Enable Access Time tCE -70-80-90ns

Output Enable Time tOE -25-25-35ns

CE & OE Disable Time (1) tDF -16-16-16ns

Output Hold Time from Address, CE or OE (1) tOH 0-0-0-ns

Notes :

1. The ICC current listed includes both the DC operati ng current and the frequency dependent component(at 5 MHz).

The read current is typically 14 mA (@ VCC=3.0V , OE at VIH.)

2. ICC active during Internal Routine(program or erase) is in progress.

3. ICC active during Read while Write is in progress.

4. The high voltage ( VHH or VID ) must be used in the range of Vcc = 3.0V ± 0.3V

5. Not 100% tested.

6. Typical value are measured at Vcc = 3.0V,TA=25°C , Not 100% tested.

CAPACITANCE(TA = 25 °C, VCC = 3.3V, f = 1.0MHz)

Note : Capacitance is periodically sampled and not 100% tested.

Item Symbol Test Condition Min Max Unit

Input Capacitance CIN VIN=0V - 10 pF

Output Capacitance COUT VOUT=0V - 10 pF

Control Pin Capacitance CIN2 VIN=0V - 10 pF

Parameter Symbol Test Conditions Min Typ Max Unit

Voltage for Autoselect and

Block Protect (4) VID VCC = 3.0V ± 0.3V 8.5 - 12.5 V

Output Low Level VOL IOL=100µA, VCC=VCCmin --0.4V

Output High Level VOH IOH=-100µA, Vcc = VCCmin VCC-0.4 - - V

Low Vcc Lock-out Voltage (5) VLKO 1.8 - 2.5 V

Vcc Vcc/2 Vcc/2

Input Pulse and Test Point

Input & Output

Test Point

Output Load

* CL= 30pF including Scope

Device

and Jig Capacitance

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Alternate WE Controlled Write

Notes : 1. Not 100% tested.

2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms.

Parameter Symbol

VCC=2.7V~3.6V

Unit

-7 -8 -9

Min Max Min Max Min Max

Write Cycle Time (1) tWC 70 - 80 - 90 - ns

Address Setup Time tAS 0 - 0-0-ns

tASO 55 - 55 - 55 - ns

Address Hold Time tAH 45 - 45 - 45 - ns

tAHT 0 - 0-0-ns

Data Setup Time tDS 35 - 35 - 45 - ns

Data Hold Time tDH 0 - 0-0-ns

Output Enable Setup Time (1) tOES 0 - 0-0-ns

Output

Enable

Hold Time

Read (1) tOEH1 0 - 0-0-ns

Toggle and Data Polling (1) tOEH2 10 - 10 - 10 - ns

CE Setup Time tCS 0 - 0-0-ns

CE Hold Time tCH 0 - 0-0-ns

Write Pulse Width tWP 35 - 35 - 45 - ns

Write Pulse Width High tWPH 25 - 25 - 30 - ns

Programming Operation Word tPGM 14(typ.) 14(typ.) 14(typ.) µs

Byte 9(typ.) 9(typ.) 9(typ.) µs

Accelerated Programming

Operation Word tACCPGM 9(typ.) 9(typ.) 9(typ.) µs

Byte 7(typ.) 7(typ.) 7(typ.) µs

Block Erase Operation (2) tBERS 0.7(typ.) 0.7(typ.) 0.7(typ.) sec

VCC Set Up Time tVCS 50 - 50 - 50 - µs

Write Recovery Time from RY/BY tRB 0 - 0-0-ns

RESET High Time Before Read tRH 50 - 50 - 50 - ns

RESET to Power Down Time tRPD 20 - 20 - 20 - µs

Program/Erase Valid to RY/BY Delay tBUSY 90 - 90 - 90 - ns

VID Rising and Falling Time tVID 500 - 500 - 500 - ns

RESET Pulse Width tRP 500 - 500 - 500 - ns

RESET Low to RY/BY High tRRB -20-20-20µs

RESET Setup Time for Temporary Unprotect tRSP 1 - 1-1-µs

RESET Low Setup Time tRSTS 500 - 500 - 500 - ns

RESET High to Address Valid tRSTW 200 - 200 - 200 - ns

Read Recovery Time Before Write tGHWL 0 - 0-0-ns

CE High during toggling bit polling tCEPH 20 - 20 - 20 - ns

OE High during toggling bit polling tOEPH 20 - 20 - 20 - ns

AC CHARACTERISTICS

Write(Erase/Program)Operations

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

AC CHARACTERISTICS

Write(Erase/Program)Operations

Alternate CE Controlled Writes

Notes : 1. No t 100% tested.

2.This does include the preprogramming time.

Parameter Symbol

VCC=2.7V~3.6V

Unit-7 -8 -9

Min Max Min Max Min Max

Write Cycle Time (1) tWC 70 - 80 - 90 - ns

Address Setup Time tAS 0-0-0-ns

Address Hold Time tAH 45 - 45 - 45 - ns

Data Setup Time tDS 35 - 35 - 45 - ns

Data Hold Time tDH 0-0-0-ns

Output Enable Setup Time (1) tOES 0-0-0-ns

Output

Enable

Hold Time

Read (1) tOEH1 0-0-0-ns

Toggle and Data Polling (1) tOEH2 10 - 10 - 10 - ns

WE Setup Time tWS 0-0-0-ns

WE Hold Time tWH 0-0-0-ns

CE Pulse Width tCP 35 - 35 - 45 - ns

CE Pulse Width High tCPH 25 - 25 - 30 - ns

Programming Operation Word tPGM 14(typ.) 14(typ.) 14(typ.) µs

Byte 9(typ.) 9(typ.) 9(typ.) µs

Accelerated Programming

Operation Word tACCPGM 9(typ.) 9(typ.) 9(typ.) µs

Byte 7(typ.) 7(typ.) 7(typ.) µs

Block Erase Operation (2) tBERS 0.7(typ.) 0.7(typ.) 0.7(typ.) sec

BYTE Switching Low to Output HIGH-Z tFLQZ 25 - 25 - 30 - ns

ERASE AND PROGRAM PERFORMANCE

Notes : 1. 25 °C, VCC = 3.0V 100,000 cycles, typical pattern.

2. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte.

In the preprogramming step of the Internal Erase Routine, all bytes are programmed to 00H before erasure.

Parameter Limits Unit Comments

Min Typ Max

Block Erase Time - 0.7 15 sec Includes 00H programming

prior to erasure

Chip Erase Time - 25 - sec

Word Programming Time - 14 330 µs Excludes system-level overhead

Byte Programming Time - 9 210 µs Excludes system-level overhead

Accelerated Byte/Word

Program Time Word Mode - 9 210 µs Excludes system-level overhead

Byte Mode - 7 150 µs Excludes system-level overhead

Chip Programming Time Word Mode - 14 42 sec Excludes system-level overhead

Byte Mode - 18 54 sec

Erase/Program Endurance 100,000 - - cycles Minimum 100,000 cycles guaran-

teed

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Read Operations

SWITCHING WAVEFORMS

Address

tCE

tOEH1

Outputs

HIGH-Z Output Valid

tRC

Address Stable

tAA

tOE

tOH

HIGH-Z

tDF

RY/BY HIGH

Note : 1. Not 100% tested.

Parameter Symbol -7 -8 -9 Unit

Min Max Min Max Min Max

Read Cycle Time tRC 70 - 80 - 90 - ns

Address Access Time tAA -70-80-90ns

Chip Enable Access Time tCE -70-80-90ns

Output Enable Time tOE -25-25-35ns

CE & OE Disable Time (1) tDF -16-16-16ns

Output Hold Time from Address, CE or OE tOH 0-0-0-ns

OE Hold Time tOEH1 0-0-0-ns

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Hardware Reset/Read Operations

SWITCHING WAVEFORMS

Parameter Symbol -7 -8 -9 Unit

Min Max Min Max Min Max

Read Cycle Time tRC 70 - 80 - 90 - ns

Address Access Time tAA -70-80-90ns

Chip Enable Access Time tCE -70-80-90ns

Output Hold Time from Address, CE or OE tOH 0-0-0-ns

RESET Pulse Width tRP 500 - 500 - 500 - ns

RESET High Time Before Read tRH 50 - 50 - 50 - ns

RESET

Address

Outputs High-Z

tRC

Address Stable

tAA

tCE

tOH

tRH

tRHtRP

Output Valid

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Alternate WE Controlled Program Operations

SWITCHING WAV EFORMS

Notes : 1. DQ7 is the output of the complement of the data written to the device.

2. DOUT is the output of the data written to the device.

3. PA : Program Address, PD : Program Data

4. The illustration shows the last two cycles of the program command sequence.

Address

tCS

DATA

tAH

tOH

tDF

tAS

tRC

tOE

tCE

tDS

tDH

tWP

tOES

tPGM

Status DOUT

555H PA PA

A0H

Data Polling

tCH

tWPH

RY/BY tBUSY tRB

tWC

Parameter Symbol -7 -8 -9 Unit

Min Max Min Max Min Max

Write Cycle Time tWC 70 - 80 - 90 - ns

Address Setup Time tAS 0-0-0-ns

Address Hold Ti me tAH 45 - 45 - 45 - ns

Data Setup Time tDS 35 - 35 - 45 - ns

Data Hold Time tDH 0-0-0-ns

CE Setup Time tCS 0-0-0-ns

CE Hold Time tCH 0-0-0-ns

OE Setup Time tOES 0-0-0-ns

Write Pulse Width tWP 35 - 35 - 45 - ns

Write Pulse Width High tWPH 25 - 25 - 30 - ns

Programming Operation Word tPGM 14(typ.) 14(typ.) 14(typ.) us

Byte 9(typ.) 9(typ.) 9(typ.) us

Accelerated Programming

Operation Word tACCPGM 9(typ.) 9(typ.) 9(typ.) µs

Byte 7(typ.) 7(typ.) 7(typ.) µs

Read Cycle Time tRC 70 - 80 - 90 - ns

Chip Enable Access Time tCE -70-80-90ns

Output Enable Time tOE -25-25-35ns

CE & OE Disable Time tDF -16-16-16ns

Output Hold Time from Address, CE or OE tOH 0-0-0-ns

Program/Erase Valide to RY/BY Delay tBUSY 90 - 90 - 90 - ns

Recovery Time from RY/BY tRB 0-0-0-ns

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Alternate CE Controlled Program Operations

SWITCHING WAVEFORMS

Notes :

1. DQ7 is the output of the complement of the data written to the device.

2. DOUT is the output of the dat a written to the device.

3. PA : Program Address, PD : Program Data

4. The illustration shows the last two cycles of th e program comman d seque nce.

Address

DATA

tAH

tAS

tDS

tDH

tCP

tOES

A0H

555H PA PA

Status DOUT

Data Polling

tCPH

tWS

tPGM

RY/BY tBUSY tRB

tWC

Parameter Symbol -7 -8 -9 Unit

Min Max Min Max Min Max

Write Cycle Time tWC 70 - 80 - 90 - ns

Address Setup Time tAS 0-0-0-ns

Address Hold Time tAH 45 - 45 - 45 - ns

Data Setup Time tDS 35 - 35 - 45 - ns

Data Hold Time tDH 0-0-0-ns

OE Setup Time tOES 0-0-0-ns

WE Setup Time tWS 0-0-0-ns

WE Hold Time tWH 0-0-0-ns

CE Pulse Width tCP 35 - 35 - 45 - ns

CE Pulse Width High tCPH 25 - 25 - 30 - ns

Programming Operation Word tPGM 14(typ.) 14(typ.) 14(typ.) µs

Byte 9(typ.) 9(typ.) 9(typ.) µs

Accelerated Programming

Operation Word tACCPGM 9(typ.) 9(typ.) 9(typ.) µs

Byte 7(typ.) 7(typ.) 7(typ.) µs

Program/Erase Valide to RY/BY Delay tBUSY 90 - 90 - 90 - ns

Recovery Time from RY/BY tRB 0-0-0-ns

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

SWITCHING WAVEFORMS

Parameter Symbol -7 -8 -9 Unit

Min Max Min Max Min Max

Chip Enable Access Time tCE -70-80-90ns

CE to BYTE Switching Low or High tELFL/tELFH -5-5-5ns

BYTE Switching Low to Output HIGH-Z tFLQZ -25-25-30ns

BYTE Switching High to Output Active tFHQV -25-25-35ns

tFLQZ

DQ0-DQ7

BYTE

BYTE Timing Diagram for Write Operation

The falling edge of the last WE signal

BYTE

tHOLD(tAH)

DQ15/A-1

tELFL

Address Input (A-1)

tSET

(tAS)

Word to Byte Timing Diagram for Read Operation

Byte to Word Timing Diagram for Read Operation

Data Output

(DQ0-DQ7)

DQ8-DQ14 Data Output

(DQ8-DQ14)

Data Output

(DQ15)

tFHQV

DQ0-DQ7

BYTE

DQ15/A-1

tELFH

Data Output

DQ8-DQ14

Address Input

(A-1)

Data Output

(DQ8-DQ14)

(DQ15)

tCE

Data Output

(DQ0-DQ7)

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

SWITCHING WAVEFORMS

Chip/Block Erase Operations

Parameter Symbol -7 -8 -9 Unit

Min Max Min Max Min Max

Write Cycle Time tWC 70 - 80 - 90 - ns

Address Setup Time tAS 0-0-0-ns

Address Hold Time tAH 45 - 45 - 45 - ns

Data Setup Time tDS 35 - 35 - 45 - ns

Data Hold Time tDH 0-0-0-ns

OE Setup Time tOES 0-0-0-ns

CE Setup Time tCS 0-0-0-ns

Write Pulse Width tWP 35 - 35 - 45 - ns

Write Pulse Width High tWPH 25 - 25 - 30 - ns

Read Cycle Time tRC 70 - 80 - 90 - ns

VCC Set Up Time tVCS 50 - 50 - 50 - µs

Address

tCS

DATA

tAH

tAS

tRC

tDS

tDH

80H AAH

AAH 55H 30H

10H for Chip Erase

555H 2AAH 555H 555H 2AAH BA

555H for Chip Erase

tWPH

tWP

tOES

55H

RY/BY

tWC

tVCS

Vcc

Note : BA : Block Address

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Read While Write Operations

SWITCHING WAVEFORMS

Parameter Symbol -7 -8 -9 Unit

Min Max Min Max Min Max

Write Cycle Time tWC 70 - 80 - 90 - ns

Write Pulse Width tWP 35 - 35 - 45 - ns

Write Pulse Width High tWPH 25 - 25 - 30 - ns

Address Setup Time tAS 0-0-0-ns

Address Hold Time tAH 45 - 45 - 45 - ns

Data Setup Time tDS 35 - 35 - 45 - ns

Data Hold Time tDH 0-0-0-ns

Read Cycle Time tRC 70 - 80 - 90 - ns

Chip Enable Access Time tCE -70-80-90ns

Address Access Time tAA -70-80-90ns

Output Enable Access Time tOE -25-25-35ns

OE Setup Time tOES 0-0-0-ns

OE Hold Time tOEH2 10 - 10 - 10 - ns

CE & OE Disable Time tDF -16-16-16ns

Address Hold Time tAHT 0-0-0-ns

CE High during toggle bit polling tCEPH 20 - 20 - 20 - ns

Note : This is an example in the program-case of the Read While Write function.

DA1 : Address of Bank1, DA2 : Address of Bank 2

PA = Program Address at one bank , RA = Read Address a t the other bank, PD = Prog ram Dat a In , RD = Read Dat a Out

tRC

Read Command CommandRead Read Read

tAH tAA

tCE

tAS

tAHT

tAS

CEPH

tOE

tOES

tWP

tOEH2 tDF

tDS

DA1 DA2 DA1 DA1

DA2 DA2

(555H) (PA) (PA)

Valid

Output Valid

Output

Valid

Input

Valid

Output

Valid

Input Status

Address

(A0H) (PD)

tRCtRC tRCtWC tWC

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Data Polling During Internal Routine Operation

SWITCHING WAVEFORMS

Parameter Symbol -7 -8 -9 Unit

Min Max Min Max Min Max

Program/Erase Valid to RY/BY Delay tBUSY 90 - 90 - 90 - ns

Chip Enable Access Time tCE -70-80-90ns

Output Enable Time tOE -25-25-35ns

CE & OE Disable Time tDF -16-16-16ns

Output Hold Time from Address, CE or OE tOH 0-0-0-ns

OE Hold Time tOEH2 10 - 10 - 10 - ns

tCE

tOEH2

DQ7

tOE

HIGH-Z

tDF

Note : *DQ7=Vaild Data (The device has completed the internal operation).

DQ7 *DQ7 = Valid Data

tOH

tPGM or tBERS

HIGH-Z

Valid Data

DQ0-DQ6

Data In

RY/BY Timing Diagram During Program/Erase Operation

The rising edge of the last WE signal

RY/BY

BUSY

Entire progrming

or erase operation

Status Data

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Toggle Bit During Internal Routine Operation

SWITCHING WAVEFORMS

tDH

Address*

DQ6/DQ2

RY/BY

Data In

tAHT

tASO

tAS

tCEPH

tOEH2

tOEPH

Status

Data

Status

Data Status

Data Array Data Out

Note : Address for the write operation must include a bank address (A19) where the data is writte n.

DQ6

DQ2

Enter

Embedded

Erasing Erase

Suspend Enter Erase

Suspend Program

Erase

Suspend

Program

Erase

Resume

Erase Erase Suspend

Read Erase Erase

Complete

Erase Suspend

Read

Note : DQ2 is read from the erase-suspended block.

Toggle

DQ2 and DQ6

with OE or CE

Parameter Symbol -7 -8 -9 Unit

Min Max Min Max Min Max

Output Enable Access Time tOE -25-25-35ns

OE Hold Time tOEH2 10 - 10 - 10 - ns

Address Hold Time tAHT 0-0-0-ns

Address Setup tASO 55 - 55 - 55 - ns

Address Setup Time tAS 0-0-0-ns

Data Hold Time tDH 0-0-0-ns

CE High during toggle bit polling tCEPH 20 - 20 - 20 - ns

OE High during toggle bit polling tOEPH 20 - 20 - 20 - ns

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

RESET Timing Diagram

SWITCHING WAVEFORMS

Parameter Symbol -7 -8 -9 Unit

Min Max Min Max Min Max

RESET Pulse Width tRP 500 - 500 - 500 - ns

RESET Low to Valid Data

(During Internal Routine) tREADY -20-20-20µs

RESET Low to Valid Data

(Not during Internal Routine) tREADY - 500 - 500 - 500 ns

RESET High Time Before Read tRH 50 - 50 - 50 - ns

RY/BY Recovery Time tRB 0-0-0-ns

RESET High to Address Valid tRSTW 200 - 200 - 200 - ns

RESET Low Set-up Time tRSTS 500 - 500 - 500 - ns

RESET

Power-up and RESET Timing Diagram

CE or OE

RY/BY

READY

RESET

CE or OE

RY/BY

READY

Reset Timings NOT during Internal Routine

Reset Timings during Internal Routine

High

RESET

tAA

Vcc

Address

DATA

tRSTS

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

Block Group Protect & Unprotect Operations

SWITCHING WAVEFORMS

Temporary Block Group Unprotect

Program or Erase Command Sequence

RESET

tRSP

RY/BY

tVID

VID

Vss,VIL,

or VIH Vss,VIL,

or VIH

tRRB tVID

BGA,A6

A1,A0

RESET

DATA

Vss,VIL,

60H 60H 40H Status*

Block Group Protect / Unprotect Verify

1µsBlock Group Protect:150µs

Block Group UnProtect:15ms

Notes : Block Group Protect (A6=VIL , A1=VIH , A0=VIL) , Status=01H

Block Group Unprotect (A6=VIH , A1=VIH, A0=VIL) , S tatus=00H

BGA = Block Group Address (A12 ~ A19)

RY/BY

VID

Valid Valid

Valid

tBUSY

tRB

or VIH Vss,VIL,

or VIH

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

PACKAGE DIMENSIONS

48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220F Unit :mm/Inch

0.787±0.008

20.00±0.20

#24

0.20+0.07

-0.03

0.008+0.003

-0.001

0.50

0.0197

#48

#25

0.488

12.40MAX

12.00

0.472

0.10

0.004 MAX

0.25

0.010

()

0.039±0.002

1.00±0.05 0.002

0.05 MIN

0.047

1.20 MAX

0.45~0.75

0.018~0.030

0.724±0.004

18.40±0.10

0~8’C

0.010

0.25 TYP

0.125+0.075

-0.035

0.005+0.003

-0.001

0.50

0.020

()

FLASH MEMORYK8D1716UTC / K8D1716UBC

Revision 1.0

December 2004

PACKAGE DIMENSIONS

48-Ball Fine Ball Grid Array Package (measured in millimeters)

Side View

0.45±0.05

0.08MAX

0.32±0.05

0.90±0.10

8.50±0.10

Top View Bottom View

#A1 A

0.80 x 5=4.00 A

0.80x7=5.60

2.00

48-

∅

0.45±0.05

2.80

0.80

0.20

A B

∅

(Datum A)

(Datum B)

0.80

8.50±0.10

6.00±0.10

142 65 3

8.50±0.10

6.00±0.10