MAX15034BEVKIT+ - Maxim Integrated Products, Inc.

General Description

The MAX15034 two-phase, configurable single- or dual-

output buck controller has an input voltage range of

4.75V to 5.5V or 5V to 28V. A mode select input allows

for a dual-output supply or connecting two phases

together for a single-output, high-current supply. Each

output channel of the MAX15034 drives n-channel

MOSFETs and is capable of providing more than 25A of

load current. The MAX15034 uses average current-

mode control with a switching frequency up to 1MHz

per phase where each phase is 180° out of phase with

respect to the other. Out-of-phase operation results in

significantly reduced input capacitor ripple current and

output voltage ripple in dual-phase, single-output volt-

age applications. Each controller has its own high-per-

formance current and voltage-error amplifier that can

be compensated for optimum output filter L-C values

and transient response.

The MAX15034 offers two enable inputs with accurate

turn-on thresholds to allow for output voltage sequencing

of the two outputs. The device’s switching frequency can

be programmed from 100kHz to 1MHz with an external

resistor. The MAX15034 can be synchronized to an

external clock. Each output voltage is adjustable from

0.61V to 5.5V. Additional features include thermal shut-

down and hiccup-mode, short-circuit protection. Use the

MAX15034 with adaptive voltage positioning for applica-

tions that require a fast transient response or accurate

output voltage regulation.

The MAX15034 is available in a thermally enhanced 28-

pin TSSOP package capable of dissipating 2.1W. The

device is rated for operation over the -40°C to +125°C

automotive temperature range.

Applications

High-End Computers/Workstations/Servers

Graphics Cards

Networking Systems

Point-of-Load High-Current/High-Density

Telecom DC-DC Regulators

RAID Systems

Features

o4.75V to 5.5V or 5V to 28V Input

oDual-Output Synchronous Buck Controller

oConfigurable for Two Separate Outputs (25A) or

One Single Output (50A)

oAverage Current-Mode Control with Accurate

Adjustable Current Limit

o180° Interleaved Operation Reduces Size of Input

Filter Capacitors

oLimits Reverse Current Sinking When Operated in

Parallel Mode

oEach Output is Adjustable from 0.61V to 5.5V

oIndependently Programmable Adaptive Voltage

Positioning

oMonotonic Startup into Prebiased Outputs

oIndependent Shutdown for Each Output

o100kHz to 1MHz per Phase Programmable

Switching Frequency

oOscillator Frequency Synchronization from

200kHz to 2MHz

oDigital Soft-Start on Outputs

oHiccup-Mode Overcurrent Protection

oOvertemperature Shutdown

oThermally Enhanced 28-Pin TSSOP Package

Capable of Dissipating 2.1W

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-4218; Rev 0; 7/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX15034AAUI+ -40°C to +125°C 28 TSSOP

MAX15034BAUI+ -40°C to +125°C 28 TSSOP-EP*

Denotes a lead-free/RoHS-compliant package.

EP = Exposed pad.

EVALUATION KIT

AVAILABLE

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

IN, LX_ to AGND.....................................................-0.3V to +30V

BST_ to AGND........................................................-0.3V to +35V

DH_ to LX_ ....................................-0.3V to (VBST_ - VLX_) + 0.3V

DL_ to PGND..............................................-0.3V to (VDD + 0.3V)

BST_ to LX_ ..............................................................-0.3V to +6V

VDD to PGND............................................................-0.3V to +6V

AGND to PGND .....................................................-0.3V to +0.3V

AVGLIMIT, REG, RT/CLKIN, CSP_,

CSN_ to AGND ......................................................-0.3V to +6V

All Other Pins to AGND ............................-0.3V to (VREG + 0.3V)

REG Continuous Output Current

(limited by power dissipation, no thermal or short-circuit

protection).........................................................................67mA

Continuous Power Dissipation (TA= +70°C) (Note 1)

28-Pin TSSOP (derate 14mW/°C above +70°C) ..........1117mW

28-Pin TSSOP-EP (derate 27mW/°C above +70°C)........2162mW

Package Thermal Resistance (θJA) (Note 1)

MAX15034A ................................................................71.6°C/W

MAX15034B ...................................................................37°C/W

Package Thermal Resistance (θJC) (Note 1)

MAX15034A ...................................................................13°C/W

MAX15034B .....................................................................2°C/W

Operating Temperature Range .........................-40°C to +125°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

ELECTRICAL CHARACTERISTICS

(VIN = VREG = VDD = VEN_ = +5V, TA= TJ= TMIN to TMAX, unless otherwise noted, circuit of Figure 6. Typical values are at TA= +25°C.)

(Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SYSTEM SPECIFICATIONS

528

Input Voltage Range VIN IN and REG shorted together for +5V

operation 4.75 5.50 V

Quiescent Supply Current IIN fOSC = 500kHz, DH_ or DL_ = open 7 17 mA

STARTUP/INTERNAL REGULATOR OUTPUT (REG)

REG Undervoltage Lockout UVLO VREG rising 4.0 4.15 4.5 V

Hysteresis VHYST 200 mV

REG Output Accuracy VIN = 5.8V to 28V, ISOURCE = 0 to 65mA 4.75 5.10 5.30 V

REG Dropout VIN < 5.8V, ISOURCE = 60mA 0.5 V

INTERNAL REFERENCE

Internal Reference Voltage VEAN_

EAN_ connected to

EAOUT_

(Note 3)

TA = -40°C to +125°C 0.605 0.6125 0.620 V

Digital Ramp Period for Soft-Start 1024 Clock

cycles

Soft-Start Voltage Steps 64 Steps

MOSFET DRIVERS

p-Channel Output Driver

Impedance RON_P 1.35 3 Ω

n-Channel Output Driver

Impedance RON_N 0.45 1.35 Ω

Output Driver Source Current IDH_, IDL_ 2.5 A

Output Driver Sink Current IDH_, IDL_ 5A

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VIN = VREG = VDD = VEN_ = +5V, TA= TJ= TMIN to TMAX, unless otherwise noted, circuit of Figure 6. Typical values are at TA= +25°C.)

(Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CDH_ or CDL_ = 5nF -7.5 +7.5

Nonoverlap Time (Dead Time) tNO fSW = 1MHz nominal, RRT = 12.4kΩ-10 +10 %

RT/CLKIN Output Voltage VRT/CLKIN 1.225 V

RT/CLKIN Current Sourcing

Capability IRT/CLKIN 0.5 mA

RT/CLKIN Logic-High Threshold VRT/CLKIN_H 2.4 V

RT/CLKIN Logic-Low Threshold VRT/CLKIN_L 0.8 V

RT/CLKIN High Pulse Width tRT/CLKIN 30 ns

RT/CLKIN Synchronization

Frequency Range fRT/CLKIN 200 2000 kHz

CURRENT LIMIT

Internal Average Current-Limit

Threshold VCL_ VCSP_ - VCSN_ 20.4 22.5 24.75 mV

Reverse Average Current-Limit

Threshold VRCL_ VCSP_ - VCSN_ -3.0 -1.53 -0.1 mV

External Average Current-Limit

Threshold Adjustment VCL_ADJ Resistor-divider connected from REG

to AVGLIMIT to AGND

VAVGLIMIT -

0.6/36 V

AVGLIMIT Ground Threshold

Voltage VAVGLIMIT_GND 550 mV

Leakage Current at AVGLIMIT IAVGLIMIT VAVGLIMIT = 3V 100 nA

DIGITAL FAULT INTEGRATION (DF_)

Number of Switching Cycles to

Shutdown in Current Limit NSDF_ 32,768 Clock

cycles

Number of Switching Cycles to

Recover from Shutdown NRDF_ 524,288 Clock

cycles

CURRENT-SENSE AMPLIFIER

CSP_ to CSN_ Input Resistance RCS_ 3.8 kΩ

VIN = VREG = 4.75V to 5.5V or

VIN = 5V to 10V -0.3 +3.6 V

Common-Mode Range VCMR(CS)

VIN = 7V to 28V -0.3 +5.5 V

Input Offset Voltage VOS(CS) 100 μV

Amplifier Gain AV(CS) 36 V/V

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VIN = VREG = VDD = VEN_ = +5V, TA= TJ= TMIN to TMAX, unless otherwise noted, circuit of Figure 6. Typical values are at TA= +25°C.)

(Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

-3dB Bandwidth f-3dB 4 MHz

VCSP_ = 5.5V, sinking 120

CSP_ Input Bias Current ICSA(IN) VCSP_ = 0V, sourcing 30 μA

CURRENT-ERROR AMPLIFIER (CEA_)

Transconductance gm550 μS

Open-Loop Gain AVOL(CEA) No load 50 dB

VOLTAGE-ERROR AMPLIFIER (EAOUT_)

Open-Loop Gain AVOL(EA) 70 dB

Unity-Gain Bandwidth fUGEA 3 MHz

EAN_ Input Bias Current IBIAS(EA) VEAN_ = 2.0V 100 nA

Error-Amplifier Output Clamping

High Voltage VC LM P_H I (E A) With respect to VCM 1V

Error-Amplifier Output Clamping

Low Voltage VC LM P_LO

(

)

With respect to VCM -0.234 V

EN_ INPUTS

EN_ Input High Voltage VENH EN rising 1.2 1.222 1.245

EN_ Hysteresis 0.05 V

EN_ Input Leakage Current IEN -200 +200 nA

Startup Delay Time to OUT_ tSTART_DELAY From EN_ rising to VOUT_ rising 1 ms

MODE INPUT

MODE Logic-High Threshold VMODE_H 2.4 V

MODE Logic-Low Threshold VMODE_L 0.8 V

MODE Input Pulldown IPULLDWN 5μA

PREBIASED OUTPUT

Peak Sink Current-Limit

Threshold during Reference

Soft-Start

VCSP_ - VCSN_ -2.1 mV

Digital Ramp Period for

Stepping Peak Sink Current

Limit after Reference Soft-Start

448 Clock

cycles

THERMAL SHUTDOWN

Thermal Shutdown TSHDN 160

Thermal Shutdown Hysteresis THYST 10 °C

Note 2: The device is 100% production tested at TA= TJ= +125°C. Limits at TA= -40°C and TA= +25°C are guaranteed by design.

Note 3: The internal reference voltage accuracy is measured at the negative input of the error amplifiers (EAN_). Output voltage

accuracy must include external resistor-divider tolerances.

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

OSCILLATOR FREQUENCY vs. RT

MAX15034 toc01

RT (kΩ)

OSCILLATOR FREQUENCY (kHz)

900800700600500400300200100

100

1000

10,000

0 1000

CDH_ = CDL_ = 0

SUPPLY CURRENT

vs. TEMPERATURE AND FREQUENCY

(VIN = 5V)

MAX15034 toc02a

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

11095-25 -10 5 35 50 6520 80

-40 125

CDH_ = CDL_ = 0 fSW = 1MHz

fSW = 250kHz

fSW = 500kHz

fSW = 125kHz

SUPPLY CURRENT

vs. TEMPERATURE AND FREQUENCY

(VIN = 12V)

MAX15034 toc02b

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

11095-25 -10 535 50 6520 80

-40 125

CDH_ = CDL_ = 0 fSW = 1MHz

fSW = 250kHz

fSW = 500kHz

fSW = 125kHz

SUPPLY CURRENT

vs. TEMPERATURE AND FREQUENCY

(VIN = 24V)

MAX15034 toc02c

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

11095-25 -10 535 50 6520 80

-40 125

CDH_ = CDL_ = 0 fSW = 1MHz

fSW = 250kHz

fSW = 500kHz

fSW = 125kHz

SUPPLY CURRENT

vs. OSCILLATOR FREQUENCY

MAX15034 toc03

FREQUENCY (kHz)

SUPPLY CURRENT (mA)

18001600400 600 800 12001000 1400

200 2000

CDH_ = CDL_ = 0

VIN = 24V

VIN = 5V

VIN = 12V

SUPPLY CURRENT

vs. DRIVER LOAD CAPACITANCE

MAX15034 toc04

CLOAD (nF)

SUPPLY CURRENT (mA)

252015105

100

030

CLOAD = CDH_ = CDL_

REG LOAD REGULATION

MAX15034 toc05

IREG (mA)

VREG (V)

908070605040302010

4.95

5.00

5.05

5.10

4.90

0100

VIN = 12V

VIN = 24V

VIN = 5.5V

REG LINE REGULATION

MAX15034 toc06

VIN (V)

VREG (V)

2321191715131197

4.98

5.00

5.02

5.04

5.06

5.08

5.10

4.96

IREG = 0

IREG = 60mA

OUTPUT LOAD-TRANSIENT RESPONSE

MAX15034 toc07

2ms/div

10A/div

IOUT

VOUT

100mV/div

AC-COUPLED

20A

Typical Operating Characteristics

(Circuit of Figure 6, TA= +25°C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)

_______________________________________________________________________________________ 5

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

6 _______________________________________________________________________________________

DRIVER RISE TIME

vs. LOAD CAPACITANCE

MAX15034 toc08

CLOAD (nF)

tRISE (ns)

201814 164 6 8 10 122

100

022

DL_

DH_

DRIVER FALL TIME

vs. LOAD CAPACITANCE

MAX15034 toc09

CLOAD (nF)

tFALL (ns)

201814 164 6 8 10 122

022

DL_

DH_

HIGH-SIDE DRIVER RISE TIME

(VIN = 12V, CLOAD = 10nF)

MAX15034 toc10

DH_

2V/div

20ns/div

HIGH-SIDE DRIVER FALL TIME

(VIN = 12V, CLOAD = 10nF)

MAX15034 toc11

DH_

2V/div

20ns/div

LOW-SIDE DRIVER RISE TIME

(VIN = 12V, CLOAD = 10nF)

MAX15034 toc12

DL_

2V/div

20ns/div

LOW-SIDE DRIVER FALL TIME

(VIN = 12V, CLOAD = 10nF)

MAX15034 toc13

DL_

2V/div

20ns/div

Typical Operating Characteristics (continued)

(Circuit of Figure 6, TA= +25°C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

TURN-ON/TURN-OFF WAVEFORM

MAX15034 toc15

1ms/div

VOUT1

1V/div

EN1

5V/div

EN2

5V/div

VOUT2

1V/div

_______________________________________________________________________________________ 7

OUT1/OUT2 OUT-OF-PHASE WAVEFORMS

(VOUT1 = 0.8V, VOUT2 = 1.3V)

MAX15034 toc14

OUT1

100mV/div

10μs/div

OUT2

100mV/div

LX2

10V/div

LX1

10V/div

Typical Operating Characteristics (continued)

(Circuit of Figure 6, TA= +25°C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)

SHORT-CIRCUIT CURRENT WAVEFORMS

(VIN = 5V)

MAX15034 toc16

200ms/div

IOUT2

10A/div

IOUT1

10A/div

AVERAGE CURRENT LIMIT

vs. VAVGLIMIT

MAX15034 toc17

VAVGLIMIT (V)

AVERAGE CURRENT LIMIT (mV)

2.52.01.51.00.503.0

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX15034 toc18

TEMPERATURE (°C)

INTERNAL REFERENCE VOLTAGE (V)

1109580655035205-10-25

0.610

0.615

0.620

0.605

-40 125

SWITCHING FREQUENCY

vs. TEMPERATURE

MAX15034 toc19

TEMPERATURE (°C)

SWITCHING FREQUENCY (kHz)

475

500

525

550

450

1109580655035205-10-25-40 125

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(Circuit of Figure 6, TA= +25°C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)

SOFT-START WAVEFORM

MAX15034 toc22

400μs/div

EN2

5V/div

VOUT2

500mV/div

VEAN2

200mV/div

PREBIASED OUTPUT CONDITION

MAX15034 toc23

400μs/div

EN2

5V/div

VOUT2

500mV/div

DH2

5V/div

DL2

5V/div EAOUT2

1V/div

INTERNAL AVERAGE CURRENT LIMIT

vs. TEMPERATURE

MAX15034 toc20

TEMPERATURE (°C)

INTERNAL AVERAGE CURRENT LIMIT (mV)

1109580655035205-10-25-40 125

INTERNAL AVERAGE REVERSE

CURRENT LIMIT vs. TEMPERATURE

MAX15034 toc21

INTERNAL AVERAGE CURRENT LIMIT (mV)

-2.5

-2.0

-1.5

-1.0

-0.5

-3.0

TEMPERATURE (°C)

1109580655035205-10-25-40 125

PEAK PULLUP AND PULLDOWN CURRENT

OR DRIVER AT DH_ AND DL_

MAX15034 toc24

200ns/div

CLOAD = 10nF

DH_

500mV/div

DL_

500mV/div

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

_______________________________________________________________________________________ 9

Pin Description

PIN NAME FUNCTION

1 CSN2

Current-Sense Differential Amplifier Negative Input for Output 2. Connect CSN2 to the negative terminal of

the sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified by the current-

sense amplifier (AV(CS) = 36V/V).

2 CSP2

Current-Sense Differential Amplifier Positive Input for Output 2. Connect CSP2 to the positive terminal of the

sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified by the current-sense

amplifier (AV(CS) = 36V/V).

3 EAOUT2

Voltage Error-Amplifier Output 2. Connect to an external gain-setting feedback resistor. The error-amplifier

gain determines the output voltage load regulation for adaptive voltage positioning. This output also serves

as the compensation network connection from EAOUT2 to EAN2. A resistive network results in a drooped

output-voltage-regulation characteristic. An integrator configuration results in very tight output-voltage

regulation (see the Adaptive Voltage Positioning section).

4 EAN2

Voltage Error-Amplifier Inverting Input for Output 2. Connect a resistive divider from VOUT2 to EAN2 to

AGND to set the output voltage. A compensation network connects from EAOUT2 to EAN2. A resistive

network results in a drooped output-voltage-regulation characteristic. An integrator configuration results in

very tight output-voltage regulation (see the Adaptive Voltage Positioning section).

5 CLP2 Current-Error Amplifier Output 2. Compensate the current loop by connecting an R-C network from CLP2 to

AGND.

6 AVGLIMIT Average Current-Limit Programming. Connect a resistor-divider between REG, AVGLIMIT, and AGND to set

the average current-limit value (see the Programming Average the Current Limit section).

7 RT/CLKIN

External Clock Input or Internal Frequency-Setting Connection. Connect a resistor from RT/CLKIN to AGND

to set the switching frequency. Connect an external clock at RT/CLKIN for external frequency

synchronization.

8 AGND Analog Ground

9 MODE

Mode Function Input. MODE selects between a single-output dual phase or a dual-output buck regulator.

When MODE is grounded, VEA1 and VEA2 connect to CEA1 and CEA2, respectively (see Figure 1) and the

device operates as a two-output, out-of-phase buck regulator. When MODE is connected to REG (logic

high), VEA2 is disconnected and VEA1 is routed to both CEA1 and CEA2.

10 CLP1 Current-Error Amplifier Output 1. Compensate the current loop by connecting an R-C network from CLP1 to

AGND.

11 EAN1

Voltage Error-Amplifier Inverting Input for Output 1. Connect a resistive divider from VOUT1 to EAN1 to

regulate the output voltage. A compensation network connects from EAOUT1 to EAN1. A resistive network

results in a drooped output-voltage-regulation characteristic. An integrator configuration results in very tight

output-voltage regulation (see the Adaptive Voltage Positioning section).

12 EAOUT1

Voltage Error-Amplifier Output 1. Connect to an external gain-setting feedback resistor. The error-amplifier

gain determines the output-voltage-load regulation for adaptive voltage positioning. This output also serves

as the compensation network connection from EAOUT1 to EAN1. A resistive network results in a drooped

output-voltage-regulation characteristic. An integrator configuration results in very tight output-voltage

regulation (see the Adaptive Voltage Positioning section).

13 CSP1

Current-Sense Differential Amplifier Positive Input for Output 1. Connect CSP1 to the positive terminal of the

sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified by the current-sense

amplifier (AV(CS) = 36V/V).

14 CSN1

Current-Sense Differential Amplifier Negative Input for Output 1. Connect CSN1 to the negative terminal of

the sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified by the current-

sense amplifier (AV(CS) = 36V/V).

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

10 ______________________________________________________________________________________

Detailed Description

The MAX15034 switching power-supply controller can

be configured two ways. With the MODE input high, this

device operates as single-output, dual-phase, step-

down switching regulators where each output is 180°

out of phase. With MODE connected low, the

MAX15034 operates as a dual-output, step-down

switching regulator. The average current-mode control

topology of the MAX15034 offers high-noise immunity

while having benefits similar to those of peak current-

mode control. Average current-mode control has the

intrinsic ability to accurately limit the average current

sourced by the converter during a fault condition. When

a fault condition occurs, the error-amplifier output volt-

age (EAOUT1 or EAOUT2) that connects to the positive

input of the transconductance amplifier (CA1 or CA2) is

clamped, thus limiting the output current.

The MAX15034 has internal logic to ensure each output’s

monotonic startup under prebias load conditions. This

facilitates glitch-free output voltage power-up in the pres-

ence of another redundant/parallel voltage regulator.

The MAX15034 contains all blocks necessary for two

independently regulated average current-mode PWM

regulators. This device has two voltage error amplifiers

(VEA1 and VEA2), two current-error amplifiers (CEA1

and CEA2), two current-sensing amplifiers (CA1 and

CA2), two PWM comparators (CPWM1 and CPWM2),

and drivers for both low- and high-side power MOSFETs

(see Figure 1). Each PWM section is also equipped with

a pulse-by-pulse, current-limit protection and a fault

integration block for hiccup protection.

Pin Description (continued)

PIN NAME FUNCTION

15 EN1 Output 1 Enable. A logic-low shuts down channel 1’s MOSFET drivers. EN1 can be used for output

sequencing.

16 BST1 Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side MOSFET driver

supply. Connect a 0.47μF ceramic capacitor between BST1 and LX1.

17 DH1 High-Side Gate Driver Output 1. DH1 drives the gate of the high-side MOSFET.

18 LX1 External Inductor Connection and Source Connection for the High-Side MOSFET for Output 1. LX1 also

serves as the return terminal for the high-side MOSFET driver.

19 DL1 Low-Side Gate Driver Output 1. Gate driver output for the synchronous MOSFET.

20 VDD

Supply Voltage for Low-Side Drivers. REG powers VDD. Connect a parallel combination of 0.1μF and 1μF

ceramic capacitors from VDD to PGND and a 1Ω resistor from VDD to REG to filter out the high-peak

currents of the driver from the internal circuitry.

21 REG Internal 5V Regulator Output. REG is derived internally from IN and is used to power the internal bias

circuitry. Bypass REG to AGND with a 4.7μF ceramic capacitor.

22 IN Supply Voltage Connection. Connect IN to a 5V to 28V input supply.

23 PGND Power Ground. Source connection for the low-side MOSFET. Connect VDD’s bypass capacitor returns to

PGND.

24 DL2 Low-Side Gate Driver Output 2. Gate driver for the synchronous MOSFET.

25 LX2 External Inductor Connection and Source Connection for the High-Side MOSFET for Output 2. Also serves

as the return terminal for the high-side MOSFET driver.

26 DH2 High-Side Gate Driver Output 2. DH2 drives the gate of the high-side MOSFET.

27 BST2 Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side MOSFET driver

supply. Connect a 0.47μF ceramic capacitor between BST2 and LX2.

28 EN2 Output 2 Enable. A logic-low shuts down channel 2’s MOSFET drivers. EN2 can be used for output

sequencing.

— EP Exposed Pad. Connect exposed pad to ground plane (MAX15034BAUI only).

MAX15034

Two enable comparators (CEN1 and CEN2) are avail-

able to control and sequence the two PWM sections

through the enable (EN1 or EN2) inputs. An oscillator,

with an externally programmable frequency generates

two clock pulse trains and two ramps for both PWM

sections. The two clocks and the two ramps are 180°

out of phase with each other.

A linear regulator (REG) generates the 5V to supply the

device. This regulator has the output-current capability

necessary to provide for the MAX15034’s internal

circuitry and the power for the external MOSFET’s gate

drivers. Internal UVLO circuitry ensures that the

MAX15034 starts up when VREG is at the correct volt-

age levels to guarantee safe operation of the IC and of

the power MOSFETs.

Finally, a thermal-shutdown feature protects the device

during thermal faults and shuts down the MAX15034

when the die temperature exceeds +160°C.

BST1

DH1

LX1

DL1

BST2

DH2

LX2

DL2

PGND

VDD

2CSP2

1CSN2

13 CSP1

14 CSN1

CA1

EAN1

AVGLIMIT

AGND 8

EN1 15

EN2 28

CA2

CPWM1

CPWM2

7RT/CLKIN

CEA1

CEA2

12EAOUT1

MODE

EAOUT2

CLP2

CLP1

REG

1.225V

THERMAL

SHUTDOWN

VDD

MUX

EAN2

CEN1

VEA1

DF1 AND

HICCUP

LOGIC

EXTERNAL FREQUENCY SYNC

0°

CONTROL

AND DRIVER

LOGIC 1

CONTROL

AND DRIVER

LOGIC 2

DF2 AND

HICCUP

LOGIC

OSCILLATOR

AND PHASE

SPLITTER

180°

2VP-P

RAMP

VREG = 5V

FOR INTERNAL

BIASING

UVLO

VINTREF = 0.61V

VEA2

CEN2

2VP-P

RAMP

Figure 1. Block Diagram

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

______________________________________________________________________________________ 11

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

12 ______________________________________________________________________________________

Dual-Output/Dual-Phase Select (MODE)

The MAX15034 can operate as a dual-output, indepen-

dently regulated buck converter, or as a dual-phase,

single-output buck converter. The MODE input selects

between the two operating modes. When MODE is

grounded (logic-low), VEA1 and VEA2 connect to CEA1

and CEA2, respectively (see Figure 1), and the device

operates as a two-output DC-DC converter. When

MODE is connected to REG (logic-high), VEA2 is dis-

connected and VEA1 is routed to both CEA1 and CEA2

and the device works as a dual-phase, single-output

buck regulator with each output 180° out of phase with

respect to each other.

Supply Voltage Connections (VIN/VREG)

The MAX15034 accepts a wide input voltage range at

IN of 5V to 28V. An internal linear regulator steps down

VIN to 5.1V (typ) and provides power to the MAX15034.

The output of this regulator is available at REG. For VIN

= 4.75V to 5.5V, connect IN and REG together external-

ly. REG can supply up to 65mA for external loads.

Bypass REG to AGND with a 4.7μF ceramic capacitor

for high-frequency noise rejection and stable operation.

REG supplies the current for the MAX15034’s internal

circuitry and for the MOSFET gate drivers (when con-

nected externally to VDD), and can source up to 65mA.

Calculate the maximum bias current (IBIAS) for the

MAX15034:

where IIN is the quiescent supply current into IN (4mA,

typ), QGQ1, QGQ2, QGQ3, QGQ4 are the total gate

charges of MOSFETs Q1 through Q4 at VGS = 5V (see

Figure 6), and fSW is the switching frequency of each

individual phase.

Low-Side MOSFET Driver Supply (VDD)

VDD is the power input for the low-side MOSFET dri-

vers. Connect the regulator output REG externally to

VDD through an R-C lowpass filter. Use a 1Ωresistor

and a parallel combination of 1μF and 0.1μF ceramic

capacitors to filter out the high peak currents of the

MOSFET drivers from the sensitive internal circuitry.

High-Side MOSFET Drive Supply (BST_)

BST1 and BST2 supply the power for the high-side

MOSFET drivers for output 1 and output 2, respectively.

Connect BST1 and BST2 to VDD through rectifier

diodes D1 and D2 (see Figure 6). Connect a 0.1μF

ceramic capacitor between BST_ and LX_.

Minimize the trace inductance from BST_ and VDD to

the rectifier diodes, D1 and D2, and from BST_ and LX_

to the boost capacitors, C8 and C9 (see Figure 6). This

is accomplished by using short, wide trace lengths.

Undervoltage Lockout (UVLO)/

Power-On Reset (POR)/Soft-Start

The MAX15034 includes an undervoltage lockout

(UVLO) with hysteresis, and a power-on reset circuit for

converter turn-on and monotonic rise of the output volt-

age. The UVLO threshold monitors VREG and is inter-

nally set between 4.0V and 4.5V with 200mV of

hysteresis. Hysteresis eliminates chattering during

startup. Most of the internal circuitry, including the

oscillator, turns on when VREG reaches 4.5V. The

MAX15034 draws up to 4mA (typ) of current before

VREG reaches the UVLO threshold.

The compensation network at the current-error ampli-

fiers (CLP1 and CLP2) provides an inherent soft-start of

the output voltage. It includes (R14 and C10) in parallel

with C11 at CLP1 and (R15 and C12) in parallel with

C13 at CLP2 (see Figure 6). The voltage at the current-

error amplifier output limits the maximum current avail-

able to charge the output capacitors. The capacitor at

CLP_ in conjunction with the finite output-drive current

of the current-error amplifier yields a finite rise time for

the output current and thus, the output voltage.

Setting the Switching Frequency (fSW)

An internal oscillator generates the 180oout-of-phase

clock signals required for both PWM modulators. The

oscillator also generates the 2VP-P voltage ramps nec-

essary for the PWM comparators. The oscillator fre-

quency can be set from 200kHz to 2MHz by an external

resistor (RT) connected from RT/CLKIN to AGND (see

Figure 6). The equation below shows the relationship

between RTand the switching frequency:

where RRT is in ohms and the per-phase switching fre-

quency is fSW = fOSC/2.

Use RT/CLKIN as a clock input to synchronize the

MAX15034 to an external frequency (fRT/CLKIN).

Applying an external clock to RT/CLKIN allows each

PWM section to work at a frequency equal to

fRT/CLKIN/2. An internal comparator with a 1.6V thresh-

old detects fRT/CLKIN. If fRT/CLKIN is present, internal

logic switches from the internal oscillator clock, to the

clock present at RT/CLKIN.

RHz

OSC RT

=×25 10

IIfQQQQ

BIAS IN SW GQ GQ GQ GQ

=+× +++

()

1234

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

______________________________________________________________________________________ 13

Hiccup Fault Protection

The MAX15034 includes overload fault protection circuitry

that prevents damage to the power MOSFETs. The fault

protection consists of two digital fault integration blocks

that enable hiccuping under overcurrent conditions. This

circuit works as follows: for every clock cycle the current-

limit threshold is exceeded, the fault integration counter

increments by one count. Thus, if the current-limit condi-

tion persists, the counter reaches its shutdown threshold

in 32,768 counts and shuts down the external MOSFETs.

When the MAX15034 shuts down due to a fault, the

counter begins to count down (since the current-limit con-

dition has ended), once every 16 clock cycles. Thus, the

device counts down for 524,288 clock cycles. At this

point, switching resumes. This produces an effective duty

cycle of 6.25% power-up and 93.75% power-down under

fault conditions. With a switching frequency set to

250kHz, power-up and power-down times are approxi-

mately 131ms and 2.09s, respectively.

Control Loop

The MAX15034 uses an average current-mode control

topology to regulate the output voltage. The control

loop consists of an inner current loop and an outer volt-

age loop. The inner current loop controls the output

current, while the outer voltage loop controls the output

voltage. The inner current loop absorbs the inductor

pole, reducing the order of the outer voltage loop to

that of a single-pole system. Figure 2 is the block dia-

gram of OUT1’s control loop.

The current loop consists of a current-sense resistor,

RSENSE, a current-sense amplifier (CA1), a current-

error amplifier (CEA1), an oscillator providing the carri-

er ramp, and a PWM comparator (CPWM1). The

precision current-sense amplifier (CA1) amplifies the

sense voltage across RSENSE by a factor of 36. The

inverting input to CEA1 senses the output of CA1. The

output of CEA1 is the difference between the voltage-

error amplifier output (EAOUT1) and the gained-up volt-

age from CA1. The RC compensation network

connected to CLP1 provides external frequency com-

pensation for the respective CEA1 (see the

Compensation

section). The start of every clock cycle

enables the high-side driver and initiates a PWM on-

cycle. Comparator CPWM1 compares the output volt-

age from CEA1 against a 0 to 2V ramp from the

oscillator. The PWM on-cycle terminates when the ramp

voltage exceeds the error voltage from the current-error

amplifier (CEA1).

DRIVE

VIN

VOUT1

COUT

VREF = 0.61V

CCFF

CCF

RCF

CSN1 CSP1

CLP1

2VP-P

RSENSE

LOAD

CA 1

CEA1

CPWM1

VEA1

Figure 2. Current and Voltage Loops

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

14 ______________________________________________________________________________________

The outer voltage control loop consists of the voltage-

error amplifier (VEA1). The noninverting input (EAN1) is

externally connected to the midpoint of a resistive volt-

age-divider from OUT1 to EAN1 to AGND. The voltage

loop gain is set by using an external resistor from the

output of this amplifier (EAOUT1) to its inverting input

(EAN1). The noninverting input of (VEA1) is connected

to the 0.61V internal reference.

Current-Error Amplifier

The MAX15034 features two dedicated transconduc-

tance current-error amplifiers CEA1 and CEA2 with a

typical gmof 550μS and 320μA output sink and source

capability. The current-error amplifier outputs (CLP1 and

CLP2) serve as the inverting input to the PWM compara-

tors. CLP1 and CLP2 are externally accessible to pro-

vide frequency compensation for the inner current loops

(see CCFF, CCF, and RCF in Figure 2). Compensate the

current-error amplifier so that the inductor current down

slope, which becomes the up slope at the inverting

input of the PWM comparator, is less than the slope of

the internally generated voltage ramp (see the

Compensation

section).

PWM Comparator and R-S Flip-Flop

The PWM comparator (CPWM1 or CPWM2) sets the

duty cycle for each cycle by comparing the current-

error amplifier output to a 2VP-P ramp. At the start of

each clock cycle an R-S flip-flop resets and the high-

side drivers (DH1 and DH2) turn on. The comparator

sets the flip-flop as soon as the ramp voltage exceeds

the current-error amplifier output voltage, thus terminat-

ing the on-cycle.

Voltage-Error Amplifier

The voltage-error amplifier (VEA_) sets the gain of the

voltage control loop. Its output clamps to 1.14V and

-0.234V relative to VCM = 0.61V. Set the MAX15034 out-

put voltage by connecting a voltage-divider from the

output to EAN_ to GND (see Figure 4). At no load, the

output of the voltage error amplifier is zero.

Use the equation below to calculate the no load voltage:

The voltage at full load is given by:

where ΔVOUT is the voltage-positioning window

described in the

Adaptive Voltage Positioning

section.

Adaptive Voltage Positioning

Powering new-generation ICs requires new techniques

to reduce cost, size, and power dissipation. Voltage

positioning (Figure 5) reduces the total number of out-

put capacitors to meet a given transient response

requirement. Setting the no-load output voltage slightly

higher than the output voltage during nominally loaded

conditions allows a larger downward voltage excursion

when the output current suddenly increases.

Regulating at a lower output voltage under a heavy

load allows a larger upward-voltage excursion when

the output current suddenly decreases. A larger

allowed voltage-step excursion reduces the required

number of output capacitors and/or allows the use of

higher ESR capacitors.

The MAX15034 internal 0.6125V reference provides a

tolerance of ±1.25%. Using 0.1% resistors for R1 and

R2 allows a 4% variation from the nominal output volt-

age. This available voltage range allows the reduction

of the total number of output capacitors to meet a given

transient response requirement resulting in a voltage-

positioning window as shown in Figure 5.

From the allowable voltage-positioning window calcu-

late the value of RFfrom the equation below.

where ΔVOUT is the allowable voltage-positioning win-

dow, RSENSE is the sense resistor, 36 is the current-

sense amplifier gain, and R1is as shown in Figure 4.

RIR R

FOUT SENSE

OUT

=×××36 1

OUT FL OUT() .=×+

⎛

⎝

⎜

⎞

⎠

⎟−0 6125 1 1

OUT NL() .=×+

⎛

⎝

⎜

⎞

⎠

⎟

0 6125 1 1

MAX15034

MOSFET Gate Drivers (DH_, DL_)

The high-side drivers (DH1 and DH2) and low-side dri-

vers (DL1 and DL2) drive the gates of external n-channel

MOSFETs. The high-peak sink and source current capa-

bility of these drivers provides ample drive for the fast

rise and fall times of the switching MOSFETs. Faster rise

and fall times result in reduced switching losses. For low-

output, voltage-regulating applications where the duty

cycle is less than 50%, choose high-side MOSFETs (Q2

and Q4, Figure 6) with a moderate RDS(ON) and a very

low gate charge. Choose low-side MOSFETs (Q1 and

Q3, Figure 6) with very low RDS(ON) and moderate gate

charge. The driver block also includes a logic circuit that

provides an adaptive nonoverlap time (30ns typ) to pre-

vent shoot-through currents during transition. Figure 7

shows the dual-phase, single-output buck regulator.

2 x fSW (V/S)

RAMP

CLK

CSP_

CSN_

GMIN

EN_

1.225V

CLP_

VDD

BST_

DH_

LX_

DL_

PGND

AV = 36V/V

PWM

COMPARATOR

gm = 500μS

Figure 3. Current Comparator and MOSFET Driver Logic

LOAD

COUT

VOUT

VREF = 0.61V

EAN_

EAOUT_

Figure 4. Voltage Error Amplifier

LOAD (A)

VCNTR

NO LOAD 1/2 LOAD FULL LOAD

VOLTAGE-POSITIONING WINDOW

VCNTR + ΔVOUT/2

VCNTR - ΔVOUT/2

Figure 5. Defining the Voltage-Positioning Window

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

______________________________________________________________________________________ 15

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

16 ______________________________________________________________________________________

24.9kΩ

29.4kΩ

VREG

4.64kΩ

1.74kΩ

680μF

0.8V/10A

2mΩ

0.5μH

IRF7832

IRF7821

0.1μF

(100mA, 30V)

1μF

IRF7821

(100mA, 30V)

0.1μF

4.7μF

1Ω

10μF

VIN

1.3V/10A

0.1μF

IRF7832

0.8μHR2

2mΩ

R14

1kΩ

C10

15nF

C11

120pF

R15

1kΩ

C12

15nF

C13

120pF

AGND

AVGLIMIT

VREG

RT/CLKIN

EN2

PGND

EN1

EAOUT1

EAN1

CSP1

CSN1

DL1

LX1

DH1

BST1

VDD

IN REG

BST2

DH2

LX2

DL2

PGND

CSP2

CSN2

EAN2

EAOUT2

MODE

CLP1

CLP2

MAX15034

680μF

60.4kΩ

4.75kΩ

5.11kΩ

EXTERNAL FREQUENCY SYNC

22Ω

R16

100kΩ

R17

100kΩ

C14

0.1μF

C15

0.1μF

R19

10kΩ

R18

19.6kΩ

Figure 6. Dual-Output Buck Regulator

MAX15034

24.9kΩ

60.4kΩ

4.75kΩ

5.11kΩ

680μF

1.3V/20A

2mΩ

0.8μH

IRF7832

IRF7821

0.1μF

(100mA, 30V)

1μF

IRF7821

(100mA, 30V)

0.1μF

4.7μF

1Ω

10μF

VIN

0.1μF

IRF7832

0.8μHR2

2mΩ

R14

1kΩ

C10

15nF

C11

120pF

R15

1kΩ

C12

15nF

C13

120pF

AGND

AVGLIMIT

RT/CLKIN

EN2

EN1

EAOUT1

EAN1

CSP1

CSN1

DL1

LX1

DH1

BST1

VDD

IN REG

BST2

DH2

LX2

DL2

PGND

CSP2

CSN2

EAN2

EAOUT2

MODE

CLP1

CLP2

MAX15034

EXTERNAL FREQUENCY SYNC

22Ω

TO REG

VREG R16

100kΩ

R17

100kΩ

C14

0.1μF

C15

0.1μF

PGND

Figure 7. Dual-Phase, Single-Output Buck Regulator

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

______________________________________________________________________________________ 17

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

18 ______________________________________________________________________________________

Design Procedures

Inductor Selection

The switching frequency per phase, peak-to-peak ripple

current in each phase, and allowable voltage ripple at

the output, determine the inductance value. Selecting

higher switching frequencies reduces the inductance

requirement, but at the cost of lower efficiency due to

the charge/discharge cycle of the gate and drain

capacitances in the switching MOSFETs. The situation

worsens at higher input voltages, since capacitive

switching losses are proportional to the square of the

input voltage. Lower switching frequencies on the other

hand increase the peak-to-peak inductor ripple current

(ΔIL), and therefore, increase the MOSFET conduction

losses (see the

Power MOSFET Selection

section for a

detailed description of MOSFET power loss).

When using higher inductor ripple current, the ripple can-

cellation in the multiphase topology, reduces the input

and output capacitor RMS ripple current. Use the follow-

ing equation to determine the minimum inductance value:

Choose ΔILto be equal to approximately 30% of the out-

put current per channel. Since ΔILaffects the output-rip-

ple voltage, the inductance value may need minor

adjustment after choosing the output capacitors for full-

rated efficiency. Choose inductors from the standard

high-current, surface-mount inductor series available

from various manufacturers. Particular applications may

require custom-made inductors. Use high-frequency core

material for custom inductors. High ΔILcauses large

peak-to-peak flux excursion increasing the core losses at

higher frequencies. The high-frequency operation cou-

pled with high ΔIL, reduces the required minimum induc-

tance and even makes the use of planar inductors

possible. The advantages of using planar magnetics

include low-profile design, excellent current sharing

between phases due to the tight control of parasitics, and

low cost. For example, the minimum inductance at VIN =

12V, VOUT = 0.8V, ΔIL= 3A, and fSW = 500kHz is 0.5μH.

The average current-mode control feature of the

MAX15034 limits the maximum inductor current, which

prevents the inductor from saturating. Choose an

inductor with a saturating current greater than the

worst-case peak inductor current:

where 24.75mV is the maximum average current-limit

threshold for the current-sense amplifier and RSENSE is

the sense resistor.

Power MOSFET Selection

When choosing the MOSFETs, consider the total gate

charge, RDS(ON), power dissipation, the maximum

drain-to-source voltage, and package thermal imped-

ance. The product of the MOSFET gate charge and on-

resistance is a figure of merit, with a lower number

signifying better performance. Choose MOSFETs opti-

mized for high-frequency switching applications. The

average gate-drive current from the MAX15034’s output

is proportional to the total capacitance it drives at DH1,

DH2, DL1, and DL2. The power dissipated in the

MAX15034 is proportional to the input voltage and the

average drive current. See the

Supply Voltage

Connections (V

REG

)

and the

Low-Side MOSFET

Drives Supply (V

)

sections to determine the maxi-

mum total gate charge allowed from all driver outputs

together.

The losses may be broken into four categories: conduc-

tion loss, gate drive loss, switching loss, and output loss.

The following simplified power loss equation is true for

both MOSFETs in the synchronous buck-converter:

For the low-side MOSFET, the PSWITCH term becomes

virtually zero because the body diode of the MOSFET is

conducting before the MOSFET is turned on.

Tables 1 and 2 describe the different losses and shows

an approximation of the losses during that period.

Input Capacitance

The discontinuous input-current waveform of the buck

converter causes large ripple currents in the input

capacitor. The switching frequency, peak inductor cur-

rent, and the allowable peak-to-peak voltage ripple

reflected back to the source, dictate the capacitance

requirement. Increasing the number of phases increas-

es the effective switching frequency and lowers the

peak-to-average current ratio, yielding lower input

capacitance requirement. It can be shown that the

worst-case RMS current occurs when only one con-

troller section is operating. The controller section with

the highest output power needs to be used in determin-

ing the maximum input RMS ripple current requirement.

Increasing the output current drawn from the other out-

of-phase controller section results in reducing the input

PP P

LOSS CONDUCTION GATEDRIVE

SWITCH OUTP

UUT

L PEAK SENSE

=×+

−

24 75 10

3Δ

LVV V

Vf I

OUT IN MAX OUT

IN SW L

=−

××

()

MAX15034

ripple current. A low-ESR input capacitor that can han-

dle the maximum input RMS ripple current of one chan-

nel must be used. The maximum RMS capacitor ripple

current is given by:

where IMAX is the full load current of the regulator. VOUT

is the output voltage of the same regulator and CIN is C5

in Figure 6. The ESR of the input capacitors wastes

power from the input and heats up the capacitor.

Reducing the ESR is important to maintain a high overall

efficiency and in reducing the heating of the capacitors.

Output Capacitors

The worst-case peak-to-peak inductor ripple current,

the allowable peak-to-peak output ripple voltage, and

the maximum deviation of the output voltage during

step loads determine the capacitance and the ESR

requirements for the output capacitors. The output rip-

ple can be approximated as the inductor current ripple

multiplied by the output capacitor’s ESR (RESR_OUT).

The peak-to-peak inductor current ripple is given by:

During a load step, the allowable deviation of the output

voltage during the fast transient load dictates the output

capacitance and ESR. The output capacitors supply the

load step until the controller responds with a greater duty

cycle. The response time (tRESPONSE) depends on the

closed-loop bandwidth of the regulator. The resistive

drop across the capacitor’s ESR and capacitor discharge

causes a voltage drop during a load step. Use a combi-

nation of SP polymer and ceramic capacitors for better

transient load and ripple/noise performance.

ΔIVD

LOUT

=−

()1

VVV

CIN RMS MAX OUT IN OUT

()

≈−

LOSS DESCRIPTION SEGMENT LOSS

Conduction Loss

Losses associated with MOSFET on-time and

on-resistance. IRMS is a function of load current

and duty cycle.

Gate Drive Loss

Losses associated with charging and

discharging the gate capacitance of the

MOSFET every cycle. Use the MOSFET’s (QG)

specification.

Switching Loss

Losses during the drain voltage and drain

current transitions for every switching cycle.

Losses occur only during the QGS2 and QGD

time period and not during the initial QGS1

period. The initial QGS1 period is the rise in the

gate voltage from zero to VTH. RDH_ is the high-

side MOSFET driver’s on-resistance and RGATE

is the internal gate resistance of the high-side

MOSFET (QGD and QGS2 are found in the

MOSFET data sheet).

Output Loss

Losses associated with QOSS of the MOSFET

occur every cycle when the high-side MOSFET

turns on. The losses are caused by both

MOSFETs, but are dissipated in the high-side

MOSFET.

Table 1. High-Side MOSFET Losses

PIR

where I V

CONDUCTION RMS DS ON

RMS OUT

=×

≈×

2()

IILOAD

PVQQf

GATEDRIVE DD G GD SW

=×

()

×−

PVI

SWITCH IN LOA

=× DDSW GS GD

GATE

fQQ

×× +()

GATE DD

where I V

=×(_

2++ RGATE )

=+××PQQVf

OUTPUT

OSS HS OSS LS

IN SW

() ()

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

______________________________________________________________________________________ 19

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

20 ______________________________________________________________________________________

Keep the maximum output-voltage deviation less than

or equal to the adaptive voltage-positioning window

(ΔVOUT). During a load step, assume a 50% contribu-

tion each from the output capacitance discharge and

the voltage drop across the ESR (ΔVOUT = ΔVESR_OUT

+ ΔVQ_OUT). Use the following equations to calculate

the required ESR and capacitance value:

where ILOAD_STEP is the step in load current and

tRESPONSE is the response time of the controller.

Controller response time depends on the control-loop

bandwidth. COUT is C6 and C7 in Figure 6.

Current Limit

The MAX15034 incorporates two forward current-limit

protection mechanisms, average current limit and hic-

cup fault current limit, which accurately limit the output

current per phase. The average current-mode control

technique of the MAX15034 accurately limits the maxi-

mum average output current per phase. The

MAX15034 senses the voltage across either a sense

resistor or can implement lossless inductor sense,

sensing the voltage across the parasitic resistance of

the inductor (DCR). Use either mechanism to limit the

maximum inductor current.

The minimum average voltage, at which the voltage

across the current-sense resistor is clamped, is either

internally set to 20.4mV or is controlled by the voltage

at AVGLIMIT. The AVGLIMIT ground threshold of

550mV (typ) is the threshold above which the control of

the average current-limit voltage is transferred from the

internal 20.4mV (min) reference to the externally set

VAVGLIMIT. For using the internal average current-limit

value, short AVGLIMIT to AGND. The minimum (inter-

nally set) average current limit is set at:

For example, the current-sense resistor:

for a maximum output current limit of 10A. A standard

value is 2mΩ. Also, adjust the value of the current-

sense resistor to compensate for parasitics associated

with the PCB. Select a noninductive resistor with an

appropriate wattage rating.

The implementation is shown in Figure 8.

When sensing directly across the inductor, connect an

RC circuit directly across the shunt or inductor (see

Figure 9).

RmV

SENSE ==

20 4

10 204

..Ω

ImV

LIMIT MIN SENSE

()

=20 4

CIt

ESR OUT ESR OUT

LOAD STEP

OUT LOAD STEP RESPONSE

Q OUT

=×

LOSS DESCRIPTION SEGMENT LOSSES

Conduction Loss Losses associated with MOSFET on-time, IRMS

is a function of load current and duty cycle.

Gate Drive Loss

Losses associated with charging and

discharging the gate of the MOSFET every

cycle. There is no QGD charging involved in this

MOSFET due to the zero-voltage turn-on. The

charge involved is (QG - QGD).

Table 2. Low-Side MOSFET Losses

PIR

where I VV

CONDUCTION RMS DS ON

RMS IN OUT

IN LOAD

=×

≈−×

2()

PVQQf

GATEDRIVE DD G GD SW

=×

()

×−

Note: The gate drive losses are distributed between the drivers and the MOSFETs in the ratio of the gate driver’s resistance and the

MOSFET’s internal gate resistance.

MAX15034

Set the RC time constant to be 1.1 to 1.2 times the

inductor time constant (L/DCR). Select C1 to be in the

0.1μF to 0.47μF range, and then calculate R1 from:

In some applications, it may be useful to add a resistor

(R2 in Figure 9) in series with the CSN_ connection to

minimize input offset error. Set R2 equal to R1. It may

also prove useful to add capacitor C3 (Figure 9) in

parallel with R2 to aid in short-circuit recovery. Set C3

equal to C1. Finally, it may be helpful to add a 100pF

(C2) capacitor immediately across the CSP_ and CSN_

inputs to minimize high-frequency noise pick-up at the

IC in some applications.

For current-sense resistors that have a noticeable

inductance component, use lossless inductor sense

implementation (and design procedure). See Figure 10.

Table 3 highlights the tradeoffs of each current-sense

method.

Rk LH

DCR m C F

112

[] .[]

[] []

ΩΩ

=×

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

______________________________________________________________________________________ 21

LOUT RSENSE

VOUT

LX_

CSP_

MAX15034

CSN_

Figure 8. Noninductive Resistive Sense

INDUCTOR

DCR

VOUT

LX_

CSP_

MAX15034

CSN_

C2*

R1 C1

C3*

*OPTIONAL.

R2*

Figure 9. Lossless Inductor Sense

Table 3. Current-Sense Configurations

METHOD CURRENT-SENSE

ACCURACY

INDUCTOR-SATURATION

PROTECTION

CURRENT-SENSE POWER

LOSS (EFFICIENCY)

Output Current-Sense Resistor High Allowed (highest accuracy) RSENSE x IOUT2

Equivalent Inductor DC Resistance Low Allowed No additional loss

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

22 ______________________________________________________________________________________

The MAX15034 provides precision average current-limit

programmability while using standard sense resistors

or shunts. Use the equation below to determine the

appropriate VAVGLIMIT external reference voltage at

AVGLIMIT:

For example, assuming the desired average current

limit is 18A, and RSENSE = 2mΩ.

where RSENSE is determined from maximum load cur-

rent, wattage rating, and circuit parasitics (see above)

and ILOAD(MAX) from circuit requirements. VAVGLIMIT is

the average current-limit reference voltage selected for

a desired ILOAD(MAX) and is set by a resistive voltage-

divider from REG to AGND. See the

Programming the

Average Current Limit

section.

The second current-protection circuit is the hiccup fault

protection as explained in the

Hiccup Fault Protection

section. The average current during a short at the out-

put is given by:

Programming the Average Current Limit

The MAX15034 average current-limit reference voltage

is set by connecting a resistor-divider network from

REG to AGND, the center node is connected to

AVGLIMIT. The resistive divider’s upper resistor, R1, is

connected between REG and the AVGLIMIT. The resis-

tive divider’s lower resistor, R2, is connected between

the AVGLIMIT and AGND.

The resistor-divider values are determined by first,

choosing R2. To minimize reference noise select R2

such that (R1 + R2) < 100kΩ; a typical value is 10kΩ.

Next, determine R1 from:

From the example above, assuming VAVGLIMIT = 1.91V:

A standard value for R1 is 16.2kΩ. Connect AVGLIMIT

to AGND for default current limit

20 4..

RSENSE

⎛

⎝

⎜

⎞

⎠

⎟

Rk V

Vk110 5

191 11618=× −

⎛

⎝

⎜⎞

⎠

⎟=ΩΩ

RR V

REG

AVGLIMIT

AVGLIMT

12 1

10 5

=× −

⎛

⎝

⎜

⎞

⎠

⎟

=×Ω

(()

[]

MAX V−

⎛

⎝

⎜

⎞

⎠

⎟

AVG SHORT LOAD MAX() ()

.=×0 0625

VmAmV

mV V

AVGLIMIT =××

()

2 36 18 612 5

1910 1 91

Ω.

VRmIA

AVGLIMIT SENSE LOAD MAX

=× ×

()

+56 [ ] [ ]

()

Ω6612 5.m

ESL

SENSE RESISTOR (INDUCTIVE)

RSENSE

VOUT

LX_

CSP_

MAX15034

CSN_

R1 C1

LOUT

Figure 10. Inductive Sense Resistor

MAX15034

Reverse Current Limit

The MAX15034 limits the reverse current when the out-

put capacitor voltage is higher than the preset output

voltage. Calculate the maximum reverse current limit

based on VCLMP_LO and the current-sense resistor

RSENSE.

Output-Voltage Setting

The output voltage is set by the combination of resistors

R1, R2, and RFas described in the

Voltage-Error

Amplifier

section. First select a value for resistor R2. Then

calculate the value of R1 from the following equation:

where VOUT(NL) is the voltage at no load. Then find the

value of RFfrom the following equation:

where ΔVOUT is the allowable drop in voltage from no

load to full load. RFis R8 and R9, R1 is R4 and R6, R2

is R5 and R7 in Figure 6.

Compensation

The MAX15034 uses an average current-mode control

scheme to regulate the output voltage (see Figure 2).

The main control loop consists of an inner current loop

and an outer voltage loop. The voltage error amplifier

(VEA1 and VEA2) provides the controlling voltage for

the current loop in each phase. The output inductor is

hidden inside the inner current loop. This simplifies the

design of the outer voltage control loop and also

improves the power-supply dynamics. The objective of

the inner current loop is to control the average inductor

current. The gain-bandwidth characteristic of the cur-

rent loop can be tailored for optimum performance by

the compensation network at the output of the current-

error amplifier (CEA1 or CEA2). Compared with peak

current-mode control, the current-loop gain crossover

frequency, fC, can be made approximately the same,

but the gain at low frequencies is much higher. This

results in the following advantages over peak current-

mode control.

1) The average current tracks the programmed cur-

rent with a high degree of accuracy.

2) Slope compensation is not required, but there is a

limit to the loop gain at the switching frequency to

achieve stability.

3) Noise immunity is excellent.

4) The average current-mode method can be used to

sense and control the current in any circuit branch.

For stability of the current loop, the amplified inductor-

current downslope at the negative input of the PWM

comparator (CPWM1 and CPWM2) must not exceed

the ramp slope at the comparator’s positive input. This

puts an upper limit on the current-error amplifier gain at

the switching frequency. The inductor current downs-

lope is given by VOUT/L where L is the value of the

inductor (L1 and L2 in Figure 6) and VOUT is the output

voltage. The amplified inductor current downslope at

the negative input of the PWM comparator is given by:

where RSENSE is the current-sense resistor (R1 and R2

in Figure 6) and gMx RCF is the gain of the current-error

amplifier (CEA_) at the switching frequency. The slope

of the ramp at the positive input of the PWM comparator

is 2V x fSW. Use the following equation to calculate the

maximum value of RCF (R14 or R15 in Figure 6).

The highest crossover frequency fCMAX is given by:

or alternatively:

Equation (1) can now be rewritten as:

RfL

VR g

CF C

IN S m

=××

×××

92()

ffV

SW CMAX OUT

=××2π

ffV

CMAX SW IN

OUT

=×

×2π

RfL

VR g

CF SW

OUT SENSE m

≤××

×××

36 1()

LRgR

LOUT SENSE m C

=× ×××36

RIR R

FOUT SENSE

OUT

=×××36 1

RVR

OUT NL

10 6125

0 6125 2

(.)

()

=−×

REVERSE SENSE

=×−

155 10 3

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

______________________________________________________________________________________ 23

MAX15034

In practical applications, pick the crossover frequency

(fC) in the range of:

First calculate RCF in equation 2 above. Calculate CCF

so that:

where CCF is C10 and C12 in Figure 6.

Calculate CCFF so that:

where CCFF is C11 and C13 in Figure 6.

Applications Information

Independent Turn-On and Turn-Off

The MAX15034 can be used to regulate two outputs

from one controller. Each of the two outputs can be

turned on and off independently of one another by con-

trolling the enable input of each phase (EN1 and EN2).

A logic-low on each enable pin shuts down the

MOSFET drivers for that phase. When the voltage on the

enable pin exceeds 1.2V, the drivers are turned on and

the output can come up to regulation. This method of

turning on the outputs allows the MAX15034 to be used

for power sequencing.

PCB Layout Guidelines

Careful PCB layout is critical to achieve low losses, low

output noise, and clean and stable operation. This is

especially true for dual-phase converters where one

channel can affect the other. Use the following guide-

lines for PCB layout:

1) Place the VDD, REG, and the BST1 and BST2 bypass

capacitors close to the MAX15034.

2) Minimize all high-current switching loops.

3) Keep the power traces and load connections short.

This practice is essential for high efficiency. Use

thick copper PCBs (2oz or higher) to enhance effi-

ciency and minimize trace inductance and resis-

tance.

4) Run the current-sense lines CSP_ and CSN_ very

close to each other to minimize loop areas. Do not

cross these critical signal lines through power cir-

cuitry. Sense the current right at the pads of the

current-sense resistors.

5) Place the bank of output capacitors close to the

load.

6) Isolate the power components on the top side from

the analog components on the bottom side with a

ground plane in between.

7) Provide enough copper area around the switching

MOSFETs, inductors, and sense resistors to aid in

thermal dissipation and reducing resistance.

8) Distribute the power components evenly across the

top side for proper heat dissipation.

9) Keep AGND and PGND isolated and connect them

at one single point close to the IC. Do not connect

them together anywhere else.

10) Place all input bypass capacitors for each input as

close to each other as is practical.

CfR

CFF CCF

=×× × ×

210π

CfR

CF CCF

=×× ×

2π

fff

SW CSW

10 2

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

24 ______________________________________________________________________________________

MAX15034

Configurable, Single-/Dual-Output, Synchronous

Buck Controller for High-Current Applications

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________

Package Information

For the latest package outline information, go to

www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

28 TSSOP U28-2 21-0066

28 TSSOP-EP U28E-4 21-0108

EN2

BST2

DH2

LX2

DL2

PGND

EN1

REG

VDD

DL1

LX1

DH1

BST1

CSN1

CSP1

EAOUT1

EAN1

CLP1

MODE

AGND

RT/CLKIN

AVGLIMIT

CLP2

EAN2

EAOUT2

CSP2

CSN2

TSSOP

TOP VIEW

MAX15034

*EXPOSED PAD

*CONNECT EXPOSED PAD TO GROUND PLANE.

MAX15034A DOES NOT HAVE AN EXPOSED PAD.

Pin Configuration Chip Information

PROCESS: BiCMOS