EN5322QI 2 A Voltage Mode Synchronous Buck PWM DC-DC Converter Evaluation Board DESCRIPTION FEATURES The EN5322 evaluation board is configured to provide a 1.2 V output at up to 2 A from a 2.4 V to 5.5 V input. The output can be set to 7 different voltages through the three VID output voltage select pins. * Input Voltage Range: 2.4 V - 5.5 V * 7 Output Voltage Options via VID Pins * Adjustable Output Voltage via External Resistor Divider * 2 A Load Current Guaranteed * Fully Assembled and Tested If using the external divider option, VOUT can be adjusted from 0.6 V up to VIN - VDROPOUT, where VDROPOUT = ILOAD * RDROPOUT. Applications * The 4 MHz operation allows for the use of tiny MLCC capacitors. It also enables a very wide control loop bandwidth providing excellent transient performance and reduced output impedance. The internal compensation is designed for unconditional stability for all operating conditions. The Power OK signal is available. * * * * Point of Load Regulation for Low Power Processors, Network Processors, DSPs' FPGAs and ASICs Replacement of LDOs Noise Sensitive Applications such as A/V and RF Computing, Computer Peripherals, Storage, Networking, and Instrumentation DSL, STB, DVR, DTV, and iPC EVALUATION BOARD BILL OF MATERIALS Ref Des Qty C2 C3 C11 U1 R41 1 1 1 1 1 Description Ceramic Capacitor, 10 uF, 10 V, X7R, 0805 Ceramic Capacitor, 47 uF, 6.3 V, X5R, 1206 Ceramic Capacitor, 1 uF, 6.3 V, X7R, 0603 2 A PWM Converter Resistor, 100 kOHM, 5%, 1/8 W, 0805 Manufacturer P/N Murata: GRM21BR71A106KE51L Murata: GRM31CR60J476ME19L Panasonic: ECJ1VB0J105K Enpirion: EN5322QI-T Digikey: 311-100KACT-ND C82 1 Electrolytic Capacitor, 150 uF, 10 V Panasonic: EEVFK1A151P 2 C10 1 Ceramic Capacitor, 10 uF, 10 V, X7R, 0805 Murata: GRM21BR71A106KE51L D12 1 TVS Unidirect, 600 W, 6.5 V Littlefuse: SMBJ6.5A FB12 1 Multilayer Ferrite Bead, 4000MA, 0805 Wurth: 742792012 2 J1 1 Connector, Custom, Vertical Header Samtec: ASP12192002 TP5-TP92 5 Connector, Test Point Keystone: 5016 C1, C4, C5, C6, C9, C12 Not Used R1, R2 Not Used TP1-TP2 Not Used Note 1: R4 is not required if POK is not used. Note 2: These components are only for demonstration purposes, and are not needed for circuit design. (c)Enpirion 2008 all rights reserved, E&OE 1 www.enpirion.com February 2008 EN5322QI EVALUATION BOARD CIRCUIT VS2 17 18 19 D1 SMBJ6V5A VS1 J1 + 13 14 15 C8 150u VS0 ENABLE 5 6 7 Vin 9 10 11 POK 1 2 3 Input Protection ASP12192002 PGND FB1 Vin PGND C10 10 uF 1 2 TP1 N/U VIN TP8 1 C1 N/U 0805 Vin R4 100 k C2 10 uF 0805 0603 C12 0805 POK C11 1 uF 17 POK 19 18 ENABLE VIN VIN 20 21 NC21 47 uF C4 0805 N/U C5 0805 N/U C6 0805 N/U 14 13 VS0 VS2 10 9 PGND PGND VOUT C3 1206 TP3 15 PGND 0805 R2 N/U TP2 C9 N/U 0805 2 1 1 8 5 TP7 VSENSE 7 VOUT 1 NC4 TP10 Vout VFB 1 0805 PGND 4 AGND EN5322Q U1 16 12 3 VOUT 22 PGND TP9 AVIN VS1 2 PGND NC22 NC1 11 1 NC23 1 VOUT TP6 PGND 6 1 NC24 TP5 23 24 1 R1 N/U Figure 1. Customer Evaluation Board Schematic (c)Enpirion 2008 all rights reserved, E&OE 2 www.enpirion.com February 2008 EN5322QI PRINTED CIRCUIT BOARD LAYOUT Figure 2: Component Placement Figure 3: Top Layer Layout Figure 4: Bottom Layer Layout Figure 5: Drills (c)Enpirion 2008 all rights reserved, E&OE 3 www.enpirion.com February 2008 EN5322QI QUICK START GUIDE 1. Preset power supply to 2.4 V VIN 5.5 V. 2. Turn power supply off. 3. Place jumper ENABLE at the left position to pull the pin high and enable the EN5322. Placing jumper ENABLE at the right position will pull the pin low and disable the EN5322. 4. Place jumper POK at the left position to connect pull up resistor R4 to VIN. Leave the jumper open if the POK function is not used. 5. Place jumpers VS0, VS1, and VS2 according to Table 1 (R: right position; L: left position) to set the desired output voltage. Table 1: VID Code Setting VS2 VS1 VS0 Output Voltage R R R R L L L L R R L L R R L L R L R L R L R L 3.3V 2.5V 1.8V 1.5V 1.25V 1.2V 0.8V External Divider The output voltage can also be set with an external resistor divider when VS2, VS1 and VS0 are pulled high (left position). Use a 340 k, 1 % or better resistor for R1. Then the value of the bottom resistor R2 is given as: R2 = 6. 7. 8. 9. 204 k VOUT - 0.6 where VOUT is the output voltage. For example, if the desired output voltage is 1 V, R2 should be a 511 k, 1% or better resistor. Connect input power supply terminals to +VIN (TP8) and GND (TP5). Connect load terminals to +VOUT (TP7) and GND (TP6). Turn on the power supply after making connections. The EN5322 will be enabled. The POK output can be observed at TP9. To observe noise-sensitive waveforms on input / output ripple and NC(SW), use the measurement technique as shown in Figure 6. Wrap bus wire around the GND portion of the bare probe and bring it close to the probe tip. Then solder the bus wire to the nearest GND on the board. (c)Enpirion 2008 all rights reserved, E&OE 4 Figure 6: Balanced Impedance Scope Probe for Noise Measurements www.enpirion.com February 2008 EN5322QI Contact Information Enpirion, Inc. 685 Route 202/206 Suite 305 Bridgewater, NJ 08807 Phone: 908-575-7550 Fax: 908-575-0775 Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from Enpirion.. (c)Enpirion 2008 all rights reserved, E&OE 5 www.enpirion.com