CAT28C64BL-12 - ON SEMICONDUCTOR

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

SHARC Processor

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G

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SUMMARY

High performance signal processor for communications,

graphics and imaging applications

Super Harvard Architecture

4 independent buses for dual data fetch, instruction fetch,

and nonintrusive I/O

32-bit IEEE floating-point computation units—multiplier,

ALU, and shifter

Dual-ported on-chip SRAM and integrated I/O peripherals—a

complete system-on-a-chip

Integrated multiprocessing features

240-lead thermally enhanced MQFP_PQ4 package, 225-ball

plastic ball grid array (PBGA), 240-lead hermetic CQFP

package

RoHS compliant packages

KEY FEATURES—PROCESSOR CORE

40 MIPS, 25 ns instruction rate, single-cycle instruction

execution

120 MFLOPS peak, 80 MFLOPS sustained performance

Dual data address generators with modulo and bit-reverse

addressing)

Efficient program sequencing with zero-overhead looping:

Single-cycle loop setup

IEEE JTAG Standard 1149.1 Test Access Port and on-chip

emulation

32-bit single-precision and 40-bit extended-precision IEEE

floating-point data formats or 32-bit fixed-point data

format

Figure 1. Functional Block Diagram

MULT BARREL SERIAL PORTS

(2)

LINK PORTS

(6)

IOP

REGISTERS

(MEMORY

MAPPED)

CONTROL,

STATUS AND

DATA BUFFERS

I/O PROCESSOR

TIMER INSTRUCTION

CACHE

ADDR DATA DATA ADDR

ADDR DATA ADDR

TWO INDEPENDENT

DUAL-PORTED BLOCKS

PROCESSOR PORT I/O PORT

DUAL-PORTED SRAM

JTAG

TEST AND

EMULATION

HOST PORT

ADDR BUS

MUX

IOA

IOD

MULTIPROCESSOR

INTERFACE

EXTERNAL

PORT

DATA BUS

MUX

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

BUS

CONNECT

(PX)

DAG1

40/32

CORE PROCESSOR

PROGRAM

SEQUENCER

BLOCK 0

BLOCK 1

8  4  32

DAG2

8  4  24

32  48-BIT

PM ADDRESS BUS

DATA

CONTROLLER

DMA

DATA

FILE

16  40-BIT ALU

SHIFTER

Rev. G | Page 2 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

PARALLEL COMPUTATIONS

Single-cycle multiply and ALU operations in parallel with

dual memory read/writes and instruction fetch

Multiply with add and subtract for accelerated FFT butterfly

computation

UP TO 4M BIT ON-CHIP SRAM

Dual-ported for independent access by core processor and

DMA

OFF-CHIP MEMORY INTERFACING

4 gigawords addressable

Programmable wait state generation, page-mode DRAM

support

DMA CONTROLLER

10 DMA channels for transfers between ADSP-2106x internal

memory and external memory, external peripherals, host

processor, serial ports, or link ports

Background DMA transfers at up to 40 MHz, in parallel with

full-speed processor execution

HOST PROCESSOR INTERFACE TO 16- AND 32-BIT

MICROPROCESSORS

Host can directly read/write ADSP-2106x internal memory

and IOP registers

MULTIPROCESSING

Glueless connection for scalable DSP multiprocessing

architecture

Distributed on-chip bus arbitration for parallel bus connect

of up to six ADSP-2106xs plus host

Six link ports for point-to-point connectivity and array

multiprocessing

240 MBps transfer rate over parallel bus

240 MBps transfer rate over link ports

SERIAL PORTS

Two 40 Mbps synchronous serial ports with companding

hardware

Independent transmit and receive functions

Table 1. ADSP-2106x SHARC Processor Family Features

Feature ADSP-21060 ADSP-21062 ADSP-21060L ADSP-21062L ADSP-21060C ADSP-21060LC

SRAM 4M bits 2M bits 4M bits 2M bits 4M bits 4M bits

Operating

Voltage 5 V 5 V 3.3 V 3.3 V 5 V 3.3 V

Instruction

Rate

33 MHz

40 MHz

33 MHz

40 MHz

33 MHz

40 MHz

33 MHz

40 MHz

33 MHz

40 MHz

33 MHz

40 MHz

Package

MQFP_PQ4

PBGA

MQFP_PQ4

PBGA

MQFP_PQ4

PBGA

MQFP_PQ4

PBGA CQFP CQFP

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 3 of 64 | August 2010

CONTENTS

Summary ............................................................... 1

Revision History ...................................................... 3

General Description ................................................. 4

SHARC Family Core Architecture ............................ 4

Memory and I/O Interface Features ........................... 5

Development Tools ............................................... 8

Evaluation Kit ...................................................... 9

Designing an Emulator-Compatible DSP Board

(Target) ........................................................... 9

Additional Information .......................................... 9

Related Signal Chains ............................................ 9

Pin Function Descriptions ........................................ 10

Target Board Connector for EZ-ICE Probe ................ 13

ADSP-21060/ADSP-21062 Specifications ..................... 15

Operating Conditions (5 V) .................................... 15

Electrical Characteristics (5 V) ................................ 15

Internal Power Dissipation (5 V) ............................. 16

External Power Dissipation (5 V) ............................ 17

ADSP-21060L/ADSP-21062L Specifications ................. 18

Operating Conditions (3.3 V) ................................. 18

Electrical Characteristics (3.3 V) ............................. 18

Internal Power Dissipation (3.3 V) .......................... 19

External Power Dissipation (3.3 V) .......................... 20

Absolute Maximum Ratings ................................... 20

ESD Caution ...................................................... 21

Package Marking Information ................................ 21

Timing Specifications ........................................... 21

Test Conditions .................................................. 48

Environmental Conditions .................................... 51

225-Ball PBGA Ball Configuration .............................. 52

240-Lead MQFP_PQ4/CQFP Pin Configuration ............ 54

Outline Dimensions ................................................ 56

Surface-Mount Design .......................................... 61

Ordering Guide ..................................................... 62

REVISION HISTORY

8/10—Rev. F to Rev. G

Added new section, Related Signal Chains.......................9

Revised Table 14 ..................................................... 25

Revised Table 15 ..................................................... 26

Revised Table 28 ..................................................... 43

Clarification of Table 41 Title ..................................... 54

Clarification of Table 42 Title ..................................... 55

Changes to Ordering Guide ....................................... 62

Rev. G | Page 4 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

GENERAL DESCRIPTION

The ADSP-2106x SHARC

—Super Harvard Architecture Com-

puter—is a 32-bit signal processing microcomputer that offers

high levels of DSP performance. The ADSP-2106x builds on the

ADSP-21000 DSP core to form a complete system-on-a-chip,

adding a dual-ported on-chip SRAM and integrated I/O periph-

erals supported by a dedicated I/O bus.

Fabricated in a high speed, low power CMOS process, the

ADSP-2106x has a 25 ns instruction cycle time and operates at

40 MIPS. With its on-chip instruction cache, the processor can

execute every instruction in a single cycle. Table 2 shows perfor-

mance benchmarks for the ADSP-2106x.

The ADSP-2106x SHARC represents a new standard of integra-

tion for signal computers, combining a high performance

floating-point DSP core with integrated, on-chip system fea-

tures including up to 4M bit SRAM memory (see Table 1), a

host processor interface, DMA controller, serial ports and link

port, and parallel bus connectivity for glueless DSP

multiprocessing.

The ADSP-2106x continues SHARC’s industry-leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features.

The block diagram on Page 1 illustrates the following architec-

tural features:

• Computation units (ALU, multiplier and shifter) with a

shared data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

•Interval timer

•On-chip SRAM

• External port for interfacing to off-chip memory and

peripherals

• Host port and multiprocessor Interface

• DMA controller

• Serial ports and link ports

• JTAG Test Access Port

SHARC FAMILY CORE ARCHITECTURE

The ADSP-2106x includes the following architectural features

of the ADSP-21000 family core. The ADSP-2106x processors

are code- and function-compatible with the ADSP-21020.

Independent, Parallel Computation Units

The arithmetic/logic unit (ALU), multiplier and shifter all per-

form single-cycle instructions. The three units are arranged in

parallel, maximizing computational throughput. Single multi-

function instructions execute parallel ALU and multiplier oper-

ations. These computation units support IEEE 32-bit single-

precision floating-point, extended precision 40-bit floating-

point, and 32-bit fixed-point data formats.

Data Register File

A general–purpose data register file is used for transferring data

between the computation units and the data buses, and for stor-

ing intermediate results. This 10-port, 32-register (16 primary,

16 secondary) register file, combined with the ADSP-21000

Harvard architecture, allows unconstrained data flow between

computation units and internal memory.

Table 2. Benchmarks (at 40 MHz)

Benchmark Algorithm Speed Cycles

1024 Point Complex FFT (Radix 4, with

reversal)

0.46 μs 18,221

FIR Filter (per tap) 25 ns 1

IIR Filter (per biquad) 100 ns 4

Divide (y/x) 150 ns 6

Inverse Square Root 225 ns 9

DMA Transfer Rate 240 Mbytes/s

Figure 2. ADSP-2106x System Sample Configuration

RESET JTAG

ADSP-2106x

BMS

13CLOCK

LINK

DEVICES

(6 MAX)

(OPTIONAL)

CS BOOT

EPROM

(OPTIONAL)

MEMORY-

MAPPED

DEVICES

(OPTIONAL)

DATA

DMA DEVICE

(OPTIONAL)

DATA

ADDR

DATA

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

PAGE

ADRCLK

ACK

BR1–6

DMAR1–2

CLKIN

IRQ2–0

LxCLK

TCLK0

RPBA

EBOOT

LBOOT

FLAG3–0

TIMEXP

LxACK

LxDAT3–0

DR0

DT0

RSF0

TFS0

RCLK0

TCLK1

DR1

DT1

RSF1

TFS1

RCLK1

ID2–0

SERIAL

DEVICE

(OPTIONAL)

SERIAL

DEVICE

(OPTIONAL)

REDY

HBG

HBR

DMAG1–2

SBTS

MS3–0

DATA47–0

DATA

ADDR

ACK

ADDR31–0

DATA

CONTROL

ADDRESS

ADDR

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 5 of 64 | August 2010

Single-Cycle Fetch of Instruction and Two Operands

The ADSP-2106x features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 1 on Page 1). With its separate program and data

memory buses and on-chip instruction cache, the processor can

simultaneously fetch two operands and an instruction (from the

cache), all in a single cycle.

Instruction Cache

The ADSP-2106x includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and two

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

allows full-speed execution of core, looped operations such as

digital filter multiply-accumulates and FFT butterfly processing.

Data Address Generators with Hardware Circular Buffers

The ADSP-2106x’s two data address generators (DAGs) imple-

ment circular data buffers in hardware. Circular buffers allow

efficient programming of delay lines and other data structures

required in digital signal processing, and are commonly used in

digital filters and Fourier transforms. The two DAGs of the

ADSP-2106x contain sufficient registers to allow the creation of

up to 32 circular buffers (16 primary register sets, 16 secondary).

The DAGs automatically handle address pointer wraparound,

reducing overhead, increasing performance and simplifying

implementation. Circular buffers can start and end at any mem-

ory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of

parallel operations, for concise programming. For example, the

ADSP-2106x can conditionally execute a multiply, an add, a

subtract and a branch, all in a single instruction.

MEMORY AND I/O INTERFACE FEATURES

The ADSP-2106x processors add the following architectural

features to the SHARC family core.

Dual-Ported On-Chip Memory

The ADSP-21062/ADSP-21062L contains two megabits of on-

chip SRAM, and the ADSP-21060/ADSP-21060L contains

4M bits of on-chip SRAM. The internal memory is organized as

two equal sized blocks of 1M bit each for the ADSP-21062/

ADSP-21062L and two equal sized blocks of 2M bits each for

the ADSP-21060/ADSP-21060L. Each can be configured for dif-

ferent combinations of code and data storage. Each memory

block is dual-ported for single-cycle, independent accesses by

the core processor and I/O processor or DMA controller. The

dual-ported memory and separate on-chip buses allow two data

transfers from the core and one from I/O, all in a single cycle.

On the ADSP-21062/ADSP-21062L, the memory can be config-

ured as a maximum of 64k words of 32-bit data, 128k words of

16-bit data, 40k words of 48-bit instructions (or 40-bit data), or

combinations of different word sizes up to two megabits. All of

the memory can be accessed as 16-bit, 32-bit, or 48-bit words.

On the ADSP-21060/ADSP-21060L, the memory can be config-

ured as a maximum of 128k words of 32-bit data, 256k words of

16-bit data, 80k words of 48-bit instructions (or 40-bit data), or

combinations of different word sizes up to four megabits. All of

the memory can be accessed as 16-bit, 32-bit or 48-bit words.

A 16-bit floating-point storage format is supported, which effec-

tively doubles the amount of data that can be stored on-chip.

Conversion between the 32-bit floating-point and 16-bit float-

ing-point formats is done in a single instruction.

While each memory block can store combinations of code and

data, accesses are most efficient when one block stores data,

using the DM bus for transfers, and the other block stores

instructions and data, using the PM bus for transfers. Using the

DM bus and PM bus in this way, with one dedicated to each

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache. Single-cycle execution is also maintained when one of the

data operands is transferred to or from off-chip, via the

ADSP-2106x’s external port.

On-Chip Memory and Peripherals Interface

The ADSP-2106x’s external port provides the processor’s inter-

face to off-chip memory and peripherals. The 4-gigaword off-

chip address space is included in the ADSP-2106x’s unified

address space. The separate on-chip buses—for PM addresses,

PM data, DM addresses, DM data, I/O addresses, and I/O

data—are multiplexed at the external port to create an external

system bus with a single 32-bit address bus and a single 48-bit

(or 32-bit) data bus.

Addressing of external memory devices is facilitated by on-chip

decoding of high-order address lines to generate memory bank

select signals. Separate control lines are also generated for sim-

plified addressing of page-mode DRAM. The ADSP-2106x

provides programmable memory wait states and external mem-

ory acknowledge controls to allow interfacing to DRAM and

peripherals with variable access, hold and disable time

requirements.

Host Processor Interface

The ADSP-2106x’s host interface allows easy connection to

standard microprocessor buses, both 16-bit and 32-bit, with lit-

tle additional hardware required. Asynchronous transfers at

speeds up to the full clock rate of the processor are supported.

The host interface is accessed through the ADSP-2106x’s exter-

nal port and is memory-mapped into the unified address space.

Four channels of DMA are available for the host interface; code

and data transfers are accomplished with low software

overhead.

The host processor requests the ADSP-2106x’s external bus with

the host bus request (HBR), host bus grant (HBG), and ready

(REDY) signals. The host can directly read and write the inter-

nal memory of the ADSP-2106x, and can access the DMA

channel setup and mailbox registers. Vector interrupt support is

provided for efficient execution of host commands.

Rev. G | Page 6 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Figure 3. Shared Memory Multiprocessing System

ADDR31–0

CPA

BMS

CONTROL

ADSP-2106x #1

CONTROL

ADSP-2106x #2

ADDR31–0

CONTROL

ADSP-2106x #3

ID2–0

RESET

RPBA

CLKIN

ID2–0

RESET

RPBA

ID2–0

RESET

RPBA

CLKIN

ADSP-2106x #6

ADSP-2106x #5

ADSP-2106x #4

CLOCK

RESET

ADDR

DATA

HOSTPROCESSOR

INTERFACE (OPTIONAL)

ACK

GLOBAL MEMORY

AND

PERIPHERAL (OPTIONAL)

ADDR

DATA

ADDR

DATA

BOOT EPROM (OPTIONAL)

RDx

MS3–0

SBTS

ACK

ADDR31–0

CLKIN

001

PAGE

010

011

BR1

BR2–6

REDY

HBG

HBR

WRx

CONTROL

ADDRESS

DATA

CONTROL

ADDRESS

DATA

DATA47–0

BR1–2, BR4–6

BR3

DATA47–0

BR1, BR3–6

BR2

DATA47–0

BUS

PRIORITY

CPA

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 7 of 64 | August 2010

DMA Controller

The ADSP-2106x’s on-chip DMA controller allows zero-over-

head data transfers without processor intervention. The DMA

controller operates independently and invisibly to the processor

core, allowing DMA operations to occur while the core is simul-

taneously executing its program instructions.

DMA transfers can occur between the ADSP-2106x’s internal

memory and external memory, external peripherals, or a host

processor. DMA transfers can also occur between the ADSP-

2106x’s internal memory and its serial ports or link ports. DMA

transfers between external memory and external peripheral

devices are another option. External bus packing to 16-,

32-, or 48-bit words is performed during DMA transfers.

Ten channels of DMA are available on the ADSP-2106x—two

via the link ports, four via the serial ports, and four via the

processor’s external port (for either host processor, other

ADSP-2106xs, memory, or I/O transfers). Four additional link

port DMA channels are shared with Serial Port 1 and the exter-

nal port. Programs can be downloaded to the ADSP-2106x

using DMA transfers. Asynchronous off-chip peripherals can

control two DMA channels using DMA request/grant lines

(DMAR1–2, DMAG1–2). Other DMA features include inter-

rupt generation upon completion of DMA transfers and DMA

chaining for automatic linked DMA transfers.

Multiprocessing

The ADSP-2106x offers powerful features tailored to multipro-

cessor DSP systems. The unified address space (see Figure 4)

allows direct interprocessor accesses of each ADSP-2106x’s

internal memory. Distributed bus arbitration logic is included

on-chip for simple, glueless connection of systems containing

up to six ADSP-2106xs and a host processor. Master processor

changeover incurs only one cycle of overhead. Bus arbitration is

selectable as either fixed or rotating priority. Bus lock allows

indivisible read-modify-write sequences for semaphores. A vec-

tor interrupt is provided for interprocessor commands. Maxi-

mum throughput for interprocessor data transfer is

240M bytes/s over the link ports or external port. Broadcast

writes allow simultaneous transmission of data to all

ADSP-2106xs and can be used to implement reflective

semaphores.

Figure 4. Memory Map

0x0004 0000

0x0010 0000

0x00080000

0x00180000

0x0012 0000

0x00280000

0x0038 0000

0x0000 0000

0x0002 0000

0x0040 0000

BANK 1

MS0

BANK 2

MS1

BANK 3

MS2

MS3

IOP REGISTERS

SHORT WORD ADDRESSING

(16-BIT DATA WORDS)

NORMAL WORD ADDRESSING

(32-BIT DATA WORDS

48-BIT INSTRUCTION WORDS)

ADDRESS

BANK 0

SDRAM

(OPTIONAL)

0x0FFF FFFF

NONBANKED

NOTE: BANK SIZESARE SELECTED BY

MSIZE BITSIN THE SYSCON REGISTER

0x0030 0000

INTERNAL

MEMORY

SPACE

MULTIPROCESSOR

MEMORY

SPACE

ADDRESS

INTERNAL MEMORY SPACE

WITH ID = 001

0x003F FFFF

EXTERNAL

MEMORY

SPACE

INTERNAL MEMORY SPACE

WITH ID = 010

INTERNAL MEMORY SPACE

WITH ID = 011

INTERNAL MEMORY SPACE

WITH ID = 100

INTERNAL MEMORY SPACE

WITH ID = 101

INTERNAL MEMORY SPACE

WITH ID = 110

BROADCASTWRITE

TO ALL ADSP-21061s

Rev. G | Page 8 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Link Ports

The ADSP-2106x features six 4-bit link ports that provide addi-

tional I/O capabilities. The link ports can be clocked twice per

cycle, allowing each to transfer eight bits of data per cycle. Link-

port I/O is especially useful for point-to-point interprocessor

communication in multiprocessing systems.

The link ports can operate independently and simultaneously,

with a maximum data throughput of 240M bytes/s. Link port

data is packed into 32- or 48-bit words, and can be directly read

by the core processor or DMA-transferred to on-chip memory.

Each link port has its own double-buffered input and output

registers. Clock/acknowledge handshaking controls link port

transfers. Transfers are programmable as either transmit or

receive.

Program Booting

The internal memory of the ADSP-2106x can be booted at sys-

tem power-up from an 8-bit EPROM, a host processor, or

through one of the link ports. Selection of the boot source is

controlled by the BMS (boot memory select), EBOOT (EPROM

Boot), and LBOOT (link/host boot) pins. 32-bit and 16-bit host

processors can be used for booting. The processor also sup-

ports a no-boot mode in which instruction execution is sourced

from the external memory.

DEVELOPMENT TOOLS

The ADSP-2106x is supported by a complete set of

CROSSCORE

†

software development tools, including Analog

Devices emulators and VisualDSP++

‡

development environ-

ment. The same emulator hardware that supports other SHARC

processors also fully emulates the ADSP-2106x.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The ADSP-2106x

SHARC DSP has architectural features that improve the effi-

ciency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and

stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the ADSP-2106x

development tools, including the color syntax highlighting in

the VisualDSP++ editor. This capability permits:

• Control in how the development tools process inputs and

generate outputs

• Maintenance of a one-to-one correspondence with the

tools’ command line switches

The VisualDSP++ kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state, when debugging an application that uses the VDK.

Use the expert linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the DSP or external memory with a drag of

the mouse, and examine run-time stack and heap usage. The

†

CROSSCORE is a registered trademark of Analog Devices, Inc.

‡

VisualDSP++ is a registered trademark of Analog Devices, Inc.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 9 of 64 | August 2010

expert linker is fully compatible with existing linker definition

file (LDF), allowing the developer to move between the graphi-

cal and textual environments.

In addition to the software development tools available from

Analog Devices, third parties provide a wide range of tools sup-

porting the SHARC processor family. Third party software tools

include DSP libraries, real-time operating systems, and block

diagram design tools.

EVALUATION KIT

Analog Devices offers a range of EZ-KIT Lite

†

evaluation plat-

forms to use as a cost-effective method to learn more about

developing or prototyping applications with Analog Devices

processors, platforms, and software tools. Each EZ-KIT Lite

includes an evaluation board along with an evaluation suite of

the VisualDSP++ development and debugging environment

with the C/C++ compiler, assembler, and linker. Also included

are sample application programs, power supply, and a USB

cable. All evaluation versions of the software tools are limited

for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the

board to the USB port of the user’s PC, enabling the

VisualDSP++ evaluation suite to emulate the on-board proces-

sor in-circuit. This permits the customer to download, execute,

and debug programs for the EZ-KIT Lite system. It also allows

in-circuit programming of the on-board flash device to store

user-specific boot code, enabling the board to run as a stand-

alone unit, without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),

engineers can develop software for the EZ-KIT Lite or any cus-

tom-defined system. Connecting an Analog Devices JTAG

emulator to the EZ-KIT Lite board enables high speed, nonin-

trusive emulation.

DESIGNING AN EMULATOR-COMPATIBLE DSP

BOARD (TARGET)

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG test

access port (TAP) on each JTAG DSP. Nonintrusive in-circuit

emulation is assured by the use of the processor’s JTAG inter-

face—the emulator does not affect target system loading or tim-

ing. The emulator uses the TAP to access the internal features of

the DSP, allowing the developer to load code, set breakpoints,

observe variables, observe memory, and examine registers. The

DSP must be halted to send data and commands, but once an

operation has been completed by the emulator, the DSP system

is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-2106x

architecture and functionality. For detailed information on the

ADSP-21000 family core architecture and instruction set, refer

to the ADSP-2106x SHARC User’s Manual, Revision 2.1.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

The Application Signal Chains page in the Circuits from the

Lab

site (http://www.analog.com/signalchains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

†

EZ-KIT Lite is a registered trademark of Analog Devices, Inc.

Rev. G | Page 10 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

PIN FUNCTION DESCRIPTIONS

The ADSP-2106x pin definitions are listed below. Inputs identi-

fied as synchronous (S) must meet timing requirements with

respect to CLKIN (or with respect to TCK for TMS, TDI).

Inputs identified as asynchronous (A) can be asserted asynchro-

nously to CLKIN (or to TCK for TRST).

Unused inputs should be tied or pulled to VDD or GND, except

for ADDR31–0, DATA47–0, FLAG3–0, and inputs that have

internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,

TCLKx, RCLKx, LxDAT3–0, LxCLK, LxACK, TMS, and

TDI)—these pins can be left floating. These pins have a

logic-level hold circuit that prevents the input from floating

internally.

Table 3. Pin Descriptions

Pin Type Function

ADDR31–0 I/O/T External Bus Address. The ADSP-2106x outputs addresses for external memory and peripherals on these

pins. In a multiprocessor system, the bus master outputs addresses for read/write of the internal memory

or IOP registers of other ADSP-2106xs. The ADSP-2106x inputs addresses when a host processor or multi-

processing bus master is reading or writing its internal memory or IOP registers.

DATA47–0 I/O/T External Bus Data. The ADSP-2106x inputs and outputs data and instructions on these pins. 32-bit single-

precision floating-point data and 32-bit fixed-point data is transferred over bits 47–16 of the bus. 40-bit

extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit short word data is

transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over bits 23–16. Pull-up

resistors on unused DATA pins are not necessary.

MS3–0 O/T Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of external

memory. Memory bank size must be defined in the ADSP-2106x’s system control register (SYSCON). The

MS3–0 lines are decoded memory address lines that change at the same time as the other address lines.

When no external memory access is occurring, the MS3–0 lines are inactive; they are active however when

a conditional memory access instruction is executed, whether or not the condition is true. MS0 can be used

with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a multiprocessing system the MS3–0

lines are output by the bus master.

RD I/O/T Memory Read Strobe. This pin is asserted (low) when the ADSP-2106x reads from external memory devices

or from the internal memory of other ADSP-2106xs. External devices (including other ADSP-2106xs) must

assert RD to read from the ADSP-2106x’s internal memory. In a multiprocessing system, RD is output by the

bus master and is input by all other ADSP-2106xs.

WR I/O/T Memory Write Strobe. This pin is asserted (low) when the ADSP-2106x writes to external memory devices

or to the internal memory of other ADSP-2106xs. External devices must assert WR to write to the ADSP-

2106x’s internal memory. In a multiprocessing system, WR is output by the bus master and is input by all

other ADSP-2106xs.

PAGE O/T DRAM Page Boundary. The ADSP-2106x asserts this pin to signal that an external DRAM page boundary

has been crossed. DRAM page size must be defined in the ADSP-2106x’s memory control register (WAIT).

DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for Bank

0 accesses. In a multiprocessing system, PAGE is output by the bus master

ADRCLK O/T Clock Output Reference. In a multiprocessing system, ADRCLK is output by the bus master.

SW I/O/T Synchronous Write Select. Thi s si gnal is us ed t o interface the ADSP-2106x to synchronous memory devices

(including other ADSP-2106xs). The ADSP-2106x asserts SW (low) to provide an early indication of an

impending write cycle, which can be aborted if WR is not later asserted (e.g., in a conditional write

instruction). In a multiprocessing system, SW is output by the bus master and is input by all other

ADSP-2106xs to determine if the multiprocessor memory access is a read or write. SW is asserted at the same

time as the address output. A host processor using synchronous writes must assert this pin when writing to

the ADSP-2106x(s).

A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,

T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 11 of 64 | August 2010

ACK I/O/S Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory

access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an

external memory access. The ADSP-2106x deasserts ACK as an output to add waitstates to a synchronous

access of its internal memory. In a multiprocessing system, a slave ADSP-2106x deasserts the bus master’s

ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its

ACK pin that maintains the input at the level to which it was last driven.

SBTS I/S Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address, data,

selects, and strobes in a high impedance state for the following cycle. If the ADSP-2106x attempts to access

external memory while SBTS is asserted, the processor will halt and the memory access will not be completed

until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-2106x deadlock,

or used with a DRAM controller.

IRQ2–0 I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.

FLAG3–0 I/O/A Flag Pins. Each is configured via control bits as either an input or output. As an input, they can be tested as

a condition. As an output, they can be used to signal external peripherals.

TIMEXP O Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero.

HBR I/A Host Bus Request. This pin must be asserted by a host processor to request control of the ADSP-2106x’s

external bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus master will

relinquish the bus and assert HBG. To relinquish the bus, the ADSP-2106x places the address, data, select

and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x bus requests BR6–1 in a

multiprocessing system.

HBG I/O Host Bus Grant. Acknowledges a bus request, indicating that the host processor may take control of the

external bus. HBG is asserted (held low) by the ADSP-2106x until HBR is released. In a multiprocessing system,

HBG is output by the ADSP-2106x bus master and is monitored by all others.

CS I/A Chip Select. Asserted by host processor to select the ADSP-2106x.

REDY O (O/D) Host Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchronous access

of its internal memory or IOP registers by a host. This pin is an open-drain output (O/D) by default; it can be

programmed in the ADREDY bit of the SYSCON register to be active drive (A/D). REDY will only be output if

the CS and HBR inputs are asserted.

DMAR2–1 I/A DMA Request 1 (DMA Channel 7) and DMA Request 2 (DMA Channel 8).

DMAG2–1 O/T DMA Grant 1 (DMA Channel 7) and DMA Grant 2 (DMA Channel 8).

BR6–1 I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-2106xs to arbitrate for bus master-ship. An

ADSP-2106x only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all

others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pins should be pulled

high; the processor’s own BRx line must not be pulled high or low because it is an output.

ID2–0 O (O/D) Multiprocessing ID. Determines which multiprocessing bus request (BR1– BR6) is used by ADSP-2106x.

ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor systems. These

lines are a system configuration selection that should be hardwired or changed at reset only.

RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus

arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration

selection that must be set to the same value on every ADSP-2106x. If the value of RPBA is changed during

system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.

CPA I/O (O/D) Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-2106x bus slave to interrupt

background DMA transfers and gain access to the external bus. CPA is an open drain output that is connected

to all ADSP-2106xs in the system. The CPA pin has an internal 5 kΩ pull-up resistor. If core access priority is

not required in a system, the CPA pin should be left unconnected.

DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.

DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.

TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.

RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.

Table 3. Pin Descriptions (Continued)

Pin Type Function

A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,

T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)

Rev. G | Page 12 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

TFSx I/O Transmit Frame Sync (Serial Ports 0, 1).

RFSx I/O Receive Frame Sync (Serial Ports 0, 1).

LxDAT3–0 I/O Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 kΩ internal pull-down resistor that is enabled or

disabled by the LPDRD bit of the LCOM register.

LxCLK I/O Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that is enabled or

disabled by the LPDRD bit of the LCOM register.

LxACK I/O Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal pull-down resistor that is

enabled or disabled by the LPDRD bit of the LCOM register.

EBOOT I EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-bit EPROM.

When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See the table in the BMS pin

description below. This signal is a system configuration selection that should be hardwired.

LBOOT I Link Boot. When LBOOT is high, the ADSP-2106x is configured for link port booting. When LBOOT is low,

the ADSP-2106x is configured for host processor booting or no booting. See the table in the BMS pin

description below. This signal is a system configuration selection that should be hardwired.

BMS I/OT Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1, LBOOT = 0).

In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no booting will

occur and that ADSP-2106x will begin executing instructions from external memory. See table below. This

input is a system configuration selection that should be hardwired. *Three-statable only in EPROM boot

mode (when BMS is an output).

EBOOT LBOOT BMS Booting Mode

1 0 Output EPROM (Connect BMS to EPROM chip select.)

0 0 1 (Input) Host Processor

0 1 1 (Input) Link Port

0 0 0 (Input) No Booting. Processor executes from external memory.

010 (Input) Reserved

1 1 x (Input) Reserved

CLKIN I Clock In. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN. CLKIN should

not be halted, changed, or operated below the minimum specified frequency.

RESET I/A Processor Reset. Resets the ADSP-2106x to a known state and begins program execution at the program

memory location specified by the hardware reset vector address. This input must be asserted (low) at

power-up.

TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.

TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up resistor.

TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal pull-up

resistor.

TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held

low for proper operation of the ADSP-2106x. TRST has a 20 kΩ internal pull-up resistor.

EMU OEmulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only.

ICSA O Reserved, leave unconnected.

VDD P Power Supply; nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices. (30 pins).

GND G Power Supply Return. (30 pins).

NC Do Not Connect. Reserved pins which must be left open and unconnected.

Table 3. Pin Descriptions (Continued)

Pin Type Function

A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,

T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 13 of 64 | August 2010

TARGET BOARD CONNECTOR FOR EZ-ICE PROBE

The ADSP-2106x EZ-ICE

Emulator uses the IEEE

1149.1JTAG test access port of the ADSP-2106x to monitor and

control the target board processor during emulation. The

EZ-ICE probe requires the ADSP-2106x’s CLKIN, TMS, TCK,

TRST, TDI, TDO, EMU, and GND signals be made accessible

on the target system via a 14-pin connector (a 2-row 7-pin strip

header) such as that shown in Figure 5. The EZ-ICE probe plugs

directly onto this connector for chip-on-board emulation. You

must add this connector to your target board design if you

intend to use the ADSP-2106x EZ-ICE. The total trace length

between the EZ-ICE connector and the furthest device sharing

the EZ-ICE JTAG pin should be limited to 15 inches maximum

for guaranteed operation. This length restriction must include

EZ-ICE JTAG signals that are routed to one or more

ADSP-2106x devices, or a combination of ADSP-2106x devices

and other JTAG devices on the chain.

The 14-pin, 2-row pin strip header is keyed at the Pin 3 loca-

tion—Pin 3 must be removed from the header. The pins must be

0.025 inch square and at least 0.20 inch in length. Pin spacing

should be 0.1 × 0.1 inches. Pin strip headers are available from

vendors such as 3M, McKenzie, and Samtec. The BTMS, BTCK,

BTRST, and BTDI signals are provided so that the test access

port can also be used for board-level testing.

When the connector is not being used for emulation, place

jumpers between the Bxxx pins and the xxx pins as shown in

Figure 5. If you are not going to use the test access port for

board testing, tie BTRST to GND and tie or pull up BTCK to

. The TRST pin must be asserted (pulsed low) after power-

up (through BTRST on the connector) or held low for proper

operation of the ADSP-2106x. None of the Bxxx pins (Pins 5, 7,

9, and 11) are connected on the EZ-ICE probe.

The JTAG signals are terminated on the EZ-ICE probe as shown

in Table 4.

Figure 6 shows JTAG scan path connections for systems that

contain multiple ADSP-2106x processors.

Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.

The emulator only uses CLKIN when directed to perform oper-

ations such as starting, stopping, and single-stepping multiple

ADSP-2106xs in a synchronous manner. If you do not need

these operations to occur synchronously on the multiple proces-

sors, simply tie Pin 4 of the EZ-ICE header to ground.

If synchronous multiprocessor operations are needed and

CLKIN is connected, clock skew between the multiple

ADSP-2106x processors and the CLKIN pin on the EZ-ICE

header must be minimal. If the skew is too large, synchronous

operations may be off by one or more cycles between proces-

sors. For synchronous multiprocessor operation TCK, TMS,

CLKIN, and EMU should be treated as critical signals in terms

of skew, and should be laid out as short as possible on your

board. If TCK, TMS, and CLKIN are driving a large number of

ADSP-2106xs (more than eight) in your system, then treat them

as a “clock tree” using multiple drivers to minimize skew. (See

Figure 7 and “JTAG Clock Tree” and “Clock Distribution” in

the “High Frequency Design Considerations” section of the

ADSP-2106x User’s Manual, Revision 2.1.)

If synchronous multiprocessor operations are not needed (i.e.,

CLKIN is not connected), just use appropriate parallel termina-

tion on TCK and TMS. TDI, TDO, EMU and TRST are not

critical signals in terms of skew.

For complete information on the SHARC EZ-ICE, see the

ADSP-21000 Family JTAG EZ-ICE User's Guide and Reference.

Figure 5. Target Board Connector for ADSP-2106x EZ-ICE Emulator

(Jumpers in Place)

TOP VIEW

1314

11 12

910

EMU

GND

TMS

TCK

TRST

TDI

TDO

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

Table 4. Core Instruction Rate/CLKIN Ratio Selection

Signal Termination

TMS Driven Through 22 Ω Resistor (16 mA Driver)

TCK Driven at 10 MHz Through 22 Ω Resistor (16 mA

Driver)

TRST

TRST is driven low until the EZ-ICE probe is turned on by the emulator at software

start-up. After software start-up, is driven high.

Active Low Driven Through 22 Ω Resistor (16 mA

Driver) (Pulled-Up by On-Chip 20 kΩ Resistor)

TDI Driven by 22 Ω Resistor (16 mA Driver)

TDO One TTL Load, Split Termination (160/220)

CLKIN One TTL Load, Split Termination (160/220)

EMU Active Low 4.7 kΩ Pull-Up Resistor, One TTL Load

(Open-Drain Output from the DSP)

Rev. G | Page 14 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems

Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems

TRST

EMU

TRST

ADSP-2106x

JTAG

DEVICE

(OPTIONAL)

ADSP-2106x

TDI

EZ-ICE

JTAG

CONNECTOR

OTHER

JTAG

CONTROLLER

OPTIONAL

TCK

TMS

EMU

TMS

TCK

TDO

CLKIN

TRST

TCK

TMS

TCK

TMS

TDI TDO TDI TDO TDO

TDI

TRST

EMU

SYSTEM

CLKIN

EMU

5kV

TDI TDO

5kV

TDI

EMU

TMS

TCK

TDO

TRST

CLKIN

*OPEN-DRAIN DRIVER OR EQUIVALENT, i.e.,

TDI TDO TDI TDO

TDI TDO TDI TDO TDI TDO

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 15 of 64 | August 2010

ADSP-21060/ADSP-21062 SPECIFICATIONS

Note that component specifications are subject to change

without notice.

OPERATING CONDITIONS (5 V)

ELECTRICAL CHARACTERISTICS (5 V)

A Grade C Grade K Grade

Parameter Description Min Max Min Max Min Max Unit

Supply Voltage 4.75 5.25 4.75 5.25 4.75 5.25 V

CASE

Case Operating Temperature –40 +85 –40 +100 –40 +85 °C

Applies to input and bidirectional pins: DATA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA, TFS0,

TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.

High Level Input Voltage @ V

= Max 2.0 V

+ 0.5 2.0 V

+ 0.5 V

Applies to input pins: CLKIN, RESET, TRST.

High Level Input Voltage @ V

= Max 2.2 V

+ 0.5 2.2 V

+ 0.5 V

Low Level Input Voltage @ V

= Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V

Parameter Description Test Conditions Min Max Unit

High Level Output Voltage @ V

= Min, I

= –2.0 mA 4.1 V

Low Level Output Voltage @ V

= Min, I

= 4.0 mA 0.4 V

High Level Input Current @ V

= Max, V

= V

Max 10 μA

Low Level Input Current @ V

= Max, V

= 0 V 10 μA

ILP

Low Level Input Current @ V

= Max, V

= 0 V 150 μA

OZH

Three-State Leakage Current @ V

= Max, V

= V

Max 10 μA

OZL

Three-State Leakage Current @ V

= Max, V

= 0 V 10 μA

OZHP

Three-State Leakage Current @ V

= Max, V

= V

Max 350 μA

OZLC

Three-State Leakage Current @ V

= Max, V

= 0 V 1.5 mA

OZLA

Three-State Leakage Current @ V

= Max, V

= 1.5 V 350 μA

OZLAR

Three-State Leakage Current @ V

= Max, V

= 0 V 4.2 mA

OZLS

Three-State Leakage Current @ V

= Max, V

= 0 V 150 μA

11,

Input Capacitance f

= 1 MHz, T

CASE

= 25°C, V

= 2.5 V 4.7 pF

Applies to output and bidirectional pins: DATA47–0, ADDR31-0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2,

BR6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.

See “Output Drive Currents” for typical drive current capabilities.

Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.

Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.

Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx,

TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus

mastership.)

Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

Applies to CPA pin.

Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL

is not requesting bus mastership).

Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK.

Applies to ACK pin when keeper latch enabled.

Applies to all signal pins.

Guaranteed but not tested.

Rev. G | Page 16 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

INTERNAL POWER DISSIPATION (5 V)

These specifications apply to the internal power portion of V

only. For a complete discussion of the code used to measure

power dissipation, see the technical note “SHARC Power Dissi-

pation Measurements.”

Specifications are based on the operating scenarios.

To estimate power consumption for a specific application, use

the following equation where% is the amount of time your pro-

gram spends in that state:

%PEAK I

DDINPEAK

+%HIGH I

DDINHIGH

+%LOW I

DDINLOW

%IDLE I

DDIDLE

= Power Consumption

Operation Peak Activity (I

DDINPEAK

) High Activity (I

DDINHIGH

) Low Activity (I

DDINLOW

)

Instruction Type Multifunction Multifunction Single Function

Instruction Fetch Cache Internal Memory Internal Memory

Core memory Access 2 Per Cycle (DM and PM) 1 Per Cycle (DM) None

Internal Memory DMA 1 Per Cycle 1 Per 2 Cycles 1 Per 2 Cycles

Parameter Test Conditions Max Units

DDINPEAK

Supply Current (Internal)

= 30 ns, V

= Max

= 25 ns, V

= Max

745

850

DDINHIGH

Supply Current (Internal)

= 30 ns, V

= Max

= 25 ns, V

= Max

575

670

DDINLOW

Supply Current (Internal)

= 30 ns, V

= Max

= 25 ns, V

= Max

340

390

DDIDLE

Supply Current (Idle)

= Max 200 mA

The test program used to measure I

DDINPEAK

represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power

measurements made using typical applications are less than specified.

DDINHIGH

is a composite average based on a range of high activity code. I

DDINLOW

is a composite average based on a range of low activity code.

Idle denotes ADSP-2106x state during execution of IDLE instruction.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 17 of 64 | August 2010

EXTERNAL POWER DISSIPATION (5 V)

Total power dissipation has two components, one due to inter-

nal circuitry and one due to the switching of external output

drivers. Internal power dissipation is dependent on the instruc-

tion execution sequence and the data operands involved.

Internal power dissipation is calculated in the following way:

INT

= I

DDIN

× V

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

• the number of output pins that switch during each cycle

(O)

• the maximum frequency at which they can switch (f)

• their load capacitance (C)

• their voltage swing (V

)

and is calculated by:

EXT

= O × C × V

× f

The load capacitance should include the processor’s package

capacitance (CIN). The switching frequency includes driving

the load high and then back low. Address and data pins can

drive high and low at a maximum rate of 1/(2t

). The write

strobe can switch every cycle at a frequency of 1/t

. Select pins

switch at 1/(2t

), but selects can switch on each cycle.

Example: Estimate P

EXT

with the following assumptions:

• A system with one bank of external data memory RAM

(32-bit)

• Four 128K × 8 RAM chips are used, each with a load of

10 pF

• External data memory writes occur every other cycle, a rate

of 1/(4t

), with 50% of the pins switching

• The instruction cycle rate is 40 MHz (t

= 25 ns)

The P

EXT

equation is calculated for each class of pins that can

drive:

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

TOTAL

= P

EXT

+ (I

DDIN

× 5.0 V)

Note that the conditions causing a worst-case P

EXT

are different

from those causing a worst-case P

INT

. Maximum P

INT

cannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching

simultaneously.

Table 5. External Power Calculations (5 V Devices)

Pin Type No. of Pins % Switching × C × f × V

= P

EXT

Address 15 50 × 44.7 pF × 10 MHz × 25 V = 0.084 W

MS0 10 × 44.7 pF × 10 MHz × 25 V = 0.000 W

WR 1– × 44.7 pF × 20 MHz × 25 V = 0.022 W

Data 32 50 × 14.7 pF × 10 MHz × 25 V = 0.059 W

ADDRCLK 1 – × 4.7 pF × 20 MHz × 25 V = 0.002 W

EXT

= 0.167 W

Rev. G | Page 18 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

ADSP-21060L/ADSP-21062L SPECIFICATIONS

Note that component specifications are subject to change

without notice.

OPERATING CONDITIONS (3.3 V)

ELECTRICAL CHARACTERISTICS (3.3 V)

A Grade C Grade K Grade

Parameter Description Min Max Min Max Min Max Unit

Supply Voltage 3.15 3.45 3.15 3.45 3.15 3.45 V

CASE

Case Operating Temperature –40 +85 –40 +100 –40 +85 °C

Applies to input and bidirectional pins: DATA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA,

TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1

High Level Input Voltage @ V

= Max 2.0 V

+ 0.5 2.0 V

+ 0.5 V

Applies to input pins: CLKIN, RESET, TRST

High Level Input Voltage @ V

= Max 2.2 V

+ 0.5 2.2 V

+ 0.5 V

Low Level Input Voltage @ V

= Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V

Parameter Description Test Conditions Min Max Unit

1, 2

High Level Output Voltage @ V

= Min, I

= –2.0 mA 2.4 V

Low Level Output Voltage @ V

= Min, I

= 4.0 mA 0.4 V

High Level Input Current @ V

= Max, V

= V

Max 10 μA

Low Level Input Current @ V

= Max, V

= 0 V 10 μA

ILP

Low Level Input Current @ V

= Max, V

= 0 V 150 μA

OZH

Three-State Leakage Current @ V

= Max, V

= V

Max 10 μA

OZL

Three-State Leakage Current @ V

= Max, V

= 0 V 10 μA

OZHP

Three-State Leakage Current @ V

= Max, V

= V

Max 350 μA

OZLC

Three-State Leakage Current @ V

= Max, V

= 0 V 1.5 mA

OZLA

Three-State Leakage Current @ V

= Max, V

= 1.5 V 350 μA

OZLAR

Three-State Leakage Current @ V

= Max, V

= 0 V 4.2 mA

OZLS

Three-State Leakage Current @ V

= Max, V

= 0 V 150 μA

11,

Input Capacitance f

= 1 MHz, T

CASE

= 25°C, V

= 2.5 V 4.7 pF

Applies to output and bidirectional pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2,

BR6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.

See “Output Drive Currents” for typical drive current capabilities.

Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.

Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.

Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx,

TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus

mastership.)

Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

Applies to CPA pin.

Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL

is not requesting bus mastership).

Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK.

Applies to ACK pin when keeper latch enabled.

Applies to all signal pins.

Guaranteed but not tested.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 19 of 64 | August 2010

INTERNAL POWER DISSIPATION (3.3 V)

These specifications apply to the internal power portion of V

only. For a complete discussion of the code used to measure

power dissipation, see the technical note “SHARC Power Dissi-

pation Measurements.”

Specifications are based on the operating scenarios.

To estimate power consumption for a specific application, use

the following equation where % is the amount of time your pro-

gram spends in that state:

%PEAK I

DDINPEAK

+ %HIGH I

DDINHIGH

+ %LOW I

DDINLOW

%IDLE I

DDIDLE

= Power Consumption

Operation Peak Activity (I

DDINPEAK

) High Activity (I

DDINHIGH

) Low Activity (I

DDINLOW

)

Instruction Type Multifunction Multifunction Single Function

Instruction Fetch Cache Internal Memory Internal Memory

Core memory Access 2 Per Cycle (DM and PM) 1 Per Cycle (DM) None

Internal Memory DMA 1 Per Cycle 1 Per 2 Cycles 1 Per 2 Cycles

Parameter Test Conditions Max Units

DDINPEAK

Supply Current (Internal)

= 30 ns, V

= Max

= 25 ns, V

= Max

540

600

DDINHIGH

Supply Current (Internal)

= 30 ns, V

= Max

= 25 ns, V

= Max

425

475

DDINLOW

Supply Current (Internal)

= 30 ns, V

= Max

= 25 ns, V

= Max

250

275

DDIDLE

Supply Current (Idle)

= Max 180 mA

The test program used to measure I

DDINPEAK

represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power

measurements made using typical applications are less than specified.

DDINHIGH

is a composite average based on a range of high activity code. I

DDINLOW

is a composite average based on a range of low activity code.

Idle denotes ADSP-2106xL state during execution of IDLE instruction.

Rev. G | Page 20 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

EXTERNAL POWER DISSIPATION (3.3 V)

Total power dissipation has two components, one due to inter-

nal circuitry and one due to the switching of external output

drivers. Internal power dissipation is dependent on the instruc-

tion execution sequence and the data operands involved.

Internal power dissipation is calculated in the following way:

INT

= I

DDIN

× V

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

• the number of output pins that switch during each cycle

(O)

• the maximum frequency at which they can switch (f)

• their load capacitance (C)

• their voltage swing (V

)

and is calculated by:

EXT

= O × C × V

× f

The load capacitance should include the processor’s package

capacitance (CIN). The switching frequency includes driving

the load high and then back low. Address and data pins can

drive high and low at a maximum rate of 1/(2t

). The write

strobe can switch every cycle at a frequency of 1/t

. Select pins

switch at 1/(2t

), but selects can switch on each cycle.

Example: Estimate P

EXT

with the following assumptions:

• A system with one bank of external data memory RAM

(32-bit)

• Four 128K × 8 RAM chips are used, each with a load of

10 pF

• External data memory writes occur every other cycle, a rate

of 1/(4t

), with 50% of the pins switching

• The instruction cycle rate is 40 MHz (t

= 25 ns)

The P

EXT

equation is calculated for each class of pins that can

drive:

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

TOTAL

= P

EXT

+ (I

DDIN

× 5.0 V)

Note that the conditions causing a worst-case P

EXT

are different

from those causing a worst-case P

INT

. Maximum P

INT

cannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching

simultaneously.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed Table 7 may cause permanent

damage to the device. These are stress ratings only; functional

operation of the device at these or any other conditions greater

than those indicated in the operational sections of this specifica-

tion is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Table 6. External Power Calculations (3.3 V Devices)

Pin Type No. of Pins % Switching × C × f × V

= P

EXT

Address 15 50 × 44.7 pF × 10 MHz × 10.9 V = 0.037 W

MS0 10 × 44.7 pF × 10 MHz × 10.9 V = 0.000 W

WR 1– × 44.7 pF × 20 MHz × 10.9 V = 0.010 W

Data 32 50 × 14.7 pF × 10 MHz × 10.9 V = 0.026 W

ADDRCLK 1 – × 4.7 pF × 20 MHz × 10.9 V = 0.001 W

EXT

= 0.074 W

Table 7. Absolute Maximum Ratings

Parameter

ADSP-21060/ADSP-21060C

ADSP-21062

ADSP-21060L/ADSP-21060LC

ADSP-21062L

5 V 3.3 V

Supply Voltage (V

) –0.3 V to +7.0 V –0.3 V to +4.6 V

Input Voltage –0.5 V to V

+ 0.5 V –0.5 V to V

+0.5 V

Output Voltage Swing –0.5 V to V

+ 0.5 V –0.5 V to V

+ 0.5 V

Load Capacitance 200 pF 200 pF

Storage Temperature Range –65°C to +150°C–65°C to +150°C

Lead Temperature (5 seconds) 280°C280°C

Junction Temperature Under Bias 130°C130°C

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 21 of 64 | August 2010

ESD CAUTION

PACKAGE MARKING INFORMATION

Figure 8 and Table 8 provide information on detail contained

within the package marking for the ADSP-2106x processors

(actual marking format may vary). For a complete listing of

product availability, see Ordering Guide on Page 62.

TIMING SPECIFICATIONS

The ADSP-2106x processors are available at maximum proces-

sor speeds of 33 MHz (–133), and 40 MHz (–160). The timing

specifications are based on a CLKIN frequency of 40 MHz

= 25 ns). The DT derating factor enables the calculation for

timing specifications within the min to max range of the t

specification (see Table 9). DT is the difference between the

derated CLKIN period and a CLKIN period of 25 ns:

DT = t

– 25 ns

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, you

cannot meaningfully add parameters to derive longer times.

For voltage reference levels, see Figure 28 on Page 48 under Test

Conditions.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices. (O/D) = Open Drain,

(A/D) = Active Drive.

Switching Characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use

switching characteristics to ensure that any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

Figure 8. Typical Package Brand

Table 8. Package Brand Information

Brand Key Field Description

t Temperature Range

pp Package Type

Z Lead (Pb) Free Option

ccc See Ordering Guide

vvvvvv.x Assembly Lot Code

n.n Silicon Revision

yyww Date Code

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid

performance degradation or loss of functionality.

vvvvvv.x n.n

tppZccc

ADSP-2106x

yyww country_of_origin

Rev. G | Page 22 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Clock Input

Reset

Table 9. Clock Input

Parameter

ADSP-21060

ADSP-21062

40 MHz, 5 V

ADSP-21060

ADSP-21062

33 MHz, 5 V

ADSP-21060L

ADSP-21062L

40 MHz, 3.3 V

ADSP-21060L

ADSP-21062L

33 MHz, 3.3 V

UnitMinMaxMinMaxMinMaxMinMax

Timing Requirements

CLKIN Period 25 100 30 100 25 100 30 100 ns

CKL

CLKIN Width Low 7 7 8.75 8.75

CKH

CLKIN Width High5555ns

CKRF

CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 ns

For the ADSP-21060LC, this specification is 9.5 ns min.

Figure 9. Clock Input

CLKIN

tCKH tCKL

tCK

Table 10. Reset

5 V and 3.3 V

Unit

Parameter Min Max

Timing Requirements

WRST

RESET Pulse Width Low

SRST

RESET Setup Before CLKIN High

14 + DT/2 t

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

and CLKIN (not including start-up time of external clock oscillator).

Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-2106xs commu-

nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.

Figure 10. Reset

CLKIN

RESET

tWRST

tSRST

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 23 of 64 | August 2010

Interrupts

Timer

Table 11. Interrupts

5 V and 3.3 V

Unit

Parameter Min Max

Timing Requirements

SIR

IRQ2–0 Setup Before CLKIN High

18 + 3DT/4 ns

HIR

IRQ2–0 Hold Before CLKIN High

12 + 3DT/4 ns

IPW

IRQ2–0 Pulse Width

2+t

Only required for IRQx recognition in the following cycle.

Applies only if t

SIR

and t

HIR

requirements are not met.

Figure 11. Interrupts

CLKIN

IRQ2–0

tIPW

tSIR

tHIR

Table 12. Timer

5 V and 3.3 V

Unit

Parameter Min Max

Switching Characteristic

DTEX

CLKIN High to TIMEXP 15 ns

Figure 12. Timer

CLKIN

TIMEXP

tDTEX

Rev. G | Page 24 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Flags

Table 13. Flags

5 V and 3.3 V

Unit

Parameter Min Max

Timing Requirements

SFI

FLAG3–0 IN Setup Before CLKIN High

8 + 5DT/16 ns

HFI

FLAG3–0 IN Hold After CLKIN High

0 – 5DT/16 ns

DWRFI

FLAG3–0 IN Delay After RD/WR Low

5 + 7DT/16 ns

HFIWR

FLAG3–0 IN Hold After RD/WR Deasserted

0ns

Switching Characteristics

DFO

FLAG3–0 OUT Delay After CLKIN High 16 ns

HFO

FLAG3–0 OUT Hold After CLKIN High 4 ns

DFOE

CLKIN High to FLAG3–0 OUT Enable 3 ns

DFOD

CLKIN High to FLAG3–0 OUT Disable 14 ns

Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.

Figure 13. Flags

CLKIN

FLAG3–0 OUT

FLAG OUTPUT

CLKIN

FLAG INPUT

tDFO

tHFO

tDFO tDFOD

tDFOE

tSFI tHFI

tHFIWR

tDWRFI

RD/WR

FLAG3–0 IN

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 25 of 64 | August 2010

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN. These specifications apply when the ADSP-2106x is the

bus master accessing external memory space in asynchronous

access mode. Note that timing for ACK, DATA, RD, WR, and

DMAGx strobe timing parameters only applies to asynchronous

access mode.

Table 14. Memory Read—Bus Master

5 V and 3.3 V

Unit

Parameter Min Max

Timing Requirements

DAD

Address Selects Delay to Data Valid

18 + DT+W ns

DRLD

RD Low to Data Valid

12 + 5DT/8 + W ns

HDA

Data Hold from Address, Selects

0.5 ns

HDRH

Data Hold from RD High

2.0 ns

DAAK

ACK Delay from Address, Selects

14 + 7DT/8 + W ns

DSAK

ACK Delay from RD Low

8 + DT/2 + W ns

Switching Characteristics

DRHA

Address Selects Hold After RD High 0+H ns

DARL

Address Selects to RD Low

2 + 3DT/8 ns

RD Pulse Width 12.5 + 5DT/8 + W ns

RWR

RD High to WR, RD, DMAGx Low 8 + 3DT/8 + HI ns

SADADC

Address, Selects Setup Before ADRCLK High

0 + DT/4 ns

W = (number of wait states specified in WAIT register) × t

HI = t

(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = t

(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

Data delay/setup: user must meet t

DAD

or t

DRLD

or synchronous spec t

SSDATI

The falling edge of MSx, SW, BMS is referenced.

Data hold: user must meet t

HDA

or t

HDRH

or synchronous spec t

HSDATI

. See Example System Hold Time Calculation on Page 48 for the calculation of hold times given capacitive

and dc loads.

ACK is not sampled on external memory accesses that use the internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be valid by

DAAK

or t

DSAK

or synchronous specification t

SACKC

for wait state modes external, either, or both (both, if the internal wait state is zero). For the second and subsequent cycles

of a wait stated external memory access, synchronous specifications t

SACKC

and t

HACK

must be met for wait state modes external, either, or both (both, after internal wait

states have completed).

Figure 14. Memory Read—Bus Master

WR,DMAG

ACK

DATA

ADDRESS

MSx,SW

BMS

tDARL tRW

tDAD

tSADADC

tDAAK

tHDRH

tHDA

tRWR

tDRLD

ADRCLK

(OUT)

tDRHA

tDSAK

Rev. G | Page 26 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN. These specifications apply when the ADSP-2106x is the

bus master accessing external memory space in asynchronous

access mode. Note that timing for ACK, DATA, RD, WR, and

DMAGx strobe timing parameters only applies to asynchronous

access mode.

Table 15. Memory Write—Bus Master

5 V and 3.3 V

Unit

Parameter Min Max

Timing Requirements

DAAK

ACK Delay from Address, Selects

1, 2

14 + 7DT/8 + W ns

DSAK

ACK Delay from WR Low

8 + DT/2 + W ns

Switching Characteristics

DAWH

Address Selects to WR Deasserted

17 + 15DT/16 + W ns

DAWL

Address Selects to WR Low

3 + 3DT/8 ns

WR Pulse Width 12 + 9DT/16 + W ns

DDWH

Data Setup Before WR High 7 + DT/2 + W ns

DWHA

Address Hold After WR Deasserted 0.5 + DT/16 + H ns

DATRWH

Data Disable After WR Deasserted

1 + DT/16 +H 6 + DT/16+H ns

WWR

WR High to WR, RD, DMAGx Low 8 + 7DT/16 + H ns

DDWR

Data Disable Before WR or RD Low 5 + 3DT/8 + I ns

WDE

WR Low to Data Enabled –1 + DT/16 ns

SADADC

Address, Selects Setup Before ADRCLK High

0 + DT/4 ns

W = (number of wait states specified in WAIT register) × t

H = t

(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

HI = t

(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

I = t

(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

ACK is not sampled on external memory accesses that use the internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be valid by

DAAK

or t

DSAK

or synchronous specification t

SACKC

for wait state modes external, either, or both (both, if the internal wait state is zero). For the second and subsequent cycles

of a wait stated external memory access, synchronous specifications t

SACKC

and t

HACK

must be met for wait state modes external, either, or both (both, after internal wait

states have completed).

The falling edge of MSx, SW, BMS is referenced.

See Example System Hold Time Calculation on Page 48 for calculation of hold times given capacitive and dc loads.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 27 of 64 | August 2010

Figure 15. Memory Write—Bus Master

RD,DMAG

ACK

DATA

ADDRESS

MSx,SW

BMS

tWW

tSADADC

tDAAK

tWWR

ADRCLK

(OUT)

tDWHA

tDSAK

tDAWL

tWDE tDDWR

tDATRWH

tDDWH

tDAWH

Rev. G | Page 28 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Synchronous Read/Write—Bus Master

Use these specifications for interfacing to external memory sys-

tems that require CLKIN—relative timing or for accessing a

slave ADSP-2106x (in multiprocessor memory space). These

synchronous switching characteristics are also valid during

asynchronous memory reads and writes except where noted (see

Memory Read—Bus Master on Page 25 and Memory Write—

Bus Master on Page 26). When accessing a slave ADSP-2106x,

these switching characteristics must meet the slave’s timing

requirements for synchronous read/writes (see Synchronous

Read/Write—Bus Slave on Page 30). The slave ADSP-2106x

must also meet these (bus master) timing requirements for data

and acknowledge setup and hold times.

Table 16. Synchronous Read/Write—Bus Master

5 V and 3.3 V

Unit

Parameter Min Max

Timing Requirements

SSDATI

Data Setup Before CLKIN 3 + DT/8 ns

HSDATI

Data Hold After CLKIN 3.5 – DT/8 ns

DAAK

ACK Delay After Address, Selects

1, 2

14 + 7DT/8 + W ns

SACKC

ACK Setup Before CLKIN

6.5+DT/4 ns

HACK

ACK Hold After CLKIN –1 – DT/4 ns

Switching Characteristics

DADRO

Address, MSx, BMS, SW Delay After CLKIN

7 – DT/8 ns

HADRO

Address, MSx, BMS, SW Hold After CLKIN –1 – DT/8 ns

DPGC

PAGE Delay After CLKIN 9 + DT/8 16 + DT/8 ns

DRDO

RD High Delay After CLKIN –2 – DT/8 4 – DT/8 ns

DWRO

WR High Delay After CLKIN –3 – 3DT/16 4 – 3DT/16 ns

DRWL

RD/WR Low Delay After CLKIN 8 + DT/4 12.5 + DT/4 ns

SDDATO

Data Delay After CLKIN 19 + 5DT/16 ns

DATTR

Data Disable After CLKIN

0 – DT/8 7 – DT/8 ns

DADCCK

ADRCLK Delay After CLKIN 4 + DT/8 10 + DT/8 ns

ADRCK

ADRCLK Period t

ADRCKH

ADRCLK Width High (t

/2 – 2) ns

ADRCKL

ADRCLK Width Low (t

/2 – 2) ns

The falling edge of MSx, SW, BMS is referenced.

ACK delay/setup: user must meet t

DAAK

or t

DSAK

or synchronous specification t

SAKC

for deassertion of ACK (low), all three specifications must be met for assertion of ACK

(high).

See Example System Hold Time Calculation on Page 48 for calculation of hold times given capacitive and dc loads.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 29 of 64 | August 2010

Figure 16. Synchronous Read/Write—Bus Master

CLKIN

ADDRCLK

ADDRESS,

BMS,SW,MSx

ACK

(IN)

PAGE

DATA

(OUT)

DATA (IN)

WRITE CYCLE

READ CYCLE

tDRWL

tHSDATI

tSSDATI

tDRDO

tDWRO

tDATTR

tSDDATO

tDRWL

tDADCCK

tADRCK

tADRCKL

tHADRO

tDPGC

tSACKC tHACK

tDADRO

tADRCKH

tDAAK

Rev. G | Page 30 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Synchronous Read/Write—Bus Slave

Use these specifications for bus master accesses of a slave’s IOP

registers or internal memory (in multiprocessor memory space).

The bus master must meet the bus slave timing requirements.

Table 17. Synchronous Read/Write—Bus Slave

5 V and 3.3 V

Unit

Parameter Min Max

Timing Requirements

SADRI

Address, SW Setup Before CLKIN 15 + DT/2 ns

HADRI

Address, SW Hold After CLKIN 5 + DT/2 ns

SRWLI

RD/WR Low Setup Before CLKIN

9.5 + 5DT/16 ns

HRWLI

RD/WR Low Hold After CLKIN

–4 – 5DT/16 8 + 7DT/16 ns

RWHPI

RD/WR Pulse High 3 ns

SDATWH

Data Setup Before WR High 5 ns

HDATWH

Data Hold After WR High 1 ns

Switching Characteristics

SDDATO

Data Delay After CLKIN

18 + 5DT/16 ns

DATTR

Data Disable After CLKIN

0 – DT/8 7 – DT/8 ns

DACKAD

ACK Delay After Address, SW

9ns

ACKTR

ACK Disable After CLKIN

–1 – DT/8 6 – DT/8 ns

SRWLI

(min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t

SRWLI

(min)= 4 + DT/8.

For ADSP-21060C specification is –3.5 – 5DT/16 ns min, 8 + 7DT/16 ns max; for ADSP-21060LC specification is –3.75 – 5DT/16 ns min, 8 + 7DT/16 ns max.

For ADSP-21062/ADSP-21062L/ADSP-21060C specification is 19 + 5DT/16 ns max; for ADSP-21060LC specification is 19.25 + 5DT/16 ns max.

See Example System Hold Time Calculation on Page 48 for calculation of hold times given capacitive and dc loads.

DACKAD

is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and inputs have setup times

greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of the state

of MMSWS or strobes. A slave will three-state ACK every cycle with t

ACKTR

Figure 17. Synchronous Read/Write—Bus Slave

CLKIN

ADDRESS

ACK

DATA

(OU T)

WRITE ACCESS

DATA

(IN)

READ ACCESS

tSADRI

tHADRI

tDACKAD tACKTR

tHRWLI

tSRWLI

tSDDATO tDATTR

tSRWLI tHRWLI

tHDATWH

tSDATWH

tRWHPI

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 31 of 64 | August 2010

Multiprocessor Bus Request and Host Bus Request

Use these specifications for passing of bus mastership between

multiprocessing ADSP-2106xs (BRx) or a host processor, both

synchronous and asynchronous (HBR, HBG).

Table 18. Multiprocessor Bus Request and Host Bus Request

5 V and 3.3 V

Unit

Parameter Min Max

Timing Requirements

HBGRCSV

HBG Low to RD/WR/CS Valid

20 + 5DT/4 ns

SHBRI

HBR Setup Before CLKIN

20 + 3DT/4 ns

HHBRI

HBR Hold After CLKIN

14 + 3DT/4 ns

SHBGI

HBG Setup Before CLKIN 13 + DT/2 ns

HHBGI

HBG Hold After CLKIN High 6 + DT/2 ns

SBRI

BRx, CPA Setup Before CLKIN

13 + DT/2 ns

HBRI

BRx, CPA Hold After CLKIN High 6 + DT/2 ns

SRPBAI

RPBA Setup Before CLKIN 21 + 3DT/4 ns

HRPBAI

RPBA Hold After CLKIN 12 + 3DT/4 ns

Switching Characteristics

DHBGO

HBG Delay After CLKIN 7 – DT/8 ns

HHBGO

HBG Hold After CLKIN –2 – DT/8 ns

DBRO

BRx Delay After CLKIN 7 – DT/8 ns

HBRO

BRx Hold After CLKIN –2 – DT/8 ns

DCPAO

CPA Low Delay After CLKIN

8 – DT/8 ns

TRCPA

CPA Disable After CLKIN –2 – DT/8 4.5 – DT/8 ns

DRDYCS

REDY (O/D) or (A/D) Low from CS and HBR Low

8.5 ns

TRDYHG

REDY (O/D) Disable or REDY (A/D) High from HBG

44 + 23DT/16 ns

ARDYTR

REDY (A/D) Disable from CS or HBR High

10 ns

For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 t

before RD or WR goes low or by t

HBGRCSV

after HBG goes low. This is

easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC

User’s Manual, Revision 2.1.

Only required for recognition in the current cycle.

CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.

For ADSP-21060LC, specification is 8.5 – DT/8 ns max.

For ADSP-21060L, specification is 9.5 ns max, For ADSP-21060LC, specification is 11.0 ns max, For ADSP-21062L, specification is 8.75 ns max.

(O/D) = open drain, (A/D) = active drive.

For ADSP-21060C/ADSP-21060LC, specification is 40 + 23DT/16 ns min.

Rev. G | Page 32 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Figure 18. Multiprocessor Bus Request and Host Bus Request

Rx,CPA (IN , O/ D)

HBR

RP BA

RE D Y

(O /D )

REDY

(A/D )

HBG (OUT)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

tSRPBAI

HBG (I N)

CLKIN

HBR

HBG (OUT)

BRx (OUT)

CPA (OUT, O/D)

tHHBGO

tHBRO

tTRCP A

tHRPBAI

tHBRI

tSBRI

tSHBGI

tHHBGI

tDCPAO

tDBRO

tDHBGO

tHHBRI

tSHBRI

tDRDYCStTRDYHG

tHBGRCSV

tARDYTR

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 33 of 64 | August 2010

Asynchronous Read/Write—Host to ADSP-2106x

Use these specifications for asynchronous host processor

accesses of an ADSP-2106x, after the host has asserted CS and

HBR (low). After HBG is returned by the ADSP-2106x, the host

can drive the RD and WR pins to access the ADSP-2106x’s

internal memory or IOP registers. HBR and HBG are assumed

low for this timing. Not required if and address are valid t

HBGRCSV

after goes low. For first access after asserted, ADDR31–0 must

be a non-MMS value 1/2 t

CLK

before or goes low or by t

HBGRCSV

after goes low. This is easily accomplished by driving an upper

address signal high when is asserted. See the “Host Processor

Control of the ADSP-2106x” section in the ADSP-2106x

SHARC User’s Manual, Revision 2.1.

Table 19. Read Cycle

5 V and 3.3 V

Unit

Parameter Min Max

Timing Requirements

SADRDL

Address Setup/CS Low Before RD Low

0ns

HADRDH

Address Hold/CS Hold Low After RD 0ns

WRWH

RD/WR High Width 6 ns

DRDHRDY

RD High Delay After REDY (O/D) Disable 0 ns

DRDHRDY

RD High Delay After REDY (A/D) Disable 0 ns

Switching Characteristics

SDATRDY

Data Valid Before REDY Disable from Low 2 ns

DRDYRDL

REDY (O/D) or (A/D) Low Delay After RD Low

10 ns

RDYPRD

REDY (O/D) or (A/D) Low Pulse Width for Read 45 + 21DT/16 ns

HDARWH

Data Disable After RD High

28ns

Not required if RD and address are valid t

HBGRCSV

after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 t

CLK

before RD or WR goes

low or by t

HBGRCSV

after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the

ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Revision 2.1.

For ADSP-21060L, specification is 10.5 ns max; for ADSP-21060LC, specification is 12.5 ns max.

For ADSP-21060L/ADSP-21060LC, specification is 2 ns min, 8.5 ns max.

Table 20. Write Cycle

5 V and 3.3 V

Unit

Parameter Min Max

Timing Requirements

SCSWRL

CS Low Setup Before WR Low 0 ns

HCSWRH

CS Low Hold After WR High 0 ns

SADWRH

Address Setup Before WR High 5 ns

HADWRH

Address Hold After WR High 2 ns

WWRL

WR Low Width 7 ns

WRWH

RD/WR High Width 6 ns

DWRHRDY

WR High Delay After REDY (O/D) or (A/D) Disable 0 ns

SDATWH

Data Setup Before WR High 5 ns

HDATWH

Data Hold After WR High 1 ns

Switching Characteristics

DRDYWRL

REDY (O/D) or (A/D) Low Delay After WR/CS Low 10 ns

RDYPWR

REDY (O/D) or (A/D) Low Pulse Width for Write 15 + 7DT/16 ns

SRDYCK

REDY (O/D) or (A/D) Disable to CLKIN 1 + 7DT/16 8 + 7DT/16 ns

Rev. G | Page 34 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Figure 19. Synchronous REDY Timing

Figure 20. Asynchronous Read/Write—Host to ADSP-2106x

CLKIN

RE DY ( O /D )

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

tSRDYCK

RED Y (A / D )

tSADRDL

REDY (O/D )

tDR DY R DL

tWRWH

tHADRDH

tHDARWH

tRDYPRD

tDRDHRDY

tSDATRDY

READ CYCLE

ADDRESS/CS

DA T A ( O U T )

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

tSDA TW H

tHDATWH

tWWRL

RE D Y ( O/ D )

tDRDYWRL

tWRWH

tHADWRH

tRDYPWR

tDWRHRDY

WRITE CYCLE

tSADWRH

DATA (IN)

ADDRESS

REDY (A/D)

tSCSWRL

tHCSWRH

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 35 of 64 | August 2010

Three-State Timing—Bus Master, Bus Slave

These specifications show how the memory interface is disabled

(stops driving) or enabled (resumes driving) relative to CLKIN

and the SBTS pin. This timing is applicable to bus master transi-

tion cycles (BTC) and host transition cycles (HTC) as well as the

SBTS pin.

Table 21. Three-State Timing—Bus Master, Bus Slave

5 V and 3.3 V

Unit

Parameter Min Max

Timing Requirements

STSCK

SBTS Setup Before CLKIN 12 + DT/2 ns

HTSCK

SBTS Hold Before CLKIN 6 + DT/2 ns

Switching Characteristics

MIENA

Address/Select Enable After CLKIN

–1.5 – DT/8 ns

MIENS

Strobes Enable After CLKIN

–1.5 – DT/8 ns

MIENHG

HBG Enable After CLKIN –1.5 – DT/8 ns

MITRA

Address/Select Disable After CLKIN

0 – DT/4 ns

MITRS

Strobes Disable After CLKIN

1.5 – DT/4 ns

MITRHG

HBG Disable After CLKIN 2.0 – DT/4 ns

DATEN

Data Enable After CLKIN

9 + 5DT/16 ns

DATTR

Data Disable After CLKIN

0 – DT/8 7 – DT/8 ns

ACKEN

ACK Enable After CLKIN

7.5 + DT/4 ns

ACKTR

ACK Disable After CLKIN

–1 – DT/8 6 – DT/8 ns

ADCEN

ADRCLK Enable After CLKIN –2 – DT/8 ns

ADCTR

ADRCLK Disable After CLKIN 8 – DT/4 ns

MTRHBG

Memory Interface Disable Before HBG Low

0 + DT/8 ns

MENHBG

Memory Interface Enable After HBG High

19 + DT ns

For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is –1.25 – DT/8 ns min, for ADSP-21062, specification is –1 – DT/8 ns min.

Strobes = RD, WR, PAGE, DMAG, BMS, SW.

For ADSP-21060LC, specification is 0.25 – DT/4 ns max.

In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.

Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, and BMS (in EPROM boot mode).

Figure 21. Three-State Timing (Bus Transition Cycle, SBTS Assertion)

MEMORY

INTERFACE

HBG

MEMORY INTERFACE = ADDRESS,RD,WR,MSx,SW,PAGE,DMAGx. BMS (IN EPROM BOOT MODE)

tMENHBG

tMTRHBG

Rev. G | Page 36 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Figure 22. Three-State Timing (Bus Transition Cycle, SBTS Assertion)

CLKIN

SBTS

ACK

ADRCLK

DATA

MEMORY

INTERFACE

tMITRA, tMITRS,tMITRHG

tSTSCK

tHTSCK

tDATTR

tDATEN

tACKTR

tACKEN

tADCTR

tADCEN

tMIENA, tMIENS,tMIENHG

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 37 of 64 | August 2010

DMA Handshake

These specifications describe the three DMA handshake modes.

In all three modes, DMARx is used to initiate transfers. For

Handshake mode, DMAGx controls the latching or enabling of

data externally. For External handshake mode, the data transfer

is controlled by the ADDR31–0, RD, WR, PAGE, MS3–0, ACK,

and DMAGx signals. For Paced Master mode, the data transfer

is controlled by ADDR31–0, RD, WR, MS3–0, and ACK (not

DMAG). For Paced Master mode, the Memory Read-Bus Mas-

ter, Memory Write-Bus Master, and Synchronous Read/Write-

Bus Master timing specifications for ADDR31–0, RD, WR,

MS3–0, PAGE, DATA63–0, and ACK also apply.

Table 22. DMA Handshake

5 V and 3.3 V

Unit

Parameter Min Max

Timing Requirements

SDRLC

DMARx Low Setup Before CLKIN

5ns

SDRHC

DMARx High Setup Before CLKIN

5ns

WDR

DMARx Width Low (Nonsynchronous) 6 ns

SDATDGL

Data Setup After DMAGx Low

10 + 5DT/8 ns

HDATIDG

Data Hold After DMAGx High 2 ns

DATDRH

Data Valid After DMARx High

16 + 7DT/8 ns

DMARLL

DMARx Low Edge to Low Edge 23 + 7DT/8 ns

DMARH

DMARx Width High

6ns

Switching Characteristics

DDGL

DMAGx Low Delay After CLKIN 9 + DT/4 15 + DT/4 ns

WDGH

DMAGx High Width 6 + 3DT/8 ns

WDGL

DMAGx Low Width 12 + 5DT/8 ns

HDGC

DMAGx High Delay After CLKIN –2 – DT/8 6 – DT/8 ns

VDATDGH

Data Valid Before DMAGx High

8 + 9DT/16 ns

DATRDGH

Data Disable After DMAGx High

07ns

DGWRL

WR Low Before DMAGx Low

02ns

DGWRH

DMAGx Low Before WR High 10 + 5DT/8 +W ns

DGWRR

WR High Before DMAGx High 1 + DT/16 3 + DT/16 ns

DGRDL

RD Low Before DMAGx Low 0 2 ns

DRDGH

RD Low Before DMAGx High 11 + 9DT/16 + W ns

DGRDR

RD High Before DMAGx High 0 3 ns

DGWR

DMAGx High to WR, RD, DMAGx Low 5 + 3DT/8 + HI ns

DADGH

Address/Select Valid to DMAGx High 17 + DT ns

DDGHA

Address/Select Hold After DMAGx High

–0.5 ns

W = (number of wait states specified in WAIT register) × t

HI = t

(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

Only required for recognition in the current cycle.

SDATDGL

is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can

be driven t

DATDRH

after DMARx is brought high.

VDATDGH

is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t

VDATDGH

–0.25t

CCLK

–8+(n×t

) where n equals

the number of extra cycles that the access is prolonged.

See Example System Hold Time Calculation on Page 48 for calculation of hold times given capacitive and dc loads.

For ADSP-21062/ADSP-21062L specification is –2.5 ns min, 2 ns max.

For ADSP-21060L/ADSP-21062L specification is –1 ns min.

Rev. G | Page 38 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Figure 23. DMA Handshake

CLKIN

tSDRLC

DMARx

DATA

(OUT)

DATA

(IN)

tWDR

tSDRHC

tDMARH

tDMARLL

tHDGC

tWDGH

tDDGL

DMAGx

tVDATDGH

tDATDRH

tDATRDGH

tHDATIDG

tDGWRL tDGWRH tDGWRR

tDGRDL

tDRDGH

tDGRDR

tSDATDGL

*MEMORY READ BUSMASTER, MEMORY WRITE BUSMASTER, OR SYNCHRONOUSREAD/WRITE BUSMASTER

TIMING SPECIFICATIONSFOR ADDR31–0, RD,WR,SW MS3–0, AND ACK ALSO APPLY HERE.

(EXTERNAL DEVICE TO EXTERNAL MEMORY)

(EXTERNAL MEMORY TO EXTERNAL DEVICE)

TRANSFERSBETWEEN ADSP-2106x

INTERNAL MEMORY AND EXTERNAL DEVICE

TRANSFERSBETWEEN EXTERNAL DEVICE AND

EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)

tDDGHA

ADDR

MSx, SW

tDADGH

tWDGL

(FROM EXTERNAL DEVICE TO ADSP-2106x)

(FROM ADSP-2106x TO EXTERNAL DEVICE)

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 39 of 64 | August 2010

Link Ports —1 × CLK Speed Operation

Table 23. Link Ports—Receive

5 V 3.3 V

Unit

Parameter Min Max Min Max

Timing Requirements

SLDCL

Data Setup Before LCLK Low

3.5 3 ns

HLDCL

Data Hold After LCLK Low 3 3 ns

LCLKIW

LCLK Period (1× Operation) t

LCLKRWL

LCLK Width Low 6 6 ns

LCLKRWH

LCLK Width High 55ns

Switching Characteristics

DLAHC

LACK High Delay After CLKIN High

18 + DT/2 28.5 + DT/2 18 + DT/2 28.5 + DT/2 ns

DLALC

LACK Low Delay After LCLK High –3 +13 –3 +13 ns

ENDLK

LACK Enable From CLKIN 5 + DT/2 5 + DT/2 ns

TDLK

LACK Disable From CLKIN 20 + DT/2 20 + DT/2 ns

For ADSP-21062, specification is 3 ns min.

LACK goes low with t

DLALC

relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.

For ADSP-21060C, specification is 18 + DT/2 ns min, 29 + DT/2 ns max.

Table 24. Link Ports—Transmit

5 V 3.3 V

Unit

Parameter Min Max Min Max

Timing Requirements

SLACH

LACK Setup Before LCLK High

18 18 ns

HLACH

LACK Hold After LCLK High –7 –7 ns

Switching Characteristics

DLCLK

Data Delay After CLKIN (1×

Operation)

15.5 15.5 ns

DLDCH

Data Delay After LCLK High

32.5ns

HLDCH

Data Hold After LCLK High –3 –3 ns

LCLKTWL

LCLK Width Low

/2) – 2 (t

/2) + 2 (t

/2) – 1 (t

/2) + 1.25 ns

LCLKTWH

LCLK Width High

/2) – 2 (t

/2) + 2 (t

/2) – 1.25 (t

/2) + 1 ns

DLACLK

LCLK Low Delay After LACK High

/2) + 8.5 (3 × t

/2) + 17 (t

/2) + 8 (3 × t

/2) + 17.5 ns

ENDLK

LACK Enable From CLKIN 5 + DT/2 5 + DT/2 ns

TDLK

LACK Disable From CLKIN 20 + DT/2 20 + DT/2 ns

For ADSP-21060L/ADSP-21060LC, specification is 20 ns min.

For ADSP-21060L, specification is 16.5 ns max; for ADSP-21060LC, specification is 16.75 ns max.

For ADSP-21062, specification is 2.5 ns max.

For ADSP-21062, specification is (t

/2) – 1 ns min, (t

/2) + 1.25 ns max; for ADSP-21062L, specification is (t

/2) – 1 ns min, (t

/2) + 1.5 ns max; for ADSP-21060LC

specification is (t

/2) – 1 ns min, (t

/2) + 2.25 ns max.

For ADSP-21062, specification is (t

/2) – 1.25 ns min, (t

/2) + 1 ns max; for ADSP-21062L, specification is (t

/2) – 1.5 ns min, (t

/2) + 1 ns max; for ADSP-21060C

specification is (t

/2) – 2.25 ns min, (t

/2) + 1 ns max.

For ADSP-21062, specification is (t

/2) + 8.75 ns min, (3 × t

/2) + 17 ns max; for ADSP-21062L, specification is (t

/2) + 8 ns min, (3 × t

/2) + 17 ns max; for

ADSP-21060LC specification is (t

/2) + 8 ns min, (3 × t

/2) + 18.5 ns max.

Rev. G | Page 40 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Link Ports —2 × CLK Speed Operation

Calculation of link receiver data setup and hold relative to link

clock is required to determine the maximum allowable skew

that can be introduced in the transmission path between

LDATA and LCLK. Setup skew is the maximum delay that can

be introduced in LDATA relative to LCLK:

Setup Skew = t

LCLKTWH

min – t

DLDCH

– t

SLDCL

Hold skew is the maximum delay that can be introduced in

LCLK relative to LDATA:

Hold Skew = t

LCLKTWL

min – t

HLDCH

– t

HLDCL

Calculations made directly from 2 speed specifications will

result in unrealistically small skew times because they include

multiple tester guardbands.

Note that link port transfers at 2× CLK speed at 40 MHz

= 25 ns) may fail. However, 2× CLK speed link port trans-

fers at 33 MHz (t

= 30 ns) work as specified.

Table 25. Link Port Service Request Interrupts:1× and 2× Speed Operations

5 V 3.3 V

Unit

Parameter Min Max Min Max

Timing Requirements

SLCK

LACK/LCLK Setup Before CLKIN Low

10 10 ns

HLCK

LACK/LCLK Hold After CLKIN Low

22ns

Only required for interrupt recognition in the current cycle.

Table 26. Link Ports—Receive

5 V 3.3 V

Unit

Parameter Min Max Min Max

Timing Requirements

SLDCL

Data Setup Before LCLK Low 2.5 2.25 ns

HLDCL

Data Hold After LCLK Low 2.25 2.25 ns

LCLKIW

LCLK Period (2× Operation) t

/2 t

/2 ns

LCLKRWL

LCLK Width Low

4.5 5.25 ns

LCLKRWH

LCLK Width High

4.25 4 ns

Switching Characteristics

DLAHC

LACK High Delay After CLKIN High

18 + DT/2 28.5 + DT/2 18 + DT/2 29.5 + DT/2 ns

DLALC

LACK Low Delay After LCLK High

616616ns

For ADSP-21060L, specification is 5 ns min.

For ADSP-21062, specification is 4 ns min, for ADSP-21060LC, specification is 4.5 ns min.

LACK goes low with t

DLALC

relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.

For ADSP-21060L, specification is 6 ns min, 18 ns max. For ADSP-21060C, specification is 6 ns min, 16.5 ns max. For ADSP-21060LC, specification is 6 ns min, 18.5 ns max.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 41 of 64 | August 2010

Table 27. Link Ports—Transmit

5 V 3.3 V

Unit

Parameter Min Max Min Max

Timing Requirements

SLACH

LACK Setup Before LCLK High 19 19 ns

HLACH

LACK Hold After LCLK High –6.75 –6.5 ns

Switching Characteristics

DLCLK

Data Delay After CLKIN 8 8 ns

DLDCH

Data Delay After LCLK High

2.25 2.25 ns

HLDCH

Data Hold After LCLK High

–2.0 –2 ns

LCLKTWL

LCLK Width Low

/4) – 1 (t

/4) + 1.25 (t

/4) – 0.75 (t

/4) + 1.5 ns

LCLKTWH

LCLK Width High

/4) – 1.25 (t

/4) + 1 (t

/4) – 1.5 (t

/4) + 1 ns

DLACLK

LCLK Low Delay After LACK High (t

/4) + 9 (3 × t

/4) + 16.5 (t

/4) + 9 (3 × t

/4) + 16.5 ns

For ADSP-21060/ADSP-21060C, specification is 2.5 ns max.

For ADSP-21062L, specification is –2.25 ns min.

For ADSP-21060, specification is (t

/4) – 1ns min, (t

/4) + 1 ns max; for ADSP-21060C/ADSP-21062L, specification is (t

/4) – 1 ns min, (t

/4) + 1.5 ns max.

For ADSP-21060, specification is (t

/4) – 1 ns min, (t

/4) + 1 ns max; for ADSP-21060C, specification is (t

/4) – 1.5 ns min, (t

/4) + 1 ns max.

Rev. G | Page 42 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Figure 24. Link Ports—Receive

CLKIN

LCLK

LDAT(3:0)

LACK

LCLK 1x

LCLK 2x

CLKIN

LDAT(3:0)

LACK (IN)

LCLK 1x

LCLK 2x

LDAT(3:0)

LACK (OUT)

THE

SLACH

REQUIREMENT APPLIESTO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.

CLKIN

TRANSMIT

tDLDCH

tHLDCH

tDLCLK

tLCLKTWH tLCLKTWL

tSLACH tHLACH

tDLACLK

tSLDCL

tHLDCL

tLCLKRWH

tDLAHC

tDLALC

LINK PORT ENABLE OR THREE-STATE TAKESEFFECT 2 CYCLESAFTERAWRITETOALINKPORTCONTROLREGISTER.

tENDLK tTDLK

RECEIVE

LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION

tLCLKRWL

tLCLKIW

CLKIN

tSLCK

tHLCK

LINK PORT INTERRUPT SETUP TIME

LCLK

LASTNIBBLE

TRANSMITTED

FIRSTNIBBLE

TRANSMITTED

LCLK INACTIVE

(HIGH)

OUT

LACK

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 43 of 64 | August 2010

Serial Ports

For serial ports, see Table 28, Table 29, Table 30, Table 31,

Table 32, Table 33, Table 35, Figure 26, and Figure 25. To deter-

mine whether communication is possible between two devices

at clock speed n, the following specifications must be confirmed:

1) frame sync delay and frame sync setup and hold, 2) data delay

and data setup and hold, and 3) SCLK width.

Table 28. Serial Ports—External Clock

Parameter

5 V and 3.3 V

Min Max Unit

Timing Requirements

SFSE

TFS/RFS Setup Before TCLK/RCLK

3.5 ns

HFSE

TFS/RFS Hold After TCLK/RCLK

4ns

SDRE

Receive Data Setup Before RCLK

1.5 ns

HDRE

Receive Data Hold After RCLK

6.5 ns

SCLKW

TCLK/RCLK Width

9ns

SCLK

TCLK/RCLK Period t

Referenced to sample edge.

RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.

For ADSP-21060/ADSP-21060C/ADSP-21060LC, specification is 9.5 ns min.

Table 29. Serial Ports—Internal Clock

Parameter

5 V and 3.3 V

Min Max Unit

Timing Requirements

SFSI

TFS Setup Before TCLK

; RFS Setup Before RCLK

8ns

HFSI

TFS/RFS Hold After TCLK/RCLK

1ns

SDRI

Receive Data Setup Before RCLK

3ns

HDRI

Receive Data Hold After RCLK

3ns

Referenced to sample edge.

RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.

Table 30. Serial Ports—External or Internal Clock

Parameter

5 V and 3.3 V

Min Max Unit

Switching Characteristics

DFSE

RFS Delay After RCLK (Internally Generated RFS)

13 ns

HOFSE

RFS Hold After RCLK (Internally Generated RFS)

3ns

Referenced to drive edge.

Table 31. Serial Ports—External Clock

Parameter

5 V and 3.3 V

Min Max Unit

Switching Characteristics

DFSE

TFS Delay After TCLK (Internally Generated TFS)

13 ns

HOFSE

TFS Hold After TCLK (Internally Generated TFS)

3ns

DDTE

Transmit Data Delay After TCLK

16 ns

HDTE

Transmit Data Hold After TCLK

5ns

Referenced to drive edge.

Rev. G | Page 44 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Table 32. Serial Ports—Internal Clock

Parameter Min Max Unit

Switching Characteristics

DFSI

TFS Delay After TCLK (Internally Generated TFS)

4.5 ns

HOFSI

TFS Hold After TCLK (Internally Generated TFS)

–1.5 ns

DDTI

Transmit Data Delay After TCLK

7.5 ns

HDTI

Transmit Data Hold After TCLK

0ns

SCLKIW

TCLK/RCLK Width

0.5t

SCLK

–2.5 0.5t

SCLK

+2.5 ns

Referenced to drive edge.

For ADSP-21060L/ADSP-21060C, specification is 0.5

TSCLK

– 2 ns min, 0.5t

SCLK

+ 2 ns max.

Table 33. Serial Ports—Enable and Three-State

Parameter Min Max Unit

Switching Characteristics

DDTEN

Data Enable from External TCLK

4ns

DDTTE

Data Disable from External TCLK

10.5 ns

DDTIN

Data Enable from Internal TCLK

0ns

DDTTI

Data Disable from Internal TCLK

3ns

DCLK

TCLK/RCLK Delay from CLKIN 22 + 3 DT/8 ns

DPTR

SPORT Disable After CLKIN 17 ns

Referenced to drive edge.

For ADSP-21060L/ADSP-21060C, specification is 3.5 ns min; for ADSP-21062 specification is 4.5 ns min.

For ADSP-21062L, specification is 16 ns max.

For ADSP-21062L, specification is 7.5 ns max.

Table 34. Serial Ports—GATED SCLK with External TFS (Mesh Multiprocessing)

Parameter Min Max Unit

Switching Characteristics

STFSCK

TFS Setup Before CLKIN 4 ns

HTFSCK

TFS Hold After CLKIN t

/2 ns

Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems.

Table 35. Serial Ports—External Late Frame Sync

Parameter Min Max Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External TFS or External RFS with MCE = 1,

MFD = 0

12 ns

DDTENFS

Data Enable from Late FS or MCE = 1, MFD = 0

3.5 ns

MCE = 1, TFS enable and TFS valid follow t

DDTLFSE

and t

DDTENFS

For ADSP-21062/ADSP-21062L, specification is 12.75 ns max; for ADSP-21060L/ADSP-21060LC, specification is 12.8 ns max.

For ADSP-21060/ADSP-21060C, specification is 3 ns min.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 45 of 64 | August 2010

Figure 25. Serial Ports

DRIVE EDGE DRIVE EDGE

DRIVE

EDGE

DRIVE

EDGE

TCLK/RCLK

TCLK

(INT)

TCLK/RCLK

TCLK

(EXT)

RCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

DATA RECEIVE— INTERNAL CLOCK DATA RECEIVE— EXTERNAL CLOCK

RCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED ASTHE ACTIVE SAMPLING EDGE.

TCLK

TFS

DRIVE

EDGE

SAMPLE

EDGE

TCLK

TFS

DRIVE

EDGE

SAMPLE

EDGE

DATA TRANSMIT— INTERNAL CLOCK DATA TRANSMIT— EXTERNAL CLOCK

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED ASTHE ACTIVE SAMPLING EDGE.

tDDTTE

tDDTEN

tDDTTI

tDDTIN

tSDRI tHDRI

tSFSItHFSI

tDFSE

tHOFSE

tSCLKIW

tSDRE tHDRE

tSFSEtHFSE

tDFSE

tSCLKW

tHOFSE

tDDTI

tHDTI

tSFSItHFSI

tSCLKIW

tDFSI

tHOFSI

tDDTE

tHDTE

tSFSEtHFSE

tDFSE

tSCLKW

tHOFSE

CLKIN

tDPTR

SPORT DISABLE DELAY

FROM INSTRUCTION

TCLK, RCLK

TFS,RFS,DT

TCLK (INT)

RCLK (INT)

SPORT ENABLE AND

THREE-STATE

LATENCY

ISTWO CYCLES

tDCLK

LOW TO HIGH ONLY

tSTFSCK

CLKIN tHTFSCK

NOTE: APPLIESONLY TO GATED SERIAL CLOCK MODE WITH

EXTERNAL TFS,ASUSED IN THE SERIAL PORT SYSTEM I/O

FOR MESHMULTIPROCESSING.

TFS(EXT)

Rev. G | Page 46 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Figure 26. Serial Ports—External Late Frame Sync

DRIVE SAMPLE DRIVE

TCLK

TFS

DRIVE SAMPLE DRIVE

LATE EXTERNAL TFS

EXTERNAL RFSWITH MCE = 1, MFD = 0

1ST BIT 2ND BITDT

RCLK

RFS

1ST BIT 2ND BIT

tHOFSE/I

tSFSE/I

tDDTE/I

tDDTENFS

tDDTLFSE

tHDTE/I

tHOFSE/I

tSFSE/I

tDDTE/I

TDDTENFS

tDDTLFSE

tHDTE/I

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 47 of 64 | August 2010

JTAG Test Access Port and Emulation

For JTAG Test Access Port and Emulation, see Table 36 and

Figure 27.

Table 36. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

TCK

TCK Period t

STAP

TDI, TMS Setup Before TCK High 5 ns

HTAP

TDI, TMS Hold After TCK High 6 ns

SSYS

System Inputs Setup Before TCK Low

7ns

HSYS

System Inputs Hold After TCK Low

18 ns

TRSTW

TRST Pulse Width 4t

Switching Characteristics

DTDO

TDO Delay from TCK Low 13 ns

DSYS

System Outputs Delay After TCK Low

18.5 ns

System Inputs = DATA63–0, ADDR31–0, RD, WR, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, PA, BRST, DR0, DR1, TCLK0,

TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.

For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is 18.5 ns min.

System Outputs = DATA63–0, ADDR31–0, MS3–0, RD, WR, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, FLAG3–0, TIMEXP, DT0,

DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS.

Figure 27. JTAG Test Access Port and Emulation

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tSTAP

tTCK

tHTAP

tDTDO

tSSYStHSYS

tDSYS

Rev. G | Page 48 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

TEST CONDITIONS

For the ac signal specifications (timing parameters), see Timing

Specifications on Page 21. These specifications include output

disable time, output enable time, and capacitive loading. The

timing specifications for the DSP apply for the voltage reference

levels in Figure 28.

Output Disable Time

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The time for the voltage on the bus

to decay by ΔV is dependent on the capacitive load, C

, and the

load current, I

. This decay time can be approximated by the fol-

lowing equation:

The output disable time t

DIS

is the difference between

MEASURED

and t

DECAY

as shown in Figure 29. The time t

MEASURED

the interval from when the reference signal switches to when the

output voltage decays ΔV from the measured output high or

output low voltage. t

DECAY

is calculated with test loads C

and I

and with ΔV equal to 0.5 V.

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high impedance state to when they start driv-

ing. The output enable time t

ENA

is the interval from when a

reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram (Figure 29). If multiple

pins (such as the data bus) are enabled, the measurement value

is that of the first pin to start driving.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t

DECAY

using the equation given above. Choose ΔV

to be the difference between the ADSP-2106x’s output voltage

and the input threshold for the device requiring the hold time. A

typical ΔV will be 0.4 V. C

is the total bus capacitance (per data

line), and I

is the total leakage or three-state current (per data

line). The hold time will be t

DECAY

plus the minimum disable

time (i.e., t

DATRWH

for the write cycle).

Capacitive Loading

Output delays and holds are based on standard capacitive loads:

50 pF on all pins (see Figure 30). The delay and hold specifica-

tions given should be derated by a factor of 1.5 ns/50 pF for

loads other than the nominal value of 50 pF. Figure 32,

Figure 33, Figure 37, and Figure 38 show how output rise time

varies with capacitance. Figure 34 and Figure 36 show

graphically how output delays and holds vary with load capaci-

tance. (Note that this graph or derating does not apply to output

disable delays; see the previous section Output Disable Time

under Test Conditions.) The graphs of Figure 32, Figure 33,

Figure 37, and Figure 38 may not be linear outside the ranges

shown.

Output Drive Characteristics

Figure 31 shows typical I-V characteristics for the output driv-

ers of the ADSP-2106x. The curves represent the current drive

capability of the output drivers as a function of output voltage.

Figure 28. Voltage Reference Levels for AC Measurements (Except Output

Enable/Disable)

Figure 29. Output Enable/Disable

INPUT

OUTPUT 1.5V 1.5V

PEXT

CLVΔ

--------------

REFERENCE

SIGNAL

tDIS

OUTPUT STARTS

DRIVING

VOH (MEASURED) -DV

VOL (MEASURED) +DV

tMEASURED

VOH (MEASURED)

VOL (MEASURED)

2.0V

1.0V

VOH (MEASURED)

VOL (MEASURED)

HIGH IMPEDANCE STATE.

TESTCONDITIONSCAUSE

THISVOLTAGE TO BE

APPROXIMATELY 1.5V

OUTPUT STOPS

DRIVING

tENA

tDECAY

Figure 30. Equivalent Device Loading for AC Measurements (Includes All

Fixtures)

+1.5V

50pF

OUTPUT

IOL

IOH

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 49 of 64 | August 2010

Output Characteristics (5 V)

Figure 31. ADSP-21062 Typical Output Drive Currents (V

= 5 V)

Figure 32. Typical Output Rise Time (10% to 90% V

) vs. Load Capacitance

= 5 V)

SOURCE VOLTAGE

15005.25

SOURCECURRENT

0.75 1.50 2.25 3.00 3.75 4.50

100

125

4.75V, +100°C

4.75V,+100°C

5.0V, +25°C

5.25V,

40°C

5.0V, +25°C

5.25V,

40°C

LOAD CAPACITANCE

16.0

8.0

0020020 40 60 80 100 120 140 160 180

14.0

12.0

4.0

2.0

10.0

6.0

FALL TIM E

RISETIME

RISEANDFALLTIMES

(0.5Vto4.5V

,10%to90%)

Y = 0.005x + 3.7

Y = 0.0031x + 1.1

Figure 33. Typical Output Rise Time (0.8 V to 2.0 V) vs. Load Capacitance

= 5 V)

Figure 34. Typical Output Delay or Hold vs. Load Capacitance (at Maximum

Case Temperature) (V

= 5 V)

3.5

RISEANDFALLTIMES

ns(0.8Vto2.0V)

3.0

2.5

2.0

1.5

1.0

0.5

LOAD CAPACITANCE

020020 40 60 80 100 120 140 160 180

FALL TIME

RISETIME

Y = 0.009x + 1.1

Y=0.005x+0.6

LOAD CAPACITANCE

OUTPUTDELAYORHOLD

25 20050 75 100 125 150 175

NOMINAL

Y=0.03x

1.45

Rev. G | Page 50 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Output Characteristics (3.3 V)

Figure 35. ADSP-21062 Typical Output Drive Currents (V

= 3.3 V)

Figure 36. Typical Output Delay or Hold vs. Load Capacitance (at Maximum

Case Temperature) (V

= 3.3 V)

SOURCE VOLTAGE

120

03.5

SOURCECURRENT

0.5 1.0 1.5 2.0 2.5 3.0

100

120

3.0V, +85°C

3.3V, +25°C

3.6V,

40°C

3.6V,

40°C

3.3V, +25°C

3.0V, +85°C VOH

VOL

LOAD CAPACITANCE

OUTPUTDELA

YORHOLD

25 20050 75 100 125 150 175

NOMINAL

Y=0.0329x

1.65

Figure 37. Typical Output Rise Time (10% to 90% V

) vs. Load Capacitance

= 3.3 V)

Figure 38. Typical Output Rise Time (0.8 V to 2.0 V) vs. Load Capacitance

= 3.3 V)

LOAD CAPACITANCE

20 40 60 80 100 120

Y = 0.0796x + 1.17

Y = 0.0467x + 0.55

RISETIME

FALL TIME

140 160 180 200

RISEANDFALLTIMES

ns(10%to90%)

LOAD CAPACITANCE

020 40 60 80 100 120

Y=0.0391x + 0.36

Y=0.0305x + 0.24

RISETIME

FALL TIME

140 160 180200

RISEANDFALLTIMES

ns(0.8Vto2.0V)

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 51 of 64 | August 2010

ENVIRONMENTAL CONDITIONS

The ADSP-2106x processors are rated for performance under

CASE

environmental conditions specified in the Operating Con-

ditions (5 V) on Page 15 and Operating Conditions (3.3 V) on

Page 18.

Thermal Characteristics for MQFP_PQ4 and PBGA

Packages

The ADSP-21060/ADSP-21060L and ADSP-21062/ADSP-

21062L are available in 240-lead thermally enhanced

MQFP_PQ4 and 225-ball plastic ball grid array packages. The

top surface of the thermally enhanced MQFP_PQ4 contains a

metal slug from which most of the die heat is dissipated. The

slug is flush with the top surface of the package. Note that the

metal slug is internally connected to GND through the device

substrate.

Both packages are specified for a case temperature (T

CASE

). To

ensure that the T

CASE

is not exceeded, a heatsink and/or an air-

flow source may be used. A heatsink should be attached with a

thermal adhesive.

CASE

= T

AMB

+ (PD × θ

)

CASE

= Case temperature (measured on top surface of package)

PD =Power dissipation in W (this value depends upon the spe-

cific application; a method for calculating PD is shown under

Power Dissipation).

=Value from Table 37 below.

Thermal Characteristics for CQFP Package

The ADSP-21060C/ADSP-21060LC are available in 240-lead

thermally enhanced ceramic QFP (CQFP). There are two pack-

age versions, one with a copper/tungsten heat slug on top of the

package (CZ) for air cooling, and one with the heat slug on the

bottom (CW) for cooling through the board. The ADSP-2106x

is specified for a case temperature (T

CASE

). To ensure that the

CASE

data sheet specification is not exceeded, a heatsink and/or

an air flow source may be used. A heatsink should be attached

with a thermal adhesive.

CASE

= T

AMB

+ (PD × θ

)

CASE

= Case temperature (measured on top surface of package)

PD = Power dissipation in W (this value depends upon the spe-

cific application; a method for calculating PD is shown under

Power Dissipation).

=Value from Table 38 below.

Table 37. Thermal Characteristics for Thermally Enhanced

240-Lead MQFP_PQ4

This represents thermal resistance at total power of 5 W. With airflow, no

variance is seen in θ

at 5 W.

at 0 LFM varies with power:

at 2 W, θ

= 14°C/W

at 3 W, θ

= 11°C/W

Parameter Airflow (LFM

)

LFM = Linear feet per minute of airflow.

Typical Unit

010°C/W

100 9 °C/W

200 8 °C/W

400 7 °C/W

600 6 °C/W

Table 38. Thermal Characteristics for BGA

Parameter Airflow (LFM

)

LFM = Linear feet per minute of airflow.

Typical Unit

020.70°C/W

200 15.30 °C/W

400 12.90 °C/W

Table 39. Thermal Characteristics for Thermally Enhanced

240-Lead CQFP

This represents thermal resistance at total power of 5 W. With airflow, no

variance is seen in θ

at 5W.

at 0 LFM varies with power.

ADSP-21060CW/ADSP-21060LCW:

at 2 W, θ

= 23°C/W

at 3 W, θ

= 21.5°C/W

ADSP-21060CZ/ADSP-21060LCZ:

at 2 W, θ

= 24°C/W

at 3 W, θ

= 21.5°C/W

= 0.24°C/W for all CQFP models.

Parameter Airflow (LFM

)

LFM = Linear feet per minute of airflow.

Typical Unit

ADSP-21060CW/ADSP-21060LCW

0 19.5 °C/W

100 16 °C/W

200 14 °C/W

400 12 °C/W

600 10 °C/W

ADSP-21060CZ/ADSP-21060LCZ

0 20 °C/W

100 16 °C/W

200 14 °C/W

400 11.5 °C/W

600 9.5 °C/W

Rev. G | Page 52 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

225-BALL PBGA BALL CONFIGURATION

Table 40. ADSP-2106x 225-Ball Metric PBGA Ball Assignments (B-225-2)

Ball Name

Ball

Number Ball Name

Ball

Number Ball Name

Ball

Number Ball Name

Ball

Number Ball Name

Ball

Number

BMS A01 ADDR25 D01 ADDR14 G01 ADDR6 K01 EMU N01

ADDR30 A02 ADDR26 D02 ADDR15 G02 ADDR5 K02 TDO N02

DMAR2 A03 MS2 D03 ADDR16 G03 ADDR3 K03 IRQ0 N03

DT1 A04 ADDR29 D04 ADDR19 G04 ADDR0 K04 IRQ1 N04

RCLK1 A05 DMAR1 D05 GND G05 ICSA K05 ID2 N05

TCLK0 A06 TFS1 D06 V

G06 GND K06 L5DAT1 N06

RCLK0 A07 CPA D07 V

G07 V

K07 L4CLK N07

ADRCLK A08 HBG D08 V

G08 V

K08 L3CLK N08

CS A09 DMAG2 D09 V

G09 V

K09 L3DAT3 N09

CLKIN A10 BR5 D10 V

G10 GND K10 L2DAT0 N10

PAGE A11 BR1 D11 GND G11 GND K11 L1ACK N11

BR3 A12 DATA40 D12 DATA22 G12 DATA8 K12 L1DAT3 N12

DATA47 A13 DATA37 D13 DATA25 G13 DATA11 K13 L0DAT3 N13

DATA44 A14 DATA35 D14 DATA24 G14 DATA13 K14 DATA1 N14

DATA42 A15 DATA34 D15 DATA23 G15 DATA14 K15 DATA3 N15

MS0 B01 ADDR21 E01 ADDR12 H01 ADDR2 L01 TRST P01

SW B02 ADDR22 E02 ADDR11 H02 ADDR1 L02 TMS P02

ADDR31 B03 ADDR24 E03 ADDR13 H03 FLAG0 L03 EBOOT P03

HBR B04 ADDR27 E04 ADDR10 H04 FLAG3 L04 ID0 P04

DR1 B05 GND E05 GND H05 RPBA L05 L5CLK P05

DT0 B06 GND E06 V

H06 GND L06 L5DAT3 P06

DR0 B07 GND E07 V

H07 GND L07 L4DAT0 P07

REDY B08 GND E08 V

H08 GND L08 L4DAT3 P08

RD B09 GND E09 V

H09 GND L09 L3DAT2 P09

ACK B10 GND E10 V

H10 GND L10 L2CLK P10

BR6 B11 NC E11 GND H11 NC L11 L2DAT2 P11

BR2 B12 DATA33 E12 DATA18 H12 DATA4 L12 L1DAT0 P12

DATA45 B13 DATA30 E13 DATA19 H13 DATA7 L13 L0ACK P13

DATA43 B14 DATA32 E14 DATA21 H14 DATA9 L14 L0DAT1 P14

DATA39 B15 DATA31 E15 DATA20 H15 DATA10 L15 DATA0 P15

MS3 C01 ADDR17 F01 ADDR9 J01 FLAG1 M01 TCK R01

MS1 C02 ADDR18 F02 ADDR8 J02 FLAG2 M02 IRQ2 R02

ADDR28 C03 ADDR20 F03 ADDR7 J03 TIMEXP M03 RESET R03

SBTS C04 ADDR23 F04 ADDR4 J04 TDI M04 ID1 R04

TCLK1 C05 GND F05 GND J05 LBOOT M05 L5DAT0 R05

RFS1 C06 GND F06 V

J06 L5ACK M06 L4ACK R06

TFS0 C07 V

F07 V

J07 L5DAT2 M07 L4DAT1 R07

RFS0 C08 V

F08 V

J08 L4DAT2 M08 L3ACK R08

WR C09 V

F09 V

J09 L3DAT0 M09 L3DAT1 R09

DMAG1 C10 GND F10 V

J10 L2DAT3 M10 L2ACK R10

BR4 C11 GND F11 GND J11 L1DAT1 M11 L2DAT1 R11

DATA46 C12 DATA29 F12 DATA12 J12 L0DAT0 M12 L1CLK R12

DATA41 C13 DATA26 F13 DATA15 J13 DATA2 M13 L1DAT2 R13

DATA38 C14 DATA28 F14 DATA16 J14 DATA5 M14 L0CLK R14

DATA36 C15 DATA27 F15 DATA17 J15 DATA6 M15 L0DAT2 R15

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 53 of 64 | August 2010

Figure 39. ADSP-21060/ADSP-21062 PBGA Ball Assignments (Top View, Summary)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

ADRCLK BMSADDR30

DMAR2

DT1RCLK1TCLK0RCLK0CSCLKINPAGEBR3DATA47DATA44DATA42

MS0SWADDR31HBRDR1DT0DR0REDYRDACKBR6BR2DATA45DATA43DATA39

MS3MS1

ADDR28

SBTS

TCLK1RFS1TFS0RFS0WRDMAG1BR4DATA46DATA41DATA38DATA36

ADDR25ADDR26

MS2

ADDR29

DMAR1

TFS1

CPA

HBG

DMAG2BR5

BR1DATA40DATA37DATA35DATA34

ADDR21ADDR22ADDR24ADDR27GNDGNDGNDGNDGNDGNDNCDATA33DATA30DATA32DATA31

ADDR17ADDR18ADDR20ADDR23GNDGNDVDDVDDVDDGNDGNDDATA29DATA26DATA28DATA27

ADDR14ADDR15ADDR16ADDR19GNDVDDVDDVDDVDDVDDGNDDATA22DATA25DATA24DATA23

ADDR12ADDR11ADDR13ADDR10GNDVDDVDDVDDVDDVDDGNDDATA18DATA19DATA21DATA20

ADDR9ADDR8ADDR7ADDR4GNDVDDVDDVDDVDDVDDGNDDATA12DATA15DATA16DATA17

ADDR6ADDR5ADDR3ADDR0ICSAGNDVDDVDDVDDGNDGNDDATA 8DATA11DATA13DATA14

ADDR2ADDR1FLAG0FLAG3RPBAGNDGNDGNDGNDGNDNCDATA 4DATA7DATA9DATA10

FLAG1FLAG2TIMEXPTDILBOOTL5ACKL5DAT2L4DAT2L3DAT0L2DAT3L1DAT1L0DAT0DATA2DATA 5DATA 6

EMUTDOIRQ0

IRQ1

ID2L5DAT1L4CLKL3CLKL3DAT3L2DAT0L1ACKL1DAT3L0DAT3DATA1DATA3

TRST

TMSEBOOTID0L5CLKL5DAT3L4DAT0L4DAT3L3DAT2L2CLKL2DAT2L1DAT0L0ACKL0DAT1DATA0

TCK

IRQ2RESET

ID1L5DAT0L4ACKL4DAT1L3ACKL0DAT2 L0CLK L1DAT2 L1CLK L2DAT1 L2ACK L3DAT1

Rev. G | Page 54 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

240-LEAD MQFP_PQ4/CQFP PIN CONFIGURATION

Table 41. ADSP-2106x MQFP_PQ4 and ADSP-21060CZ CQFP Pin Assignments (SP-240-2, QS-240-2A, QS-240-2B)

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

TDI 1 ADDR20 41 TCLK0 81 DATA41 121 DATA14 161 L2DAT0 201

TRST 2 ADDR21 42 TFS0 82 DATA40 122 DATA13 162 L2CLK 202

3GND43 DR0 83 DATA39 123 DATA12 163 L2ACK 203

TDO 4 ADDR22 44 RCLK0 84 V

124 GND 164 NC 204

TIMEXP 5 ADDR23 45 RFS0 85 DATA38 125 DATA11 165 V

205

EMU 6ADDR2446V

86 DATA37 126 DATA10 166 L3DAT3 206

ICSA 7 V

47 V

87 DATA36 127 DATA9 167 L3DAT2 207

FLAG3 8 GND 48 GND 88 GND 128 V

168 L3DAT1 208

FLAG2 9 V

49 ADRCLK 89 NC 129 DATA8 169 L3DAT0 209

FLAG1 10 ADDR25 50 REDY 90 DATA35 130 DATA7 170 L3CLK 210

FLAG011ADDR2651HBG 91 DATA34 131 DATA6 171 L3ACK 211

GND12ADDR2752CS 92 DATA33 132 GND 172 GND 212

ADDR0 13 GND 53 RD 93 V

133 DATA5 173 L4DAT3 213

ADDR1 14 MS3 54 WR 94 V

134 DATA4 174 L4DAT2 214

15 MS2 55 GND 95 GND 135 DATA3 175 L4DAT1 215

ADDR2 16 MS1 56 V

96 DATA32 136 V

176 L4DAT0 216

ADDR3 17 MS0 57 GND 97 DATA31 137 DATA2 177 L4CLK 217

ADDR4 18 SW 58 CLKIN 98 DATA30 138 DATA1 178 L4ACK 218

GND 19 BMS 59 ACK 99 GND 139 DATA0 179 V

219

ADDR520ADDR2860DMAG2

100 DATA29 140 GND 180 GND 220

ADDR6 21 GND 61 DMAG1 101 DATA28 141 GND 181 V

221

ADDR7 22 V

62 PAGE 102 DATA27 142 L0DAT3 182 L5DAT3 222

23 V

63 V

103 V

143 L0DAT2 183 L5DAT2 223

ADDR824ADDR2964BR6 104 V

144 L0DAT1 184 L5DAT1 224

ADDR925ADDR3065BR5 105 DATA26 145 L0DAT0 185 L5DAT0 225

ADDR10 26 ADDR31 66 BR4 106 DATA25 146 L0CLK 186 L5CLK 226

GND 27 GND 67 BR3 107 DATA24 147 L0ACK 187 L5ACK 227

ADDR11 28 SBTS 68 BR2 108 GND 148 V

188 GND 228

ADDR12 29 DMAR2 69 BR1 109 DATA23 149 L1DAT3 189 ID2 229

ADDR13 30 DMAR1 70 GND 110 DATA22 150 L1DAT2 190 ID1 230

31 HBR 71 V

111 DATA21 151 L1DAT1 191 ID0 231

ADDR14 32 DT1 72 GND 112 V

152 L1DAT0 192 LBOOT 232

ADDR15 33 TCLK1 73 DATA47 113 DATA20 153 L1CLK 193 RPBA 233

GND 34 TFS1 74 DATA46 114 DATA19 154 L1ACK 194 RESET 234

ADDR16 35 DR1 75 DATA45 115 DATA18 155 GND 195 EBOOT 235

ADDR17 36 RCLK1 76 V

116 GND 156 GND 196 IRQ2 236

ADDR18 37 RFS1 77 DATA44 117 DATA17 157 V

197 IRQ1 237

38 GND 78 DATA43 118 DATA16 158 L2DAT3 198 IRQ0 238

39 CPA 79 DATA42 119 DATA15 159 L2DAT2 199 TCK 239

ADDR19 40 DT0 80 GND 120 V

160 L2DAT1 200 TMS 240

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 55 of 64 | August 2010

Table 42. ADSP-21060CW/21060LCW CQFP Pin Assignments (QS-240-1A, QS-240-1B)

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

GND 1 DATA29 41 DMAG2 81 ADDR28 121 ADDR5 161 GND 201

DATA0 2 GND 42 ACK 82 BMS 122 GND 162 V

202

DATA1 3 DATA30 43 CLKIN 83 SW 123 ADDR4 163 L4ACK 203

DATA2 4 DATA31 44 GND 84 MS0 124 ADDR3 164 L4CLK 204

5DATA3245V

85 MS1 125 ADDR2 165 L4DAT0 205

DATA3 6 GND 46 GND 86 MS2 126 V

166 L4DAT1 206

DATA4 7 V

47 WR 87 MS3 127 ADDR1 167 L4DAT2 207

DATA5 8 V

48 RD 88 GND 128 ADDR0 168 L4DAT3 208

GND 9 DATA33 49 CS 89 ADDR27 129 GND 169 GND 209

DATA610DATA3450HBG 90 ADDR26 130 FLAG0 170 L3ACK 210

DATA7 11 DATA35 51 REDY 91 ADDR25 131 FLAG1 171 L3CLK 211

DATA812NC 52ADRCLK92V

132 FLAG2 172 L3DAT0 212

13 GND 53 GND 93 GND 133 FLAG3 173 L3DAT1 213

DATA914DATA3654V

94 V

134 ICSA 174 L3DAT2 214

DATA10 15 DATA37 55 V

95 ADDR24 135 EMU 175 L3DAT3 215

DATA11 16 DATA38 56 RFS0 96 ADDR23 136 TIMEXP 176 V

216

GND 17 V

57 RCLK0 97 ADDR22 137 TDO 177 NC 217

DATA12 18 DATA39 58 DR0 98 GND 138 V

178 L2ACK 218

DATA13 19 DATA40 59 TFS0 99 ADDR21 139 TRST 179 L2CLK 219

DATA14 20 DATA41 60 TCLK0 100 ADDR20 140 TDI 180 L2DAT0 220

21 GND 61 DT0 101 ADDR19 141 TMS 181 L2DAT1 221

DATA15 22 DATA42 62 CPA 102 V

142 TCK 182 L2DAT2 222

DATA16 23 DATA43 63 GND 103 V

143 IRQ0 183 L2DAT3 223

DATA17 24 DATA44 64 RFS1 104 ADDR18 144 IRQ1 184 V

224

GND 25 V

65 RCLK1 105 ADDR17 145 IRQ2 185 GND 225

DATA18 26 DATA45 66 DR1 106 ADDR16 146 EBOOT 186 GND 226

DATA19 27 DATA46 67 TFS1 107 GND 147 RESET 187 L1ACK 227

DATA20 28 DATA47 68 TCLK1 108 ADDR15 148 RPBA 188 L1CLK 228

29 GND 69 DT1 109 ADDR14 149 LBOOT 189 L1DAT0 229

DATA21 30 V

70 HBR 110 V

150 ID0 190 L1DAT1 230

DATA22 31 GND 71 DMAR1 111 ADDR13 151 ID1 191 L1DAT2 231

DATA23 32 BR1 72 DMAR2 112 ADDR12 152 ID2 192 L1DAT3 232

GND 33 BR2 73 SBTS 113 ADDR11 153 GND 193 V

233

DATA24 34 BR3 74 GND 114 GND 154 L5ACK 194 L0ACK 234

DATA25 35 BR4 75 ADDR31 115 ADDR10 155 L5CLK 195 L0CLK 235

DATA26 36 BR5 76 ADDR30 116 ADDR9 156 L5DAT0 196 L0DAT0 236

37 BR6 77 ADDR29 117 ADDR8 157 L5DAT1 197 L0DAT1 237

38 V

78 V

118 V

158 L5DAT2 198 L0DAT2 238

DATA27 39 PAGE 79 V

119 ADDR7 159 L5DAT3 199 L0DAT3 239

DATA28 40 DMAG1 80 GND 120 ADDR6 160 V

200 GND 240

Rev. G | Page 56 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

OUTLINE DIMENSIONS

Figure 40. 225-Ball Plastic Ball Grid Array [PBGA]

(B-225-2)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MS-034-AAJ-2

2.70 MAX

1.27

BSC

18.00

BSC SQ

1514131211 10 9876542

TOP VIEW

1.30

1.20

1.10

0.15 MAX

COPLANARITY

0.70

0.60

0.50

DETAIL A

0.90

0.75

0.60

BALL DIAMETER

BOTTOM VIEW

DETAIL A

A1 CORNER

INDEX AREA

20.10

20.00 SQ

19.90

23.20

23.00 SQ

22.80

BALL A1

INDICATOR

0.50 R

3 PLACES

SEATING

PLANE

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 57 of 64 | August 2010

Figure 41. 240-Lead Metric Quad Flat Package, Thermally Enhanced “PowerQuad” [MQFP_PQ4]

(SP-240-2)

Dimensions shown in millimeters

COMPLIANT WITH JEDEC STANDARDS MS-029-GA

0.66

0.56

0.46

4.10

3.78

3.55

SEATING

PLANE

VIEW A

0.38

0.25

0.20

0.09

0.076

COPLANARITY

3.50

3.40

3.30

7°

0°

VIEW A

ROTATED 90° CCW

240 181

180

121

120

PIN 1

HEAT SLUG

TOP VIEW

(PINS DOWN)

34.60 BSC

29.50 REF

32.00 BSC

3.92 × 45°

(4 PLACES)

24.00 REF

0.27 MAX

0.17 MIN

0.50

BSC

LEAD PITCH

Rev. G | Page 58 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Figure 42. 240-Lead Ceramic Quad Flat Package, Heat Slug Up [CQFP]

(QS-240-2A)

Dimensions shown in millimeters

32.00 BSC SQ

61 120

121

180

240 181

36.60

36.13 SQ

35.65 28.05

27.80 SQ

27.55

0.50 BSC

3.70

3.22

2.75

0.90

0.75

0.60

0.23

0.20

0.17

7°

-3°

180

181

240

120

121 60

19.00

REF SQ

BOTTOM VIEW

(PINS UP)

HEAT SLUG

NOTES:

1. LEAD FINISH = GOLD PLATE

2. LEAD SWEEP/LEAD OFFSET = 0.013mm MAX

(Sweep and/or Offset can be used as the controlling dimension).

LID

SEAL RING

TOP VIEW

(PINS DOWN)

PIN 1

INDICATOR

4.30

3.62

2.95

0.60

0.40

0.20

VIEW A

0.175

0.156

0.137

1.70

0.35

0.30

0.25

0.15

0.180

0.155

0.130

2.06 REF

LEAD THICKNESS

0.15

VIEW A

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 59 of 64 | August 2010

Figure 43. 240-Lead Ceramic Quad Flat Package, Mounted with Cavity Down [CQFP]

(QS-240-2B)

Dimensions shown in millimeters

65.90

BSC

75.50 BSC SQ

121

180

181 240

120 61

INDEX 1

GOLD

PLATED

29.50 BSC

TOP VIEW

75.00 BSC SQ 2.60

2.55

2.50

3.60

3.55

3.50

29.50

BSC

240 181

180

121

120

BOTTOM VIEW

HEAT SLUG

INDEX 2

1.50 DIA

NO GOLD

NONCONDUCTIVE

CERAMIC TIE BAR

70.00 BSC SQ

2.05

SIDE VIEW

0.50

0.90

0.80

0.70

3.42

3.17

2.92

1.22 (4×)

16.50 (8×)

LID

SEAL RING

Rev. G | Page 60 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Figure 44. 240-Lead Ceramic Quad Flat Package, Heat Slug Down [CQFP]

(QS-240-1A)

Dimensions shown in millimeters

32.00 BSC SQ

61 120

121

180

240

LID

SEAL RING

TOP VIEW

(PINS DOWN)

181

36.60

36.13 SQ

35.65

28.05

27.80 SQ

27.55

0.50 BSC

3.70

3.22

2.75

0.90

0.75

0.60

0.23

0.20

0.17

7°

-3°

19.00

REF SQ

180

181

240

120

121 60

BOTTOM VIEW

(PINS UP)

HEAT SLUG

NOTES:

1. LEAD FINISH = GOLD PLATE

2. LEAD SWEEP/LEAD OFFSET = 0.013mm MAX

(Sweep and/or Offset can be used as the controlling dimension).

1.70

0.35

0.30

0.25

0.15

0.180

0.155

0.130

2.06 REF

LEAD THICKNESS

0.15

PIN 1

INDICATOR

4.20

3.52

2.85

0.50

0.30

0.10

VIEW A

0.175

0.156

0.137

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 61 of 64 | August 2010

SURFACE-MOUNT DESIGN

Table 43 is provided as an aide to PCB design. For industry-

standard design recommendations, refer to IPC-7351, Generic

Requirements for Surface-Mount Design and Land Pattern

Standard.

Figure 45. 240-Lead Ceramic Quad Flat Package, Mounted with Cavity Up [CQFP]

(QS-240-1B)

Dimensions shown in millimeters

65.90

BSC

75.50 BSC SQ

121

180

181 240

120 61

INDEX 1

GOLD

PLATED

29.50 BSC

LID

SEAL RING

TOP VIEW

75.00 BSC SQ 2.60

2.55

2.50

3.60

3.55

3.50

29.50

BSC

240 181

180

121

120

BOTTOM VIEW

HEAT SLUG

INDEX 2

2.00 DIA

NO GOLD

NONCONDUCTIVE

CERAMIC TIE BAR

70.00 BSC SQ

2.05

SIDE VIEW

0.50

0.90

0.80

0.70

3.42

3.17

2.92

1.22 (4×)

16.50 (8×)

Table 43. BGA Data for Use with Surface-Mount Design

Package Ball Attach Type Solder Mask Opening Ball Pad Size

225-Ball Grid Array (PBGA) Solder Mask Defined 0.63 mm diameter 0.76 mm diameter

Rev. G | Page 62 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

ORDERING GUIDE

Model Notes

Temperature

Range

Instruction

Rate

On-Chip

SRAM

Operating

Voltage Package Description

Package

Option

ASDP-21060CZ-133

Model refers to package with formed leads. For model numbers of unformed lead versions (QS-240-1B, QS-240-2B), contact Analog Devices or an Analog Devices sales

representative.

RoHS compliant part.

–40°C to +100°C 33 MHz 4M Bit 5 V 240-Lead CQFP [Heat Slug Up] QS-240-2A

ASDP-21060CZ-160

1, 2

–40°C to +100°C 40 MHz 4M Bit 5 V 240-Lead CQFP [Heat Slug Up] QS-240-2A

ASDP-21060CW-133

1, 2

–40°C to +100°C 33 MHz 4M Bit 5 V 240-Lead CQFP [Heat Slug Down] QS-240-1A

ASDP-21060CW-160

1, 2

–40°C to +100°C 40 MHz 4M Bit 5 V 240-Lead CQFP [Heat Slug Down] QS-240-1A

ADSP-21060KS-133 0°C to 85°C 33 MHz 4M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21060KSZ-133

0°C to 85°C 33 MHz 4M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21060KS-160 0°C to 85°C 40 MHz 4M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21060KSZ-160

0°C to 85°C 40 MHz 4M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21060KB-160 0°C to 85°C 40 MHz 4M Bit 5 V 225-Ball PBGA B-225-2

ADSP-21060KBZ-160

0°C to 85°C 40 MHz 4M Bit 5 V 225-Ball PBGA B-225-2

ADSP-21060LKSZ-133

0°C to 85°C 33 MHz 4M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21060LKS-160 0°C to 85°C 40 MHz 4M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21060LKSZ-160

0°C to 85°C 40 MHz 4M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21060LKB-160 0°C to 85°C 40 MHz 4M Bit 3.3 V 225-Ball PBGA B-225-2

ADSP-21060LAB-160 –40°C to +85°C 40 MHz 4M Bit 3.3 V 225-Ball PBGA B-225-2

ADSP-21060LABZ-160

–40°C to +85°C 40 MHz 4M Bit 3.3 V 225-Ball PBGA B-225-2

ADSP-21060LCB-133 –40°C to +100°C 33 MHz 4M Bit 3.3 V 225-Ball PBGA B-225-2

ADSP-21060LCBZ-133

–40°C to +100°C 33 MHz 4M Bit 3.3 V 225-Ball PBGA B-225-2

ASDP-21060LCW-160

1, 2

–40°C to +100°C 40 MHz 4M Bit 3.3 V 240-Lead CQFP [Heat Slug Down] QS-240-1A

ADSP-21062KS-133 0°C to 85°C 33 MHz 2M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21062KSZ-133

0°C to 85°C 33 MHz 2M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21062KS-160 0°C to 85°C 40 MHz 2M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21062KSZ-160

0°C to 85°C 40 MHz 2M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21062KB-160 0°C to 85°C 40 MHz 2M Bit 5 V 225-Ball PBGA B-225-2

ADSP-21062KBZ-160

0°C to 85°C 40 MHz 2M Bit 5 V 225-Ball PBGA B-225-2

ADSP-21062CS-160 –40°C to +100°C 40 MHz 2M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21062CSZ-160

–40°C to +100°C 40 MHz 2M Bit 5 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21062LKS-133 0°C to 85°C 33 MHz 2M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21062LKSZ-133

0°C to 85°C 33 MHz 2M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21062LKS-160 0°C to 85°C 40 MHz 2M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21062LKSZ-160

0°C to 85°C 40 MHz 2M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21062LKB-160 0°C to 85°C 40 MHz 2M Bit 3.3 V 225-Ball PBGA B-225-2

ADSP-21062LKBZ-160

0°C to 85°C 40 MHz 2M Bit 3.3 V 225-Ball PBGA B-225-2

ADSP-21062LAB-160 –40°C to 85°C 40 MHz 2M Bit 3.3 V 225-Ball PBGA B-225-2

ADSP-21062LABZ-160

–40°C to 85°C 40 MHz 2M Bit 3.3 V 225-Ball PBGA B-225-2

ADSP-21062LCS-160 –40°C to +100°C 40 MHz 2M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21062LCSZ-160

–40°C to +100°C 40 MHz 2M Bit 3.3 V 240-Lead MQFP_PQ4 SP-240-2

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. G | Page 63 of 64 | August 2010

Rev. G | Page 64 of 64 | August 2010

registered trademarks are the property of their respective owners.

D00167-0-8/10(G)

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC