LTC2415/LTC2415-1 24-Bit No Latency TM ADCs with Differential Input and Differential Reference DESCRIPTION FEATURES 2x Speed Up Version of the LTC2410/LTC2413: 15Hz Output Rate, 50Hz or 60Hz Notch--LTC2415; 13.75Hz Output Rate, Simultaneous 50Hz/60Hz Notch--LTC2415-1 nn Differential Input and Differential Reference with GND to VCC Common Mode Range nn 2ppm INL, No Missing Codes nn 2.5ppm Gain Error nn 0.23ppm Noise nn Single Conversion Settling Time for Multiplexed Applications nn Internal Oscillator--No External Components Required nn 24-Bit ADC in Narrow SSOP-16 Package (SO-8 Footprint) nn Single Supply 2.7V to 5.5V Operation nn Low Supply Current (200A) and Auto Shutdown nn APPLICATIONS Direct Sensor Digitizer Weight Scales nn Direct Temperature Measurement nn Gas Analyzers nn Strain Gage Transducers nn Instrumentation nn Data Acquisition nn Industrial Process Control nn 6-Digit DVMs nn nn The LTC(R)2415/2415-1 are micropower 24bit differential analog to digital converters with integrated oscillator, 2ppm INL, 0.23ppm RMS noise and a 2.7V to 5.5V supply range. They use delta-sigma technology and provide single cycle settling time for multiplexed applications. Through a single pin, the LTC2415 can be configured for better than 110dB input differential mode rejection at 50Hz or 60Hz 2%, or it can be driven by an external oscillator for a user defined rejection frequency. The LTC2415-1 can be configured for better than 87dB input differential mode rejection over the range of 49Hz to 61.2Hz (50Hz and 60Hz 2% simultaneously). The internal oscillator requires no external frequency setting components. The converters accept any external differential reference voltage from 0.1V to VCC for flexible ratiometric and remote sensing measurement configurations. The full-scale differential input range is from -0.5VREF to 0.5VREF. The reference common mode voltage, VREFCM, and the input common mode voltage, VINCM, may be independently set anywhere within the GND to VCC range of the LTC2415/ LTC2415-1. The DC common mode input rejection is better than 140dB. The LTC2415/LTC2415-1 communicate through a flexible 3-wire digital interface which is compatible with SPI and MICROWIRE protocols. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and C-Load and No Latency are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION VCC 2.7V TO 5.5V 1F VCC 1F 2 VCC FO 14 LTC2415/ LTC2415-1 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 REF - ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 5 IN + SDO IN - CS 6 1, 7, 8, 9, 10, 15, 16 GND SCK = INTERNAL OSC/50Hz REJECTION (LTC2415) = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION (LTC2415) = INTERNAL 50Hz/60Hz REJECTION (LTC2415-1) BRIDGE IMPEDANCE 100 TO 10k 13 12 3 3-WIRE SPI INTERFACE 5 6 2 REF + VCC IN + IN - 4 REF - GND 1, 7, 8 9, 10, 15, 16 11 2415 TA01 12 SDO 13 SCK LTC2415/ LTC2415-1 11 CS 3-WIRE SPI INTERFACE FO 14 2415 TA02 2415fa For more information www.linear.com/LTC2415 1 LTC2415/LTC2415-1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) Supply Voltage (VCC) to GND........................ -0.3V to 7V Analog Input Pins Voltage to GND.......................................-0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND.......................................-0.3V to (VCC + 0.3V) Digital Input Voltage to GND..........-0.3V to (VCC + 0.3V) Digital Output Voltage to GND........-0.3V to (VCC + 0.3V) Operating Temperature Range LTC2415C/LTC2415-1C ............................. 0C to 70C LTC2415I/LTC2415-1I ...........................-40C to 85C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec).................... 300C TOP VIEW GND 1 16 GND VCC 2 15 GND REF + 3 14 FO REF - 4 13 SCK IN + 5 12 SDO IN - 6 11 CS GND 7 10 GND GND 8 9 GND GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125C, JA = 95C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2415CGN#PBF LTC2415CGN#TRPBF 2415 16-Lead Plastic SSOP 0C to 70C LTC2415IGN#PBF LTC2415IGN#TRPBF 2415I 16-Lead Plastic SSOP -40C to 85C LTC2415-1CGN#PBF LTC2415-1CGN#TRPBF 24151 16-Lead Plastic SSOP 0C to 70C LTC2415-1IGN#PBF LTC2415-1IGN#TRPBF 24151I 16-Lead Plastic SSOP -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3,4) PARAMETER CONDITIONS Resolution (No Missing Codes) 0.1V VREF VCC, -0.5 * VREF VIN 0.5 * VREF, (Note 5) Integral Nonlinearity 5V VCC 5.5V, REF+ = 2.5V, REF- = GND, VINCM = 1.25V, (Note 6) 5V VCC 5.5V, REF+ = 5V, REF- = GND, VINCM = 2.5V, (Note 6) REF+ = 2.5V, REF- = GND, VINCM = 1.25V, (Note 6) 2.5V REF+ VCC, REF- = GND, GND IN+ = IN- VCC, (Note 14) 2.5V REF+ VCC, REF- = GND, GND IN+ = IN- VCC 2.5V REF+ VCC, REF- = GND, IN+ = 0.75REF+, IN- = 0.25 * REF+ Offset Error Offset Error Drift Positive Gain Error MIN Positive Gain Error Drift 2.5V REF+ VCC, REF- = GND, IN+ = 0.75REF+, IN- = 0.25 * REF+ Negative Gain Error 2.5V REF+ VCC, REF- = GND, IN+ = 0.25 * REF+, IN- = 0.75 * REF+ TYP MAX 24 UNITS Bits 1 2 5 14 ppm of VREF ppm of VREF ppm of VREF 0.5 2 mV 20 2.5 nV/C 12 0.03 2.5 ppm of VREF ppm of VREF/C 12 ppm of VREF 2415fa 2 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3,4) PARAMETER CONDITIONS Negative Gain Error Drift 2.5V REF+ VCC, REF- = GND, IN+ = 0.25 * REF+, IN- = 0.75 * REF+ MIN TYP MAX UNITS 0.03 ppm of VREF/C Output Noise 5V VCC 5.5V, REF+ = 5V, REF - = GND, GND IN- = IN+ VCC, (Note 13) 1.1 VRMS CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3,4) PARAMETER CONDITIONS Input Common Mode Rejection DC 2.5V REF+ VCC, REF- = GND, GND IN- = IN+ VCC 2.5V REF+ VCC, REF- = GND, GND IN- = IN+ VCC, (Note 7) 2.5V REF+ VCC, REF- = GND, GND IN- = IN+ VCC, (Note 8) Input Common Mode Rejection 60Hz 2% (LTC2415) Input Common Mode Rejection 50Hz 2% (LTC2415) MIN TYP MAX UNITS l 130 140 l 140 dB l 140 dB dB Input Normal Mode Rejection 60Hz 2% (LTC2415) (Note 7) l 110 140 dB Input Normal Mode Rejection 50Hz 2% (LTC2415) (Note 8) l 110 140 dB Input Common Mode Rejection 49Hz to 61.2Hz (LTC2415-1) 2.5V REF+ VCC, REF- = GND, l 140 dB Input Normal Mode Rejection 49Hz to 61.2Hz (LTC2415-1) FO = GND l 87 dB Input Normal Mode Rejection External Clock fEOSC/2560 14% (LTC2415-1) External Oscillator l 87 dB Input Normal Mode Rejection External Clock fEOSC/2560 4% (LTC2415-1) External Oscillator l 110 140 dB Reference Common Mode Rejection DC 2.5V REF+ VCC, GND REF- 2.5V, VREF = 2.5V, IN- = IN+ = GND l 130 140 dB Power Supply Rejection, DC REF+ = VCC, REF- = GND, IN- = IN+ = GND 100 dB Power Supply Rejection, 60Hz 2% REF+ = 2.5V, REF- = GND, IN- = IN+ = GND, (Note 7) 120 dB Power Supply Rejection, 50Hz 2% REF+ = 2.5V, REF- = GND, IN- = IN+ = GND, (Note 8) 120 dB ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3,4) SYMBOL PARAMETER IN+ Absolute/Common Mode IN+ Voltage CONDITIONS MIN TYP MAX UNITS GND - 0.3V VCC + 0.3V V IN- Absolute/Common Mode IN- Voltage GND - 0.3V VCC + 0.3V V VIN Input Differential Voltage Range (IN+ - IN-) -VREF/2 VREF/2 V REF+ Absolute/Common Mode REF+ Voltage 0.1 VCC V REF- Absolute/Common Mode REF- Voltage GND VCC - 0.1V V VREF Reference Differential Voltage Range (REF+ - REF-) 0.1 VCC V 2415fa For more information www.linear.com/LTC2415 3 LTC2415/LTC2415-1 ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3,4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CS (IN+) IN+ Sampling Capacitance CS (IN-) IN- Sampling Capacitance 18 pF CS (REF+) REF+ Sampling Capacitance 18 pF CS (REF-) REF- Sampling Capacitance 18 pF (IN+) IN+ DC Leakage Current IDC_LEAK (IN-) IN- DC Leakage Current IDC_LEAK IDC_LEAK (REF+) REF+ DC Leakage Current IDC_LEAK (REF-) REF- DC Leakage Current 18 CS = VCC, IN+ = GND CS = VCC, IN- = GND CS = VCC, REF+ = 5V CS = VCC, REF- = GND pF -10 1 10 nA -10 1 10 nA -10 1 10 nA -10 1 10 nA DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3) SYMBOL PARAMETER VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ CONDITIONS MIN High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO 2.7V VCC 5.5V 2.7V VCC 3.3V 4.5V VCC 5.5V 2.7V VCC 5.5V 2.7V VCC 5.5V (Note 9) 2.7V VCC 3.3V (Note 9) 4.5V VCC 5.5V (Note 9) 2.7V VCC 5.5V (Note 9) 0V VIN VCC 0V VIN VCC (Note 9) High Level Output Voltage SCK Low Level Output Voltage SCK Hi-Z Output Leakage SDO TYP 2.5 2.0 -10 0.8 0.6 10 -10 10 A 0.8 0.6 2.5 2.0 (Note 9) IO = -800A IO = 1.6mA IO = -800A (Note 10) IO = 1.6mA (Note 10) UNITS V V V V V V V V A MAX 10 pF 10 pF VCC - 0.5 V 0.4 VCC - 0.5 V V -10 0.4 V 10 A POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) SYMBOL PARAMETER VCC Supply Voltage ICC Supply Current Conversion Mode Sleep Mode CONDITIONS MIN l CS = 0V (Note 12) CS = VCC (Note 12) l l TYP 2.7 200 20 MAX UNITS 5.5 V 300 30 A A 2415fa 4 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3,4) SYMBOL PARAMETER CONDITIONS MIN fEOSC External Oscillator Frequency Range l tHEO External Oscillator High Period tLEO External Oscillator Low Period tCONV Conversion Time (LTC2415) TYP MAX UNITS 2.56 500 kHz l 0.25 390 s l 0.25 390 s FO = 0V FO = VCC External Oscillator (Note 11) l l l 65.43 78.52 66.77 68.1 80.12 81.72 10278/fEOSC (in kHz) ms ms ms Conversion Time (LTC2415-1) FO = 0V External Oscillator (Note 11) l l 71.3 72.8 74.3 10278/fEOSC (in kHz) ms ms fISCK Internal SCK Frequency Internal Oscillator (Note 10), LTC2415 Internal Oscillator (Note 10), LTC2415-1 External Oscillator (Notes 10, 11) DISCK Internal SCK Duty Cycle (Note 10) l fESCK External SCK Frequency Range (Note 9) l tLESCK External SCK Low Period (Note 9) l 250 ns tHESCK External SCK High Period (Note 9) l 250 ns tDOUT_ISCK Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12), LTC2415 Internal Oscillator (Notes 10, 12), LTC2415-1 External Oscillator (Notes 10, 11) l l l 1.64 1.80 tDOUT_ESCK External SCK 32-Bit Data Output Time (Note 9) l 19.2 17.5 fEOSC/8 45 kHz kHz kHz 55 % 2000 kHz 1.67 1.70 1.83 1.86 256/fEOSC (in kHz) ms ms ms 32/fESCK (in kHz) ms t1 CS to SDO Low Z l 0 200 ns t2 CS to SDO High Z l 0 200 ns t3 CS to SCK (Note 10) l 0 200 ns t4 CS to SCK (Note 9) l 50 tKQMAX SCK to SDO Valid tKQMIN SDO Hold After SCK l 15 ns t5 SCK Set-Up Before CS l 50 ns t6 SCK Hold After CS l 220 l (Note 5) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7 to 5.5V unless otherwise specified. VREF = REF+ - REF-, VREFCM = (REF+ + REF-)/2; VIN = IN+ - IN-, VINCM = (IN+ + IN-)/2. Note 4: FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz 2% (external oscillator). ns 50 ns ns Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz 2% (external oscillator). Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: Refer to Offset Accuracy and Drift in the Applications Information section. 2415fa For more information www.linear.com/LTC2415 5 LTC2415/LTC2415-1 TYPICAL PERFORMANCE CHARACTERISTICS 105.5 TA = 25C 105.0 104.5 213 121 TA = 90C 211 209 VCC = 5V VREF = 2.5V VINCM = 1.25V REF + = 2.5V REF - = GND FO = GND 207 TA = -45C 104.0 125 205 -1.25 103.5 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 VIN (V) -0.75 TA = -45C -0.25 0.25 VIN (V) 0.75 0.5 2.5 TA = -45C 2.0 TA = 25C 1.5 INL ERROR (ppm OF VREF) INL ERROR (ppm OF VREF) 1.0 0 TA = 90C TA = 25C 1.0 0.5 0 -1.0 TA = 90C -1.5 -1.0 1 1.5 2 -2.5 -1.25 2.5 8 6 4 2 0 -105.5 -104.8 -104 -103.3 OUTPUT CODE (ppm OF VREF) -102.5 2415 G07 10 NUMBER OF READINGS (%) NUMBER OF READINGS (%) 10 GAUSSIAN DISTRIBUTION m = -103.5ppm = 0.27ppm TA = -45C -0.75 -0.25 0.25 VIN (V) 0.75 -0.75 -0.25 0.25 VIN (V) 0.75 TA = 90C 6 4 2 0 TA = 25C -2 TA = -45C -4 -6 REF + = 2.5V VCC = 2.7V VREF = 2.5V REF - = GND VINCM = 1.25V FO = GND -10 -1.25 1.25 -0.75 -0.25 0.25 VIN (V) 0.75 12 GAUSSIAN DISTRIBUTION m = -104.0ppm = 0.25ppm 2 0 -105 1.25 2415 G06 Noise Histogram (Output Rate = 45Hz, VCC = 5V, VREF = 5V) 10,000 CONSECUTIVE READINGS V = 5V 8 VCC = 5V REF VIN = 0V REF + = 5V 6 REF - = GND IN + = 2.5V IN - = 2.5V 4 FO = 460800Hz TA = 25C 1.25 Integral Nonlinearity Over Temperature (VCC = 2.7V, VREF = 2.5V) 2415 G05 Noise Histogram (Output Rate = 15Hz, VCC = 5V, VREF = 5V) 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 5V VIN = 0V REF + = 5V REF - = GND IN + = 2.5V IN - = 2.5V FO = GND TA = 25C TA = 25C 8 -8 2415 G04 12 10 TA = -45C -2.0 -1.5 -2.5 -2 -1.5 -1 -0.5 0 0.5 VIN (V) REF + = 2.5V VCC = 5V VREF = 2.5V REF - = GND VINCM = 1.25V FO = GND -0.5 -0.5 113 2415 G03 Integral Nonlinearity Over Temperature (VCC = 5V, VREF = 2.5V) Integral Nonlinearity Over Temperature (VCC = 5V, VREF = 5V) VCC = 5V VREF = 5V VINCM = 2.5V REF + = 5V REF - = GND FO = GND 117 105 -1.25 1.25 TA = 90C 2415 G02 2415 G01 1.5 REF + = 2.5V VCC = 2.7V VREF = 2.5V REF - = GND VINCM = 1.25V FO = GND 109 TA = 25C INL ERROR (ppm OF VREF) TUE (ppm OF VREF) 106.0 215 TUE (ppm OF VREF) VCC = 5V VREF = 5V VINCM = 2.5V REF + = 5V REF - = GND FO = GND TA = 90C Total Unadjusted Error Over Temperature (VCC = 2.7V, VREF = 2.5V) NUMBER OF READINGS (%) 106.5 Total Unadjusted Error Over Temperature (VCC = 5V, VREF = 2.5V) TUE (ppm OF VREF) Total Unadjusted Error Over Temperature (VCC = 5V, VREF = 5V) 10 8 6 4 Noise Histogram (Output Rate = 15Hz, VCC = 5V, VREF = 2.5V) 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 2.5V VIN = 0V REF + = 2.5V REF - = GND IN + = 1.25V IN - = 1.25V FO = GND TA = 25C GAUSSIAN DISTRIBUTION m = -209.2ppm = 0.56ppm 2 -104.5 -104 -103.5 OUTPUT CODE (ppm OF VREF) -103 2415 G08 0 -212 -210.5 -209 -207.5 OUTPUT CODE (ppm OF VREF) -206 2415 G10 2415fa 6 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 TYPICAL PERFORMANCE CHARACTERISTICS 6 4 10 8 6 4 10,000 CONSECUTIVE READINGS VCC = 2.7V VREF = 2.5V VIN = 0V REF + = 2.5V REF - = GND IN + = 1.25V IN - = 1.25V FO = GND TA = 25C 2 2 0 -211.5 -210.5 -209.5 -208.5 OUTPUT CODE (ppm OF VREF) 0 -116 -207.5 -114.5 -113 -111.5 OUTPUT CODE (ppm OF VREF) Long-Term Histogram (60Hrs) VCC = 5V VREF = 5V 10 VIN = 0V REF + = 5V REF - = GND 8 IN + = 2.5V IN - = 2.5V F = GND 6 O TA = 25C GAUSSIAN DISTRIBUTION m = -103.9ppm = 0.27ppm 4 2 -103.5 -104 -104.5 OUTPUT CODE (ppm OF VREF) 0.5 VCC = 5V VREF = 5V VIN = 0V REF + = 5V REF - = GND -101.5 -102.0 -102.5 IN + = 2.5V IN - = 2.5V FO = GND TA = 25C -103.0 -103.5 -104.0 -104.5 -105.5 -105 0.4 0.3 VCC = 5V VREF = 5V VINCM = 2.5V REF + = 5V REF - = GND FO = GND TA = 25C 0.2 0.1 0 0 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 INPUT DIFFERENTIAL VOLTAGE (V) 5 10 15 20 25 30 35 40 45 50 55 60 TIME (HRS) RMS Noise vs Temperature (TA) RMS Noise vs VCC 1400 IN + = VINCM IN - = VINCM FO = GND TA = 25C 2.5 2415 G18 2415 G17 1560 1520 1250 RMS NOISE (nV) RMS NOISE (nV) VCC = 5V VREF = 5V VIN = 0V REF + = 5V REF - = GND -107.5 2415 G14 -101.0 RMS Noise vs VINCM 1800 -110.9 -109.8 -108.6 OUTPUT CODE (ppm OF VREF) RMS Noise vs Input Differential Voltage 2415 G16 1600 0 -112 -110 -105.0 0 -103 GAUSSIAN DISTRIBUTION m = -109.8ppm = 0.50ppm 2 Consecutive ADC Readings vs Time ADC READINGS (ppm OF VREF) 12 10,000 CONSECUTIVE READINGS V = 2.7V 8 VCC = 2.5V REF VIN = 0V REF + = 2.5V 6 REF - = GND IN + = 1.25V IN - = 1.25V 4 FO = 460800Hz TA = 25C 2415 G13 2415 G11 NUMBER OF READINGS (%) 10 GAUSSIAN DISTRIBUTION m = -113.1ppm = 0.59ppm RMS NOISE (ppm OF VREF) 8 12 GAUSSIAN DISTRIBUTION m = -209.3ppm = 0.49ppm Noise Histogram (Output Rate = 45Hz, VCC = 2.7V, VREF = 2.5V) 1400 1200 1480 1100 VCC = 5V VIN = 0V REF + = 5V REF - = GND IN + = 2.5V IN - = 2.5V FO = GND 950 1000 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VINCM (V) 2415 G19 800 -50 RMS NOISE (nV) 10 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 2.5V VIN = 0V REF + = 2.5V REF - = GND IN + = 1.25V IN - = 1.25V FO = 460800Hz TA = 25C NUMBER OF READINGS (%) NUMBER OF READINGS (%) 12 Noise Histogram (Output Rate = 15Hz, VCC = 2.7V, VREF = 2.5V) NUMBER OF READINGS (%) Noise Histogram (Output Rate = 45Hz, VCC = 5V, VREF = 2.5V) -25 0 25 50 TEMPERATURE (C) 75 1440 1400 1360 1320 100 2415 G20 1280 2.7 VREF = 2.5V REF + = 2.5V REF - = GND IN + = GND IN - = GND FO = GND TA = 25C 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 2415 G21 2415fa For more information www.linear.com/LTC2415 7 LTC2415/LTC2415-1 TYPICAL PERFORMANCE CHARACTERISTICS RMS Noise vs VREF Offset Error vs VINCM -103.0 RMS NOISE (nV) 1400 1200 VCC = 5V REF - = GND IN + = GND IN - = GND FO = GND TA = 25C 1000 800 0 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 4.5 Offset Error vs Temperature (TA) VCC = 5V VREF = 5V VIN = 0V REF + = 5V REF - = GND IN + = VINCM IN - = VINCM FO = GND TA = 25C -103.4 -103.8 -104.2 -104.4 -190 -210 -230 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 -103.6 -104.4 -104.8 -105.2 2.7 3.1 3.5 3.9 4.3 4.7 VCC AND VREF (V) 3.5 3.9 4.3 VCC (V) 0 -1 -2 4.7 5.1 5.5 2415 G28 VCC = 5V REF + = 5V REF - = GND IN + = 2.5V IN - = GND FO = GND -3 -45 -30 -15 5.5 0 15 30 45 60 TEMPERATURE (C) -4 -8 0.5 90 -Full-Scale Error vs Temperature (TA) 0 4 0 75 2415 G27 - FULL-SCALE ERROR (ppm OF VREF) + FULL-SCALE ERROR (ppm OF VREF) + FULL-SCALE ERROR (ppm OF VREF) 1 3.1 1 +Full-Scale Error vs VREF 2 0 2.7 5.1 8 3 100 2 2415 G26 5 75 3 -104.0 +Full-Scale Error vs VCC 4 0 25 50 TEMPERATURE (C) +Full-Scale Error vs Temperature (TA) REF - = GND IN + = GND IN - = GND FO = GND TA = 25C 2415 G25 VREF = 2.5V REF + = 2.5V REF - = GND IN + = 1.25V IN - = GND FO = GND TA = 25C -25 2415 G24 + FULL-SCALE ERROR (ppm OF VREF) -170 -104.6 -50 Offset Error vs VCC and VREF -103.2 OFFSET ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) -150 VCC = 5V VIN = 0V REF + = 5V REF - = GND IN + = 2.5V IN - = 2.5V FO = GND 2415 G23 Offset Error vs VCC -130 -104.2 -105.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VINCM (V) 5 VREF = 2.5V REF + = 2.5V REF - = GND IN + = GND IN - = GND FO = GND TA = 25C -104.0 -104.6 2415 G22 -110 -103.8 OFFSET ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) 1600 VCC = 5V REF + = VREF REF - = GND IN + = 0.5 * REF + IN - = GND FO = GND TA = 25C 1 1.5 2 2.5 3 3.5 VREF (V) 4 4.5 5 2415 G29 -1 -2 -3 -4 -5 VCC = 5V REF + = 5V REF - = GND IN + = GND IN - = 2.5V FO = GND -6 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90 2415 G30 2415fa 8 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 TYPICAL PERFORMANCE CHARACTERISTICS -Full-Scale Error vs VCC -Full-Scale Error vs VREF PSRR vs Frequency at VCC 8 -1 -2 VREF = 2.5V REF + = 2.5V REF - = GND IN + = GND IN - = 1.25V FO = GND TA = 25C -3 -4 -5 2.7 3.5 3.1 3.9 4.3 VCC (V) 4.7 5.1 0 4 0 VCC = 5V REF + = VREF REF - = GND IN + = GND IN - = 0.5 * REF + FO = GND TA = 25C -4 -8 -12 0.5 5.5 1 1.5 2 2.5 3 3.5 VREF (V) 4 PSRR vs Frequency at VCC -100 5 -80 -100 100 10000 FREQUENCY AT VCC (Hz) -40 -60 -80 1000000 -120 15200 15300 15400 FREQUENCY AT VCC (Hz) 15500 400 SUPPLY CURRENT (A) SUPPLY CURRENT (A) 500 300 190 FO = GND CS = GND 180 SCK = SDO = N/C VCC = 5.5V VCC = 4.1V 170 VCC = 2.7V 160 140 -45 -30 -15 20 0 15 30 45 60 TEMPERATURE (C) 75 90 2415 G36 18 100 16 30 40 10 20 OUTPUT DATA RATE (READINGS/SEC) 50 VCC = 5.5V 19 17 0 VREF+ = VCC 210 V - = GND REF VIN+ = VIN- = GND 200 + 24 VREF- = VCC VREF = GND 23 VIN+ = VIN- = GND FO = GND 22 CS = V CC 21 SCK = SDO = N/C 200 0 Conversion Current vs Temperature (TA) 25 VCC = 5V REF + = 5V REF - = GND IN + = GND IN - = GND FO = EXT OSC CS = GND SCK =N/C SDO = N/C 600 250 Sleep Current vs Temperature (TA) 1000 700 100 150 200 FREQUENCY AT VCC (Hz) 2415 G35 Conversion Current vs Output Data Rate 800 50 150 2415 G34 900 0 2415 G33 220 VCC = 4.1V DC + 0.7V AC REF + = 2.5V REF - = GND IN + = IN - = GND FO = GND TA = 25C -100 1 -120 SUPPLY CURRENT (A) -20 -60 -120 -80 0 REJECTION (dB) REJECTION (dB) -40 -60 PSRR vs Frequency at VCC 0 -20 4.5 -40 2415 G32 2415 G31 REF + = 2.5V REF - = GND IN + = IN - = GND FO = GND TA = 25C VCC = 4.1V DC + 1.4V AC REF + = 2.5V REF - = GND IN + = IN - = GND FO = GND TA = 25C -20 REJECTION (dB) - FULL-SCALE ERROR (ppm OF VREF) - FULL-SCALE ERROR (ppm OF VREF) 0 15 -45 -30 -15 2415 G37 VCC = 4.1V VCC = 2.7V 0 15 30 45 60 TEMPERATURE (C) 75 90 2415 G38 2415fa For more information www.linear.com/LTC2415 9 LTC2415/LTC2415-1 PIN FUNCTIONS GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a ground plane through a low impedance connection. All seven pins must be connected to ground for proper operation. SDO (Pin 12): Three-State Digital Output. During the Data Output period, this pin is used as serial data output. When the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 1) with a 10F tantalum capacitor in parallel with 0.1F ceramic capacitor as close to the part as possible. SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface clock during the Data Output period. A weak internal pull-up is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. REF + (Pin 3), REF- (Pin 4): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, is maintained more positive than the reference negative input, REF -, by at least 0.1V. IN + (Pin 5), IN- (Pin 6): Differential Analog Input. The voltage on these pins can have any value between GND - 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ - IN-) extends from - 0.5 * (VREF) to 0.5 * (VREF). Outside this input range the converter produces unique overrange and underrange output codes. CS (Pin 11): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. FO (Pin 14): Frequency Control Pin. Digital input that controls the ADC's notch frequencies and conversion time. When the FO pin is connected to VCC (LTC2415 only), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. When the FO pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter first null is located at 60Hz (LTC2415) or simultaneous 50Hz/60Hz (LTC2415-1). When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its system clock and the digital filter first null is located at a frequency fEOSC/2560. 2415fa 10 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 FUNCTIONAL BLOCK DIAGRAM INTERNAL OSCILLATOR VCC GND IN + IN - AUTOCALIBRATION AND CONTROL + - FO (INT/EXT) SDO SERIAL INTERFACE ADC SCK CS REF + REF - DECIMATING FIR - + DAC 2415 FD Figure 1. Functional Block Diagram TEST CIRCUITS SDO VCC 1.69k CLOAD = 20pF 1.69k SDO Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z CLOAD = 20pF 2415 TA03 Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 2415 TA04 2415fa For more information www.linear.com/LTC2415 11 LTC2415/LTC2415-1 APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2415/LTC2415-1 are low power, delta-sigma analog-to-digital converters with an easy to use 3-wire serial interface (see Figure 1). Their operation is made up of three states. The converter operating cycle begins with the conversion, followed by the sleep state and ends with the data output (see Figure 2). The 3-wire interface consists of serial data output (SDO), serial clock (SCK) and chip select (CS). CONVERT Through timing control of the CS and SCK pins, the LTC2415/LTC2415-1 offer several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Conversion Clock SLEEP FALSE Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 32 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. CS = LOW AND SCK TRUE DATA OUTPUT 2415 F02 Figure 2. LTC2415 State Transition Diagram Initially, the LTC2415/LTC2415-1 perform a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced by an order of magnitude if CS is HIGH. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz or 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2415/LTC2415-1 incorporate a highly accurate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2415 achieves a minimum of 110dB rejection at the line frequency (50Hz or 60Hz 2%), while the LTC24151 achieves a minimum of 87db rejection at 50Hz 2% and 60Hz 2% simultaneously. Ease of Use The LTC2415/LTC2415-1 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. 2415fa 12 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 APPLICATIONS INFORMATION The LTC2415/LTC2415-1 perform a full-scale calibration every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of full-scale readings with respect to time, supply voltage change and temperature drift. Unlike the LTC2410 and LTC2413, the LTC2415 and LTC2415-1 do not perform an offset calibration every conversion cycle. This enables the LTC2415/LTC2415-1 to double their output rate while maintaining line frequency rejection. The initial offset of the LTC2415/LTC2415-1 is within 2mV independent of VREF. Based on the LTC2415/ LTC2415-1 new modulator architecture, the temperature drift of the offset is less then 0.01ppm/C. More information on the LTC2415/LTC2415-1 offset is described in the Offset Accuracy and Drift section of this data sheet. Power-Up Sequence The LTC2415/LTC2415-1 automatically enter an internal reset state when the power supply voltage VCC drops below approximately 2.2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2415/LTC2415-1 start a normal conversion cycle and follow the succession of states described above. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Reference Voltage Range These converters accept a truly differential external reference voltage. The absolute/common mode voltage specification for the REF+ and REF- pins covers the entire range from GND to VCC. For correct converter operation, the REF+ pin must always be more positive than the REF- pin. The LTC2415/LTC2415-1 can accept a differential reference voltage from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter's effective resolution. On the other hand, a reduced reference voltage will improve the converter's overall INL performance. Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the IN+ and IN- input pins extending from GND - 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2415/LTC2415-1 convert the bipolar differential input signal, VIN = IN+ - IN-, from -FS = -0.5 * VREF to +FS = 0.5 * VREF where VREF = REF+ - REF-. Outside this range, the converters indicate the overrange or the underrange condition using distinct output codes. Input signals applied to IN+ and IN- pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the IN+ and IN- pins without affecting the performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/ Reference Current sections. In addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. Output Data Format The LTC2415/LTC2415-1 serial output data stream is 32 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 24 bits 2415fa For more information www.linear.com/LTC2415 13 LTC2415/LTC2415-1 APPLICATIONS INFORMATION are the conversion result, MSB first. The remaining 5 bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. The third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below -FS) or an overrange condition (the differential input voltage is above +FS). Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW. Bit 28 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 29 also provides the underrange or overrange indication. If both Bit 29 and Bit 28 are HIGH, the differential input voltage is above +FS. If both Bit 29 and Bit 28 are LOW, the differential input voltage is below -FS. The function of these bits is summarized in Table 1. Table 1. LTC2415/LTC2415-1 Status Bits Bit 31 EOC Bit 30 DMY Bit 29 SIG Bit 28 MSB VIN 0.5 * VREF 0 0 1 1 0V VIN < 0.5 * VREF 0 0 1 0 Input Range -0.5 * VREF VIN < 0V 0 0 0 1 VIN < -0.5 * VREF 0 0 0 0 Bits 28-5 are the 24-bit conversion result MSB first. Bit 5 is the least significant bit (LSB). Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may be included in averaging or discarded without loss of resolution. Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 3. Whenever CS is HIGH, SDO remains high impedance and any externally generated SCK clock pulses are ignored by the internal data out shift register. In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 31 (EOC) can be captured on the first rising edge of SCK. Bit 30 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 31st SCK and may be latched on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN- pins is maintained within the -0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any differential input voltage VIN from -FS = -0.5 * VREF to +FS = 0.5 * VREF. For differential input voltages greater than +FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages below -FS, the conversion result is clamped to the value corresponding to -FS - 1LSB. Offset Accuracy and Drift Unlike the LTC2410/LTC2413 and the entire LTC2400 family, the LTC2415/LTC2415-1 do not perform an offset calibration every cycle. The reason for this is to increase the data output rate while maintaining line frequency rejection. While the initial accuracy of the LTC2415/LTC2415-1 offset is within 2mV (see Figure 4) several unique properties of the LTC2415/LTC2415-1 architecture nearly eliminate the drift of the offset error with respect to temperature and supply. As shown in Figure 5, the offset variation with temperature is less than 0.6ppm over the complete temperature range of -50C to 100C. This corresponds to a temperature drift of 0.004ppm/C. 2415fa 14 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 APPLICATIONS INFORMATION While the variation in offset with supply voltage is proportional to VCC (see Figure 4), several characteristics of this variation can be used to eliminate the effects. First, the variation with respect to supply voltage is linear. Second, the magnitude of the offset error decreases with decreased supply voltage. Third, the offset error increases with increased reference voltage with an equal and opposite magnitude to the supply voltage variation. As a result, by tying VCC to VREF, the variation with supply can be nearly eliminated, see Figure 6. The variation with supply is less than 2ppm over the entire 2.7V to 5.5V supply range. Table 2. LTC2415/LTC2415-1 Output Data Format Differential Input Voltage VIN* Bit 31 EOC Bit 30 DMY Bit 29 SIG Bit 28 MSB Bit 27 Bit 26 Bit 25 ... Bit 0 VIN* 0.5 * VREF** 0 0 1 1 0 0 0 ... 0 0.5 * VREF** - 1LSB 0 0 1 0 1 1 1 ... 1 0.25 * VREF** 0 0 1 0 1 0 0 ... 0 0.25 * VREF** - 1LSB 0 0 1 0 0 1 1 ... 1 0 0 0 1 0 0 0 0 ... 0 -1LSB 0 0 0 1 1 1 1 ... 1 - 0.25 * VREF** 0 0 0 1 1 0 0 ... 0 - 0.25 * VREF** - 1LSB 0 0 0 1 0 1 1 ... 1 - 0.5 * VREF** 0 0 0 1 0 0 0 ... 0 VIN* < -0.5 * VREF** 0 0 0 0 1 1 1 ... 1 *The differential input voltage VIN = IN+ - IN-. **The differential reference voltage VREF = REF+ - REF-. CS SDO BIT 31 BIT 30 BIT 29 BIT 28 EOC "0" SIG MSB BIT 27 BIT 5 LSB24 Hi-Z SCK 1 2 3 4 SLEEP BIT 0 5 26 27 32 DATA OUTPUT CONVERSION 2415 F03 Figure 3. Output Data Timing 50 -103.0 -103.8 OFFSET ERROR (ppm OF VREF) 0 OFFSET ERROR (ppm OF VREF) PART NO.1 OFFSET (ppm) -104.0 -50 PART NO.2 -100 -104.2 -150 -200 -250 PART NO.3 -104.4 VREF = 2.5V TA = 25C 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 2415 F04 Figure 4. Offset vs VCC -104.6 -50 -25 0 25 50 TEMPERATURE (C) 75 100 2415 F05 Figure 5. Offset vs Temperature VCC = 5V VREF = 5V REF+ = 5V -103.5 REF - = GND VIN = 0V IN+ = GND IN- = GND FO = GND TA =100C -104.0 TA =25C -104.5 TA = -50C -105.0 -105.5 2.7 3.1 3.5 3.9 4.3 4.7 VCC AND VREF (V) 5.5 5.1 2415 F06 Figure 6. Offset vs VCC (VREF = VCC) 2415fa For more information www.linear.com/LTC2415 15 LTC2415/LTC2415-1 APPLICATIONS INFORMATION Frequency Rejection Selection LTC2415 (FO) The LTC2415 internal oscillator provides better than 110dB normal mode rejection at the line frequency and its harmonics for 50Hz 2% or 60Hz 2%. For 60Hz rejection, FO should be connected to GND while for 50Hz rejection the FO pin should be connected to VCC. The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level. A selection change during the sleep or data output states will not disturb the converter operation. If the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. When a fundamental rejection frequency different from 50Hz or 60Hz is required or when the converter must be synchronized with an outside source, the LTC2415 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency fEOSC of the external signal must be at least 2560Hz (1Hz notch frequency) to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods tHEO and tLEO are observed. While operating with an external conversion clock of a frequency fEOSC, the LTC2415 provides better than 110dB normal mode rejection in a frequency range fEOSC/2560 4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from fEOSC/2560 is shown in Figure 7a. Whenever an external clock is not present at the FO pin, the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The LTC2415 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. If the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. If the change occurs during the data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. 16 Table 3a summarizes the duration of each state and the achievable output data rate as a function of FO. Frequency Rejection Selection LTC2415-1 (FO) The LTC2415-1 internal oscillator provides better than 87dB normal mode rejection over the range of 49Hz to 61.2Hz as shown in Figure 7b. For simultaneous 50Hz/60Hz rejection, FO should be connected to GND. In order to achieve 87dB normal mode rejection of 50Hz 2% and 60Hz 2%, two consecutive conversions must be averaged. By performing a continuous running average of the two most current results, both simultaneous rejection is achieved and a 2x increase in throughput is realized relative to the LTC2413 (see Normal Mode Rejection, Output Rate and Running Averages sections of this data sheet). When a fundamental rejection frequency different from the range 49Hz to 61.2Hz is required or when the converter must be synchronized with an outside source, the LTC24151 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency fEOSC of the external signal must be at least 2560Hz to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods, tHEO and tLEO, are observed. While operating with an external conversion clock of a frequency fEOSC, the LTC2415-1 provides better than 110dB normal mode rejection in a frequency range fEOSC/2560 4%. The normal mode rejection as a function of the input frequency deviation from fEOSC/2560 is shown in Figure 7a and Figure 7c shows the normal mode rejection with running averages included. Whenever an external clock is not present at the FO pin the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The LTC24151 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. If the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. If the change occurs during the For more information www.linear.com/LTC2415 2415fa LTC2415/LTC2415-1 APPLICATIONS INFORMATION data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. Table 3b summarizes the duration of each state and the achievable output data rate as a function of FO. The LTC2415/LTC2415-1 transmit the conversion results and receive the start of conversion command through a synchronous 3-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result. -80 -70 -80 -90 -100 -110 -120 -130 -140 -12 -8 -4 0 4 8 12 INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%) -80 -85 -90 NORMAL MODE REJECTION (dB) NORMAL MODE REECTION RATIO (dB) -60 REJECTION (dB) Serial Interface Pins -100 -100 -120 -130 48 50 52 54 56 58 60 62 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2415 F07b Operating Mode CONVERT Internal Oscillator External Oscillator -105 -110 -115 -120 -125 -130 -140 -12 -8 -4 0 4 8 12 DIFFERENTIAL INPUT SIGNAL FREQUENCY DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%) 2415 F07c Figure 7b. LTC2415-1 Normal Mode Rejection When Using an Internal Oscillator with Running Averages Table 3a. LTC2415 State Duration State -95 -100 -135 -140 2415 F07a Figure 7a. LTC2415/LTC2415-1 Normal Mode Rejection When Using an External Oscillator of Frequency fEOSC without Running Averages -90 Figure 7c. LTC2415/LTC2415-1 Normal Mode Rejection When Using an External Oscillator of Frequency fEOSC with Running Averages Duration FO = LOW, (60Hz Rejection) 66.6ms, Output Data Rate 15 Readings/s FO = HIGH, (50Hz Rejection) 80ms, Output Data Rate 12.4 Readings/s FO = External Oscillator with Frequency fEOSC kHz (fEOSC/2560 Rejection) 10278/fEOSCs, Output Data Rate fEOSC/10278 Readings/s SLEEP As Long As CS = HIGH Until CS = LOW and SCK DATA OUTPUT Internal Serial Clock FO = LOW/HIGH, (Internal Oscillator) FO = External Oscillator with Frequency fEOSC kHz External Serial Clock with Frequency fSCK kHz As Long As CS = LOW But Not Longer Than 1.67ms (32 SCK cycles) As Long As CS = LOW But Not Longer Than 256/fEOSCms (32 SCK cycles) As Long As CS = LOW But Not Longer Than 32/fSCKms (32 SCK cycles) Table 3b. LTC2415-1 State Duration State Operating Mode CONVERT Internal Oscillator FO = LOW Simultaneous 50Hz/60Hz Rejection 72.8ms, Output Data Rate 14 Readings/s Duration External Oscillator FO = External Oscillator with Frequency fEOSC kHz (fEOSC/2560 Rejection) 10278/fEOSCs, Output Data Rate fEOSC/10278 Readings/s SLEEP As Long As CS = HIGH Until CS = LOW and SCK DATA OUTPUT Internal Serial Clock FO = LOW/HIGH, (Internal Oscillator) As Long As CS = LOW But Not Longer Than 1.83ms (32 SCK cycles) FO = External Oscillator with Frequency fEOSC kHz As Long As CS = LOW But Not Longer Than 256/fEOSCms (32 SCK cycles) External Serial Clock with Frequency fSCK kHz As Long As CS = LOW But Not Longer Than 32/fSCKms (32 SCK cycles) 2415fa For more information www.linear.com/LTC2415 17 LTC2415/LTC2415-1 APPLICATIONS INFORMATION Serial Clock Input/Output (SCK) Chip Select Input (CS) The serial clock signal present on SCK (Pin 13) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. The active LOW chip select, CS (Pin 11), is used to test the conversion status and to enable the data output transfer as described in the previous sections. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2415/LTC2415-1 create their own serial clock by dividing the internal conversion clock by 8. In the External SCK mode of operation, the SCK pin is used as input. The internal or external SCK mode is selected on power-up and then reselected every time a HIGH-to-LOW transition is detected at the CS pin. If SCK is HIGH or floating at power-up or during this transition, the converter enters the internal SCK mode. If SCK is LOW at power-up or during this transition, the converter enters the external SCK mode. In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2415/LTC2415-1 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i.e., after the first rising edge of SCK occurs with CS = LOW). Serial Data Output (SDO) The serial data output pin, SDO (Pin 12), provides the result of the last conversion as a serial bit stream (MSB first) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states. When CS (Pin 11) is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW. The device remains in the sleep state until the first rising edge of SCK occurs while CS = LOW. Finally, CS can be used to control the free-running modes of operation, see Serial Interface Timing Modes section. Grounding CS will force the ADC to continuously convert at the maximum output rate selected by FO. Tying a capacitor to CS will reduce the output rate and power dissipation by a factor proportional to the capacitor's value, see Figures 15 to 17. SERIAL INTERFACE TIMING MODES The LTC2415/LTC2415-1 3-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 2- or 3-wire I/O, single cycle conversion and auto-start. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin. Refer to Table 4 for a summary. Table 4. LTC2415/LTC2415-1 Interface Timing Modes Configuration SCK Source Conversion Cycle Control Data Output Control Connection and Waveforms External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 8, 9 External SCK, 2-Wire I/O External SCK SCK Figure 10 Internal SCK, Single Cycle Conversion Internal CS CS Figures 11, 12 Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 13 Internal SCK, Auto-start Conversion Internal CEXT Internal Figure 14 2415fa 18 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 APPLICATIONS INFORMATION External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible) the 32nd rising edge of SCK. On the 32nd falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress. This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 8. The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Independent of CS, the device automatically enters the sleep state once the conversion is complete. While in the sleep state, if CS is high, the LTC2415/LTC2415-1 power consumption is reduced by an order of magnitude Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first rising edge and the 32nd falling edge of SCK, see Figure 9. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW. Data is shifted out the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on External Serial Clock, 2-Wire I/O This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 10. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded 2.7V TO 5.5V VCC 1F 2 VCC FO LTC2415/ LTC2415-1 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 REF - ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 5 IN + SDO IN - CS 6 1, 7, 8, 9, 10, 15, 16 = 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR = 60Hz REJECTION (LTC2415) = 50Hz/60Hz REJECTION (LTC2415-1) 14 SCK 13 3-WIRE SPI INTERFACE 12 11 GND CS TEST EOC TEST EOC SDO BIT 31 EOC Hi-Z BIT 30 BIT 29 BIT 28 SIG MSB BIT 27 BIT 26 Hi-Z BIT 5 BIT 0 LSB SUB LSB TEST EOC Hi-Z SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2415 F08 2415fa For more information www.linear.com/LTC2415 19 LTC2415/LTC2415-1 APPLICATIONS INFORMATION 2.7V TO 5.5V VCC 1F 2 VCC FO LTC2415/ LTC2415-1 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 REF - ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 5 IN + SDO IN - CS 6 1, 7, 8, 9, 10, 15, 16 = 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR = 60Hz REJECTION (LTC2415) = 50Hz/60Hz REJECTION (LTC2415-1) 14 SCK 13 3-WIRE SPI INTERFACE 12 11 GND CS BIT 0 SDO TEST EOC TEST EOC BIT 31 EOC BIT 30 EOC Hi-Z Hi-Z BIT 29 BIT 28 SIG MSB BIT 27 Hi-Z BIT 9 TEST EOC BIT 8 Hi-Z SCK (EXTERNAL) SLEEP CONVERSION SLEEP DATA OUTPUT CONVERSION 2415 F09 DATA OUTPUT Figure 9. External Serial Clock, Reduced Data Output Length approximately 0.5ms after VCC exceeds 2.2V. The level applied to SCK at this time determines if SCK is internal or external. SCK must be driven LOW prior to the end of POR in order to enter the external serial clock timing mode. Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller indicating the conversion result is ready. EOC = 1 while the conversion is in progress and EOC = 0 once the conversion enters the sleep state. On the falling edge of EOC, the conversion result is loaded into an internal static shift register. The device remains in the sleep state until the first rising edge of SCK. Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge of SCK. EOC can be latched on the first rising edge of SCK. On the 32nd falling edge of SCK, SDO goes HIGH (EOC = 1) indicating a new conversion has begun. Internal Serial Clock, Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 11. 20 In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not enter the internal serial clock mode if SCK is driven LOW on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. When testing EOC, if the conversion is complete (EOC = 0), the device will exit the sleep state and enter the data output state if CS remains LOW. In order to prevent the device from exiting the sleep state, CS must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW For more information www.linear.com/LTC2415 2415fa LTC2415/LTC2415-1 APPLICATIONS INFORMATION 2.7V TO 5.5V VCC 1F 2 VCC FO LTC2415/ LTC2415-1 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 REF - ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 5 6 1, 7, 8, 9, 10, 15, 16 = 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR = 60Hz REJECTION (LTC2415) = 50Hz/60Hz REJECTION (LTC2415-1) 14 SCK IN + SDO IN - CS 13 2-WIRE INTERFACE 12 11 GND CS BIT 31 SDO BIT 30 EOC BIT 29 BIT 28 SIG MSB BIT 27 BIT 26 BIT 5 BIT 0 LSB24 SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2415 F10 Figure 10. External Serial Clock, CS = 0 Operation (2-Wire) VCC 2.7V TO 5.5V VCC 1F 2 VCC FO LTC2415/ LTC2415-1 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 REF - ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 5 IN + SDO IN - CS 6 1, 7, 8, 9, 10, 15, 16 = 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR = 60Hz REJECTION (LTC2415) = 50Hz/60Hz REJECTION (LTC2415-1) 14 SCK 10k 13 12 3-WIRE SPI INTERFACE 11 GND <tEOCtest CS TEST EOC SDO BIT 31 EOC Hi-Z BIT 30 BIT 29 BIT 28 SIG MSB BIT 27 BIT 26 BIT 5 LSB24 Hi-Z BIT 0 TEST EOC Hi-Z Hi-Z SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2415 F11 Figure 11. Internal Serial Clock, Single Cycle Operation 2415fa For more information www.linear.com/LTC2415 21 LTC2415/LTC2415-1 APPLICATIONS INFORMATION during the falling edge of EOC). The value of tEOCtest is 23s (LTC2415), 26s (LTC2415-1) if the device is using its internal oscillator (FO = logic LOW or HIGH). If FO is driven by an external oscillator of (LTC2415-1) frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the device remains in the sleep state. The conversion result is held in the internal static shift register. of SCK, see Figure 12. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving SCK LOW, the internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW. If CS remains LOW longer than tEOCtest, the first rising edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on this first rising edge of SCK and concludes after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH and a new conversion starts. Whenever SCK is LOW, the LTC2415/LTC2415-1 internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2415/LTC2415-1 internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CS, the device is switched to the external SCK timing mode. By adding an external 10k pull-up resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z. On the next CS falling edge, the device will remain in the internal SCK timing mode. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first and 32nd rising edge VCC 2.7V TO 5.5V VCC 1F 2 VCC FO LTC2415/ LTC2415-1 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 REF - ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 5 IN + SDO IN - CS 6 1, 7, 8, 9, 10, 15, 16 > tEOCtest = 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR = 60Hz REJECTION (LTC2415) = 50Hz/60Hz REJECTION (LTC2415-1) 14 SCK 10k 13 3-WIRE SPI INTERFACE 12 11 GND <tEOCtest CS TEST EOC BIT 0 SDO TEST EOC EOC Hi-Z BIT 31 EOC Hi-Z Hi-Z BIT 30 BIT 29 BIT 28 SIG MSB BIT 27 BIT 26 Hi-Z BIT 8 TEST EOC Hi-Z SCK (INTERNAL) SLEEP CONVERSION SLEEP DATA OUTPUT CONVERSION 2415 F12 DATA OUTPUT Figure 12. Internal Serial Clock, Reduced Data Output Length 2415fa 22 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 APPLICATIONS INFORMATION A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CS goes HIGH (within the time period defined above as tEOCtest), the internal pull-up is activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a HIGH level before CS goes low again. This is not a concern under normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin. weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected). During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion. Internal Serial Clock, 2-Wire I/O, Continuous Conversion This timing mode uses a 2-wire, all output (SCK and SDO) interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 13. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 0.5ms after VCC exceeds 2.2V. An internal 2.7V TO 5.5V VCC 1F 2 VCC FO LTC2415/ LTC2415-1 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 REF - ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 5 + SDO IN - CS 6 1, 7, 8, 9, 10, 15, 16 = 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR = 60Hz REJECTION (LTC2415) = 50Hz/60Hz REJECTION (LTC2415-1) 14 IN SCK 13 12 2-WIRE INTERFACE 11 GND CS BIT 31 SDO BIT 30 EOC BIT 29 BIT 28 SIG MSB BIT 27 BIT 26 BIT 5 BIT 0 LSB24 SCK (INTERNAL) CONVERSION DATA OUTPUT CONVERSION 2415 F13 SLEEP Figure 13. Internal Serial Clock, Continuous Operation 2415fa For more information www.linear.com/LTC2415 23 LTC2415/LTC2415-1 APPLICATIONS INFORMATION Internal Serial Clock, Auto-start Conversion conversion is immediately started. This is useful in applications requiring periodic monitoring and ultralow power. Figure 17 shows the average supply current as a function of capacitance on CS. This timing mode is identical to the internal serial clock, 2-wire I/O described above with one additional feature. Instead of grounding CS, an external timing capacitor is tied to CS. It should be noticed that the external capacitor discharge current is kept very small in order to decrease the converter power dissipation in the sleep state. In the auto-start mode, the analog voltage on the CS pin cannot be observed without disturbing the converter operation using a regular oscilloscope probe. When using this configuration, it is important to minimize the external leakage current at the CS pin by using a low leakage external capacitor and properly cleaning the PCB surface. While the conversion is in progress, the CS pin is held HIGH by an internal weak pull-up. Once the conversion is complete, the device enters the low power sleep state and an internal 25nA current source begins discharging the capacitor tied to CS, see Figure 14. The time the converter spends in the sleep state is determined by the value of the external timing capacitor, see Figures 15 and 16. Once the voltage at CS falls below an internal threshold (1.4V), the device automatically begins outputting data. The data output cycle begins on the first rising edge of SCK and ends on the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. After the 32nd rising edge, CS is pulled HIGH and a new The internal serial clock mode is selected every time the voltage on the CS pin crosses an internal threshold voltage. An internal weak pull-up at the SCK pin is active while CS is discharging; therefore, the internal serial clock timing mode is automatically selected if SCK is floating. It is important to ensure there are no external drivers pulling SCK LOW while CS is discharging. 2.7V TO 5.5V VCC 1F 2 VCC 3 REF + 4 REF - ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 5 1, 7, 8, 9, 10, 15, 16 = 50Hz REJECTION (LTC2415) = EXTERNAL OSCILLATOR = 60Hz REJECTION (LTC2415) = 50Hz/60Hz REJECTION (LTC2415-1) LTC2415/ LTC2415-1 REFERENCE VOLTAGE 0.1V TO VCC 6 FO 14 SCK IN + SDO IN - CS 13 2-WIRE INTERFACE 12 11 GND CEXT VCC CS GND BIT 31 SDO EOC Hi-Z BIT 30 BIT 29 SIG BIT 0 Hi-Z SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2415 F14 Figure 14. Internal Serial Clock, Auto-start Operation 24 For more information www.linear.com/LTC2415 2415fa LTC2415/LTC2415-1 APPLICATIONS INFORMATION 7 and the conversion time of the LTC2413 is 146ms, while the LTC2415-1 is 73ms. In systems where the SDO pin is monitored for the end-of-conversion signal (SDO goes low once the conversion is complete) these two devices can be interchanged. In cases where SDO is not monitored, a wait state is inserted between conversions, the duration of this wait state must be greater than 66.6ms for the LTC2415, greater than 133ms for the LTC2410, greater than 146ms for the LTC2413 and greater than 73ms for the LTC24151. 6 tSAMPLE (SEC) 5 4 3 2 VCC = 5V 1 0 VCC = 3V 10 100 1000 10000 CAPACITANCE ON CS (pF) 1 100000 2415 F15 Figure 15. CS Capacitance vs tSAMPLE The LTC2415/LTC2415-1 are designed to reduce as much as possible conversion result sensitivity to device decoupling, PCB layout, anti-aliasing circuits, line frequency perturbations and so on. Nevertheless, in order to preserve the extreme accuracy capability of this part, some simple precautions are desirable. 8 7 SAMPLE RATE (Hz) 6 VCC = 5V 5 VCC = 3V 4 PRESERVING THE CONVERTER ACCURACY 3 2 Digital Signal Levels 1 0 0 10 100 10000 100000 1000 CAPACITANCE ON CS (pF) 2415 F16 Figure 16. CS Capacitance vs Output Rate 300 SUPPLY CURRENT (ARMS) 250 VCC = 5V The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during conversion. 200 VCC = 3V 150 100 50 0 1 10 100 1000 10000 CAPACITANCE ON CS (pF) The LTC2415/LTC2415-1 digital interface is easy to use. Its digital inputs (FO, CS and SCK in External SCK mode of operation) accept standard TTL/CMOS logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100s. However, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter. 100000 2415 F17 Figure 17. CS Capacitance vs Supply Current Timing Compatibility with the LTC2410/LTC2413 All timing modes described above are identical with respect to the LTC2410/LTC2413 and LTC2415/LTC2415-1, with one exception. The conversion time of the LTC2410 is 133ms while the conversion time of the LTC2415 is 66.6ms While a digital input signal is in the range 0.5V to (VCC - 0.5V), the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (FO, CS and SCK in External SCK mode of operation) is within this range, the LTC2415/LTC2415-1 power supply current may increase even if the signal in question is at a valid logic level. For micropower operation, it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VOH > (VCC - 0.4V)]. During the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the LTC2415/ 2415fa For more information www.linear.com/LTC2415 25 LTC2415/LTC2415-1 APPLICATIONS INFORMATION LTC24151 pins may severely disturb the analog to digital conversion process. Undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to LTC2415/LTC24151. For reference, on a regular FR-4 board, signal propagation velocity is approximately 183ps/ inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance. Parallel termination near the LTC2415/LTC24151 pins will eliminate this problem but will increase the driver power dissipation. A series resistor between 27 and 56 placed near the driver or near the LTC2415/LTC24151 pins will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology. An alternate solution is to reduce the edge rate of the control signals. It should be noted that using very slow edges will increase the converter power supply current during the transition time. The multiple ground pins used in this package configuration, as well as the differential input and reference architecture, reduce substantially the converter's sensitivity to ground currents. Particular attention must be given to the connection of the FO signal when the LTC2415/LTC24151 are used with an external conversion clock. This clock is active during the conversion time and the normal mode rejection provided by the internal digital filter is not very high at this frequency. A normal mode signal of this frequency at the converter reference terminals may result into DC gain and INL errors. A normal mode signal of this frequency at the converter input terminals may result into a DC offset error. Such perturbations may occur due to asymmetric capacitive coupling between the FO signal trace and the converter input and/or reference connection traces. An immediate solution is to maintain maximum possible separation between the FO signal trace and the input/ref- erence signals. When the FO signal is parallel terminated near the converter, substantial AC current is flowing in the loop formed by the FO connection trace, the termination and the ground return path. Thus, perturbation signals may be inductively coupled into the converter input and/ or reference. In this situation, the user must reduce to a minimum the loop area for the FO signal as well as the loop area for the differential input and reference connections. Driving the Input and Reference The input and reference pins of the LTC2415/LTC24151 converters are directly connected to a network of sampling capacitors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transferring small amounts of charge in the process. A simplified equivalent circuit is shown in Figure 18. For a simple approximation, the source impedance RS driving an analog input pin (IN+, IN-, REF+ or REF-) can be considered to form, together with RSW and CEQ (see Figure 18), a first order passive network with a time constant = (RS + RSW) * CEQ. The converter is able to sample the input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant . The sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worst-case circumstances, the errors may add. When using the internal oscillator (FO = LOW or HIGH), the LTC2415's front-end switched-capacitor network is clocked at 76800Hz corresponding to a 13s sampling period and the LTC2415-1's front end is clocked at 69900Hz corresponding to 14.2s. Thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that 13s/14 = 920ns (LTC2415) and <14.2s/14 = 1.01s (LTC24151). When an external oscillator of frequency fEOSC is used, the sampling period is 2/fEOSC and, for a settling error of less than 1ppm, 0.14/fEOSC. Input Current If complete settling occurs on the input, conversion results will be unaffected by the dynamic input current. An 2415fa 26 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 APPLICATIONS INFORMATION IREF+ VCC ILEAK VREF+ ILEAK RSW (TYP) 20k ( VIN - VCC ILEAK RSW (TYP) 20k ) AVG ) AVG = 2 1.5* VREF - VINCM + VREFCM VIN - 0.5*REQ VREF *REQ = 2 -1.5* VREF - VINCM + VREFCM VIN + 0.5*REQ VREF *REQ VREF = REF + - REF - SWITCHING FREQUENCY fSW = 76800Hz INTERNAL OSCILLATOR (LTC2415) (FO = LOW OR HIGH) fSW = 69900Hz INTERNAL OSCILLATOR (LTC2415-1) (FO = LOW) fSW = 0.5 * fEOSC EXTERNAL OSCILLATOR ILEAK VIN + VINCM - VREFCM 0.5*REQ -V + V -V = IN INCM REFCM 0.5*REQ = where : CEQ 18pF (TYP) RSW (TYP) 20k ILEAK + I REF - VCC VREF - AVG ( ILEAK IREF - ( ) I REF VCC VIN+ IIN - AVG I IN- ILEAK IIN+ ( ) I IN+ RSW (TYP) 20k ILEAK 2415 F18 REF + + REF - VREFCM = 2 VIN = IN+ - IN- IN+ - IN- VINCM = 2 REQ = 3.61M INTERNAL OSCILLATOR 60Hz Notch (FO = LOW ) LTC2415 REQ = 4.32M INTERNAL OSCILLATOR 50Hz Notch (FO = HIGH) LTC2415 ( ) REQ = 0.555* 1012 / fEOSC EXTERNAL OSCILLATOR REQ = 3.97M INTERNAL OSCILLATOR 50Hz / 60Hz Notch (FO = LOW ) LTC2415-1 Figure 18. LTC2415/LTC2415-1 Equivalent Analog Input Circuit RSOURCE VINCM + 0.5VIN IN + CIN CPAR 20pF RSOURCE VINCM - 0.5VIN LTC2415/ LTC2415-1 IN - CIN CPAR 20pF 2415 F19 +FS ERROR (ppm OF VREF) The effect of this input dynamic current can be analyzed using the test circuit of Figure 19. The CPAR capacitor includes the LTC2415/LTC24151 pin capacitance (5pF typical) plus the capacitance of the test fixture used to obtain the results shown in Figures 20 and 21. A careful implementation can bring the total input capacitance (CIN + CPAR) closer to 5pF thus achieving better performance than the one predicted by Figures 20 and 21. For simplicity, two distinct situations can be considered. 50 CIN = 0.01F CIN = 0.001F 40 CIN = 100pF CIN = 0pF 30 VCC = 5V REF + = 5V REF - = GND IN + = 5V IN - = 2.5V FO = GND TA = 25C 20 10 0 1 10 100 1k RSOURCE () 10k 100k 2415 F20 Figure 20. +FS Error vs RSOURCE at IN+ or IN- (Small CIN) 0 -FS ERROR (ppm OF VREF) incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade the INL performance of the converter. Figure 18 shows the mathematical expressions for the average bias currents flowing through the IN+ and IN- pins as a result of the sampling charge transfers when integrated over a substantial time period (longer than 64 internal clock cycles). VCC = 5V REF + = 5V REF - = GND IN + = GND IN - = 2.5V FO = GND TA = 25C -10 -20 -30 CIN = 0.01F CIN = 0.001F -40 -50 CIN = 100pF CIN = 0pF 1 10 100 1k RSOURCE () 10k 100k 2415 F21 Figure 19. An RC Network at IN + and IN- Figure 21. -FS Error vs RSOURCE at IN+ or IN- (Small CIN) For more information www.linear.com/LTC2415 2415fa 27 LTC2415/LTC2415-1 APPLICATIONS INFORMATION For relatively small values of input capacitance (CIN < 0.01F), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CIN will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them. Nevertheless, when small values of CIN are unavoidably present as parasitics of input multiplexers, wires, connectors or sensors, the LTC2415/ LTC24151 can maintain their exceptional accuracy while operating with relative large values of source resistance as shown in Figures 20 and 21. These measured results may be slightly different from the first order approximation suggested earlier because they include the effect of the actual second order input network together with the nonlinear settling process of the input amplifiers. For small CIN values, the settling on IN+ and IN- occurs almost independently and there is little benefit in trying to match the source impedance for the two pins. Larger values of input capacitors (CIN > 0.01F) may be required in certain configurations for anti-aliasing or general input signal filtering. Such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. When FO = LOW (internal oscillator and 60Hz notch), the typical differential input resistance is 1.8M (LTC2415), 1.97M (LTC24151) which will generate a gain error of approximately 0.28ppm for each ohm of source resistance driving IN+ or IN-. For the LTC2415, when FO = HIGH (internal oscillator and 50Hz notch), the typical differential input resistance is 2.16M which will generate a gain error of approximately 0.23ppm for each ohm of source resistance driving IN+ or IN-. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential input resistance is 0.28 * 1012/fEOSC and each ohm of source resistance driving IN+ or IN- will result in 1.78 * 10-6 * fEOSCppm gain error. The effect of the source resistance on the two input pins is additive with respect to this gain error. The typical +FS and -FS errors as a function of the sum of the source resistance seen by IN+ and IN- for large values of CIN are shown in Figures 22 and 23. In addition to this gain error, an offset error term may also appear. The offset error is proportional to the mismatch between the source impedance driving the two input pins IN+ and IN- and with the difference between the input and reference common mode voltages. While the input drive circuit nonzero source impedance combined with the converter average input current will not degrade the INL performance, indirect distortion may result from the modulation of the offset error by the common mode component of the input signal. Thus, when using large CIN capacitor values, it is advisable to carefully match the source impedance seen by the IN+ and IN- pins. When FO = LOW (internal oscillator and 60Hz notch), every 1 mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.28ppm. When FO = HIGH (internal oscillator and 50Hz notch), every 1 mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.23ppm. When FO is driven by an external oscillator with a frequency fEOSC, every 1 mismatch in source impedance transforms a fullscale common mode input signal into a differential mode input signal of 1.78 * 10-6 * fEOSCppm. Figure 24 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the IN+ and IN- pins when large CIN values are used. If possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. This configuration eliminates the offset error caused by mismatched source impedances. The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/C) are used for the external source impedance seen by IN+ and IN-, the expected drift of the dynamic current, offset and gain 2415fa 28 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 APPLICATIONS INFORMATION errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (10nA max), results in a small offset shift. A 100 source resistance will create a 0.1V typical and 1V maximum offset voltage. 240 180 VCC = 5V REF + = 5V REF - = GND IN + = 3.75V IN - = 1.25V FO = GND TA = 25C 0 CIN = 1F, 10F CIN = 0.01F -FS ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) 300 CIN = 0.1F 120 60 0 CIN = 0.01F -60 -120 -240 -300 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE () VCC = 5V REF + = 5V REF - = GND IN + = 1.25V IN - = 3.75V FO = GND TA = 25C -180 2415 F23 Figure 22. +FS Error vs RSOURCE at IN+ or IN- (Large CIN) 120 100 OFFSET ERROR (ppm OF VREF) CIN = 1F, 10F 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE () 2415 F22 60 B 40 Figure 23. -FS Error vs RSOURCE at IN+ or IN- (Large CIN) VCC = 5V REF + = 5V REF - = GND IN + = IN - = VINCM A 80 C 20 D 0 E -20 F -40 -60 FO = GND TA = 25C RSOURCEIN - = 500 CIN = 10F G -80 -100 -120 CIN = 0.1F 0 0.5 1 1.5 A: RIN = +400 B: RIN = +200 C: RIN = +100 D: RIN = 0 2 2.5 3 VINCM (V) 3.5 4 4.5 5 E: RIN = -100 F: RIN = -200 G: RIN = -400 2415 F24 Figure 24. Offset Error vs Common Mode Voltage (VINCM = IN+ = IN-) and Input Source Resistance Imbalance (RIN = RSOURCEIN+ - RSOURCEIN-) for Large CIN Values (CIN 1F) 2415fa For more information www.linear.com/LTC2415 29 LTC2415/LTC2415-1 APPLICATIONS INFORMATION Reference Current In a similar fashion, the LTC2415/LTC24151 sample the differential reference pins REF+ and REF- transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in the same two distinct situations. For relatively small values of the external reference capacitors (CREF < 0.01F), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (CREF > 0.01F) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. For the LTC2415, when FO = LOW (internal oscillator and 60Hz notch), the typical differential reference resistance is 1.3M which will generate a gain error of approximately 0.38ppm for each ohm of source resistance driving REF+ or REF-. When FO = HIGH (internal oscillator and 50Hz notch), the typical differential reference resistance is 1.56M which will generate a gain error of approximately 0.32ppm for each ohm of source resistance driving REF+ or REF-. For the LTC24151, the typical differential reference resistance is 1.43M. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differen50 VCC = 5V REF + = 5V REF - = GND IN + = 5V IN - = 2.5V FO = GND TA = 25C -10 -20 -30 CREF = 0.01F CREF = 0.001F -40 -50 -FS ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) 0 CREF = 100pF CREF = 0pF 1 10 100 1k RSOURCE () 10k 40 CREF = 100pF CREF = 0pF 30 VCC = 5V REF + = 5V REF - = GND IN + = GND IN - = 2.5V FO = GND TA = 25C 20 10 0 100k CREF = 0.01F CREF = 0.001F 1 10 100 1k RSOURCE () 2415 F25 Figure 25. +FS Error vs RSOURCE at REF+ or REF- (Small CIN) -180 -360 -450 Figure 26. -FS Error vs RSOURCE at REF+ or REF- (Small CIN) 450 CREF = 0.01F -90 -270 2415 F26 CREF = 0.1F VCC = 5V REF + = 5V REF - = GND IN + = 3.75V IN - = 1.25V FO = GND TA = 25C CREF = 1F, 10F 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE () -FS ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) 0 360 270 180 90 0 2415 F27 Figure 27. +FS Error vs RSOURCE at REF+ and REF- (Large CREF) 30 100k 10k VCC = 5V REF + = 5V REF - = GND IN + = 1.25V IN - = 3.75V FO = GND TA = 25C CREF = 1F, 10F CREF = 0.1F CREF = 0.01F 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE () 2415 F28 Figure 28. -FS Error vs RSOURCE at REF+ and REF- (Large CREF) For more information www.linear.com/LTC2415 2415fa LTC2415/LTC2415-1 APPLICATIONS INFORMATION tial reference resistance is 0.20 * 1012/fEOSC and each ohm of source resistance driving REF+ or REF- will result in 2.47 * 10-6 * fEOSCppm gain error. The effect of the source resistance on the two reference pins is additive with respect to this gain error. The typical +FS and -FS errors for various combinations of source resistance seen by the REF+ and REF- pins and external capacitance CREF connected to these pins are shown in Figures 25, 26, 27 and 28. In addition to this gain error, the converter INL performance is degraded by the reference source impedance. When FO = LOW (internal oscillator and 60Hz notch), every 100 of source resistance driving REF+ or REF- translates into about 1.34ppm additional INL error. For the LTC2415, when FO = HIGH (internal oscillator and 50Hz notch), every 100 of source resistance driving REF+ or REF- translates into about 1.1ppm additional INL error; and for the LTC24151 operating with simultaneous 50Hz/60Hz rejection, every 100 of source resistance leads to an additional 1.22ppm of additional INL error. When FO is driven by an external oscillator with a frequency fEOSC, every 100 of source resistance driving REF+ or REF- translates into about 8.73 * 10-6 * fEOSCppm additional INL error. Figure 26 shows the typical INL error due to the source resistance driving the REF+ or REF- pins when large CREF values are used. The effect of the source resistance on the two reference pins is additive with respect to this INL error. In general, matching of source impedance for the REF+ and REF- pins does not help the gain or the INL error. The user is thus advised to minimize the combined source impedance driving the REF+ and REF- pins rather than to try to match it. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/C) are used for the external source impedance seen by REF+ and REF-, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient. In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (10nA max), results in a small gain error. A 100 source resistance will create a 0.05V typical and 0.5V maximum full-scale error. 15 12 9 INL (ppm OF VREF) VCC = 5V REF+ = 5V REF- = GND VINCM = 0.5 * (IN + + IN -) = 2.5V FO = GND CREF = 10F TA = 25C RSOURCE = 1000 RSOURCE = 500 6 3 0 -3 RSOURCE = 100 -6 -9 -12 -15 -0.5 -0.4-0.3-0.2-0.1 0 0.1 0.2 0.3 0.4 0.5 VINDIF/VREFDIF 2415 F29 Figure 29. INL vs Differential Input Voltage (VIN = IN+ - IN-) and Reference Source Resistance (RSOURCE at REF+ and REF- for Large CREF Values (CREF 1F) 2415fa For more information www.linear.com/LTC2415 31 LTC2415/LTC2415-1 APPLICATIONS INFORMATION Normal Mode Rejection, Output Rate and Running Averages a running average can be performed. By averaging two consecutive ADC readings, a Sinc1 notch is combined with the Sinc4 digital filter yielding the frequency response shown in Figures 33 and 34. In order to preserve the 2x output rate, adjacent results are averaged with the following algorithm: The LTC2415/LTC2415-1 both contain an identical Sinc4 digital filter (see Figures 30 and 31) which offers excellent line frequency noise rejection. For the LTC2415, a notch frequency of either 50Hz or 60Hz (see Figure 32) is user selectable by tying pin FO high or low, respectively. On the other hand, the LTC2415-1 offers simultaneous rejection of 50Hz and 60Hz by tying FO low. This sets the notch frequency to approximately 55Hz (see Figure 32). Result 1 = average (sample 0, sample 1) Result 2 = average (sample 1, sample 2) Result 3 = average (sample 2, sample 3) ... At a notch frequency of 55Hz, the LTC2415-1 rejects 50Hz 2% and 60Hz 2% better than 72dB. In order to achieve better than 87dB rejection of both 50Hz and 60Hz 2%, VCC = 5V VREF = 5V VIN = 2.5V FO = 0 -40 -60 -80 -20 -70 -80 -60 -80 -100 -100 -120 -60 -40 REJECTION (dB) REJECTION (dB) -20 0 REJECTION (dB) 0 Result N = average (sample n-1, sample n) 50 100 150 200 FREQUENCY AT VIN (Hz) -140 250 fS/2 0 fS INPUT FREQUENCY Figure 31. Rejection vs Frequency at VIN 0 -90 -20 NORMAL MODE REJECTION (dB) NORMAL MODE REJECTION RATIO (dB) -140 -12 -8 -4 0 4 8 12 INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%) 2415 F32 2415 F31 -80 -100 -100 -120 -130 -140 -110 -130 2415 F30 Figure 30. Rejection vs Frequency at VIN -100 -120 -120 1 -90 48 50 52 54 56 58 60 62 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) Figure 32. Rejection vs Frequency at VIN MEASURED DATA CALCULATED DATA -40 VCC = 5V REF + = 5V REF - = GND VINCM = 2.5V VIN(P-P) = 5V TA = 25C - 60 -80 -100 -120 0 20 40 60 80 100 120 140 INPUT FREQUENCY (Hz) 160 180 200 220 2415 F34 2415 F33 Figure 33. Normal Mode Rejection when Using an Internal Oscillator Figure 34. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% of Full Scale 2415fa 32 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 APPLICATIONS INFORMATION Sample Driver for LTC2415/LTC2415-1 SPI Interface The code begins by declaring variables and allocating four memory locations to store the 32-bit conversion result. This is followed by initializing PORT D's SPI configuration. The program then enters the main sequence. It activates the LTC2415/LTC24151 serial interface by setting the SS output low, sending a logic low to CS. It next waits in a loop for a logic low on the data line, signifying end-ofconversion. After the loop is satisfied, four SPI transfers are completed, retrieving the conversion. The main sequence ends by setting SS high. This places the LTC2415/ LTC24151 serial interface in a high impedance state and initiates another conversion. Figure 35 shows the use of an LTC2415/LTC24151 with a differential multiplexer. This is an inexpensive multiplexer that will contribute some error due to leakage if used directly with the output from the bridge, or if resistors are inserted as a protection mechanism from overvoltage. Although the bridge output may be within the input range of the A/D and multiplexer in normal operation, some thought should be given to fault conditions that could result in full excitation voltage at the inputs to the multiplexer or ADC. The use of amplification prior to the multiplexer will largely eliminate errors associated with channel leakage developing error voltages in the source impedance. The performance of the LTC2415/LTC24151 can be verified using the demonstration board DC291A, see Figure 40 for the schematic. This circuit uses the computer's serial port to generate power and the SPI digital signals necessary for starting a conversion and reading the result. It includes a Labview application software program (see Figure 39) which graphically captures the conversion results. It can be used to determine noise performance, stability and with an external source, linearity. As exemplified in the schematic, the LTC2415/LTC24151 are extremely easy to use. This demonstration board and associated software is available by contacting Linear Technology. The LTC2415/LTC24151 have a very simple serial interface that makes interfacing to microprocessors and microcontrollers very easy. The listing in Figure 38 is a simple assembler routine for the 68HC11 microcontroller. It uses PORT D, configuring it for SPI data transfer between the controller and the LTC2415/LTC24151. Figure 36 shows the simple 3-wire SPI connection. 5V 5V + 16 12 14 15 11 3 REF + 4 REF - 5 2 13 5 3 IN + 6 IN - 6 4 8 9 2 VCC LTC2415/ LTC2415-1 74HC4052 1 TO OTHER DEVICES 47F 10 GND 1, 7, 8, 9, 10, 15, 16 2415 F35 A0 A1 Figure 35. Use a Differential Multiplexer to Expand Channel Capability SCK LTC2415/ SDO LTC2415-1 CS 13 12 11 68HC11 SCK (PD4) MISO (PD2) SS (PD5) 2415 F36 Figure 36. Connecting the LTC2415/LTC2415-1 to a 68HC11 MCU Using the SPI Serial Interface For more information www.linear.com/LTC2415 2415fa 33 LTC2415/LTC2415-1 APPLICATIONS INFORMATION Correlated Double Sampling with the LTC2415/LTC2415-1 Figure 37 shows the LTC2415/LTC2415-1 in a correlated double sampling circuit that achieves a noise floor of under 100nV. In this scheme, the polarity of the bridge is alternated every other sample and the result is the average of a pair of samples of opposite sign. This technique has the benefit of canceling any fixed DC error components in the bridge, amplifiers and the converter, as these will alternate in polarity relative to the signal. Offset voltages and currents, thermocouple voltages at junctions of dissimilar metals and the lower frequency components of 1/f noise are virtually eliminated. The LTC2415/LTC2415-1 have the virtue of being able to digitize an input voltage that is outside the range defined by the reference, thereby providing a simple means to implement a ratiometric example of correlated double sampling. This circuit uses a bipolar amplifier (LT1219--U1 and U2) that has neither the lowest noise nor the highest gain. It does, however, have an output stage that can effectively suppress the conversion spikes from the LTC2415/ LTC2415-1. The LT1219 is a C-LoadTM stable amplifier that, by design, needs at least 0.1F output capacitance to remain stable. The 0.1F ceramic capacitors at the outputs (C1 and C2) should be placed and routed to minimize lead inductance or their effectiveness in preventing envelope detection in the input stage will be reduced. Alternatively, several smaller capacitors could be placed so that lead inductance is further reduced. This is a consideration because the frequency content of the conversion spikes extends to 50MHz or more. The output impedance of most op amps increases dramatically with frequency but the effective output impedance of the LT1219 remains low, determined by the ESR and inductance of the capacitors above 10MHz. The conversion spikes that remain at the output of other bipolar amplifiers pass through the feedback network and often overdrive the input of the amplifier, producing envelope detection. RFI may also be present on the signal lines from the bridge; C3 and C4 provide RFI suppression at the signal input, as well as suppressing transient voltages during bridge commutation. The wideband noise density of the LT1219 is 33nVHz, seemingly much noisier than the lowest noise amplifiers. However, in the region just below the 1/f corner that is not well suppressed by the correlated double sampling, the average noise density is similar to the noise density of many low noise amplifiers. If the amplifier is rolled off below about 1500Hz, the total noise bandwidth is determined by the converter's Sinc4 filter at about 12Hz. The use of correlated double sampling involves averaging even numbers of samples; hence, in this situation, two samples would be averaged to give an input-referred noise level of about 100nVRMS. Level shift transistors Q4 and Q5 are included to allow excitation voltages up to the maximum recommended for the bridge. In the case shown, if a 10V supply is used, the excitation voltage to the bridge is 8.5V and the outputs of the bridge are above the supply rail of the ADC. U1 and U2 are also used to produce a level shift to bring the outputs within the input range of the converter. This instrumentation amplifier topology does not require well-matched resistors in order to produce good CMRR. However, the use of R2 requires that R3 and R6 match well, as the common mode gain is approximately -12dB. If the bridge is composed of four equal 350 resistors, the differential component associated with mismatch of R3 and R6 is nearly constant with either polarity of excitation and, as with offset, its contribution is canceled. 2415fa 34 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 APPLICATIONS INFORMATION 10V ELIMINATE FOR 5V OPERATION (CONNECT 2.7k RESISTORS TO 100 RESISTORS) 1.5k 1.5k Q2 100 DIFFERENCE AMP 10V 0.1f Q3 3 100 R2 27k 22 5V Q4 5V 22 Q5 - 1k 1000pF 2.7k 2 + 7 U1 LT1219 4 5k 6 5 C1 0.1F SHDN 5V R4 499 R3 10k 2.7k 5 C3 2.2nF C4 2.2nF 350 x4 R5 499 6 IN- LTC2415/ LTC2415-1 3 REF+ R6 10k 1000pF 10V POL 0.1f 1k 74HC04 2 Q1 3 - + 22 R1 61.9 0.1% 5k 6 REF- GND 5 C2 0.1F SHDN 33 100 22 4 7 U2 LT1219 4 IN+ Q1: SILICONIX Si9802DY Q2, Q3: MMBD2907 Q4, Q5: MMBD3904 (800) 554-5565 30pF 30pF 2415 F37 Figure 37. Correlated Double Sampling Resolves 100nV 2415fa For more information www.linear.com/LTC2415 35 LTC2415/LTC2415-1 TYPICAL APPLICATIONS ************************************************************ * This example program transfers the LTC2415/LTC2415-1 32-bit output * * conversion result into four consecutive 8-bit memory locations. ************************************************************ *68HC11 register definition PORTD EQU $1008 Port D data register * " - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD" DDRD EQU $1009 Port D data direction register SPSR EQU $1028 SPI control register * "SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0" SPSR EQU $1029 SPI status register * "SPIF,WCOL, - ,MODF; - , - , - , - " SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * RAM variables to hold the LTC2415/LTC2415-1's 32 conversion result * DIN1 EQU $00 This memory location holds the LTC2415/LTC2415-1's bits $01 This memory location holds the LTC2415/LTC2415-1's bits DIN2 EQU DIN3 EQU $02 This memory location holds the LTC2415/LTC2415-1's bits DIN4 EQU $03 This memory location holds the LTC2415/LTC2415-1's bits * ********************** * Start GETDATA Routine * ********************** * ORG $C000 Program start location INIT1 LDS #$CFFF Top of C page RAM, beginning location of stack LDAA #$2F -,-,1,0;1,1,1,1 -, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X * STAA PORTD Keeps SS* a logic high when DDRD, bit 5 is set LDAA #$38 -,-,1,1;1,0,0,0 STAA DDRD SS*, SCK, MOSI are configured as Outputs * MISO, TxD, RxD are configured as Inputs *DDRD's bit 5 is a 1 so that port D's SS* pin is a general output LDAA #$50 STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0 and the clock rate is E/2 * * (This assumes an E-Clock frequency of 4MHz. For higher EClock frequencies, change the above value of $50 to a value * that ensures the SCK frequency is 2MHz or less.) * PSHX GETDATA PSHY PSHA LDX #$0 The X register is used as a pointer to the memory locations * that hold the conversion data LDY #$1000 BCLR PORTD, Y %00100000 This sets the SS* output bit to a logic *low, selecting the LTC2415/LTC2415-1 * * 31 23 15 07 - 24 16 08 00 2415fa 36 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 TYPICAL APPLICATIONS ******************************************** * The next short loop waits for the * * LTC2415/LTC2415-1's conversion to finish before * * starting the SPI data transfer * ******************************************** * CONVEND LDAA PORTD Retrieve the contents of port D ANDA #%00000100 Look at bit 2 * Bit 2 = Hi; the LTC2415/LTC2415-1's conversion is not * complete * Bit 2 = Lo; the LTC2415/LTC2415-1's conversion is complete BNE CONVEND Branch to the loop's beginning while bit 2 remains high * * ******************** * The SPI data transfer * ******************** * Load accumulator A with a null byte for SPI transfer TRFLP1 LDAA #$0 STAA SPDR This writes the byte in the SPI data register and starts * the transfer WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial transfer/exchange by reading the SPI Status Register BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR's MSB and is set to one at the end of an SPI transfer. The branch * * will occur while SPIF is a zero. LDAA SPDR Load accumulator A with the current byte of LTC2415/LTC2415-1 data that was just received STAA 0,X Transfer the LTC2415/LTC2415-1's data to memory INX Increment the pointer CPX #DIN4+1 Has the last byte been transferred/exchanged? BNE TRFLP1 If the last byte has not been reached, then proceed to the * next byte for transfer/exchange BSET PORTD,Y %00100000 This sets the SS* output bit to a logic high, de-selecting the LTC2415/LTC2415-1 * PULA Restore the A register PULY Restore the Y register PULX Restore the X register RTS Figure 38. This is an Example of 68HC11 Code That Captures the LTC2415/LTC2415-1 Conversion Results Over the SPI Serial Interface Shown in Figure 40 2415fa For more information www.linear.com/LTC2415 37 LTC2415/LTC2415-1 TYPICAL APPLICATIONS Figure 39. Display Graphic PCB LAYOUT AND FILM LTC2415CGN Differential Input 24-Bit ADC with 2 Output Rate Demo Circuit DC382 www.linear-tech.com LTC Confidential For Customer Use Only Silkscreen Top Top Layer 2415fa 38 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 PCB LAYOUT AND FILM Bottom Layer 2415fa For more information www.linear.com/LTC2415 39 LTC2415/LTC2415-1 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641 Rev B) .189 - .196* (4.801 - 4.978) .045 .005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .0165 .0015 .150 - .157** (3.810 - 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .0532 - .0688 (1.35 - 1.75) 2 3 4 5 6 7 8 .004 - .0098 (0.102 - 0.249) 0 - 8 TYP .016 - .050 (0.406 - 1.270) .008 - .012 (0.203 - 0.305) TYP NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .0250 (0.635) BSC GN16 REV B 0212 3. DRAWING NOT TO SCALE 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 2415fa 40 For more information www.linear.com/LTC2415 LTC2415/LTC2415-1 REVISION HISTORY REV DATE DESCRIPTION A 08/15 Reduced external oscillator maximum frequency to 500kHz. PAGE NUMBER Removed noise histogram plots for 105Hz output rate. Adjusted output data rate on G27 to maximum of 50 readings/second. 5 6, 7 9 2415fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC2415 41 LTC2415/LTC2415-1 TYPICAL APPLICATION VCC U1 LT1460ACN8-2.5 JP1 JUMPER 1 3 6 VOUT + 2 VIN VCC 2 GND C1 10F 35V R2 3 + 4 U2 LT1236ACN8-5 JP2 JUMPER 1 2 6 VOUT + C2 22F 25V C3 10F 35V + 4 10 VCC J5 GND 1 C6 0.1F 1 BANANA JACK J6 1 REF + + 3 4 5 BANANA JACK J7 1 REF - 6 BANANA JACK J8 1 VIN+ C5 10F 35V 1 J2 GND 2 11 CS FO REF - SCK VIN+ SDO VIN - 6 13 R3 51k 2 7 3 8 2 VCC REF + 12 11 U4 LTC2415/ LTC2415-1 GND GND GND U3B 74HC14 4 4 9 U3A 74HC14 3 2 5 R4 51k 1 14 13 U3C 74HC14 12 16 15 5 U3D 74HC14 6 10 9 R5 49.9 R6 3k 8 1 R7 22k 3 2 R8 51k JP5 JUMPER 2 J1 VEXT P1 DB9 U3F 74HC14 GND GND GND GND 1 7 8 9 1 1 3 C4 100F 16V 1 JP4 JUMPER 1 3 VCC J3 BANANA JACK J10 1 GND 2 GND U3E 74HC14 2 BANANA JACK J9 1 VIN - R1 10 1 JP3 JUMPER 1 3 BANANA JACK J4 1 VEXT VIN D1 BAV74LT1 2 Q1 MMBT3904LT1 VCC NOTES: INSTALL JUMBER JP1 AT PIN 1 AND PIN 2 INSTALL JUMBER JP2 AT PIN 1 AND PIN 2 INSTALL JUMBER JP3 AT PIN 1 AND PIN 2 BYPASS CAP FOR U3 C7 0.1F 2415 F40 Figure 40. 24-Bit A/D Demo Board Schematic RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1019 Precision Bandgap Reference, 2.5V, 5V 3ppm/C Drift, 0.05% Max Initial Accuracy LT1025 Micropower Thermocouple Cold Junction Compensator 80A Supply Current, 0.5C Initial Accuracy LTC1043 Dual Precision Instrumentation Switched Capacitor Building Block Precise Charge, Balanced Switching, Low Power LTC1050 Precision Chopper Stabilized Op Amp No External Components 5V Offset, 1.6VP-P Noise LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max Initial Accuracy, 5ppm/C Drift LT1460 Micropower Series Reference 0.075% Max Initial Accuracy, 10ppm/C Max Drift, LTC2400 24-Bit, No Latency ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ADCs in MSOP LTC2414/LTC2418 4-/8-Channel, 24-Bit, No Latency ADCs with Differential Inputs 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A LTC2410 24-Bit, No Latency ADC with Differential Inputs 800nVRMS Noise, Pin Compatible with LTC2415 LTC2411 24-Bit, No Latency ADC with Differential Inputs in MSOP 1.45VRMS Noise, 4ppm INL LTC2413 24-Bit, No Latency ADC with Differential Inputs Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise LTC2420 20-Bit, No Latency ADC in SO-8 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 2415fa 42 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2415 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC2415 LT 0815 REV A * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2001