Micropower, OVP, Rail-to-Rail Input/Output Operational Amplifier ADA4091-2 PIN CONFIGURATION Single-supply operation: 3 V to 36 V Wide input voltage range Rail-to-rail output swing Low supply current: 250 A/amplifier Wide bandwidth: 1.2 MHz Slew rate: 0.46 V/s Low offset voltage: 500 V maximum No phase reversal Overvoltage protection (OVP) 25 V above/below supply rails at 5 V 12 V above/below supply rails at 15 V OUTA 1 8 +V ADA4091-2 7 OUTB TOP VIEW -V 4 (Not to Scale) 6 -INB 5 +INB -INA 2 +INA 3 07671-001 FEATURES Figure 1. 8-Lead, Narrow-Body SOIC APPLICATIONS Industrial process control Battery-powered instrumentation Power supply control and protection Telecommunications Remote sensors Low voltage strain gage amplifiers DAC output amplifiers GENERAL DESCRIPTION The ADA4091-2 is a dual, micropower, single-supply, 1.2 MHz bandwidth amplifier featuring rail-to-rail inputs and outputs. It is guaranteed to operate from a +3 V single supply as well as from 15 V dual supplies. The ADA4091 family of op amps features a unique input stage that allows the input voltage to exceed either supply safely without any phase inversion or latch-up; this is called overvoltage protection, or OVP. The output voltage swings to within 10 mV of the supplies. Applications for these amplifiers include portable telecommunications equipment, power supply control and protection, and interface for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezoelectric, and resistive transducers. The ability to swing rail-to-rail at both the input and output enables designers to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios. The ADA4091 family of op amps is specified over the extended industrial temperature range of -40C to +125C. The ADA4091-2 is part of a growing family of 36 V, low power op amps from Analog Devices, Inc., (see Table 1). The ADA4091-2 is available in an 8-lead plastic SOIC surfacemount package. Table 1. Low Power, 36 V Operational Amplifiers Family Single Dual Quad Rail-to-Rail I/O PJFET ADA4091-2 AD8682 AD8684 Low Noise OP1177 OP2177 OP4177 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008-2009 Analog Devices, Inc. All rights reserved. ADA4091-2 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 Pin Configuration ............................................................................. 1 Theory of Operation ...................................................................... 14 General Description ......................................................................... 1 Input Stage ................................................................................... 14 Revision History ............................................................................... 2 Output Stage................................................................................ 14 Specifications..................................................................................... 3 Input Overvoltage Protection ................................................... 15 Electrical Specifications ............................................................... 3 Outline Dimensions ....................................................................... 16 Absolute Maximum Ratings............................................................ 6 Ordering Guide .......................................................................... 16 Thermal Resistance ...................................................................... 6 REVISION HISTORY 7/09--Rev. 0 to Rev. A Changes to Data Sheet Title ............................................................ 1 Changes to Features.......................................................................... 1 Changes to Table 2 ............................................................................ 3 Changes to Table 3 ............................................................................ 4 Changes to Table 4 ............................................................................ 5 Added Input Current Parameter, Table 5 ...................................... 6 Added New Figure 12 and Figure 13, Renumbered Sequentially ....................................................................................... 8 Added New Figure 24 and Figure 25 ........................................... 10 Added New Figure 36 and Figure 37 ........................................... 12 Added New Figure 43..................................................................... 13 Changes to Input Overvoltage Protection Section ..................... 15 Changes to Ordering Guide .......................................................... 16 10/08--Revision 0: Initial Version Rev. A | Page 2 of 16 ADA4091-2 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VSY = 1.5 V, VCM = 0.0 V, VO = 0.0 V, TA = 25C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions VOS -40C TA +125C Input Bias Current IB -40C TA +85C -40C TA +125C Input Offset Current IOS -40C TA +85C -40C TA +125C Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain AVO Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short-Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density 1.5 V < VSY 18 V -40C TA +125C RL = 100 k, VO = -1.2 V to +1.2 V -40C TA +125C RL = 10 k, VO = -1.2 V to +1.2 V -40C TA +125C Min Typ Max Unit -250 -600 -50 -55 -275 -5 -5 -75 -1.5 76 70 106 100 93 85 -40 +250 +600 +50 +55 +275 +5 +5 +75 +1.5 V V nA nA nA nA nA nA V dB dB dB dB dB dB V/C VOS/T VOH VOL ISC ZOUT PSRR ISY -44 -0.5 100 113 94 2.5 RL = 100 k to GND -40C to +125C RL = 10 k to GND -40C to +125C RL = 100 k to GND -40C to +125C RL = 10 k to GND -40C to +125C Sink/source f = 1 MHz, AV = 1 1.495 1.490 1.475 1.455 VSY = 2.7 V to 36 V -40C TA +125C IO = 0 mA -40C TA +125C 100 100 1.497 1.483 -1.499 -1.496 -1.498 -1.498 -1.495 -1.491 31 102 126 165 200 300 V V V V V V V V mA dB dB A A SR tS GBP M RL = 100 k, CL = 30 pF To 0.01% 0.46 22 1.22 69 V/s s MHz Degrees en p-p en 0.1 Hz to 10 Hz f = 1 kHz 2 24 V p-p nV/Hz Rev. A | Page 3 of 16 ADA4091-2 VSY = 5.0 V, VCM = 0.0 V, VO = 0.0 V, TA = 25C, unless otherwise noted. Table 3. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions VOS -40C TA +125C Input Bias Current IB -40C TA +85C -40C TA +125C Input Offset Current Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain AVO Output Voltage Low Short-Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Typ Max Unit -250 -600 -60 -80 -350 -45 +250 +600 +60 +80 +350 2 +7 30 +5 V V nA nA nA nA nA nA V dB dB dB dB dB dB IOS VOH VOL ISC ZOUT PSRR ISY -53 0 -40C TA +85C -40C TA +125C OUTPUT CHARACTERISTICS Output Voltage High Min 1.5 V < VCM 18 V -40C TA +125C RL = 100 k, VO = 4.7 V -40C TA +125C RL = 10 k, VO = 4.7 V -40C TA +125C -7 -5 88 82 113 103 98 87 RL = 100 k to GND -40C to +125C RL =10 k to GND -40C TA +125C RL = 100 k to GND -40C to +125C RL =10 k to GND -40C TA +125C Sink/source f = 1 MHz, AV = 1 4.980 4.980 4.950 4.900 VSY = 2.7 V to 36 V -40C TA +125C VO = 0 V -40C TA +125C 100 100 113 117 100 4.992 4.960 -4.998 -4.990 -4.990 -4.980 -4.980 -4.975 20 77 126 180 225 300 V V V V V V V V mA dB dB A A SR GBP M RL = 100 k, CL = 30 pF 0.46 1.22 70 V/s MHz Degrees en p-p en 0.1 Hz to 10 Hz f = 1 kHz 0.8 24 V p-p nV/Hz Rev. A | Page 4 of 16 ADA4091-2 VSY = 15.0 V, VCM = 0.0 V, VO = 0.0 V, TA = 25C, unless otherwise noted. Table 4. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions VOS -40C TA +125C Input Bias Current IB -40C TA +85C -40C TA +125C Input Offset Current IOS -40C TA +85C -40C TA +125C Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain AVO OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short-Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density VOH VOL ISC ZOUT PSRR ISY 1.5 V < VCM < 18 V -40C TA +125C RL = 100 k, VO = 14.7 V -40C TA +125C RL = 10 k, VO = 14.7 V -40C TA +125C Min Typ Max Unit -250 -600 -55 -80 -510 -2 -10 -140 -15 95 90 116 106 102 92 -35 +250 +600 +55 +80 +510 +2 +10 +140 +15 V V nA nA nA nA nA nA V dB dB dB dB dB dB RL = 100 k to GND -40C to +125C RL = 10 k to GND -40C TA +125C RL = 100 k to GND -40C to +125C RL = 10 k to GND -40C to +125C Sink/source f = 1 MHz, AV = 1 14.975 14.950 14.900 14.800 VSY = 2.7 V to 36 V -40C TA +125C IO = 0 mA -40C TA +125C 100 100 SR GBP M CS RL = 100 k, CL = 30 pF en p-p en -50 0 121 119 104 14.982 14.919 -14.996 -14.975 -14.990 -1.4990 -14.950 -14.940 20 71 126 200 250 350 V V V V V V V V mA dB dB A A f = 1 kHz 0.46 1.27 72 100 V/s MHz Degrees dB 0.1 Hz to 10 Hz f = 1 kHz 0.8 25 V p-p nV/Hz Rev. A | Page 5 of 16 ADA4091-2 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Supply Voltage Input Voltage Differential Input Voltage1 Input Current Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) 1 Input current should be limited to 5 mA. Rating 36 V Refer to the Input Overvoltage Protection section VSY 10 mA Indefinite -65C to +150C -40C to +125C -65C to +150C 300C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE JA is specified for the device soldered on a 4-layer JEDEC standard PCB with zero air flow. The exposed pad is soldered to the application board. Table 6. Thermal Resistance Package Type 8-Lead SOIC (R-8) ESD CAUTION Rev. A | Page 6 of 16 JA 155 JC 45 Unit C/W ADA4091-2 TYPICAL PERFORMANCE CHARACTERISTICS 200 10,000 ADA4091-2 TA = 25C VSY = 1.5V 180 160 1000 120 100 80 60 100 VDD - VOH 10 VOL - VSS 1 40 20 50 100 150 200 250 VOS (V) 0.1 0.001 OPEN-LOOP GAIN (dB) FREQUENCY 150 100 80 80 60 60 4 5 6 7 8 TCVOS (V/C) ADA4091-2 VSY = 1.5V RL = 1M CL = 35pF 300 0 10k 100k -20 10M 1M FREQUENCY (Hz) Figure 3. Input Offset Voltage vs. Temperature 350 40 20 -20 1k 07671-035 3 GAIN 20 0 2 100 40 50 1 100 PHASE 200 0 10 100 ADA4091-2 -40C TA +125C VSY = 1.5V -1 1 Figure 5. Dropout Voltage vs. Load Current 300 0 0.1 LOAD CURRENT (mA) Figure 2. Input Offset Voltage Distribution 250 0.01 PHASE (Degrees) 0 07671-007 -250 -200 -150 -100 -50 07671-034 0 ADA4091-2 VSY = 1.5V 07671-017 VOUT TO RAIL (mV) FREQUENCY 140 Figure 6. Open-Loop Gain and Phase vs. Frequency 50 ADA4091-2 VSY = 1.5V 40 AV = 100 250 100 50 +85C 0 -50 -100 -150 -1.5 +25C -40C -1.0 -0.5 0 0.5 1.0 1.5 VCM (V) 07671-033 IB (nA) 150 Figure 4. Input Bias Current vs. Input Common-Mode Voltage 30 20 AV = 10 10 0 AV = 1 ADA4091-2 -10 V = 1.5V SY RL = 1M CL = 35pF -20 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 7. Closed-Loop Gain vs. Frequency Rev. A | Page 7 of 16 10M 07671-010 CLOSED-LOOP GAIN (dB) +125C 200 ADA4091-2 3.0 1k 2.5 VOUT SWING (V) 100 10 AV = 10 1.5 1.0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 0 100 1k 2.0 1.6 1.5 1.4 OUTPUT VOLTAGE (V) 0 ADA4091-2 VSY = 1.5V TA = 25C RL = 100k CL = 100pF AV = +1 -0.5 -1.0 1.0 0.8 0.6 0.4 0.2 -1.5 ADA4091-2 TA = 25C VSY = 1.5V 0 5 10 15 20 25 30 35 40 45 50 TIME (s) -0.2 07671-025 0 0 10 0.06 0 0.04 -0.2 OUTPUT VOLTAGE (V) ADA4091-2 VSY = 1.5V TA = 25C RL = 100k CL = 100pF AV = +1 -0.06 60 70 80 90 -0.6 -0.8 -1.0 -1.2 ADA4091-2 TA = 25C VSY = 1.5V -1.4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TIME (s) 07671-028 VOUT (V) 40 50 TIME (s) -0.4 0.02 -0.08 30 Figure 12. Positive Overload Recovery Figure 9. Large Signal Transient Response -0.04 20 07671-051 VOUT (V) 0.5 -0.02 1M 1.2 1.0 0 100k Figure 11. Output Swing vs. Frequency Figure 8. Output Impedance vs. Frequency -2.0 10k FREQUENCY (Hz) 07671-036 10 ADA4091-2 VSUPP = 1.5V VIN = 2.8V p-p RL = 100k 0.5 ADA4091-2 TA = 25C VSY = 1.5V -1.6 0 10 20 30 40 50 TIME (s) 60 70 Figure 13. Negative Overload Recovery Figure 10. Small Signal Transient Response Rev. A | Page 8 of 16 80 90 07671-045 0.1 2.0 AV = 1 1 07671-013 ZOUT () AV = 100 ADA4091-2 0.06 225 ADA4091-2 TA = 25C VSY = 5V 200 0.04 175 0.02 VOUT (V) FREQUENCY 150 125 100 ADA4091-2 VSY = 5V TA = 25C RL = 100k CL = 100pF AV = +1 0 -0.02 75 -0.04 50 -250 -200 -150 -100 -50 0 50 100 150 200 250 VOS (V) -0.08 07671-037 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TIME (s) Figure 14. Input Offset Voltage Distribution Figure 17. Small Signal Transient Response 400 500 ADA4091-2 -40C TA +125C VSY = 5V 350 ADA4091-2 VSY = 5V 400 300 300 250 IB (nA) 200 200 +125C 100 150 +85C 100 -100 50 -1 0 1 2 3 4 5 6 7 8 TCVOS (V/C) -200 07671-038 0 +25C 0 -40C -5 -4 -3 -2 -1 0 1 2 3 4 5 VCM (V) Figure 15. Input Offset Voltage vs. Temperature 07671-032 FREQUENCY 07671-029 -0.06 25 Figure 18. Input Bias Current vs. Common-Mode Voltage 100 100 6 0 ADA4091-2 VSY = 5V TA = 25C RL = 100k CL = 100pF AV = +1 -2 -6 0 5 10 15 20 25 30 35 40 TIME (s) 45 50 80 60 60 GAIN 40 40 20 20 0 ADA4091-2 VSY = 5V RL = 1M CL = 35pF -20 1k 10k -4 07671-026 VOUT (V) 2 80 0 100k 1M FREQUENCY (Hz) Figure 16. Large Signal Transient Response Figure 19. Open-Loop Gain and Phase vs. Frequency Rev. A | Page 9 of 16 -20 10M 07671-005 OPEN-LOOP GAIN (dB) 4 PHASE (Degrees) PHASE ADA4091-2 50 AV = 100 40 CLOSED-LOOP GAIN (dB) ZOUT () 100 AV = 100 10 AV = 10 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 07671-012 0.1 AV = 10 20 10 AV = 1 0 ADA4091-2 -10 VSY = 5V RL = 1M CL = 35pF -20 10 100 ADA4091-2 TA = 25C VSY = 5V AV = 1 30 1k 10k 100k 1M 10M FREQUENCY (Hz) 07671-009 1k Figure 23. Closed-Loop Gain vs. Frequency Figure 20. Output Impedance vs. Frequency 10 6 9 5 VOUT SWING (V) 7 6 5 4 3 1 ADA4091-2 VSY = 5V VIN = 9.8V p-p RL = 100k 0 100 1k 10k 100k 1M FREQUENCY (Hz) 3 2 1 ADA4091-2 TA = 25C VSY = 5V 0 0 10 20 07671-015 2 4 Figure 21. Output Voltage Swing vs. Frequency 30 40 50 TIME (s) 60 70 80 90 07671-046 OUTPUT VOLTAGE (V) 8 Figure 24. Positive Overload Recovery 10,000 1 0 100 VOL - VSS 10 -1 -2 -3 -4 1 ADA4091-2 TA = 25C VSY = 5V -5 0.1 0.001 ADA4091-2 VSY = 5V 0.01 0.1 1 10 LOAD CURRENT (mA) 100 -6 0 10 20 30 40 50 TIME (s) 60 Figure 25. Negative Overload Recovery Figure 22. Dropout Voltage vs. Load Current Rev. A | Page 10 of 16 70 80 07671-047 OUTPUT VOLTAGE (V) VDD - VOH 07671-018 VOUT TO RAIL (mV) 1000 ADA4091-2 250 100 ADA4091-2 TA = 25C VSY = 15V 100 80 60 60 0 50 100 150 200 250 VOS (V) 20 ADA4091-2 VSY = 15V RL = 1M CL = 35pF -20 1k 07671-041 0 0 10k 100k -20 10M 1M FREQUENCY (Hz) Figure 29. Open-Loop Gain and Phase vs. Frequency Figure 26. Input Offset Voltage Distribution 20 350 ADA4091-2 TA = -40C AND +125C VSY = 15V 300 15 10 250 5 200 VOUT (V) 150 ADA4091-2 VSY = 15V TA = 25C RL = 100k CL = 100pF AV = +1 0 -5 100 -10 50 -1 0 1 2 3 4 5 6 7 8 TCVOS (V/C) -20 -25 07671-042 0 -15 600 25 50 75 100 125 150 175 200 TIME (s) Figure 27. Offset Voltage TC 700 0 07671-027 FREQUENCY 40 20 50 -250 -200 -150 -100 -50 GAIN 40 PHASE (Degrees) 150 80 07671-006 OPEN-LOOP GAIN (dB) FREQUENCY 200 0 100 PHASE Figure 30. Large Signal Transient Response 0.06 ADA4091-2 VSY = 15V 0.04 500 0.02 400 +125C VOUT (V) 200 +85C 100 0 -0.02 +25C 0 ADA4091-2 VSY = 15V TA = 25C RL = 100k CL = 100pF AV = +1 -0.04 -100 -40C -300 -15 -10 -5 0 5 -0.06 10 VCM (V) 15 Figure 28. Input Bias Current vs. Common-Mode Voltage -0.08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TIME (s) Figure 31. Small Signal Transient Response Rev. A | Page 11 of 16 07671-030 -200 07671-031 IB (nA) 300 ADA4091-2 50 30 40 VOUT SWING (V) 25 20 15 10 0 100 1k 10k 100k 1M FREQUENCY (Hz) 30 AV = 10 20 10 AV = 1 0 -10 ADA4091-2 -20 VSY = 15V RL = 1M CL = 35pF -30 10 100 07671-016 5 ADA4091-2 VSY = 15V VIN = 29.8V p-p RL = 100k AV = 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 07671-008 CLOSED-LOOP GAIN (dB) 35 Figure 35. Closed-Loop Gain vs. Frequency Figure 32. Output Voltage Swing vs. Frequency 10,000 16 14 12 OUTPUT VOLTAGE (V) VDD - VOH 100 VOL - VSS 10 8 6 4 2 1 0.01 0.1 1 10 100 LOAD CURRENT (mA) ADA4091-2 TA = 25C VSY = 15V 0 ADA4091-2 VSY = 15V -2 07671-019 0.1 0.001 10 0 Figure 33. Dropout Voltage vs. Load Current 10 20 30 40 50 TIME (s) 60 70 80 90 07671-048 VOUT TO RAIL (mV) 1000 Figure 36. Positive Overload Recovery 1k 2 0 -2 AV = 100 AV = 10 -6 -8 -10 -12 ADA4091-2 TA = 25C VSY = 15V AV = 1 0.1 10 -4 100 1k 10k 100k 1M FREQUENCY (Hz) 10M ADA4091-2 TA = 25C VSY = 15V -14 -16 0 10 20 30 40 50 TIME (s) 60 Figure 37. Negative Overload Recovery Figure 34. Output Impedance vs. Frequency Rev. A | Page 12 of 16 70 80 07671-049 1 OUTPUT VOLTAGE (V) 10 07671-011 ZOUT () 100 ADA4091-2 100 0.5 ADA4091-2 VSY = 1.5V, 5V, 15V 0.4 80 0.3 60 0.1 PSRR (dB) 0 -0.1 20 -0.2 -0.3 ADA4091-2 VSY = 15V 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) -20 100 07671-043 0 1k 1M 10M 500 ADA4091-2 450 TA = 25C ADA4091-2 VSY = 15V -70 400 -80 350 300 -90 ISY (A) CHANNEL SEPARATION (dB) 100k Figure 41. PSRR vs. Frequency Figure 38. Voltage Noise, V p-p -60 10k FREQUENCY (Hz) 07671-003 0 -0.4 -0.5 PSRR+ PSRR- 40 -100 250 200 150 -110 100 -120 100 10 1k 10k 100k FREQUENCY (Hz) 0 07671-044 -130 50 0 5 20 25 30 35 Figure 42. Supply Current vs. Supply Voltage 1k ADA4091-2 VSY = 5V, 15V 100 15 VSY (V) Figure 39. Channel Separation vs. Frequency 110 10 07671-004 NOISE (V) 0.2 VOLTAGE NOISE (nV/ Hz) 90 80 VSY = 1.5V 60 50 40 30 20 1k 10k 100k FREQUENCY (Hz) 1M 10M 10 0.01 0.1 1 10 FREQUENCY (Hz) Figure 43. Voltage Noise Density Figure 40. CMRR vs. Frequency Rev. A | Page 13 of 16 100 1k 07671-050 0 100 100 ADA4091-2 TA = 25C VSY = 5V 10 07671-002 CMRR (dB) 70 ADA4091-2 THEORY OF OPERATION The ADA4091-2 is a single-supply, micropower amplifier featuring rail-to-rail inputs and outputs. To achieve wide input and output ranges, this amplifier employs unique input and output stages. Q1 and Q2 are high enough to turn on Q3, which diverts the tail current away from the PNP input stage, turning it off. The tail current of the PNP pair is diverting to the Q4/Q7 current mirror to activate the NPN input stage. INPUT STAGE A common practice in bipolar amplifiers to protect the input transistors from large differential voltages is to include series resistors and differential diodes. See Figure 45 for the full input protection circuitry. These diodes turn on whenever the differential voltage exceeds approximately 0.6 V. In this condition, current flows between the input pins, limited only by the two 5 k resistors. Evaluate each application carefully to make sure that the increase in current does not affect performance. In Figure 44, the input stage comprises two differential pairs, a PNP pair (PNP input stage) and an NPN pair (NPN input stage). These input stages do not work in parallel. Instead, only one stage is on for any given input common-mode signal level. The PNP stage (Transistor Q1 and Transistor Q2) is required to ensure that the amplifier remains in the linear region when the input voltage approaches and reaches the negative rail. Alternatively, the NPN stage (Transistor Q5 and Transistor Q6) is needed for input voltages up to and including the positive rail. OUTPUT STAGE The output stage in the ADA4091-2 device uses a PNP and an NPN transistor, as do most output stages. However, Q32 and Q33, the output transistors, connect with their collectors to the output pin to achieve the rail-to-rail output swing. For the majority of the input common-mode range, the PNP stage is active, as shown in Figure 4, Figure 16, and Figure 24. Notice that the bias current switches direction at approximately 1.5 V below the positive rail. At voltages below this level, the bias current flows out of the ADA4091-2, from the PNP input stage. Above this voltage, however, the bias current enters the device, due to the NPN stage. The actual mechanism within the amplifier for switching between the input stages comprises Transistor Q3, Transistor Q4, and Transistor Q7. As the input common-mode voltage increases, the emitters of Q1 and Q2 follow that voltage plus a diode drop. Eventually, the emitters of As the output voltage approaches either the positive or negative rail, these transistors begin to saturate. Thus, the final limit on output voltage is the saturation voltage of these transistors, which is about 50 mV. The output stage has inherent gain arising from the transistor output impedance, as well as any external load impedance; consequently, the open-loop gain of the op amp is dependent on the load resistance and decreases when the ouput voltage is close to either rail. -IN Q32 Q3 Q16 Q5 Q6 Q1 Q2 Q8 Q9 Q10 Q11 Q12 Q13 Q15 Q18 Q4 Q17 Q14 Q19 Q33 07671-024 +IN Q7 Figure 44. Simplified Schematic Without Input Protection (see Figure 45) Rev. A | Page 14 of 16 ADA4091-2 INPUT OVERVOLTAGE PROTECTION The ADA4091-2 has two different ESD circuits for enhanced protection, as shown in Figure 45. For a worst-case design analysis, consider two cases. The ADA4091-2 has a normal ESD structure from the internal op amp inputs to the supply rails. In addition, it has 42 V DIACs from the external inputs to the rails, as shown in Figure 44. Therefore, two conditions have to be considered to determine which one is the limiting factor. V+ D3 R1 D7 R2 D8 D6 Condition 1. Consider, for example, that when operating on 15 V, the inputs can go +42 V above the negative supply rail. With the -V pin equal to -15 V, +42 V above this supply (the negative supply) is +27 V. * Condition 2. There is also a restriction on the input current of 5 mA through a 5 k resistor to the ESD structure to the positive rail. In Condition 1, +27 V through the 5 k resistor to +15 V gives a current of 2.4 mA. Thus, the DIAC is the limiting factor. If the ADA4091-2 supply voltages are changed to 5 V, then -5 V + 42 V = 37 V. However, +5 V + (5 k x 5 mA) = 30 V. Thus, the normal resistor diode structure is the limitation when running on lower supply voltages. D1 D2 D5 * D4 07671-023 V- Figure 45. Complete Input Protection Network One circuit is a series resistor of 5 k to the internal inputs and diodes (D1 and D2 or D5 and D6) from the internal inputs to the supply rails. The other protection circuit is a circuit with two DIACs (D3 and D4 or D7 and D8) to the supply rails. A DIAC can be considered a bidirectional Zener diode with a transfer characteristic, as shown in Figure 46. 5 4 The flatband voltage noise of the ADA4091-2 is approximately 24 nV/Hz, and a 5 k resistor has a noise of 9 nV/Hz. Adding an additional 5 k resistor increases the total noise by less than 15% root-sum-square (rss). Therefore, maintain resistor values below this value when overall noise performance is critical. Note that this represents input protection under abnormal conditions only. The correct amplifier operation input voltage range (IVR) is specified in Table 2, Table 3, and Table 4 of this data sheet. 3 2 1 0 -1 -2 -3 -50 -40 -30 -20 -10 0 10 20 VOLTAGE (V) 30 40 50 07671-100 CURRENT (mA) Additional resistance can be added externally in series with each input to protect against higher peak voltages; however, the additional thermal noise of the resistors must be considered. Figure 46. DIAC Transfer Characteristic Rev. A | Page 15 of 16 ADA4091-2 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 4.00 (0.1574) 3.80 (0.1497) Figure 47. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADA4091-2ARZ-R2 1 ADA4091-2ARZ-R71 ADA4091-2ARZ-RL1 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] Z = RoHS Compliant Part. (c)2008-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07671-0-7/09(A) Rev. A | Page 16 of 16 Package Option R-8 R-8 R-8