M25P80-VMW6T - STMicroelectronics

1/34

TARGET SPECIFICATION

January 2002

This is preliminary information on a new product forseen to be developped. Details are subject to change without notice.

M25P80

8 Mbit, Low Voltage, Serial Flash Memory

With 25 MHz SPI Bus Interface

FEATURES SUMMARY

■8 Mbit of Flash Memory

■Page Program (up to 256 Bytes) in 2 m s

(typical)

■Sector Eras e (512 Kbit) in 2 s (typical)

■Bulk Erase (8 Mbi t) in 10 s (typical)

■2.7 V to 3.6 V Single Supply Voltage

■SPI Bus Compatible Serial Interface

■25 MHz Clock Rate (maximum)

■Deep Power-down Mode 1 µA (ty p ica l)

■Electronic Signature (13h)

■More than 100,000 Erase/Program Cyc les per

Sector

■More than 20 Year Data Retention

Figure 1. Packages

SO8 (MW)

200 mil width

M25P80

2/34

SUMMARY DESCRIPTION

The M25P80 is a 8 Mbit (1M x 8) Serial Flash

Memory, with advanced write protection mecha-

nisms, acces se d by a high speed SPI -compatible

bus.

The memory can be programmed 1 to 256 bytes at

a time, using the Page Program instruction.

The memory is organized as 16 sectors, each con-

taining 256 p ages. Each page is 256 bytes wide.

Thus, the whole memory can be viewed as con-

sisting of 4096 pages, or 1,048,576 bytes.

The whole mem ory can b e erased using t he Bulk

Erase instruction, or a sector at a time, using the

Sector Erase instruction.

Figure 2. Logic Diagram

Figu re 3. SO C onnections

Table 1. Sign al Names

AI04964

VCC

M25P80

HOLD

VSS

AI04965

5DVSS C

HOLDQ

M25P80

C Serial Clock

D Serial Data Input

Q Serial Data Outp ut

SChip Select

W Write Protect

HOLD Hold

VCC Supply Voltage

VSS Ground

3/34

M25P80

SIGNAL DESCRIPTION

Serial Data Output (Q). This output signal is

used to transfer data serially out of the device.

Data is shifted out on the falling edge of Serial

Clock (C).

Serial Data Input (D). This input si gnal is used to

transfer data serial ly into t he device. It receives in-

structions, addresses, and the data to be pro-

grammed. Values are latched on the rising edge of

Serial Clock (C).

Serial Clock (C). This input signal provides the

timing of the s erial interface. Instructions , address-

es, or data present at Serial Data Input (D) are

latched on the ris ing edge of Serial Clock (C) . Data

on Serial Data Output (Q) changes after the falling

edge of Serial Clock (C).

Chip Select (S). When this input signal is High,

the device is deselected and Serial Data Output

(Q) is at high impedance. Unless an internal Pro-

gram, Erase or Write Status Register cycle is in

progress, the device will b e in the Standby mode

(this is not the Deep Power-down mode). Driving

Chip S ele c t (S) Low enables the device, placing it

in the active power mode.

After Power-up, a falling edge on Chip Select (S)

is required prior to the start of any instruction.

Hold (HOLD). The Hold (HOLD) signal is used to

pause any serial communi cations with the device

without deselecti ng the device.

During the Hold condition, the Serial Data Output

(Q) is hig h impedance, and Serial D ata Input (D)

and Serial Clock (C) are Don’t Care.

To start the Hol d condit ion, t he devi ce must be se-

lected, with C hip S ele c t ( S) driven Low.

Write Protect (W). The main purpose of this in-

put signal is to freeze the size of the area of m em-

ory that is protected against program or erase

instructions (as specifi ed by the values in t he BP 2,

BP1 and BP0 bits of the Status Register).

M25P80

4/34

SPI MODES

These dev ices can be drive n by a microcont roller

with its SPI peripheral running in ei ther of the two

following modes:

– CP OL= 0, CPHA=0

– CP OL= 1, CPHA=1

For these two modes, input data is latched in on

the rising edge of Serial Clock (C), and output data

is available from the falling edge of Serial Clock

(C).

The difference between the two modes, as shown

in Figure 5, is the clock polarity when the bus mas-

ter is in Stand-by mode and not transferring data:

– C re mains at 0 for (CPOL=0, CPHA=0 )

– C re mains at 1 for (CPOL=1, CPHA=1 )

Figure 4. Bus Master and Memo ry Devi ces on the SPI Bus

No te : 1. The W ri te Protect (W ) and Hol d (HOLD) signal s should be drive n, High or Low as appropri ate.

Figu re 5. S PI Modes S up ported

AI03746D

Bus Master

(ST6, ST7, ST9,

ST10, Others) SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WHOLD WHOLD WHOLD

AI01438B

MSB

CPHA

CPOL

MSB

5/34

M25P80

OPERATING FEATURES

Page P rogramm i ng

To program one data byte, t wo instructions are re-

quired: Write Enable (WREN), which is one byte,

and a Page Program (PP) sequence, which con-

sists of four bytes plus data. This is f ollowed by the

internal Program cycle (of duration tPP).

To spread this ove rhead, the Page P rogram (PP)

instruction allows up to 256 bytes to be pro-

grammed at a time (changing bits from 1 to 0), pro-

vided that they lie in consecutive addresses on the

same page of memory.

Sector Erase and Bul k Erase

The Page Program (PP) instruction allows bits to

be reset from 1 to 0. Before this can be applied, the

bytes of memo ry need to hav e been erased to a ll

1s (FFh). Thi s can be achieved either a s ector at a

time, using the Sector Erase (SE) instruction, or

throughout the entire memory, using the Bulk

Erase (BE) instruction.

Polling Duri ng a Wri te, Program or Erase Cycle

A further improvement in the time to Write Status

BE) can be achieved by not waiting for the worst

case delay (tW, tPP, tSE, or tBE). The Write In

Progress (WIP) bit is provided in t he Status Regis-

ter so that the application program can m onitor its

value, polling it to establish when the previous

Write cycle, Program cycle or Erase cycle is com-

plete.

Active Power, St a nd - b y Power and De ep

Power-Down Modes

When Chip Select (S) is Low, the device is en-

abled, and in the Active Power mode.

When Chip Select (S) is High, the device is dis-

abled, but could remain in the Active Power mode

until all internal cycles have com pleted (Program,

Erase, Write Status Register). The device then

goes in t o the Stand-by P ower mode. T he dev ice

consump tion drops to ICC1.

The Deep Power-down mode is entered when the

specific instruction (the Enter Deep Power-down

Mode (DP) instruction) is executed. The device

consump tion drops further to ICC2. The device re-

mains in this mode until another specific instruc-

tion (the Release from Deep Power-down Mode

and Read Elect ronic Sig nature (RES ) instruction)

is executed.

All other instructions are igno re d while the device

is in the Deep Power-down mode. This can be

used as an ext ra soft ware protection mecha nism,

when the device is not in active use, to protect the

device from inadvertant Write, Program or Erase

instructions.

Status Register

The Status Register contains a number of status

and control bits tha t can be read or set (as appro-

priate) by specific instructions.

WIP bit. The Writ e In Progress (WIP) bit indic ates

whether the memory is busy with a Write Status

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the int ernal Write Enable Latch.

BP2, BP1, BP0 bits. The Block Protect (BP2,

BP1, BP0) bits are non-volatile. They define the

size of the area to be software protected against

Program and Eras e instructions.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected mode. In this mode, the non-v olati le bits

of the Status Register (SRWD, BP2, BP1, BP0)

become read-only bits.

M25P80

6/34

P rotec t i on Modes

The environments where non-vol atile memory de-

vices are used can be very noisy. No SPI device

can operate correct ly in the presence of excessi ve

noise. To help combat t his, the M25P80 boasts the

following data protection mechanisms:

■Power-On Reset and an i nternal timer (tPUW)

can provide protection against inadvert ant

change s while the power supply is outside the

operating specification.

■Program, Erase and Write Status Register

instructions are checked that they consist of a

number of clock pulses that is a multiple of

eight, bef ore they are accepted for execution.

■All instructions that modify data mus t be

preceded by a Write Enable (WREN) instruction

to set the Write Enable Latch (WEL) bit . This bit

is returned to its reset state by the following

events:

– Power-up

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction

completion

– Page Program (PP) i nstruction completion

– Sector Erase (SE) instruction completion

– Bul k Eras e (BE) instru ctio n co mpl et i on

■The Block Protect (BP2, BP1, BP0) bits allow

part of the memory to be configured as read-

only. This is the Software Protected Mod e

(SPM).

■The Write Protect (W) signal allows the Block

Protect (BP2, BP1, BP0) bits and Status

protected. This is the Hardware Protected Mode

(HPM).

■In addition to the low power consumption

feature, the Deep Power-down mode offers

extra software protection from inadvertant

Write, Program and Erase instruc tions , as all

instructions are ignored except one particular

instruction (the Release from Deep Power-

down instruction).

Table 2. Pro tected Area Sizes

Note: 1. The de vice is ready to accept a Bul k E rase in st ruction i f, and on l y if, all Block Protect (BP 2, BP 1, BP0) are 0.

Status Register

Content Memory Content

BP2

Bit BP1

Bit BP0

Bit Protected Area Unprotected Area

0 0 0 none All sectors1 (sixteen sectors: 0 to 15)

0 0 1 Upper sixteenth (Sector 15) Lower fifteen-sixteenths (fifteen sectors: 0 to 14)

0 1 0 Upper eighth (two sectors: 14 and 15) Lower seven-eighths (fourteen sectors: 0 to 13)

0 1 1 Upper quarter (four sectors: 12 to 15) Lower three-quarters (twelve sectors: 0 to 11)

1 0 0 Upper half (eight sectors: 8 to 15) Lower half (eight sectors: 0 to 7)

1 0 1 All sectors (sixteen sectors: 0 to 15) none

1 1 0 All sectors (sixteen sectors: 0 to 15) none

1 1 1 All sectors (sixteen sectors: 0 to 15) none

7/34

M25P80

Hold Conditio n

The Hold (HOLD ) signal is used to pause any se-

rial communicat ion s with the device without rese t-

ting the clocking sequence. However, taking this

signal Low does not terminate any Write Status

in progress.

To enter the Hold condition, the device must be

sele c te d , wit h C h ip Select (S) Low.

The Hold condit ion starts on the falling edge of the

Hold (HOLD) signal, provided that this coincides

with Serial Clock (C) bei ng L ow (as shown i n F ig-

ure 6).

The Hold condition ends on the rising edge of t he

Hold (HOLD) signal, provided that this coincides

with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial

Clock (C) being Low, the Hold condition starts

when Serial Clock (C) next goes Low. Similarly, if

the rising edge does not coincide with Serial Clock

rial Clock (C) nex t goes Low. (This is shown in Fig-

ure 6).

During the Hold condition, the Serial Data Ou tput

(Q) is hig h impedance, and Serial D ata Input (D)

and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip

Select (S) driven Low, for the whole duration of the

Hold condition. This is to en su re that the state of

the internal logic remains unchanged from the mo-

ment of entering the Hold condition.

If Chip Select (S) go es High whil e the device is in

the Hold condition, this has the effect of reset ting

the internal logic of the device. To restart commu-

nication with the device, it is necessary to drive

Hold (HOLD) High, and then to drive Chip Select

(S) Low. This prevent s t he device from going back

to the Hold condition.

Figure 6. Hold Condition Activation

AI02029D

HOLD

Hold

Condition Hold

Condition

M25P80

8/34

ME M O RY OR GANIZA TI ON

The memory is organized as :

■1,048,576 by tes (8 bits each)

■16 sectors (512 Kbits, 65536 bytes each)

■4096 pages (256 bytes each).

Each page can be individually programmed (bits

are programmed from 1 to 0). The device is Sec tor

or Bulk Erasable (bits are erased from 0 to 1) but

not Page Erasable.

Table 3. Memory Organization

Sector Address Range

15 F0000h FFFFFh

14 E0000h EFFFFh

13 D0000h DFFFFh

12 C0000h CFFFFh

11 B0000h BFFFFh

10 A0000h AFFFFh

9 90000h 9FFFFh

8 80000h 8FFFFh

7 70000h 7FFFFh

6 60000h 6FFFFh

5 50000h 5FFFFh

4 40000h 4FFFFh

3 30000h 3FFFFh

2 20000h 2FFFFh

1 10000h 1FFFFh

0 00000h 0FFFFh

9/34

M25P80

Figu re 7. Blo ck D ia gra m

AI04987

HOLD

WControl Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter 256 Byte

Data Buffer

256 Bytes (Page Size)

X Decoder

Y Decoder

Size of the

read-only

memory area

Status

00000h

FFFFFh

000FFh

M25P80

10/34

INSTRUCTIONS

All instructions, addresses and data are shifted in

and out of the device, most significant bit first.

Serial Data Input (D) is sampled on the first rising

edge of Serial Clock (C) after Chip Select (S) is

driven Low. Then, the one-byte instruction code

must be shifted in t o the device, most significant bit

first, on Serial Data Input (D), each bit being

latched on the rising edges of Seri al Clock (C).

The instruction set is listed in Tab le 4.

Depending on the instruction, the one-byte in-

struction code i s follo wed by addre ss by tes, or by

data bytes, or by both or none. Chip Select (S)

must be driven High af ter the last bi t of the i nstruc-

tion sequence has been shifted in.

At the en d of a Page Program (PP), Se ctor Er ase

(SE), Bulk Erase (BE) or Write Status Register

(WRSR) instru ction, Chip Select (S) m ust be driv-

en High exac tly at a byte bound ary, otherwise t he

instruction is rejected, and is not executed. That is,

Chip Select (S) must driven High when the number

of clock pulses after Chip Select (S) being driven

Low is an exact multiple of eight.

All at tempts t o access the mem ory array du ring a

Write Status Register cycle, Program cycle or

Erase cycle are ignored, and the internal Write

Status Regist er cycle, Program cycle or Erase cy-

cle cont i nues unaf fected.

Table 4. Instructi on Set

Instruction Description One-byte Instruction Code Address

Bytes Dummy

Bytes Data

Bytes

WREN Write Enable 0000 0110 0 0 0

WRDI Write Disable 0000 0100 0 0 0

RDSR Read Status Register 0000 0101 0 0 1 to ∞

WRSR Write Status Register 0000 0001 0 0 1

READ Read Data Bytes 0000 0011 3 0 1 to ∞

FAST_READ Read Data Bytes at Higher Speed 0000 1011 3 1 1 to ∞

PP Page Program 0000 0010 3 0 1 to 256

SE Sector Erase 1101 1000 3 0 0

BE Bulk Erase 1100 0111 0 0 0

DP Deep Power-down 1011 1001 0 0 0

RES Release from Deep Power-down,

and Read Electronic Signature 1010 1011 0 3 1 to ∞

Release from Deep Power-down 0 0 0

11/34

M25P80

Figure 8. Write En able (WRE N) Sequen ce

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 8)

sets the Write Enable Latc h (WEL) bit.

The Write Enabl e Latch (WEL) bi t must be set pri-

or to every Page Program (PP), Sector Erase

(SE), Bulk Erase (BE) and Write Status Register

(WRSR) instruction.

The Write Enable (WREN) instruction is entered

by driving Chip Select (S) Low, sending the in-

struction code, and then driving Chip Select (S)

High.

Figure 9. Write Disable (WRDI) Sequence

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 9)

resets the Write Enable Latch (WEL ) bit.

The Write Disable (WRDI) instruction is entered by

driving Chip Select (S) Low, sending the instruc-

tion code, and then driving Chip Select (S ) High.

The Write Enable Latch (WEL) bit is reset under

the following conditions:

– Power-up

– Write Disable (WRDI) instruction completion

– Write S tatus Register (WRSR) instruction com-

pletion

– P age P rogram (PP) instruction completion

– Sect or Erase (SE) instruction completion

– B ulk Erase (BE) instruction completion

AI02281E

21 34567

High Impedance

Instruction

AI03750D

21 34567

High Impedance

Instruction

M25P80

12/34

Figure 10. Read Status Register (RDSR) Sequence

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction al-

lows the Status Register to be read. The Status

Program, Erase or Write Status Register cycle is in

progress. When one of these cycl es i s in progress,

it is recommended to check the Write In P rogress

(WIP) bit before sending a new instruction to the

device. It is also poss ible to read the S tatus Reg-

ister continuously, as shown in Figure 10.

Table 5. Status Register Format

The status and cont rol bits of the Stat us Register

are as follows:

WIP bit. The Writ e In Progress (WIP) bit indic ates

whether the memory is busy with a Write Status

such a cycle is in progress, when reset to 0 no

suc h cycle is in pro gr es s.

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the int ernal Write Enable Latch.

When set to 1 the internal Write Enable Latch is

set, whe n set to 0 the inte rnal Write Enabl e Latch

is reset and no Write Status Reg ister, Program or

Erase instruction is accepted.

BP2, BP1, BP0 bits. The Block Protect (BP2,

BP1, BP0) bits are non-volatile. They define the

size of the area to be software protected against

Program and Erase instructions. These bits are

written with the Write Status Register (WRSR) in-

struction. When one or both of the Block Protect

(B P2, BP1, BP0) bit s i s s et t o 1, the rel evan t me m-

ory area (as def ined in Tabl e 2) becomes protect-

ed against Page Program (PP) and Sector Erase

(SE) instructions. The Block Protect (BP2, BP1,

BP0) bits can be written provided that the Hard-

ware Protected m ode has not been s et. T he Bulk

Erase (BE) instruction is executed if, and only if,

both Block Protect (BP2, BP1, BP0) bits are 0.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected mode (when the Status Register Write

Disable (SRWD) bit is set to 1, and Wri te Protect

(W) is driven Low). In this mode, the non-volatile

bits of the Status Register (SRWD, BP2, BP1,

BP0) bec ome read-on ly bits and t he Write Status

for execution.

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

b7 b0

SRWD 0 0 BP2 BP1 BP0 WEL WIP

Status Regis ter

Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

13/34

M25P80

Figure 11. Write Status Register (WRSR) Sequence

Write Status Regist er (WRSR)

The Write Status Register (WRSR) instruction al-

lows new val ues to be written to the Status Regis-

ter. Before it can be accepted, a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Wri te Enable (WREN) instruction

has been d ecoded and ex ecuted, the de vice se ts

the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is

entered by driving Chip Select (S) Low, followed

by the instruction code and the dat a byt e on Serial

Data Input (D).

The instruction sequenc e is shown in Figure 11.

The Write Stat us Register (WRSR) instructi on has

no effect on b6, b5, b1 and b0 of the Status Reg-

ister. b6 and b5 are always read as 0.

Chip Select (S) must be driven High after the

eighth bit of the data byte has been latched in. If

not, the W rite Status Register (WRSR) i nstruction

is not executed. As soon as Chip Select (S) is dri v-

en Hig h, th e self -timed Write S tatus Register cycle

(whose du ration is t W) is init iated . While the Writ e

Status Register cycle is in progress, the Status

Write In P rogress (WIP) bit. The Write In Progress

(WIP) bit is 1 during the self-timed Write Status

When the cycle is completed, the Write Enable

Latch (WEL) is reset.

The Write Status Register (WRSR) instruction al-

lows the user to change the values of the Block

Protect (BP2, BP1, BP0) bits, to define the size of

the area that is to b e trea ted as re ad-only, as de-

fined in Table 2. The Write Status Register

(WRSR) instruction also allows the user to set or

reset the Status Register Write Disable (SRWD)

bit in accordance with the Write Protect (W) signal.

The St atus Register Write Disable (SRWD) bit and

Write Protect (W) signal allow the devi ce to be put

in the Hardware Protected Mode (HPM). The Write

Status Register (WRSR) in struction is n ot execut-

ed once the Hardware Protected Mode (HPM) is

entered.

AI02282D

21 3456789101112131415

High Impedance

Instruction Status

765432 0

MSB

M25P80

14/34

Table 6. Pro tection M ode s

Note: 1. As defi ned by th e values in the Block Protect (BP2, BP1, BP0) bits of the Status Regis ter, as shown in Ta bl e 2.

The prot ection f eat ures of the device are summ a-

rized in Tabl e 6.

When the Status Register Write Disable (SRWD)

bit of the Status Register is 0 (its initial delivery

state), it is possible to write to the Status Regi ster

provided that the Write Enable Latch (WEL) bit has

previously been set by a Write Enable (WREN) in-

struction, rega rdless o f the wh ether W rite Protect

(W) is driven High or Low.

When the Status Register Write Disable (SRWD)

bit of the Status Register is set to 1, two cases

need to be considered , depending on the state of

Write Protect (W):

– I f Write Protect (W) is driven Hi gh, it is possible

to write to the Status Regis ter provided that the

Write Enable Latch (WEL) bit has previously

been set by a Write Enable (WREN) instruction.

– I f Write Protect (W) is driven Low, it is

not

pos-

sible to write to th e Status Register

even

if the

Write Enable Latch (WEL) bit has previously

been set by a Write Enable (WREN) instruction.

(Attempts t o write to the Status Register are re-

jected, and are no t accepted for ex ecution). As

a consequence, all the data bytes in the memo-

ry area that are sof tware protected (SPM) by the

Blo ck Pro tec t (BP2, BP1, BP0 ) bi ts of th e St atus

data modifica tion.

Regardless of the order of the two events, the

Hardware Protected Mode (HPM) can be ent ered:

– by setting the Status Register Write Disable

(SRWD) bi t after driving Writ e Protect (W) Low

– or by dri ving Write Protect (W) Low after setting

the Status Register Write Disable (SRWD) bit.

The only way to exit the Hardware Protected Mode

(HPM) once entered is to pull Write Protect (W)

High.

If Write Protect (W) is permanently tied High, the

Hardware Protected Mode (HPM) can never be

activated, and only the Software Protected Mode

(SPM), using the Block Protect (BP2, BP1, BP0)

bits of the Status R egister, can be used.

Signal SRWD

Bit Mode Write Protection of the

Status Register

Memory Content

Protected Area1Unprotected Area1

Software

Protected

(SPM)

Status Register is

Writable (if the WREN

instruction has set the

WEL bit)

The values in the SRWD,

BP2, BP1 and BP0 bits

can be changed

Protected again st Page

Program, Sector Erase

and Bulk Erase

Ready to accept Page

Program and Sector

Erase instructions

Hardware

Protected

(HPM)

Status Register is

Hardware write protected

The values in the SRWD,

BP2, BP1 and BP0 bits

cannot be changed

Protected again st Page

Program, Sector Erase

and Bulk Erase

Ready to accept Page

Program and Sector

Erase instructions

15/34

M25P80

Figure 12. Read Data Bytes (READ) Sequence

Note: 1. Address bits A23 to A20 are Don’ t Care.

Read Data Bytes (READ)

The de vice is f irst s el ected by driving Chip Sele ct

(S) Low. The instruction code for the Read Data

Bytes (READ) instruction is followed by a 3-byte

address (A23-A0), each bit being latched-in during

the rising edge of Serial Cl ock (C). T hen t he mem-

ory contents , at that address, is shifted out on Se-

rial Data Output (Q), eac h b it bein g shift ed out, at

a maximum frequency fR, dur ing the falling edge of

Serial Clock (C).

The instruction sequenc e is shown in Figure 12.

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift -

ed out. T he whole memory c an, th erefore, be read

with a singl e Read Data Byt es (READ) i nst ruction.

When the highes t address is reached, the address

counter rolls over to 000000h, allowing the read

sequence to be continued indefinitely.

The Read Data Bytes (READ) instructi on is termi-

nated by driving Chi p Select (S) High. Chip Select

(S) can be driven High at any time during data out-

put. Any Read Data Bytes (READ) instruction,

while an Erase, Program or Write cycle is in

progress, is rej ected without having any ef fects on

th e cycle tha t is i n progr es s.

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data Out 1

Instruction 24-Bit Address

MSB

Data Out 2

M25P80

16/34

Figure 13. Read Data Bytes at Hi gher Speed (FAST_READ) Sequence

Note: 1. Address bits A23 to A20 are Don’ t Care.

Read Data Bytes at Hig her Speed

(FAST_READ)

The de vice is f irst s el ected by driving Chip Sele ct

(S) Low. The instruction code for the Read Data

Bytes at Higher Speed (FAST_READ) instruction

is followed by a 3-byte address (A23-A0) and a

dummy byte, each bit being latched-in during the

rising edge of S erial Clock (C). Then the memory

contents, at that address, is shifted out on Serial

Data Output (Q), each bit being shifted out, at a

maximum frequency fC, durin g the falling edg e of

Serial Clock (C).

The instruction sequenc e is shown in Figure 13.

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift -

ed out. T he whole memory c an, th erefore, be read

with a single Read Data Bytes at Higher Speed

(FAST_READ) instruction. When the highest ad-

dress is reached, the address counter rolls over to

000000h, allowing the read sequence to be contin-

ued indefinitely.

The Read Data Bytes at Higher Speed

(FAST_REA D) instruction is terminated by driving

Chip Select ( S) Hi gh. Chip Select (S) can be driv-

en High at any time during data outp ut. Any Read

Data Bytes at Higher Speed (FAST_READ) in-

struction, while an Erase, Program or W rite cycle

is in progress, is rejected without having any ef-

fects on the cycle that is in progress.

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24 BIT ADDRESS

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy Byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

17/34

M25P80

Figure 14. Page Program (PP) Sequence

Note: 1. Address bits A23 to A20 are Don’ t Care.

Page Prog ram (PP)

The Page Pr ogram (PP) instruction allows bytes to

be programmed in t he memory ( changing bits from

1 to 0). Before i t can be ac cept ed, a Wri te Enable

(WREN) instruction must previously have been ex-

ecuted. After the Wri te Enable (WREN) instruction

has been decoded , the device sets the Write En-

able Latch (WEL).

The Page Pro gram (PP) instru ction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, three address bytes and at least

one data byte on Serial Data Input (D). If the 8

least significant address bits (A7-A0) are not all

zero, all transmitted dat a that goes beyond the end

of the current page are programmed from the star t

address of the same page (from the address

whose 8 l east si gnificant bi ts (A7-A0) are all zero).

Chip Select ( S) must be driven Low for the entire

duration of the seq uence.

The instruction sequenc e is shown in Figure 14.

If more than 256 bytes are sent to the device, pre-

viously latched data are discarded and the last 256

data bytes are guaranteed to be programmed cor-

rectly within the sam e pag e. If less than 256 Data

bytes are sent to device, they are correctly pro-

grammed at the requested addresses without hav-

ing any effects on the other bytes of the same

page.

Chip Select (S) must be driven High after the

eighth bi t of the last data byte has been l atched in,

otherwise the Page Program (PP) instruction is not

executed.

As soon as Chip Select (S ) is driv en H ig h , t h e se lf -

timed Page Program cycle (whose durati o n is tPP)

is initiated. While the Page Program cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit .

The Write In Progress ( WIP) bit is 1 during the self-

timed Page Program cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is completed, the Write Enable Latch (WEL)

bit is reset.

A Page Program (PP) instruction applied to a page

which is protected by the Block Protect (BP2, BP1,

BP0) bits (see Tables 3 and 2) is not executed.

AI04082B

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte 256

2079

2078

2077

2076

2075

2074

2073

765432 0

2072

MSB MSB

MSB MSB MSB

M25P80

18/34

Figure 15. Sector Erase (SE) Sequence

Note: 1. Address bits A23 to A20 are Don’ t Care.

Sector Erase (SE)

The Sector E rase (SE) instruction sets to 1 (FFh)

all bits inside the chosen sector. Before it can be

accepted, a Write Enable (WREN) instruction

must previously have been executed. After the

Write Enable (WREN) instruction has been decod-

ed, the device sets the Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, and three address bytes on Serial

Data Input (D). Any address inside the Sector (see

Table 3) is a valid address for the Sector Erase

(SE) instruction. Chip Select (S) must be driven

Low for the entire duration of the sequence.

The instruction sequenc e is shown in Figure 15.

Chip Select (S) must be driven High after the

eighth bit of the last address byte has been latched

in, otherwise the Sector Erase (SE) instruction is

not executed. As soon as Chip Sel ect (S) is driven

High, t he self-timed Sector Erase cycle (whose du-

ration is tSE) is initiated. While the Sector Erase cy-

cle is in progress, the Status Register may be read

to check the value of the Wri te In Progress (WIP)

bit. The Wri t e In Progress (WI P) bit is 1 during the

self-timed Sector Erase cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is completed, the Write Enable Latch (WEL)

bit is reset.

A Sec tor E ras e (SE ) instruction applie d to a page

which is protected by the Block Protect (BP2, BP1,

BP0) bits (see Tables 3 and 2) is not executed.

24 Bit Address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

19/34

M25P80

Figure 16. Bulk Erase (BE) Sequ enc e

Bulk Erase (BE)

The Bulk Erase (BE) instruction sets all bits to 1

(FFh). Before it can be accepted, a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Wri te Enable (WREN) instruction

has been decoded , the device sets the Write En-

able Latch (WEL).

The Bulk Erase (BE) instruction i s entered by dri v-

ing Chip Select (S) Low, followed by t he ins truction

code on Serial Data Input (D). Chip Select (S)

must be driven Low for the entire duration of the

sequence.

The instruction sequenc e is shown in Figure 16.

Chip Select (S) must be driven High after the

eighth bi t of the instruction code has been l atched

in, otherwise the Bulk Erase instruction is not exe-

cuted. As soon as Chip Select (S) is driven High,

th e s elf -timed Bu l k Era se cycl e (who se duration i s

tBE) is initiated. While the Bulk Erase cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit .

The Write In Progress ( WIP) bit is 1 during the self-

timed Bulk Erase cycle, and is 0 when it is com-

pleted. At some unspecified tim e before the cycle

is completed, the Write Enable Latch (WEL) bit is

reset.

The Bulk Erase (BE) instruction is executed only if

all Block Protect (BP2, BP1, BP0) bits are 0. The

Bulk Erase (BE) instruction is ignored if one, or

more, sectors are protected.

AI03752D

21 345670

Instruction

M25P80

20/34

Figure 17. Deep Power-down ( DP) Sequence

Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction

is the only way to put the device in the lowest con-

sumption mode (the Deep Power-down mode). It

can also be used as an extra software protection

mechanism , while the device is not in active use,

since in this mode, the device ignores all Write,

Program and Eras e instructions.

Driving Chip Select (S) High deselect s the device,

and puts the dev ice in the S tandby m ode (if there

is no internal cycle currently in progress). But this

mode is not the Deep Power-down mode. The

Deep Power-down mode can only be entered by

executing the Deep Power-down (DP) instru ction,

to reduce the standby current (from ICC1 to I CC2,

as specified in Table 12).

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Power-down and Read Elec-

tronic Signature (RES) instruction. This releases

the device from this mode. The Release from

Deep Power-down and Read Electronic Signature

(RES) instructio n also allows the Electronic Signa-

ture of the device to be output on Serial Data Out-

put (Q).

The Deep P ower-down m ode automatically stops

at Power-down, and the device always Powers-up

in the St andby mode.

The Deep Power-down (DP) instruction is entered

by driving Chip Select (S) Low, followed by the in-

struction code on Serial Data Inp ut (D). Ch ip Se-

lect (S) m ust be d riven Low for the entire durat ion

of the seq uence.

The instruct ion sequence is shown in Figure 17.

Chip Select (S) must be driven High after the

eighth bi t of the instruction code has been l atched

in, otherwise t he Deep Power-down (DP) instruc-

tion is not executed. As soon as Chip Select (S) i s

driven High, it requires a delay of tDP before the

supply current is reduced to ICC2 and the Deep

Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an

Erase, Program or Write cycle is in progress, is re-

jected wi th o ut havi ng any effects on the cycl e tha t

is in progr ess.

AI03753D

21 345670 t

Deep Power-down Mode

Stand-by Mode

Instruction

21/34

M25P80

Figure 18. Rel ease from Deep Po wer-d ow n and Read Electro nic Sign atur e (RES) Sequen ce

Release from Deep Power-do wn and Read

Electronic Signature (RES)

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Power-down and Read Elec-

tronic Signature (RES) instruction. Executing this

instruction takes the device out of the Deep Pow-

er-down mode. The instruction can also be used to

read, on Serial Data Output (Q), the 8-bit Elec tron-

ic Signature of the device.

Except while an Erase, Program or Write Status

Deep Power-down and Read Electronic Signature

(RES) instruction always provides access to the

Electronic Signature of the device, and can be ap-

plied even if the Deep Po wer-down mode has not

been entered.

Any Release from Deep Power-down and Read

Electronic Signature (RES) instruction while an

Erase, Program or Write Status Register cycle is in

progress, is not decoded, and has no effect on the

cycle that is in progress.

This instruction serves a s econd purpose. The de-

vice features an 8-bit Electronic Signature, whose

value for the M25P 80 is 13h. This can be read us-

ing the Release from Deep Power-down and Read

Electronic Signature (RES) instruction.

The de vice is f irst s el ected by driving Chip Sel ect

(S) Low. The instruction code is followed by 3

dummy bytes, each bit being latched-in on Serial

Data Input (D) during the rising edge of Serial

Clock (C). Then, the 8-bit Electronic Signature,

stored in the memory, is shift ed out on Serial Data

Output (Q), each bit being shifted out during the

falling edge of Serial Clock (C).

The instruct ion sequence is shown in Fi gure 18.

The Release from Deep Power-down and Read

Electronic Si gnature (RES) instruct ion is terminat -

ed by driving Chip Sele ct (S) High after the Elec-

tronic Signature has been read at least once.

Sending additional clock cycles on Serial Clock

(C), while Chip Select (S) is dr iven Low, c ause the

Electronic Signature to be output repeatedly.

When Chip Select (S) i s dri ven High, t he de vice is

put in the Standby mode. If the device was previ-

ously in the Deep Power-down mode, the transi-

tion to the Standby mode is delayed by tRES2. Chip

Select (S) must remain High for at least

tRES2(max ), as specified i n Table 13. Once in t he

Standby mode, the device waits to be sel ected, so

that it can receive, decode and execute instruc-

tions.

AI04047C

21 345678910 2829303132333435

2221 3210

36 37 38

765432 0

High Impedance Electronic Signature Out

Instruction 3 Dummy Bytes

MSB

Stand-by Mode

Deep Power-down Mode

MSB

tRES2

M25P80

22/34

Figure 19. Rel ease from Deep Power-d ow n (RES) Seque nce

Driving Chip Select (S) High after the 8-bit instru c-

tion byte has been received by the device, but be-

fore the whole of the 8-bit Electronic Signature has

been transmit ted for the first time (as shown in Fig-

ure 19), st ill insures t hat the device is taken out of

the Deep Power-down mode, but incurs a delay

(tRES1) before the device is pu t in Standb y mode.

Chip Select (S) must remain High for at least

tRES1(max ), as specified i n Table 13. Once in t he

Standby mode, the device waits to be sel ected, so

that it can receive, decode and execute instruc-

tions.

AI04078B

21 345670 t

RES1

Stand-by Mode

Deep Power-down Mode

QHigh Impedance

Instruction

23/34

M25P80

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must

not be selected (that is Chip Select (S) must follow

the volt age appl i ed on VCC) until VCC reache s the

correct value:

–V

CC(min) at Power-up, and then for a further de-

lay o f tVSL

–V

SS at Power-down

Usually a simple pull-up resistor on Chip Select (S)

can be used to insure safe and proper Power-up

and Power-down.

To avoid data corruption and inadvertent write

operations during power up, a Power On Reset

(POR) circuit is included. The logic inside the

device is held reset while VCC is less than the POR

threshold value, VWI – all operations are disabled,

and the device does not respond to any

instruction.

Moreover, the device ignores all Write Enable

(WREN), Page Program (PP), Sector Erase (SE),

Bulk Erase (BE) and Write Status Register

(WRSR) instructions until a time delay of tPUW has

elapsed after the moment that VCC ris es above the

VWI threshold. However, the correct operation of

the device is not guaranteed if, by t his time, VCC is

still below VCC(min). No Write Status Register,

Program or Erase instructions should be sent until

the later of:

–t

PUW af ter VCC passed the VWI threshold

–t

VSL afterVCC pass ed the VCC(min) level

These values are specified in Table 7.

If the delay, tVSL, has el apsed, after VCC has risen

above VCC(min), the device can be selected for

READ instructions even if the tPUW delay is not yet

fully elapsed.

At Power-up, the dev ice is in the f ollowing sta te:

– The device is in the Standby mode (not the

Deep Power-down mode).

– The Write Enable Latch (WEL) bit is reset.

At Power-down, when VCC drops from the

operating voltage, to below the POR threshold

value, VWI, all operations are disabled and the

device does not respond to any instruction. (The

designer needs to be aw are that if a Power-down

occurs while a Write, Program or Erase cycle is in

progress, some data corruption can result.)

Figure 20. Power-up Timing

Table 7. Power-Up Timing and VWI Th re shold

No te : 1. Thes e param eters are character i zed only.

Symbol Parameter Min. Max. Unit

tVSL1VCC(min) to S low 10 µs

tPUW1Time delay to Write instruction 1 10 ms

VWI1Write Inhibit Voltage 1 2 V

VCC

AI04009C

VCC(min)

VWI

Reset State

of the

Device

Chip Selection Not Allowed

Program, Erase and Write Commands are Rejected by the Device

tVSL

tPUW

time

Read Access allowed Device fully

accessible

VCC(max)

M25P80

24/34

INITIAL DELIVERY STATE

The device is delivered with the memory array

erased: all bits are set to 1 (each byte contains

FFh). The Status Register cont ains 00h (all Status

25/34

M25P80

MAX I MUM R AT I N G

Stressing the device ab ove t he rati ng l isted in t he

Absolute Maximum Ratings" table may caus e per-

manent damage to the device. These are stress

ratings only and operation of the device at t hes e or

any other con ditions ab ove those i ndicated i n the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Not e: 1. I PC/ JED EC J- STD- 020 A

2. JED EC Std JESD22-A11 4A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Min. Max. Unit

TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering (20 seconds max.)1235 °C

VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V

VCC Supply Voltage –0.6 4.0 V

VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V

M25P80

26/34

DC AND AC PARAME TERS

This section summarizes the operating and m ea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Des igners shoul d c heck that the operating

conditions i n their circuit match the meas urement

conditions when relying on the quoted parame-

ters.

Table 9. Operating Conditions

Table 10. AC Measurement Conditions

Note: 1. Output Hi-Z i s defined as the point where data out is no l onger dri ven.

Figure 21. AC Measurement I/O Waveform

Table 11. Capacitance

Note: Sampled o nl y, not 100% tested, at TA= 25°C and a frequen cy of 20 MHz .

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.7 3.6 V

TAAmbient Operati ng Tem peratur e –40 85 °C

Symbol Parameter Min. Max. Unit

CLLoad Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC V

AI00825

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol Parameter Test Condition Min.Max.Unit

COUT Output Capacitance (Q) VOUT = 0V 8 pF

CIN Input Capacitance (other pins) VIN = 0V 6 pF

27/34

M25P80

Table 12. DC Characteristics

Symbol Parameter Test Condition

(in addition to those in Table 9) Min. Max. Unit

ILI Input Leaka ge Curren t ± 2 µA

ILO Output Leakage Current ± 2 µA

ICC1 Standby Current S = VCC, VIN = VSS or VCC 50 µA

ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 5µA

CC3 Operating Current (READ) C = 0.1VCC / 0.9.VCC at 25 MHz,

Q = open 4mA

CC4 Operating Current (PP) S = VCC 15 mA

ICC5 Operating Current (WRSR) S = VCC 15 mA

ICC6 Operating Current (SE) S = VCC 15 mA

ICC7 Operating Current (BE) S = VCC 15 mA

VIL Input Low Voltage – 0.5 0.3VCC V

VIH Input High Volta ge 0.7VCC VCC+0.4 V

VOL Output Low Voltage IOL = 1.6 mA 0.4 V

VOH Output High Voltage IOH = –100 µAV

CC–0.2 V

M25P80

28/34

Table 13. AC Characteristics

Note: 1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guaranteed by characterization, not 100% tested in production.

Test conditions specified in Table 9 and Table 10

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfCClock Frequency for the following instructions:

FAST_READ, PP, SE, BE, DP, RES,

WREN, WRDI, RDSR, WRSR D.C. 25 MHz

fRClock Fre quen cy for READ instruc tions D.C. 2 0 MH z

tCH 1tCLH Clock High Time 18 ns

tCL 1tCLL Clock Low Time 18 ns

Clock Slew Rate 2 (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 10 ns

tCHSL S Not Active Hold Time (relative to C) 10 ns

tDVCH tDSU Data In Setup Time 5 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 10 ns

tSHCH S Not Active Setup Time (relative to C) 10 ns

tSHSL tCSH S Dese lect Time 100 ns

tSHQ Z 2tDIS O utput Disable Time 15 ns

tCLQV tVClock Low to Output Valid 15 ns

tCLQX tHO O utput Hold Time 0 ns

tHLCH HOLD Setup Time (relative to C) 10 ns

tCHHH HOLD Hold Time (relative to C) 10 ns

tHHCH HOLD Setup Time (relative to C) 10 ns

tCHHL HOLD Hold Time (relative to C) 10 ns

tHHQX 2tLZ HOLD to Output Low-Z 15 ns

tHLQZ 2tHZ HOLD to Output High-Z 20 ns

tDP 2S High to Deep Power-down Mode 3 µs

tRES1 2S High to Standby Mode without Electronic

Signature Read 3µs

tRES2 2S High to Standby Mode with Electronic

Signature Read 1.8 µs

tWWrite Status Register Cycle Time 5 15 ms

tPP Page Program Cycle Time 2 5 ms

tSE Sector Erase Cycle Time 2 3 s

tBE Bulk Erase Cycle Time 10 20 s

29/34

M25P80

Figure 22. S erial Input Timing

Figu re 23 . H ol d Timing

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

AI02032

HOLD

tCHHL

tHLCH

tHHCH

tCHHH

tHHQXtHLQZ

M25P80

30/34

Figure 24. Output Timing

AI01449D

LSB OUT

DADDR.LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

31/34

M25P80

PACKAGE MECHANICAL

SO8 wide – 8 lead Plastic Smal l Outline, 200 mils body wi dth

Not e: Drawing is not to scale.

SO8 wide – 8 lead Plastic Smal l Outline, 200 mils body wi dth

SO-b

LA1 α

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 2.03 0.080

A1 0.10 0.25 0.004 0.010

A2 1.78 0.070

B 0.35 0.45 0.014 0.018

C 0.20 – – 0.008 – –

D 5.15 5.35 0.203 0.211

E 5.20 5.40 0.205 0.213

e 1.27 – – 0.050 – –

H 7.70 8.10 0.303 0.319

L 0.50 0.80 0.020 0.031

α0° 10° 0° 10°

N8 8

CP 0.10 0.004

M25P80

32/34

PART NUMBERING

Table 14. Ordering Information Scheme

For a list of available options (speed, package,

etc.) or for further information on any aspect of this

device, please con tact your nearest ST Sales O f-

fice.

Example: M25P80 –VMW6T

Device Type

M25P

Device Function

80 = 8 Mbit (1M x 8)

Operating Voltage

V = VCC = 2.7 to 3.6V

Package

MW = SO8 (200 mil width)

Temperature Range

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

33/34

M25P80

RE VISION HI ST ORY

Table 15. Document Revisio n History

Date Rev. Description of Revision

11-Sep-2001 0.1 Target Specification Document written

16-Jan-2002 0.2 FAST_READ instruction added. Document revised with new timings, VWI, ICC3 and clock slew

rate. Descriptions of Polling, Hold Condition, Page Programming, Release for Deep Power-

down made more precise. Value of tW(max) modified.

M25P80

34/34

Information furnished is believed to be accurate and re liable. However, STMicroelectronics assumes no r esponsibility for the c onsequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by i m pl i cation or oth erwise under any pat ent or paten t r i ghts of STMic roelectronics. Spec i fications mentioned i n this public atio n are s ubj ect

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized f or u se as critical com ponents in life support devices or system s without exp res s wri t ten approval of STM i croelectronics.

The ST logo is registered trademark of STMicroelectronics

All other nam e s are th e property of their respective owners

STM ic roelec t ronics group o f c om panies Austral i a - Brazil - Canada - China - Finland - F rance - Germany - Hong Kong -

India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Swit zerland - United Kingdom - United States.