REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R166-92 92-03-30 Michael A. Frye B Boilerplate update, part of 5 year review. ksr 06-12-11 Raymond Monnin THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV B B SHEET 15 16 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY James E. Jamison STANDARD MICROCIRCUIT DRAWING Kenneth Rice APPROVED BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE Michael A. Frye DRAWING APPROVAL DATE 91-01-21 AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil CHECKED BY REVISION LEVEL B MICROCIRCUIT, MEMORY, DIGITAL, CMOS UV ERASABLE PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 . 1 OF 5962-90611 16 5962-E012-07 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-90611 01 X A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 1/ 01 02 Circuit function tPD 32-Macrocell EPLD 32-Macrocell EPLD 35 ns 25 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter X Y Descriptive designator GDIP4-T28 or CDIP3-T28 GQCC1-J28 Terminals Package style 28 28 dual-in-line package J leaded chip carrier package 2/ 2/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage to ground potential ..................................................................-2.0 V dc to +7.0 V dc DC input voltage .............................................................................................-2.0 V dc to +7.0 V dc Maximum power dissipation 3/ .......................................................................1.5 W Lead temperature (soldering, 10 seconds)......................................................+260C Thermal resistance, junction-to-case (JC): Cases X and Y ..............................................................................................See MIL-STD-1835 Junction temperature (TJ) ...............................................................................+175C Storage temperature range .............................................................................-65C to +150C Temperature under bias..................................................................................-55C to +125C Endurance.......................................................................................................25 erase/write cycles (minimum) Data retention .................................................................................................10 years, (minimum) 1.4 Recommended operating conditions. Supply voltage (VCC) .......................................................................................+4.5 V dc to +5.5 V dc Ground voltage (GND) ....................................................................................0 V dc Input high voltage (VIH)....................................................................................2.2 V dc minimum Input low voltage (VIL) .....................................................................................0.8 V dc maximum Operating case temperature range (TC) ..........................................................-55C to +125C 1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103. 2/ Lid shall be transparent to permit ultraviolet light erasure. 3/ Must withstand the added PD due to short circuit test; (e.g., IOS). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 2 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for nonJAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MILPRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MILPRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. 3.2.3.1 Unprogrammed or erased devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in groups A, B, C, or D (see 4.3), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of cells shall be programmed or at least 25 percent of the total number of cells to any altered item drawing. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 3 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. 3.5.1 Certification/compliance mark. A compliance indicator "C" shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator "C" shall be replaced with a "Q" or "QML" certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing EPLDs. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.10.1 Erasure of EPLDs. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.4 herein. 3.10.2 Programmability of EPLDs. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5 herein. 3.10.3 Verification of erasure of programmed EPLDs. When specified, devices shall be verified as either programmed to specified program or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.11 Endurance. A reprogrammability test shall be completed as part of the vendor's reliability monitors. This reprogrammability test shall be done only for initial characterization and after any design or process changes which may affect the reprogrammability of the device. The methods and procedures may be vendor specific, but will guarantee the number of program/erase endurance cycles listed in section 1.3 herein. The vendors procedure shall be under document control and shall be made available upon request. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 4 c. A data retention stress test shall be included as part of the screening procedure and shall consist of the following steps: (Steps 1 through 4 may be performed at the wafer level. The maximum storage temperature shall not exceed 200C for packaged devices and 300C for unassembled devices.) Margin test method. (1) (2) (3) (4) (5) (6) (7) (8) Program a minimum of 95% of the total number of cells, including the slowest programming cell (see 3.10.2). Bake, unbiased, for 72 hours at +140C, or for 48 hours at +150C, or for 8 hours at +200C, or for unassembled devices only 2 hours at 300C. Perform electrical test (see 4.2b) at 25 including a margin test at Vm = 5.7 V and loose timing (i.e., = 1 s). Erase (see 3.10.1). Program a minimum of 50 percent of the total number of cells, including the slowest programming cell (see 3.10.2). Perform electrical test (see 4.2b) at 25 including a margin test at Vm = 5.7 V and loose timing (i.e., = 1 s). Perform burn-in (see 4.2a). Perform electrical test (see 4.2b) at 25 including a margin test at Vm = 5.7 V and loose timing (i.e., = 1 s). (9) Repeat step 8 at tC = +125C and -55C. (10) Erase (see 3.10.1). Devices may be submitted for groups A, C, and D testing prior to erasure provided the devices have been 100 percent seal tested in accordance with method 5004 of MIL-STD-883. (11) Verify erasure (see 3.10.3). 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5, and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN and COUT measurement) shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input and output terminals tested. d. See footnote 4/ of table II. e. All devices selected for testing shall be programmed per 3.2.3.1 herein. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) The devices selected for testing shall be programmed per 3.2.3.1 herein. After completion of testing, the devices shall be erased and verified (except devices submitted for group D testing). (2) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (3) TA = +125C, minimum. (4) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 5 TABLE I. Electrical performance characteristics. Symbol Test Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Output high voltage VOH VCC = 4.5 V, IOH = -4.0 mA VIH = 2.2 V, VIL = 0.8 V 1, 2, 3 All Output low voltage VOL VCC = 4.5 V, IOL = 8.0 mA VIH = 2.2 V, VIL = 0.8 V 1, 2, 3 All Input high voltage 1/ 2/ VIH 1, 2, 3 All Input low voltage 1/ 2/ VIL 1, 2, 3 All Input leakage current IIL 1, 2, 3 All Output leakage current IOZ VCC = 5.5 V, VOUT = 5.5 V to GND 1, 2, 3 Output short circuit current 2/ 3/ IOS VCC = 5.5 V and 4.5 V,, VOUT = 0.5 V Power supply current 2/ 4/ ICC1 VCC = 5.5 V, IOUT = 0 mA Power supply current (standby) 4/ ICC2 VCC = 5.5 V, IOUT = 0 mA VIN = VCC to GND Input capacitance 2/ CIN Output capacitance 2/ COUT VCC = 5.0 V TA = +25C, f = 1 MHz VIN = 0.0 V See 4.3.1c VCC = 5.5 V, VIN = 5.5 V to GND Max 2.4 V 0.45 V 2.2 V 0.8 V -10 10 A All -40 40 A 1, 2, 3 All -30 -90 A 1, 2, 3 All 270 mA 1, 2, 3 All 200 mA 4 All 10 pF 4 All 12 pF 7,8A, 8B All f = fMAX1 VIN = VCC to GND Functional tests See 4.3.1d See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 6 TABLE I. Electrical performance characteristics - Continued. Symbol Test Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max External Synchronous Switching Characteristics Dedicated input to combinatorial output delay 6/ tPD1 I/O input to combinatorial output delay 7/ tPD2 Dedicated input to combinatorial output delay with expander delay 2/ 8/ I/O input to combinatorial output delay with expander delay 2/ 9/ Input to output enable delay 2/ 10/ Input to output disable delay 2/ 10/ See figure 4 5/ 01 35 02 25 01 35 02 25 01 60 02 40 01 60 02 40 01 35 02 25 01 35 02 25 01 23 02 15 01 46 9, 10, 11 02 30 9, 10, 11 01 21 02 15 9, 10, 11 9, 10, 11 9, 10, 11 tPD3 9, 10, 11 tPD4 9, 10, 11 tEA 9, 10, 11 tER ns ns ns ns ns ns Synchronous clock input to output delay tCO1 Synchronous clock to local feedback to combinatorial output 2/ 11/ tCO2 Any input or feedback setup time to synchronous clock input tS Input hold time from synchronous clock input tH 9, 10, 11 All 0 ns Synchronous clock input high time 2/ tWH 9, 10, 11 01 10 ns 02 8 9, 10, 11 ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 7 TABLE I. Electrical performance characteristics - Continued. Symbol Test Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max External Synchronous Switching Characteristics Synchronous clock input low time 2/ 9, 10, 11 tWL See figure 4 Asynchronous clear width 5/ 9, 10, 11 tRW 12/ Asynchronous clear recovery time 12/ Asynchronous clear to registered output delay 12/ tRO Asynchronous preset width 12/ tPW Asynchronous preset recovery time 12/ tPO Synchronous clock to local feedback input 2/ 13/ tCF External synchronous clock period (tCO1 + tS) tP Maximum frequency with internal only feedback 1/ (tCF + tS) 2/ 15/ 9, 10, 11 9, 10, 11 9, 10, 11 tPR Asynchronous preset to registered output delay 12/ External maximum frequency 1/ (tCO1 + tS) 14/ 9, 10, 11 tRR 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 fMAX1 9, 10, 11 fMAX2 01 10 02 8 01 33 02 28 01 35 02 25 ns ns ns 01 33 02 28 01 33 02 28 01 38 02 25 ns ns 01 33 02 28 01 13 02 7 01 44 02 30 01 22.7 02 33.3 01 29.4 02 45.4 ns ns ns ns MHz MHz See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 8 TABLE I. Electrical performance characteristics - Continued. Symbol Test Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max External Synchronous Switching Characteristics Data path maximum frequency, least of 1/ (tWH + tWL) , 1/ (tH + tS1) or 1/ (tCO1 ) 12/ 16/ Maximum register toggle frequency 1/ (tWH + tWL) 12/ 17/ Output data stable time from synchronous clock input 12/ 18/ fMAX3 See figure 4 5/ 9, 10, 11 9, 10, 11 fMAX4 9, 10, 11 tOH 01 43.4 02 62.5 01 50.0 02 62.5 All 2 MHz MHz ns External Asynchronous Switching Characteristics Asynchronous clock input to output delay Asynchronous clock input to local feedback to combinatorial output 2/ 19/ Dedicated input or feedback setup time to asynchronous clock input tACO1 9, 10, 11 9, 10, 11 9, 10, 11 tAS tAH Asynchronous clock input high time 2/ tAWH Asynchronous clock to local feedback input 2/ 20/ 5/ tACO2 Input hold time from asynchronous clock input Asynchronous clock input low time 2/ See figure 4 9, 10, 11 9, 10, 11 9, 10, 11 tAWL 9, 10, 11 tACF 01 35 02 25 01 62 02 46 01 15 02 12 01 17.5 02 12 01 30 02 11 01 30 02 11 ns ns ns ns ns ns 01 27 02 21 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 9 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max External Synchronous Switching Characteristics External asynchronous clock period (tACO1 + tAS) or 2/ (tAWH + tAWL) External maximum frequency in asynchronous mode 1/(tAP) 2/ 21/ Maximum internal asynchronous frequency 1/ (tACF + tAS) 2/ 22/ Data path maximum frequency in asynchronous mode 2/ 23/ Maximum asynchronous register toggle frequency 1/(tAWH + tAWL) 2/ 24/ Output data stable time from asynchronous clock input 12/ 25/ tAP See figure 4 5/ 9, 10, 11 fMAXA1 9, 10, 11 01 50 02 37 01 20.0 02 27.0 ns MHz fMAXA2 9, 10, 11 01 02 16.6 25.0 MHz fMAXA3 9, 10, 11 01 02 16.6 40.0 MHz fMAXA4 9, 10, 11 01 02 16.6 45.0 MHz tAOH 9, 10, 11 All 14 ns 1/ These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2/ Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the limits specified in Table I. 3/ For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed one second. 4/ Measured with device programmed with manufacturer test pattern and the test pattern shall be made available upon request. 5/ AC tests are performed with input rise and fall times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and the output load on figure 3, circuit A. 6/ This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function. (see figure 4) 7/ This parameter is the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to form the logic function. 8/ This parameter is the delay from an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 10 TABLE I. Electrical performance characteristics - Continued. 9/ This parameter is the delay from an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. 10/ Transition is measured + 0.5 V from steady state voltage on the output from the 1.5 V level on the input with the load on figure 3, circuit B. 11/ This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output for which the registered output signal is used as an input. This parameter assumes that no expanders are used in the logic of the combinatorial output and the register is synchronously clocked. (see figure 4) 12/ Values guaranteed by design and are not tested. 13/ This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, tS, is the minimum internal period for an internal state machine configuration. 14/ This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only feedback can operate. 15/ This specification indicates the guaranteed maximum frequency at which a state machine with internal only feedback can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. This specification assumes no expander logic is used. 16/ This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes that no expander logic is used. 17/ This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled by a clock signal applied to either a dedicated input pin or an I/O pin. 18/ This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin. 19/ This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to a combinatorial output for which the registered output signal is used as an input. Assumes no expanders are used in logic of combinatorial output or the asynchronous clock input. 20/ This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clocked register. This delay plus the asynchronous register setup time, tAS, is the minimum internal period for an asynchronously clocked state machine configuration. This delay assumes no expander logic in the asynchronous clock path. (see figure 4) 21/ This parameter indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed no expander logic is employed in the clock signal path or data input path. 22/ This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal only feedback can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. This specification assumes no expander logic is utilized. 23/ This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode. If this frequency is less than 1/(tACO1) or 1/(tAS + tAH). It also indicates the maximum frequency at which the device may operate in the asynchronously clocked data path mode. Assumes no expander logic used. 24/ This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to either a dedicated input or an I/O pin. 25/ This parameter indicates the minimum time that the previous register output data is maintained on the output pin, after an asynchronous register clock is input to an external dedicated input or I/O pin. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 11 Device types Case outlines Terminal number ALL X Y Terminal symbol 1 2 3 4 5 6 7 I I/CLK I/O I/O I/O I/O 8 9 10 11 12 13 14 15 16 17 18 19 20 21 GND I/O I/O I/O I/O I I I I I/O I/O I/O I/O GND 22 23 24 25 26 27 28 VCC VCC I/O I/O I/O I/O I I VCC I/O I/O I/O I/O I I I I/CLK I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I I I I I/O I/O I/O I/O GND FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 12 Input pins Output pins CP/I I I/O X X Z NOTES: 1. X = Don't care 2. Z = High impedance FIGURE 2. Truth table (unprogrammed). AC test conditions Input pulse levels Input rise and fall times Input timing reference levels Output reference levels GND to 3.0 V 5 ns 1.5 V 1.5 V FIGURE 3. Output load circuit and test conditions. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 13 FIGURE 4. Switching waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 14 FIGURE 4. Switching waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 15 4.4 Erasing procedure. The recommended erasure procedure is exposure to shortwave ultraviolet light which has a wavelength of 2,537 Angstroms (A). The integrated dose (i.e., ultraviolet intensity times exposure time) for erasure should be minimum of 25 Ws/cm2. The erasure time with this dosage is approximately 35 minutes using an ultraviolet lamp with a 12,000 W/cm2 power rating. The device should be placed within 1 inch of the lamp tubes during erasure. The maximum integrated dose the device can be exposed to without damage is 7,258 Ws/cm2 (1 week at 12,000 W/cm2). Exposure of the device to high intensity ultraviolet light for long periods may cause permanent damage. 4.5 Programming procedures. The programming procedures shall be as specified by the device manufacturer and shall be made available upon request. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (method 5004) Final electrical test parameters (method 5004) 1 1*, 2, 3, 7*, 8A, 8B, 9, 10, 11 Group A test requirements (method 5005) 1, 2, 3, 4**, 7, 8A, 8B, 9, 10, 11 Groups C and D end-point electrical parameters (method 5005) 1/ 2/ 3/ 4/ 2, 3, 7, 8A, 8B (*) indicates PDA applies to subgroups 1 and 7. Any or all subgroups may be combined when using high speed testers. (**) see 4.3.1c. Subgroup 7 functional tests shall verify that no cells are programmed for unprogrammed devices, and that the altered item drawing pattern exists for programmed devices, or that the devices comply with 3.2.3.1 herein. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0547. 6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MILHDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-90611 A REVISION LEVEL B SHEET 16 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 06-12-11 Approved sources of supply for SMD 5962-90611 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-9061101XA 0C7V7 CY7C344-35WMB 5962-9061101YA 0C7V7 CY7C344-35HMB 5962-9061102XA 0C7V7 CY7C344-25WMB 3/ EPM5032DM883B 0C7V7 CY7C344-25HMB 3/ EPM5032JM883B 5962-9061102YA 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the Vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source. Vendor CAGE number 0C7V7 Vendor name and address QP Semiconductor 2945 Oakmead Village Court Santa Clara, CA 95051 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.