512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM DDR SDRAM Registered Module 184pin Registered Module based on 512Mb B-die (x4, x8) with 1,200mil Height & 72-bit ECC 60 FBGA with Pb-Free (RoHS compliant) Revision 1.2 Oct. 2004 Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM Revision History Revision 1.0 (Feburary, 2004) - First release Revision 1.1 (March, 2004) - Added 512MB RDIMM. Revision 1.2 (October, 2004) - Corrected typo. Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM 184Pin Registered DIMM based on 512Mb B-die FBGA (x4, x8) Ordering Information Part Number Density Organization M312L6523BZ0-CB3/A2/B0 512MB 64Mx72 Component Composition M312L2923BZ0-CB3/A2/B0 1GB 128M x 72 64Mx8( K4H510838B) * 18EA 1,125mil M312L2920BZ0-CB3/A2/B0 1GB 128M x 72 128Mx4( K4H510438B) * 18EA 1,125mil M312L5720BZ0-CB3/A2/B0 2GB 256M x 72 128Mx4( K4H510438B) * 36EA 1,200mil 64Mx8( K4H510838B) * 9EA Height 1,125mil Operating Frequencies B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Speed @CL2 133MHz 133MHz 100MHz Speed @CL2.5 166MHz 133MHz 133MHz CL-tRCD-tRP 2.5-3-3 2-3-3 2.5-3-3 Feature * Power supply : Vdd: 2.5V 0.2V, Vddq: 2.5V 0.2V * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe(DQS) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM * SSTL_2 Interface Pb-Free * RoHS compliant SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM Pin Configuration (Front side/back side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ *CK1 */CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS *CK2 */CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 VSS DQ4 DQ5 VDDQ DM0/DQS9 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1/DQS10 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2/DQS11 VDD DQ22 A8 DQ23 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS A6 DQ28 DQ29 VDDQ DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8/DQS17 A10 CB6 VDDQ CB7 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 /RAS DQ45 VDDQ /CS0 /CS1 DM5/DQS14 VSS DQ46 DQ47 */CS3 VDDQ DQ52 DQ53 *A13 VDD DM6/DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD KEY 53 54 55 56 57 58 59 60 61 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 KEY 145 146 147 148 149 150 151 152 153 VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44 Note : 1. * : These pins are not used in this module. 2. Pins 111, 158 are NC for 1row module [M312L2920BZ0] & used for 2row module [M312L2923BZ0, M312L5720BZ0 ] 3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module). Pin Description Pin Name Function Pin Name Function A0 ~ A12 Address input (Multiplexed) DM0 ~ DM8 Data - in mask BA0 ~ BA1 Bank Select Address VDD Power supply (2.5V) DQ0 ~ DQ63 Data input/output VDDQ Power Supply for DQS(2.5V) DQS0 ~ DQS17 Data Strobe input/output VSS Ground CK0,CK0 ~ CK2, CK2 Clock input VREF Power supply for reference CKE0, CKE1(for double banks) Clock enable input VDDSPD Serial EEPROM Power/Supply ( 2.3V to 3.6V ) CS0, CS1(for double banks) Chip select input SDA Serial data I/O RAS Row address strobe SCL Serial clock CAS Column address strobe SA0 ~ 2 Address in EEPROM WE Write enable NC No connection CB0 ~ CB7 Check bit(Data-in/data-out) Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM 512MB, 64M x 72 ECC Module (M312L6523BZ0) (Populated as 1 bank of x8 DDR SDRAM Module) Functional Block Diagram RCS0 DQS0 DM0 DQS4 DM4 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 DQS D0 DQS CS D4 DQS5 DM5 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 CS DQS D1 CS DQS D5 DQS6 DM6 DQS2 DM2 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS DQS D2 CS DQS D6 DQS7 DM7 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 CS DQS D3 DQS8 DM8 VDDSPD CS DQS CS SPD VDD/VDDQ DDR SDRAMs D0 - D8 VREF DDR SDRAMs D0 - D8 VSS DDR SDRAMs D0 - D8 D8 Serial PD PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams CS0 BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK R E G I S T E R DQS D7 RCS0 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RWE SCL SDA WP A0 A1 A2 SA0 SA1 SA2 BA0 -BA1 : DDR SDRAMs D0 - D8 A0 -A12 : DDR SDRAMs D0 - D8 RAS : DDR SDRAMs D0 - D8 CAS : DDR SDRAMs D0 - D8 CKE : DDR SDRAMs D0 - D8 WE: DDR SDRAMs D0 - D8 RESET Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM 1GB, 128M x 72 ECC Module (M312L2923BZ0) (Populated as 2 bank of x8 DDR SDRAM Module) Functional Block Diagram RCS1 RCS0 DQS0 DM0 DQS4 DM4 DM/ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 DM/ DQS I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 D0 CS DQS DM/ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D9 DQS1 DM1 I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM/ I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 D4 CS DQS D13 DQS5 DM5 DM/ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 DQS DM/ I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 D1 CS DQS DM/ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D10 DQS2 DM2 I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM/ I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 D5 CS DQS D14 DQS6 DM6 DM/ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 DQS DM/ I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 D2 CS DQS DM/ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D11 DQS3 DM3 I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM/ I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 D6 CS DQS D15 DQS7 DM7 DM/ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 DQS DM/ I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 D3 CS DM/ DQS D12 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D7 DM/ I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D16 DQS8 DM8 DM/ CS I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQS DM/ I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 D8 CS DQS D17 Serial PD SCL SDA WP A0 A1 SA0 CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1 WE PCK R E G I S T E R SA1 VDDSPD SPD VDD/VDDQ D0 - D17 D0 - D17 A2 VREF D0 - D17 VSS D0 - D17 SA2 RCS0 RCS1 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RCKE1 RWE RESET BA0 -BA1 : DDR SDRAM DQ0 - D17 A0 -A12 : DDR SDRAM D0 - D17 RAS : DDR SDRAM D0 - D17 CAS : DDR SDRAM DQ0 - D17 CKE : DDR SDRAM D0 - D8 CKE : DDR SDRAM D9 - D17 WE: DDR SDRAM D0 - D17 PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. PCK Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM 1GB, 128M x 72 ECC Module (M312L2920BZ0) (Populated as 1 bank of x4 DDR SDRAM Module) Functional Block Diagram VSS RCS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ8 DQ9 DQ10 DQ11 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ16 DQ17 DQ18 DQ19 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ24 DQ25 DQ26 DQ27 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ32 DQ33 DQ34 DQ35 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ40 DQ41 DQ42 DQ43 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ48 DQ49 DQ50 DQ51 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ56 DQ57 DQ58 DQ59 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D0 DQS1 CS DM CS DM CS DM CS DM CS DM CS DM CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS D8 DM DQ20 DQ21 DQ22 DQ23 DQS I/O 0 I/O 1 I/O 2 I/O 3 D11 DQ28 DQ29 DQ30 DQ31 DQS I/O 0 I/O 1 I/O 2 I/O 3 D12 DQ36 DQ37 DQ38 DQ39 DQS I/O 0 I/O 1 I/O 2 I/O 3 D13 DQ44 DQ45 DQ46 DQ47 DQS I/O 0 I/O 1 I/O 2 I/O 3 D14 DQ52 DQ53 DQ54 DQ55 DQS I/O 0 I/O 1 I/O 2 I/O 3 D15 DQ60 DQ61 DQ62 DQ63 DQS I/O 0 I/O 1 I/O 2 I/O 3 D16 DQS16 (DM7) D7 DQS8 D10 DQS15 (DM6) D6 DQS7 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS14 (DM5) D5 DQS6 DQ12 DQ13 DQ14 DQ15 DQS13 (DM4) D4 DQS5 D9 DQS12 (DM3) D3 DQS4 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS11 (DM2) D2 DQS3 DQ4 DQ5 DQ6 DQ7 DQS10 (DM1) D1 DQS2 CB0 CB1 CB2 CB3 DQS9 (DM0) DQS17 (DM8) CB4 CB5 CB6 CB7 BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK R E G I S T E R RCS0_2 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0A RCKE0B RWE CS CS CS CS CS CS DM DM DM DM DM DM Serial PD DM SCL SDA WP CS DM VDDSPD CS A0 A1 A2 SA0 SA1 SA2 SPD VDD/VDDQ D0 - D17 VREF D0 - D17 VSS D0 - D17 DM D0 - D17 D17 PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams RCS0_1 CS0 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS BA0 -BA1 : DDR SDRAM DQ0 - D17 A0 -A12 :DDR SDRAM D0 - D17 RAS : DDR SDRAM D0 - D17 CAS : DDR SDRAM DQ0 - D17 CKE : DDR SDRAM D0 - D8 CKE : DDR SDRAM D9 - D17 WE:DDR SDRAM D0 - D17 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM resistors: 22 Ohms. RESET Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM 2GB, 256M x 72 ECC Module [M312L5720BZ0] (Populated as 2 bank of x4 DDR SDRAM Module) Functional Block Diagram VSS RCS1 RCS0 DQS0 CS DQ0 DQ1 DQ2 DQ3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ8 DQ9 DQ10 DQ11 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ16 DQ17 DQ18 DQ19 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ24 DQ25 DQ26 DQ27 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ32 DQ33 DQ34 DQ35 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ40 DQ41 DQ42 DQ43 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ48 DQ49 DQ50 DQ51 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ56 DQ57 DQ58 DQ59 CS CB0 CB1 CB2 CB3 DQS I/O 3 I/O 2 I/O 1 I/O 0 DM D0 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS9 (DM0) DM CS D18 DQS1 DM D1 DQS I/O 0 I/O 1 I/O 2 I/O 3 D19 D2 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D20 D3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D21 D4 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D22 D5 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D23 D6 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D24 D7 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D25 D8 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D11 DQ28 DQ29 DQ30 DQ31 DQS I/O 0 I/O 1 I/O 2 I/O 3 D12 DQ36 DQ37 DQ38 DQ39 DQS I/O 0 I/O 1 I/O 2 I/O 3 D13 DQ44 DQ45 DQ46 DQ47 DQS I/O 0 I/O 1 I/O 2 I/O 3 D14 DQ52 DQ53 DQ54 DQ55 DQS I/O 0 I/O 1 I/O 2 I/O 3 D15 DQ60 DQ61 DQ62 DQ63 DQS I/O 0 I/O 1 I/O 2 I/O 3 D16 CB4 CB5 CB6 CB7 DQS I/O 0 I/O 1 I/O 2 I/O 3 D17 DQS17 (DM8) DQS8 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS16 (DM7) DQS7 DM DQ20 DQ21 DQ22 DQ23 DQS15 (DM6) DQS6 DM D10 DQS14 (DM5) DQS5 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS13 (DM4) DQS4 DM DQ12 DQ13 DQ14 DQ15 DQS12 (DM3) DQS3 DM D9 DQS11 (DM2) DQS2 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS10 (DM1) DM CS DQ4 DQ5 DQ6 DQ7 D26 WE PCK R E G I S T E R RCS0 RCS1 BA0-BA1: DDR SDRAM D0 - D35 A0-A12: DDR SDRAM D0 - D35 RBA0 - RBA1 RA0 - RA12 DDR SDRAM D0 - D35 RRAS RAS: RCAS RCKE0 CAS: DDR SDRAM D0 - D35 CKE: DDR SDRAM D0 - D17 DDR SDRAM D18 - D35 DDR SDRAM D0 - D35 RCKE1 CKE: RWE WE: CS CS CS CS CS CS CS DM DM DM DM DM DM DM DM DM DQS I/O 3 I/O 2 I/O 1 I/O 0 D27 DQS I/O 3 I/O 2 I/O 1 I/O 0 D28 DQS I/O 3 I/O 2 I/O 1 I/O 0 D29 CS CS CS DQS I/O 3 I/O 2 I/O 1 I/O 0 D30 DQS I/O 3 I/O 2 I/O 1 I/O 0 D31 DQS I/O 3 I/O 2 I/O 1 I/O 0 D32 CS CS CS DQS I/O 3 I/O 2 I/O 1 I/O 0 D33 DQS I/O 3 I/O 2 I/O 1 I/O 0 D34 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS CS CS DM DM DM DM DM DM DM DM DM D35 SPD VDD/VDDQ D0 - D35 SDA WP CS0 CS VDDSPD Serial PD SCL CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1 CS D0 - D35 A0 A1 A2 VREF D0 - D35 SA0 SA1 SA2 VSS D0 - D35 PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. RESET PCK Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD,VDDQ -1.0 ~ 3.6 V TSTG -55 ~ +150 C Power dissipation PD 1.5 * # of component W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Power & DC Operating Conditions (SSTL_2 In/Out) Recommended operating conditions (Voltage referenced to VSS=0V, TA=0 to 70C) Parameter Symbol Min Max Supply voltage(for device with a nominal VDD of 2.5V) VDD 2.3 2.7 I/O Supply voltage VDDQ 2.3 2.7 V I/O Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1 I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V 2 Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V 4 Input logic low voltage VIL(DC) -0.3 VREF-0.15 V 4 Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and CK inputs VID(DC) 0.3 VDDQ+0.6 V II -2 2 uA Output leakage current IOZ -5 5 uA Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9 mA Input leakage current Unit Note 3 Notes : 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled to VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHz. Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM DDR SDRAM IDD spec table M312L6523BZ0 [ (64M x 8) * 9 , 512MB Module ] (VDD=2.7V, T = 10C) Symbol B3 (DDR333@CL=2.5) A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) Unit IDD0 1,880 1,490 1,490 mA IDD1 2,100 1,720 1,720 mA IDD2P 420 350 350 mA IDD2F 1,020 770 770 mA IDD2Q 600 480 480 mA IDD3P 650 570 570 mA IDD3N 1,200 950 950 mA IDD4R 2,370 1,850 1,850 mA IDD4W 2,420 1,900 1,900 mA IDD5 3,000 2,660 2,660 mA IDD6 Normal 420 350 350 mA Low power 410 330 330 mA 4,260 3,560 3,560 mA IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. M312L2923BZ0 [ (64M x 8) * 18 , 1GB Module ] (VDD=2.7V, T = 10C) Symbol B3 (DDR333@CL=2.5) A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) Unit IDD0 2,450 2,190 2,190 mA IDD1 2,680 2,370 2,370 mA mA IDD2P 590 540 540 IDD2F 1,420 1,290 1,290 mA IDD2Q 950 810 810 mA IDD3P 1,040 990 990 mA IDD3N 1,780 1,650 1,650 mA IDD4R 2,810 2,420 2,420 mA IDD4W 3,040 2,550 2,550 mA IDD5 3,580 3,360 3,360 mA IDD6 Normal 590 540 540 mA Low power 560 510 510 mA 4,930 4,170 4,170 mA IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM DDR SDRAM IDD spec table M312L2920BZ0 [ (128M x 4) * 18 , 1GB Module ] (VDD=2.7V, T = 10C) Symbol B3 (DDR333@CL=2.5) A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) Unit IDD0 3,000 2,610 2,610 mA IDD1 3,450 2,970 2,970 mA IDD2P 470 420 420 mA IDD2F 1,290 1,170 1,170 mA IDD2Q 830 690 690 mA IDD3P 920 870 870 mA IDD3N 1,650 1,530 1,530 mA IDD4R 3,720 3,060 3,060 mA IDD4W 4,170 3,330 3,330 mA IDD5 5,250 4,950 4,950 mA IDD6 Normal 670 420 420 mA Low power 430 380 380 mA 7,950 6,570 6,570 mA IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. M312L5720BZ0 [ (128M x 4) * 36, 2GB Module ] (VDD=2.7V, T = 10C) Symbol B3 (DDR333@CL=2.5) A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) Unit IDD0 4,030 3,630 3,630 mA IDD1 4,480 3,990 3,990 mA IDD2P 680 630 630 mA mA IDD2F 1,960 1,830 1,830 IDD2Q 1,400 1,170 1,170 mA IDD3P 1,580 1,530 1,530 mA IDD3N 2,680 2,550 2,550 mA IDD4R 4,750 4,080 4,080 mA IDD4W 5,200 4,350 4,350 mA IDD5 6,280 5,970 5,970 mA 680 630 630 mA IDD6 Normal Low power IDD7A 610 560 560 mA 8,980 7,590 7,590 mA Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM AC Operating Conditions Parameter/Condition Max Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) Input Differential Voltage, CK and CK inputs VID(AC) 0.7 Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 Unit Note V 3 VREF - 0.31 V 3 VDDQ+0.6 V 1 0.5*VDDQ+0.2 V 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. Vtt=0.5*VDDQ RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ Output Load Circuit (SSTL_2) Input/Output Capacitance Parameter (VDD=2.5V, VDDQ=2.5V, TA= 25C, f=1MHz) Symbol M312L6523BZ0, M312L2920BZ0 Min Max Unit Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1 9 11 pF Input capacitance(CKE0) CIN2 9 11 pF Input capacitance( CS0) CIN3 9 11 pF Input capacitance( CLK0, CLK0 ) CIN4 11 12 pF Input capacitance(DM0~DM8) CIN5 10 11 pF Data & DQS input/output capacitance(DQ0~DQ63) Cout1 10 11 pF Data input/output capacitance (CB0~CB7) Cout2 10 11 pF Parameter Symbol M312L2923BZ0, M312L5720BZ0 Min Unit Max Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1 9 11 pF Input capacitance(CKE0,CKE1) CIN2 9 11 pF Input capacitance( CS0, CS1) CIN3 9 11 pF Input capacitance( CLK0, CLK0 ) CIN4 11 12 pF Input capacitance(DM0~DM8) CIN5 13 15 pF Data & DQS input/output capacitance(DQ0~DQ63) Cout1 13 15 pF Data input/output capacitance (CB0~CB7) Cout2 13 15 pF Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM AC Timming Parameters & Specifications Symbol Parameter Row cycle time Refresh row cycle time B3 (DDR333@CL=2.5)) Min Max A2 (DDR266@CL=2) Min Max B0 (DDR266@CL=2.5) Min Max Uni t Note tRC 60 65 65 ns tRFC 72 75 75 ns Row active time tRAS 42 RAS to CAS delay tRCD 18 20 20 ns tRP 18 20 20 ns Row precharge time 70K 45 120K 45 120K ns Row active to Row active tRRD 12 15 15 ns Write recovery time tWR 15 15 15 ns Last data in to Read command tWTR 1 1 1 tCK Col. address to Col. address tCCD 1 1 1 tCK Clock cycle time CL=2.0 CL=2.5 tCK 7.5 12 7.5 12 10 12 ns 6 12 7.5 12 7.5 12 ns Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tDQSCK -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns tAC -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput tDQSQ - 0.4 - 0.5 - 0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRE 0 0 0 ns DQS-in hold time tWPRE 0.25 0.25 0.25 tCK DQS falling edge to CK ris- tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK tDSH 0.2 0.2 0.2 tCK DQS-out access time from Output data access time DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 tCK DQS-in cycle time tDSC 0.9 tIS 0.75 0.9 0.9 ns i,5.7~ Address and Control Input tIH 0.75 0.9 0.9 ns i,5.7~ Address and Control Input tIS 0.8 1.0 1.0 ns i, 6~9 Address and Control Input tIH 0.8 1.0 1.0 ns i, 6~9 Data-out high impedence time from CK/CK tHZ +0.75 ns 1 Data-out low impedence time from CK/CK tLZ -0.7 +0.75 ns 1 Input Slew Rate(for input tSL(I) 0.5 0.5 0.5 V/ 0.5 0.5 0.5 V/ ns tSL(IO) 0.9 +0.7 +0.7 1.1 0.9 +0.75 -0.75 +0.75 -0.75 1.1 3 Address and Control Input Input Slew Rate(for I/O pins) 1.1 12 Output Slew Rate(x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 Output Slew Rate Matching tSLMR 0.67 1.5 0.67 1.5 0.67 1.5 tCK V/ Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free Parameter Symbol B3 (DDR333@CL=2.5)) Min DDR SDRAM A2 (DDR266@CL=2) Max Min B0 (DDR266@CL=2.5) Max Min Unit Note Max Mode register set cycle time tMRD 12 15 15 ns DQ & DM setup time to DQS tDS 0.45 0.5 0.5 ns j, k DQ & DM hold time to DQS tDH 0.45 0.5 0.5 ns j, k Control & Address input tIPW 2.2 2.2 2.2 ns 8 DQ & DM input pulse width tDIPW 1.75 1.75 1.75 ns 8 Power down exit time tPDEX 6 7.5 7.5 ns Exit self refresh to non-Read tXSNR 75 75 75 ns Exit self refresh to read com- tXSRD 200 200 200 tCK Refresh interval time tREFI 7.8 7.8 us 4 - - ns 11 - tCLmin or tCHmin - ns 10, 11 0.75 ns 11 0.6 tCK 2 tCK 13 tQH Clock half period tHP tCLmin or tCHmin - tWPST 0.4 0.6 Active to Read with Auto precharge command tRAP 18 20 20 Autoprecharge write recovery + Precharge time tDAL (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) DQS write postamble time tQHS tCLmin or tCHmin 7.8 Output DQS valid window Data hold skew factor - tHP -tQHS tHP -tQHS tHP -tQHS 0.5 0.75 0.4 0.6 0.4 System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM AC CHARACTERISTICS DDR333 DDR266 DDR200 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX Units Notes DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) DCSLEW TBD TBD TBD TBD 0.5 4.0 V/ns a, m Table 2 : Input Setup & Hold Time Derating for Slew Rate Input Slew Rate tIS tIH Units Notes 0.5 V/ns 0 0 ps i 0.4 V/ns +50 0 ps i 0.3 V/ns +100 0 ps i Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate Input Slew Rate tDS tDH Units 0.5 V/ns 0 0 ps Notes k 0.4 V/ns +75 +75 ps k 0.3 V/ns +150 +150 ps k Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate Delta Slew Rate tDS tDH Units Notes +/- 0.0 V/ns 0 0 ps j +/- 0.25 V/ns +50 +50 ps j +/- 0.5 V/ns +100 +100 ps j Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only) Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h Pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h Table 6 : Output Slew Rate Characteristice (X16 Devices only) Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h Pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h Table 7 : Output Slew Rate Matching Ratio Characteristics AC CHARACTERISTICS DDR333 DDR266 PARAMETER MIN MAX MIN MAX Notes Output Slew Rate Matching Ratio (Pullup to Pulldown) TBD TBD TBD TBD e,m Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1. Test point Output 50 VSSQ Figure 1 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 2. VDDQ 50 Output Test point Figure 2 : Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 C (T Ambient), VDDQ = 2.5V, typical process Minimum : 70 C (T Ambient), VDDQ = 2.3V, slow - slow process Maximum : 0 C (T Ambient), VDDQ = 2.7V, fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotony. Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free Command Truth Table DDR SDRAM (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A0 ~ A9 A11, A12 Note Register Extended MRS H X L L L L OP CODE 1, 2 Register Mode Register Set H X L L L L OP CODE 1, 2 L L L H X L H H H Auto Refresh Refresh Entry Self Refresh Exit H H L L H H X X X Bank Active & Row Addr. H X L L H H V Read & Column Address Auto Precharge Disable H X L H L H V Write & Column Address Auto Precharge Disable H X L H L L V H X L H H L Auto Precharge Enable Auto Precharge Enable Burst Stop Precharge Bank Selection H X Entry H L Exit L H Entry H L Exit L H All Banks Active Power Down Precharge Power Down Mode DM H No operation (NOP) : Not defined H L L H L H X X X L V V V X X X X H X X X L H H H H X X X V V V L X X X X X L H H H 3 X 3 Row Address (A0~A9, A11,A12) L Column Address H L Column Address H X V L X H 4 4 4 4, 6 7 X 5 X X X H 3 3 X 8 9 9 Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM Physical Dimensions: 64Mx72 (M312L6523BZ0) Units : Millimeters 133.35 A 128.95 A 1.27 +/-0.1 2x 3.00 MIN W1 12.00 2x DIA. 2.50 +0.1/-0.00 N 6.35 b a 1 64.77 P2 10.00 B2 19.80 B1 28.575 +/-0.15 B 4x 4.00+/-0.1 V1 92 2.99 MAX 49.53 P3 120.65 P1 93 184 6.35 X 2.175 X1 X2 4.175 D 1.0 +/-0.05 G V 2.50 0.20 +/-0.15 T 3.80 W 1.80 MAX 0.178 Detail A D1 E 1.27 Detail B Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx8 DDR SDRAM, FBGA DDR SDRAM Part No. : K4H510838B-Z***, Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM Physical Dimensions: 128Mx72 (M312L2923BZ0), (M312L2920BZ0) Units : Millimeters 133.35 A 128.95 A 1.27 +/-0.1 2x 3.00 MIN W1 12.00 2x DIA. 2.50 +0.1/-0.00 N 6.35 b a 1 64.77 P2 10.00 B2 19.80 B1 28.575 +/-0.15 B 4x 4.00+/-0.1 V1 92 3.99 MAX 49.53 P3 120.65 P1 93 184 6.35 X 2.175 X1 X2 4.175 D 1.0 +/-0.05 G V 2.50 0.20 +/-0.15 T 3.80 W 1.80 MAX 0.178 Detail A D1 E 1.27 Detail B Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx8, 128Mx4 DDR SDRAM, FBGA DDR SDRAM Part No. : K4H510838B-Z***, K4H510438B-Z*** Revision 1.2 Oct. 2004 512MB, 1GB, 2GB Registered DIMM Pb-Free DDR SDRAM Physical Dimensions: 256Mx72 (M312L5720BZ0) Units : Millimeters 133.35 A 128.95 A 1.27 +/-0.1 2x 3.00 MIN W1 12.0 10.0 1 2x DIA. 2.50 +0.1/-0.00 N 6.35 b a 64.77 P2 10.00 B2 19.80 B1 30.48 +/-0.15 B 4x 4.00+/-0.1 V1 92 3.99 MAX 49.53 P3 120.65 P1 93 184 6.35 X 2.175 X1 X2 4.175 D 1.0 +/-0.05 G V 2.50 0.20 +/-0.15 T 3.80 W 1.80 MAX 0.178 Detail A D1 E 1.27 Detail B Tolerances : 0.005(.13) unless otherwise specified The used device is 128Mx4 DDR SDRAM, FBGA DDR SDRAM Part No : K4H510438B-Z*** Revision 1.2 Oct. 2004