AUIRLR3636
VDSS 60V
RDS(on) typ. 5.4m
ID (Silicon Limited) 99A
max. 6.8m
ID (Package Limited) 50A
Features
Advanced Process Technology
Ultra Low On-Resistance
Logic Level Gate Drive
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
Description
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to
achieve extremely low on-resistance per silicon area. Additional
features of this design are a 175°C junction operating temperature,
fast switching speed and improved repetitive avalanche rating .
These features combine to make this design an extremely efficient
and reliable device for use in Automotive applications and a wide
variety of other applications.
1 2015-11-4
HEXFET® is a registered trademark of Infineon.
*Qualification standards can be found at www.infineon.com
AUTOMOTIVE GRADE
Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 99
A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 70
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited) 50
IDM Pulsed Drain Current 396
PD @TC = 25°C Maximum Power Dissipation 143 W
Linear Derating Factor 0.95 W/°C
VGS Gate-to-Source Voltage ± 16 V
EAS Single Pulse Avalanche Energy (Thermally Limited) 170
mJ
IAR Avalanche Current See Fig. 14, 15, 22a, 22b A
EAR Repetitive Avalanche Energy mJ
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds (1.6mm from case) 300
dv/dt Peak Diode Recovery 22 V/ns
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless
otherwise specified.
Thermal Resistance
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case ––– 1.05
°C/W
RJA Junction-to-Ambient ( PCB Mount) ––– 50
RJA Junction-to-Ambient ––– 110
D-Pak
AUIRLR3636
Base part number Package Type Standard Pack Orderable Part Number
Form Quantity
AUIRLR3636 D-Pak Tube 75 AUIRLR3636
Tape and Reel Left 3000 AUIRLR3636TRL
G D S
Gate Drain Source
S
G
D
HEXFET® Power MOSFET
AUIRLR3636
2 2015-11-4
Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 50A. Note that current
limitations arising from heating of the device leads may occur with some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
Limited by TJmax , starting TJ = 25°C, L = 0.136mH, RG = 25, IAS = 50A, VGS =10V. Part not recommended for use above this value.
ISD 50A, di/dt 1109A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994
Ris measured at TJ approximately 90°C.
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 60 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.07 ––– V/°C Reference to 25°C, ID = 5mA
RDS(on) Static Drain-to-Source On-Resistance ––– 5.4 6.8 mVGS = 10V, ID = 50A
––– 6.6 8.3 VGS = 4.5V, ID = 50A
VGS(th) Gate Threshold Voltage 1.0 ––– 2.5 V VDS = VGS, ID = 100µA
gfs Forward Trans conductance 31 ––– ––– S VDS = 25V, ID = 50A
RG(Int) Internal Gate Resistance ––– 0.6 –––
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 60V, VGS = 0V
––– ––– 250 VDS = 60V,VGS = 0V,TJ =125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 16V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Qg Total Gate Charge ––– 33 49
nC
ID = 50A
Qgs Gate-to-Source Charge ––– 11 ––– VDS = 30V
Qgd Gate-to-Drain Charge ––– 15 ––– VGS = 4.5V
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 18 –––
td(on) Turn-On Delay Time ––– 45 –––
ns
VDD = 39V
tr Rise Time ––– 216 ––– ID = 50A
td(off) Turn-Off Delay Time ––– 43 ––– RG = 7.5
tf Fall Time ––– 69 ––– VGS = 4.5V
Ciss Input Capacitance ––– 3779 –––
pF
VGS = 0V
Coss Output Capacitance ––– 332 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 163 ––– ƒ = 1.0MHz
Coss eff. (ER) Effective Output Capacitance (Energy Related) ––– 437 ––– VGS = 0V, VDS = 0V to 48V
Coss eff. (TR) Effective Output Capacitance (Time Related) ––– 636 ––– VGS = 0V, VDS = 0V to 48V
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 99
A
MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current ––– ––– 396 integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C,IS = 50A,VGS = 0V
trr Reverse Recovery Time ––– 27 ––– ns TJ = 25°C
––– 32 ––– TJ = 125°C
Qrr Reverse Recovery Charge ––– 31 –––
nC TJ = 25°C
––– 43 ––– TJ = 125°C
––– 2.1 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
VR = 51V,
IF = 50A
di/dt = 100A/µs
AUIRLR3636
3 2015-11-4
Fig. 2 Typical Output Characteristics
Fig. 3 Typical Transfer Characteristics
Fig. 1 Typical Output Characteristics
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 4 Normalized On-Resistance vs. Temperature
0.1 110 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM 2.7V
60µs PULSE WIDTH
Tj = 25°C
2.7V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM 2.7V
60µs PULSE WIDTH
Tj = 175°C
2.7V
1234567
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
VDS = 25V
60µs PULSE WIDTH
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 50A
VGS = 10V
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 5 10 15 20 25 30 35 40
QG, Total Gate Charge (nC)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VGS, Gate-to-Source Voltage (V)
VDS= 48V
VDS= 30V
VDS= 12V
ID= 50A
AUIRLR3636
4 2015-11-4
Fig 8. Maximum Safe Operating Area
Fig. 7 Typical Source-to-Drain Diode Forward Voltage
Fig 10. Drain-to-Source Breakdown Voltage
Fig. 9 Maximum Drain Current vs. Case Temperature
Fig 12. Maximum Avalanche Energy vs. Drain Current
Fig. 11 Typical COSS Stored Energy
0.1 0.4 0.7 1 1.3 1.6 1.9
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA LIMITED BY R
DS(on)
Tc = 25°C
Tj = 175°C
Single Pulse
100µsec
1msec
10msec
DC
LIMITED BY PACKAGE
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
10
20
30
40
50
60
70
80
90
100
110
ID, Drain Current (A)
Limited By Package
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Temperature ( °C )
50
55
60
65
70
75
80
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 5mA
0 5 10 15 20 25 30 35 40 45 50 55 60 65
VDS, Drain-to-Source Voltage (V)
0.0
0.2
0.4
0.6
0.8
Energy (µJ)
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
700
800
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 5.69A
10.64A
BOTTOM 50A
AUIRLR3636
5 2015-11-4
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.infineon.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 13, 14).
t
av = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
Z
thJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 15. Maximum Avalanche Energy Vs. Temperature
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
Thermal Response ( Z thJC ) °C/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) i (sec)
0.02028 0.000011
0.49179 0.001393
0.24336 0.00725
0.29406 0.000158
J
J
1
1
2
2
3
3
R
1
R
1
R
2
R
2
R
3
R
3
Ci= iRi
Ci= iRi
C
C
4
4
R
4
R
4
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
50
100
150
200
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 50A
Fig 14. Typical Avalanche Current Vs. Pulse width
AUIRLR3636
6 2015-11-4
Fig 16. Threshold Voltage vs. Temperature
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VGS(th), Gate threshold Voltage (V)
ID = 100µA
ID = 250µA
ID = 1.0mA
ID = 1.0A
0200 400 600 800 1000
diF /dt (A/µs)
0
2
4
6
8
10
12
14
IRRM (A)
IF = 20A
VR = 51V
TJ = 25°C
TJ = 125°C
Fig. 17 - Typical Recovery Current vs. dif/dt
0200 400 600 800 1000
diF /dt (A/µs)
0
2
4
6
8
10
12
14
16
IRRM (A)
IF = 30A
VR = 51V
TJ = 25°C
TJ = 125°C
0200 400 600 800 1000
diF /dt (A/µs)
0
50
100
150
200
250
300
350
QRR (nC)
IF = 20A
VR = 51V
TJ = 25°C
TJ = 125°C
0200 400 600 800 1000
diF /dt (A/µs)
0
50
100
150
200
250
300
350
QRR (nC)
IF = 30A
VR = 51V
TJ = 25°C
TJ = 125°C
AUIRLR3636
7 2015-11-4
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Fig 22a. Unclamped Inductive Test Circuit
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
Fig 22b. Unclamped Inductive Waveforms
tp
V
(BR)DSS
I
AS
Fig 24b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 24a. Gate Charge Test Circuit
AUIRLR3636
8 2015-11-4
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches))
YWWA
XX XX
Date Code
Y= Year
WW= Work Week
AULR3636
Lot Code
Part Number
IR Logo
D-Pak (TO-252AA) Part Marking Information
AUIRLR3636
9 2015-11-4
D-Pak (TO-252AA) Tape & Reel Information (Dimensions are shown in millimeters (inches))
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
TRR TRL
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
AUIRLR3636
10 2015-11-4
Qualification Information
Qualification Level
Automotive
(per AEC-Q101)
Comments: This part number(s) passed Automotive qualification. Infineon’s
Industrial and Consumer qualification level is granted by extension of the higher
Automotive level.
Moisture Sensitivity Level D-Pak MSL1
ESD
Machine Model Class M4 (+/- 600V)†
AEC-Q101-002
Human Body Model Class H1C (+/- 2000V)†
AEC-Q101-001
Charged Device Model Class C5 (+/- 2000V)†
AEC-Q101-005
RoHS Compliant Yes
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
Revision History
Date Comments
11/4/2015 Updated datasheet with corporate template
Corrected ordering table on page 1.
3/18/2014 Added "Logic Level Gate Drive" bullet in the features section on page 1
Updated data sheet with new IR corporate template
4/9/2014 Updated package outline on page 8.
Updated typo on the fig.19 and fig.20, unit of y-axis from "A" to "nC" on page 6.
† Highest passing voltage.
