8XC152JA/JB/JC/JD UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER X 8K Factory Mask Programmable ROM Available Y Superset of 80C51 Architecture Y 64KB Data Memory Addressing Y Multi-Protocol Serial Communication I/O Port (2.048 Mbps/2.4 Mbps Max) SDLC/HDLC Only CSMA/CD and SDLC/HDLC User Definable Protocols Y 256 Bytes On-Chip RAM Y Dual On-Chip DMA Channels Y Hold/Hold Acknowledge Y Two General Purpose Timer/Counters Y Full Duplex/Half Duplex Y 5 or 7 I/O Ports Y MCSE-51 Compatible UART Y 56 Special Function Registers Y 16.5 MHz Maximum Clock Frequency Y 11 Interrupt Sources Y Multiple Power Conservation Modes Y Y 64KB Program Memory Addressing Available in 48 Pin Dual-in-Line Package and 68 Pin Surface Mount PLCC Package (See Packaging Spec. Order Y231369) The 80C152, which is based on the MCSE-51 CPU, is a highly integrated single-chip 8-bit microcontroller designed for cost-sensitive, high-speed, serial communications. It is well suited for implementing Integrated Services Digital Networks (ISDN), emerging Local Area Networks, and user defined serial backplane applications. In addition to the multi-protocol communication capability, the 80C152 offers traditional microcontroller features for peripheral I/O interface and control. Silicon implementations are much more cost effective than multi-wire cables found in board level parallel-toserial and serial-to-parallel converters. The 83C152 contains, in silicon, all the features needed for the serialto-parallel conversion. Other 83C152 benefits include: 1) better noise immunity through differential signaling or fiber optic connections, 2) data integrity utilizing the standard, designed in CRC checks, and 3) better modularity of hardware and software designs. All of thesecost, network parameter and real estate improvements apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board. *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT (c) INTEL CORPORATION, 1995 October 1989 Order Number: 270431-003 8XC152JA/JB/JC/JD 270431 - 2 270431 - 1 270431 - 3 Figure 1. Connection Diagrams 2 8XC152JA/JB/JC/JD *On 80C152JB/JD Only 270431 - 18 Figure 2. Block Diagram 3 8XC152JA/JB/JC/JD EPSEN is used in conjunction with Port 5 and Port 6 program memory operations. EPSEN functions like PSEN during program memory operation, but supports Port 5 and Port 6. EPSEN is the read strobe to external program memory for Port 5 and Port 6. EPSEN is activated twice during each machine cycle unless an external data memory operation occurs on Port(s) 0 and Port 2. When external data memory is accessed the second activation of EPSEN is skipped, which is the same as when using PSEN. Note that data memory fetches cannot be made through Ports 5 and 6. 80C152JB/JD General Description The 80C152JB/JD is a ROMless extension of the 80C152 Universal Communication controller. The 80C152JB has the same five 8-bit I/O ports of the 80C152, plus an additional two 8-bit I/O ports, Port 5 and Port 6. The 80C152JB/JD also has two additional control pins, EBEN (EPROM Bus ENable), and EPSEN (EPROM bus Program Store ENable). EBEN selects the functionality of Port 5 and Port 6. When EBEN is low, these ports are strictly I/O, similar to Port 4. The SFR location for Port 5 is 91H and Port 6 is 0A1H. This means Port 5 and Port 6 are not bit addressable. With EBEN low, all program memory fetches take place via Port 0 and Port 2. (The 80C152 is a ROMless only product). When EBEN is high, Port 5 and Port 6 form an address/data bus called the E-Bus (EPROM-Bus) for program memory operations. When EBEN is high and EA is low, all program memory operations take place via Ports 5 and 6. The high byte of the address goes out on Port 6, and the low byte is output on Port 5. ALE is still used to latch the address on Port 5. Next, the op code is read on Port 5. The timing is the same as when using Ports 0 and 2 for external program memory operations. Table 1. Program Memory Fetches EBEN EA Program Fetch via PSEN EPSEN 0 0 P0, P2 Active Inactive 0 1 N/A N/A N/A 1 0 P5, P6 Inactive Active 1 1 P5, P6 P0, P2 Inactive Active Active Inactive Comments Addresses 0 - 0FFFFH Invalid Combination Addresses 0 - 0FFFFH Addresses 0 - 1FFFH Addresses t 2000H Table 2. 8XC152 Product Differences ROMless Version 80C152JA 80C152JB 80C152JC 80C152JD CSMA/CD and HDLC/SDLC HDLC/SDLC Only * * PLCC and DIP *(83C152JA) * *(83C152JC) * PLCC Only 5 I/O Ports 7 I/0 Ports * * * * NOTES: * e options available 0 standard frequency range 3.5 MHz to 12 MHz 0 ``b1'' frequency range 3.5 MHz to 16.5 MHz 4 ROM Version Available * * * * 8XC152JA/JB/JC/JD DIP Pin Y PLCC(1) Pin Description 48 2 VCCSupply voltage. 24 18-21, 25-28 3,33(2) 27-30, 34-37 VSSCircuit ground. Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program memory if EBEN is pulled low. During accesses to external Data Memory, Port 0 always emits the low-order address byte and serves as the multiplexed data bus. In these applications it uses strong internal pullups when emitting 1s. Port 0 also outputs the code bytes during program verification. External pullups are required during program verification. 1-8 4-11 Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the internal pullups. Port 1 also serves the functions of various special features of the 8XC152, as listed below: Pin P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 29-36 41-48 10- 17 14-16, 18, 19, 23-25 Name GRXD GTXD DEN TXC RXC HLD HLDA Alternate Function GSC data input pin GSC data output pin GSC enable signal for an external driver GSC input pin for external transmit clock GSC input pin for external receive clock DMA hold input/output DMA hold acknowledge input/output Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory if EBEN is pulled low. During accesses to external Data Memory that use 16bit addresses (MOVX @ DPTR and DMA operations), Port 2 emits the high-order address byte. In these applications it uses strong internal pullups when emitting 1s. During accesses to external Data Memory that use 8-bit addresses (MOVX @ Ri), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits during program verification. Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the pullups. Port 3 also serves the functions of various special features of the MCS-51 Family, as listed below: Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Name RXD TXD INT0 INT1 T0 T1 WR RD Alternate Function Serial input line Serial output line External Interrupt 0 External Interrupt 1 Timer 0 external input Timer 1 external input External Data Memory Write strobe External Data Memory Read strobe 5 8XC152JA/JB/JC/JD Pin Description (Continued) Pin Y 6 Pin Description 47-40 65-58 Port 4Port 4 is an 8-bit bidirectional I/O port with internal pullups. Port 4 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 4 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the internal pullups. In addition, Port 4 also receives the low-order address bytes during program verification. RSTReset input. A logic low on this pin for three machine cycles while the oscillator is running resets the device. An internal pullup resistor permits a power-on reset to be generated using only an external capacitor to VSS. Although the GSC recognizes the reset after three machine cycles, data may continue to be transmitted for up to 4 machine cycles after Reset is first applied. 9 13 38 55 37 54 39 56 23 32 22 N/A 31 17, 20 21, 22 38, 39 40, 49 XTAL2Output from the inverting oscillator amplifier. Port 5Port 5 is an 8-bit bidirectional I/O port with internal pullups. Port 5 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 5 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the internal pullups. Port 5 is also the multiplexed low-order address and data bus during accesses to external program memory if EBEN is pulled high. In this application it uses strong pullups when emitting 1s. N/A 67, 66 52, 57 50, 68 1, 51 Port 6Port 6 is an 8-bit bidirectional I/O port with internal pullups. Port 6 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 6 pins that are externally pulled low will source current (IIL, on the data sheet) because of the internal pullups. Port 6 emits the high-order address byte during fetches from external Program Memory if EBEN is pulled high. In this application it uses strong pullups when emitting 1s. N/A 12 EBENE-Bus Enable input that designates whether program memory fetches take place via Ports 0 and 2 or Ports 5 and 6. Table 1 shows how the ports are used in conjunction with EBEN. N/A 53 EPSENE-bus Program Store Enable is the Read strobe to external program memory when EBEN is high. Table 2 shows when EPSEN is used relative to PSEN depending on the status of EBEN and EA. ALEAddress Latch Enable output signal for latching the low byte of the address during accesses to external memory. In normal operation ALE is emitted at a constant rate of (/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. While in Reset, ALE remains at a constant high level. PSENProgram Store Enable is the Read strobe to External Program Memory. When the 8XC152 is executing from external program memory, PSEN is active (low). When the device is executing code from External Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to External Data Memory. While in Reset, PSEN remains at a constant high level. EAExternal Access enable. EA must be externally pulled low in order to enable the 8XC152 to fetch code from External Program Memory locations 0000H to 0FFFH. EA must be connected to VCC for internal program execution. XTAL1Input to the inverting oscillator amplifier and input to the internal clock generating circuits. 8XC152JA/JB/JC/JD OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 3. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the Data Sheet must be observed. 270431 - 6 Figure 4. External Clock Drive IDLE MODE An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF. In Idle Mode, the CPU puts itself to sleep while most of the on-chip peripherals remain active. The major peripherals that do not remain active during Idle, are the DMA channels. The Idle Mode is invoked by software. The content of the on-chip RAM and all the Special Function Registers remain unchanged during this mode. The Idle Mode can be terminated by any enabled interrupt or by a hardware reset. POWER DOWN MODE In Power Down Mode, the oscillator is stopped and all on-chip functions cease except that the on-chip RAM contents are maintained. The mode Power Down is invoked by software. The Power Down Mode can be terminated only by a hardware reset. 270431 - 5 Figure 3. Using the On-Chip Oscillator Table 3. Status of the External Pins During Idle and Power Down Modes 80C152JA/83C152JA/80C152JC/83C152JC Mode Program Memory ALE PSEN Port 0 Port 1 Port 2 Port 3 Port 4 Idle Internal 1 1 Data Data Data Data Data Idle External 1 1 Float Data Address Data Data Power Down Internal 0 0 Data Data Data Data Data Power Down External 0 0 Float Data Data Data Data 80C152JB/80C152JD Mode Instruction ALE PSEN EPSEN Port 0 Port 1 Bus Port 2 Port 3 Port 4 Port 5 Port 6 Idle P0, P2 1 1 1 Float Data Address Data Data 0FFH Idle P5, P6 1 1 1 Data Data Data Data Data 0FFH Address 0FFH Power Down P0, P2 0 0 1 Float Data Data Data Data 0FFH 0FFH Power Down P5, P6 0 1 0 Data Data Data Data Data 0FFH 0FFH NOTE: For more detailed information on the reduced power modes refer to the Embedded Controller Handbook, and Application Note AP-252, ``Designing with the 80C51BH.'' Note difference of logic level of PSEN during Power Down for ROM JA/JC and ROM emulation mode for JC/JD. 7 8XC152JA/JB/JC/JD ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias AAAA0 C to a 70 C Storage Temperature AAAAAAAAAA b 65 C to a 150 C Voltage on Any pin to VSS AA b 0.5V to (VCC a 0.5V) Voltage on VCC to VSSAAAAAAAAAAA b 0.5V to a 6.5V Power Dissipation AAAAAAAAAAAAAAAAAAAAAAA1.0W(9) D.C. CHARACTERISTICS Symbol NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability. (TA e 0 C to a 70 C; VCC e 5V g 10%; VSS e 0V) Parameter Min Typ (Note 3) Max Unit Test Conditions VIL Input Low Voltage (All Except EA, EBEN) b 0.5 0.2VCC b 0.1 V VIL1 Input Low Voltage (EA, EBEN) b 0.5 0.2VCC b 0.3 V VIH Input High Voltage (Except XTAL1, RST) 0.2VCC a 0.9 VCC a 0.5 V VIH1 Input High Voltage (XTAL1, RST) 0.7VCC VCC a 0.5 V VOL Output Low Voltage (Ports 1, 2, 3, 4, 5, 6) 0.45 V IOL e 1.6 mA (Note 4) VOL1 Output Low Voltage (Port 0, ALE, PSEN, EPSEN) 0.45 V IOL e 3.2 mA (Note 4) VOH Output High Voltage (Ports 1, 2, 3, 4, 5, 6 COMM9 ALE, PSEN, EPSEN) 2.4 V IOH e b 60 mA VCC e 5V g 10% 0.9VCC V IOH e b 10 mA 2.4 V IOH e b 400 mA VCC e 5V g 10% 0.9VCC V IOH e b 40 mA (Note 5) b 50 mA VIN e 0.45V b 650 mA VIN e 2V g 10 mA 0.45 k VIN k VCC VOH1 Output High Voltage (Port 0 in External Bus Mode) IIL Logical 0 Input Current (Ports 1, 2, 3, 4, 5, 6) ITL Logical 1 to 0 Transition Current (Ports 1, 2, 3, 4, 5, 6) ILI Input Leakage (Port 0, EA) RRST Reset Pullup Resistor IIH Logical 1 Input Current (EBEN) ICC Power Supply Current : Active (16.5 MHz) Idle (16.5 MHz) Power Down Mode 8 40 kX 31 8 10 a 60 mA 41.1 15.4 mA (Note 6) mA (Note 6) mA VCC e 2.0V to 5.5V 8XC152JA/JB/JC/JD MAX Icc (ACTIVE) e (2.24 c FREQ) a 4.16 (Note 6) MAX Icc (IDLE) e (0.8 c FREQ) a 2.2 (Note 6) 270431 - 7 Figure 5. ICC vs Frequency EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters. The first character is always a `T' (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address. C: Clock D: Input data. H: Logic level HIGH. I: Instruction (program memory contents). L: Logic level LOW, or ALE. P: Q: R: T: V: W: X: Z: PSEN. Output data. READ signal. Time. Valid. WRITE signal. No longer a valid logic level. Float. For example, TAVLL e Time for Address Valid to ALE Low. TLLPL e Time for ALE Low to PSEN Low. 9 8XC152JA/JB/JC/JD A.C. CHARACTERISTICS (TA e 0 C to a 70 C; VCC e 5V g 10%; VSS e 0V; Load Capacitance for Port 0, ALE, and PSEN e 100 pF; Load Capacitance for All Other Outputs e 80 pF) EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS Symbol Parameter 1/TCLCL Oscillator Frequency 80C152JA/JC 83C152JA/JC 80C152JB/JD 80C152JA/JC-1 83C152JA/JC-1 80C152JB/JD-1 ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Address to Valid Instruction In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After RD Data Float After RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low Address to RD or WR Low Data Valid to WR Transition Data Hold After WR RD Low to Address Float RD or WR High to ALE High TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX(8) TWHQX TRLAZ TWHLH 10 16.5 MHz Min Max 81 5 25 MHz 3.5 16.5 MHz 4TCLCL-100 ns ns ns ns 3TCLCL-105 ns ns ns 2TCLCL-40 TCLCL-55 TCLCL-35 142 20 137 TCLCL-40 3TCLCL-45 77 0 0 Unit ns 35 TCLCL-25 ns 198 5TCLCL-105 ns 10 10 ns 5TCLCL-165 ns ns ns 51 335 2TCLCL-70 8TCLCL-150 ns ns ns 380 9TCLCL-165 ns 3TCLCL a 50 ns 263 263 6TCLCL-100 6TCLCL-100 138 0 132 (Note 7, 10) Variable Oscillator Min Max 3.5 12 0 232 3TCLCL-50 112 4TCLCL-130 ns 196 6TCLCL-167 ns 10 TCLCL-50 0 20 100 TCLCL-40 0 ns ns TCLCL a 40 ns 8XC152JA/JB/JC/JD EXTERNAL PROGRAM MEMORY READ CYCLE 270431 - 8 EXTERNAL DATA MEMORY READ CYCLE 270431 - 9 11 8XC152JA/JB/JC/JD EXTERNAL DATA MEMORY WRITE CYCLE 270431 - 10 EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency 3.5 16.5 MHz TCHCX High Time 20 TCLCX Low Time 20 TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns ns ns EXTERNAL CLOCK DRIVE WAVEFORM 270431 - 11 12 8XC152JA/JB/JC/JD LOCAL SERIAL CHANNEL TIMINGSHIFT REGISTER MODE Symbol Parameter 16.5 MHz Min Variable Oscillator Max Min Units Max TXLXL Serial Port Clock Cycle Time 727 12TCLCL ns TQVXH Output Data Setup to Clock Rising Edge 473 10TCLCL-133 ns TXHQX Output Data Hold After Clock Rising Edge 4 2TCLCL-117 ns TXHDX Input Data Hold After Clock Rising Edge 0 0 ns TXHDV Clock Rising Edge to Input Data Valid 473 10TCLCL-133 ns SHIFT REGISTER MODE TIMING WAVEFORMS 270431 - 12 A.C. TESTING: INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORM 270431 - 13 AC Inputs During Testing are Driven at VCC b 0.5 for a Logic ``1'' and 0.45V for a Logic ``0''. Timing Measurements are made at VIH Min for a Logic ``1'' and VIL Max for a Logic ``0''. 270431 - 14 For Timing Purposes a Port Pin is no Longer Floating when a 100 mV change from Load Voltage Occurs, and Begins to Float when a 100 mV change from the Loaded VOH/VOL Level occurs IOL/IOH t g 20 mA. 13 8XC152JA/JB/JC/JD GLOBAL SERIAL PORT TIMINGSInternal Baud Rate Generator Symbol Parameter 16.5 MHz (BAUD e 0) Min Max Variable Oscillator Min Unit Max HBTJR Allowable jitter on the Receiver for (/2 bit time (Manchester encoding only) 0.0375 (0.125 c (BAUD a 1) c 8TCLCL) b 25 ns ms FBTJR Allowable jitter on the Receiver for one full bit time (NRZI and Manchester) 0.10 (0.25 c (BAUD a 1) c 8TCLCL) b 25 ns ms HBTJT Jitter of data from Transmitter for (/2 bit time (Manchester encoding only) g 10 g 10 ns FBTJT Jitter of data from Transmitter for one full bit time (NRZI and Manchester) g 10 g 10 ns DRTR Data rise time for Receiver(11) 20 20 ns DFTR Data fall time for Receiver(12) 20 20 ns GSC RECEIVER TIMINGS (INTERNAL BAUD RATE GENERATOR) 270431 - 15 14 8XC152JA/JB/JC/JD GSC TRANSMIT TIMINGS (INTERNAL BAUD RATE GENERATOR) 270431 - 16 GLOBAL SERIAL PORT TIMINGSExternal Clock Symbol Parameter 16.5 MHz Min Variable Oscillator Max Min Max 2.4 0.009 FOSC c 0.145 Unit 1/ECBT GSC Frequency with an External Clock ECH External Clock High 170 2TCLCL a 45 ns ns ECL(13) External Clock Low 170 2TCLCL a 45 ns ns ECRT External Clock Rise Time(11) 20 20 ns ECFT External Clock Fall Time(12) 20 20 ns ECDVT External Clock to Data Valid Out - Transmit (to External Clock Negative Edge) 150 150 ECDHT External Clock Data Hold - Transmit (to External Clock Negative Edge) MHz ns ns 0 0 ECDSR External Clock Data Set-up - Receiver (to External Clock Positive Edge) 45 45 ns ECDHR External Clock to Data Hold - Receiver (to External Clock Positive Edge) 50 50 ns 15 8XC152JA/JB/JC/JD GSC TIMINGS (EXTERNAL CLOCK) 270431 - 17 NOTES: 1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications. 2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices. 3. ``Typicals'' are based on samples taken from early manufacturing lots and are not guaranteed. The measurements were made with VCC e 5V at room temperature. 4. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1to-0 transitions during bus operations. In the worst cases (capacitive loading l 100 pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 5. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 6. ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL e 5 ns, VIL e VSS a 0.5V, VIH e VCC b 0.5V; XTAL2 N.C.; Port 0 pins connected to VCC. ``Operating'' current is measured with EA connected to VCC and RST connected to VSS. ``Idle'' current is measured with EA connected to VSS, RST connected to VCC and GSC inactive. 7. The specifications relating to external data memory characteristics are also applicable to DMA operations. 8. TQVWX should not be confused with TQVWX as specified for 80C51BH. On 80C152, TQVWX is measured from data valid to rising edge of WR. On 80C51BH, TQVWX is measured from data valid to falling edge of WR. See timing diagrams. 9. This value is based on the maximum allowable die temperature and the thermal resistance of the package. 10. All specifications relating to external program memory characteristics are applicable to: EPSEN for PSEN Port 5 for Port 0 Port 6 for Port 2 when EBEN is at a Logical 1 on the 80C152JB/JD. 11. Same as TCLCH, use External Clock Drive Waveform. 12. Same as TCHCL, use External Clock Drive Waveform. 13. When using the same external clock to drive both the receiver and transmitter, the minimum ECL spec effectively becomes 195 ns at all frequencies (assuming 0 ns propagation delay) because ECDVT (150 ns) plus ECDSR (45 ns) requirements must also be met (150 a 45 e 195 ns). The 195 ns requirement would also increase to include the maximum propagation delay between receivers and transmitters. 16 8XC152JA/JB/JC/JD DESIGN NOTES Within the 8XC152 there exists a race condition that may set both the RDN and AE bits at the end of a valid reception. This will not cause a problem in the application as long as the following steps are followed: Never give the receive error interrupt a higher priority than the valid reception interrupt Do not leave the valid reception interrupt service routine when AE is set by using a RETI instruction until AE is cleared. To clear AE set the GREN bit, this enables the receiver. If the user desires that the receiver remain disabled, clear GREN after setting it before leaving the interrupt service routine. If the AE bit is checked by user software in response to a valid reception interrupt, the status of AE should be considered invalid. The race condition is dependent upon both the temperature that the device is currently operating at and the processing the device received during the wafer fabrication. When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. DATA SHEET REVISION SUMMARY The following represent the key differences between the ``-003'' and the ``-002'' version of the 80C152/83C152 data sheet. Please review this summary carefully. 1. Removed minimum GSC frequency spec when used with an external clock. 2. Change figure ``External Program Memory Read Cycle'' to show Port 0/Port 5 address floating after PSEN goes low. 3. Added design note on terminating idle with reset. 4. Added status of PSEN during Power Down mode to Table 3. 5. Moved all notes to back of data sheet. 6. Changed microcomputer to microcontroller. 7. Added External Oscillator start-up capacitance note. The following represent the key differences between the ``-002'' and the ``-001'' version of the 80C152/ 83C152 data sheet. Please review this summary carefully. 1. Status of data sheet changed from ``ADVANCED'' to ``PRELIMINARY''. 2. 80C152JC, 83C152JC, and 80C152JD were added. 3. Added AE/RDN design note. 4. This revision summary was added. 5. Note Y13 was added (Effective ECL spec at higher clock rates). 6. Table Y2 changed to Table Y3 (Status of pins during Idle/Power Down). 7. Current Table Y2 was added (JA vs. JB vs. JC vs. JD matrix). 8. Transmit jitter spec changed from g 35 ns and g 70 ns to g 10 ns. 17