LTC5583
1
5583fa
TYPICAL APPLICATION
FEATURES DESCRIPTION
Matched Dual-Channel
6GHz RMS Power Detector
The LTC
®
5583 is a dual-channel RMS power detector,
capable of measuring two AC signals with wide dynamic
range, from –59dBm to 4dBm, depending on frequency.
Each AC signal’s power in decibel-scaled value is precisely
converted to a DC voltage on a linear scale, independent
of the crest factor of the input signal waveforms. The
LTC5583 is suitable for precision power measurement and
level control for a variety of RF standards, including LTE,
EDGE, W-CDMA, CDMA2000, TD-SCDMA, and WiMAX.
Good channel-to-channel isolation is necessary for oper-
ating the dual channels simultaneously. For applications
where the two input signals are at the same frequency (e.g.
measuring VSWR), the LTC5583 provides 40dB isolation
at 2.14GHz even with single-ended inputs. No baluns are
needed. When the two input signals are at different frequen-
cies, the isolation can be as high as 50dB. The isolation
can be improved to >55dB with differential inputs.
The power difference of the two input signals is provided
at a difference output pin. Each channel also has a fast
envelope detector, which tracks the RF input signal’s en-
velope and outputs a voltage directly proportional to the
signal’s instantaneous power. The envelope detectors can
be disabled to reduce power consumption.
APPLICATIONS
n Frequency Range: 40MHz to 6GHz
n Linear Dynamic Range: Up to 60dB
n ±0.5dB (Typ) Accuracy Over Temperature
n 40dB Channel-to-Channel Isolation at 2GHz Even
with Single-Ended RF Inputs
n Matched Dual-Channel Outputs: <1.25dB (Typ)
n Single-Ended RF Inputs—No Transformer Required
n Accurate RMS Power Measurement of High Crest
Factor Modulated Waveforms
n Difference Output Provides VSWR Measurement
n Fast Envelope Detector Outputs
n Fast Response Time: 140ns Rise Time
n Small 4mm × 4mm QFN24 Package
n VSWR Monitor
n MIMO Transmit Power Control
n Basestation PA Control
n Transmit and Receive Gain Control
n RF Instrumentation
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 7262661, 7317357, 7622981.
5583 BD
LTC5583
ENVA
IN+AIN
–A
IN+BIN
–B
ENVELOPE
DETECT
RMS
DETECT
ENVB
ENVELOPE
DETECT
RMS
DETECT
INV
VOA
VODF
VOB
VOS
–
+
DIFFERENCE
AMPLIFIER
INPUT POWER (dBm)
–65
0
VOA, VOB (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 TA01b
5
85°C, CH A
85°C, CH B
25°C, CH A
25°C, CH B
–40°C, CH A
–40°C, CH B
Output Voltage and Linearity Error
vs RF Input Power, 2140MHz CW
Inputs, Single-Ended Drive
Block Diagram
LTC5583
2
5583fa
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Supply Voltage .........................................................3.8V
Enable Voltage .................................–0.3V to VCC + 0.3V
VOS Voltage ......................................–0.3V to VCC + 0.3V
INV Voltage ............................................... –0.3V to 3.6V
Input Signal Power (Single-Ended, 50) .............18dBm
Input Signal Power (Differential, 50) .................24dBm
TJMAX .................................................................... 125°C
Operating Temperature Range .................–40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
(Note 1)
24 23 22 21 20 19
7 8 9
TOP VIEW
25
GND
UF PACKAGE
24-LEAD (4mm s 4mm) PLASTIC QFN
10 11 12
6
5
4
3
2
1
13
14
15
16
17
18
DECA
VCCA
VCCR
EN
VCCB
DECB
VOA
RT1
VODF
VOS
RT2
VOB
IN+A
IN–A
RP1
FLTA
ENVA
VCCN
IN+B
IN–B
RP2
FLTB
ENVB
INV
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC5583IUF#PBF LTC5583IUF#TRPBF 5583 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC5583
3
5583fa
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, –40°C to 85°C, otherwise specifications are at TA = 25°C, VCC = 3.3V, EN = 3.3V. Test circuits are shown in
Figures 1 and 2 (Note 2).
PARAMETER CONDITIONS MIN TYP MAX UNITS
AC Input
Input Frequency Range (Note 4) 40 to 6000 MHz
Input Impedance Differential 400//0.5 Ω//pF
fRF = 450MHz (Single-Ended Inputs)
Linear Dynamic Range CW, 50, ±1dB Linearity Error (Note 5) 63 dB
l57 dB
RF Input Power Range CW, 50Ω, ±1dB Linearity Error (Note 5) –59 to 4 dBm
Output Slope 29.6 mV/dB
Logarithmic Intercept (Note 3) –78.5 dBm
Deviation from CW Response 11dB Peak to Average Ratio (3-Carrier CDMA2K)
12dB Peak to Average Ratio (4-Carrier WCDMA)
0.7
0.4
dB
dB
Input A to Input B Isolation Single-Ended Inputs 77 dB
lnput A to Output B Isolation
Input B to Output A Isolation
Single-Ended Inputs Frequency Separation = 0Hz
(Notes 6, 7) Frequency Separation = 1MHz
Frequency Separation = 10MHz
50
>55
>55
dB
dB
dB
fRF = 880MHz (Single-Ended Inputs)
Linear Dynamic Range CW, 50, ±1dB Linearity Error (Note 5) 61 dB
l56 dB
RF Input Power Range CW, 50Ω, ±1dB Linearity Error (Note 5) –58 to 3 dBm
Output Slope 29.7 mV/dB
Logarithmic Intercept (Note 3) –77.8 dBm
Deviation from CW Response 11dB Peak to Average Ratio (3-Carrier CDMA2K)
12dB Peak to Average Ratio (4-Carrier WCDMA)
0.7
0.4
dB
dB
Input A to Input B Isolation Single-Ended inputs 68 dB
Input A to Output B Isolation
Input B to Output A Isolation
Single-Ended inputs Frequency Separation = 0Hz
(Notes 6, 7) Frequency Separation = 1MHz
Frequency Separation = 10MHz
41
52
51
dB
dB
dB
fRF = 2140MHz (Single-Ended Inputs)
Linear Dynamic Range CW, 50, ±1dB Linearity Error (Note 5) 50 60 dB
l55 dB
RF Input Power Range CW, 50Ω, ±1dB Linearity Error (Note 5) –58 to 2 dBm
Output Slope 26 29.6 34 mV/dB
Logarithmic Intercept (Note 3) –90 –77.4 –64 dBm
Channel Mismatch Input Power = 0dBm to Both Channels <1.25 dB
Deviation from CW Response 11dB Peak to Average Ratio (3-Carrier CDMA2K)
12dB Peak to Average Ratio (4- Carrier WCDMA)
0.6
0.3
dB
dB
Input A to Input B Isolation Single-Ended Inputs 54 dB
Input A to Output B Isolation
Input B to Output A Isolation
Single-Ended Inputs Frequency Separation = 0Hz
(Notes 6, 7) Frequency Separation = 1MHz
Frequency Separation = 10MHz
40
52
51
dB
dB
dB
Differential Inputs Frequency Separation = 0Hz
(Notes 6, 7) Frequency Separation = 1MHz
Frequency Separation = 10MHz
>55
>55
>55
dB
dB
dB
LTC5583
4
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PARAMETER CONDITIONS MIN TYP MAX UNITS
fRF = 2700MHz (Single-Ended Inputs)
Linear Dynamic Range CW, 50, ±1dB Linearity Error (Note 5) 59 dB
l52 dB
RF Input Power Range CW, 50Ω, ±1dB Linearity Error (Note 5) –56 to 3 dBm
Output Slope 30.0 mV/dB
Logarithmic Intercept (Note 3) –74.9 dBm
Deviation from CW Response 12dB Peak to Average Ratio (WiMAX OFDM) 0.6 dB
Input A to Input B Isolation Single-Ended Inputs 52 dB
lnput A to Output B Isolation
Input B to Output A Isolation
Singled-Ended Inputs Frequency Separation = 0Hz
(Notes 6, 7) Frequency separation = 1MHz
Frequency separation = 10MHz
33
45
44
dB
dB
dB
Differential Inputs Frequency Separation = 0Hz
(Notes 6, 7) Frequency separation = 1MHz
Frequency separation = 10MHz
50
>55
>55
dB
dB
dB
fRF = 3600MHz (Differential Inputs)
Linear Dynamic Range CW, 50, ±1dB Linearity Error (Note 5) 56 dB
l49 dB
RF Input Power Range CW, 50Ω, ±1dB Linearity Error (Note 5) –53 to 3 dBm
Output Slope 30.2 mV/dB
Logarithmic Intercept (Note 3) –73.1 dBm
Deviation from CW Response 12dB Peak to Average Ratio (WiMAX OFDM) 0.4 dB
Input A to Input B Isolation Differential Inputs 70 dB
lnput A to Output B Isolation
Input B to Output A Isolation
Differential Inputs Frequency Separation = 0Hz
(Notes 6, 7) Frequency Separation = 1MHz
Frequency Separation = 10MHz
47
>55
>55
dB
dB
dB
fRF = 5800MHz (Differential Inputs)
Linear Dynamic Range CW, 50Ω, ±1dB Linearity Error (Note 5) 49 dB
l44 dB
RF Input Power Range CW, 50Ω, ±1dB Linearity Error (Note 5) –44 to 5 dBm
Output Slope 31.3 mV/dB
Logarithmic Intercept (Note 3) –63.2 dBm
Deviation from CW Response 12dB Peak to Average Ratio (WiMAX OFDM) 0.5 dB
Input A to Input B Isolation Differential Inputs 50 dB
lnput A to Output B Isolation
Input B to Output A Isolation
Differential Inputs Frequency Separation = 0Hz
(Notes 6, 7) Frequency Separation = 1MHz
Frequency Separation = 10MHz
30
42
41
dB
dB
dB
Output Interface
VOA, VOB Output DC Voltage No RF Signal Present 0.45 V
Output Impedance 50
IOUT Source/Sink 5/5 mA
Rise Time, 10% to 90% 0.5V to 2.2V, fRF = 100MHz, CFLTRA = CFLTRB = 8.2nF 140 ns
Fall Time, 90% to 10% 2.2V to 0.5V, fRF = 100MHz, CFLTRA = CFLTRB = 8.2nF 3.5 µs
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, –40°C to 85°C, otherwise specifications are at TA = 25°C, VCC = 3.3V, EN = 3.3V. Test circuits are shown in
Figures 1 and 2 (Note 2).
LTC5583
5
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PARAMETER CONDITIONS MIN TYP MAX UNITS
VODF Output DC Voltage No RF Signal Present, VOS = 0V 0.05 V
Output Impedance 5
IOUT Source/Sink 5/5 mA
Rise Time, 10% to 90% 50mV to 1.8V, fRF = 100MHz, CFLTRA = CFLTRB = 8.2nF 170 ns
Fall Time, 90% to 10% 1.8V to 50mV, fRF = 100MHz, CFLTRA = CFLTRB = 8.2nF 3.5 µs
ENVA
ENVB
Output DC Voltage No RF Signal Present 2.15 V
Output Impedance 140
IOUT Source/Sink 4.0/1.8 mA
Rise Time, 10% to 90% 0.9V to 2.1V 11 ns
Fall Time, 90% to 10% 2.1V to 0.9V 11 ns
–3dB Bandwidth 50 MHz
Control Interface
EN Input High Voltage l2V
Input Low Voltage l0.3 V
Input Current Applied Voltage = 3.3V 100 180 µA
INV Input High Voltage 2V
Input Low Voltage 1V
Input Current Applied Voltage = 3.3V 0 µA
VOS Input Voltage Range 0 2.4 V
Input Current Applied Voltage = 2.4V 77 µA
Power Supply
Supply Voltage 3.1 3.3 3.5 V
Supply Current Envelope Detectors Turned Off 80.5 100 mA
Supply Current Envelope Detectors Turned On 90.1 mA
Shutdown Current EN = 0V, VCC = 3.5V 0.1 20 µA
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, –40°C to 85°C, otherwise specifications are at TA = 25°C, VCC = 3.3V, EN = 3.3V. Test circuits are shown in
Figures 1 and 2 (Note 2).
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC5583 is guaranteed functional over the temperature range
from –40°C to 85°C.
Note 3: Logarithmic Intercept is an extrapolated input power level from the
best-fit log-linear straight line, where the output voltage is 0V.
Note 4: Operation over a wider frequency range is possible with reduced
performance. Consult the factory for information and assistance.
Note 5: Linearity error is the difference in dB between the actual output
and the best-fit straight line at 25°C (using linear regression between
PIN = –50dBm and 0dBm for 450MHz, 880MHz, 2140MHz, 2700MHz;
between PIN = –40dBm and 0dBm for 3600MHz, 5800MHz). The dynamic
range is defined as the range of input power over which the linearity error
is within ±1dB.
Note 6: Input A to Output B (Channel A to Channel B) isolation is defined
as the ratio of input power levels at the two channels when the interfering
channel (Channel A with higher power) results in a 1dB output deviation
in the interfered channel (Channel B with lower power) and vice versa.
Sweep one channel input power level while holding the other channel input
at –45dBm for 450MHz, 880MHz, 2140MHz, 2700MHz, 3600MHz, and at
–35dBm for 5800MHz.
Note 7: For frequency separation = 0Hz between the two input signals,
channel-to-channel isolation is a function of the phase difference between
these two signals. The worst-case isolation is assumed.
LTC5583
6
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TYPICAL PERFORMANCE CHARACTERISTICS
Logarithmic Intercept
vs Frequency
Slope Distribution vs Temperature
2140MHz CW Input
Intercept Distribution vs Temperature
2140MHz CW Input
Output Voltage vs RF Input Power
CW Input at Various Frequencies
Linearity Error vs RF Input Power
CW Input at Various Frequencies
Slope vs Frequency
VCC = 3.3V, EN = 3.3V, TA = 25°C, unless otherwise noted. Test circuits shown in Figures 1 and 2.
INPUT POWER (dBm)
–70
0.2
VOA, VOB (V)
0.6
1.0
1.4
1.8
2.2
2.6
–50 –30 –10–60 –40 –20 0
5583 G01
10
450MHz, CHA
880MHz, CHA
2140MHz, CHA
2700MHz, CHA
3600MHz, CHA
5800MHz, CHA
450MHz, CHB
880MHz, CHB
2140MHz, CHB
2700MHz, CHB
3600MHz, CHB
5800MHz, CHB
INPUT POWER (dBm)
–70
–3
LINEARITY ERROR (dB)
–2
–1
0
1
2
3
–50 –30 –10–60 –40 –20 0
5583 G02
10
450MHz, CHA
880MHz, CHA
2140MHz, CHA
2700MHz, CHA
3600MHz, CHA
5800MHz, CHA
450MHz, CHB
880MHz, CHB
2140MHz, CHB
2700MHz, CHB
3600MHz, CHB
5800MHz, CHB
FREQUENCY (GHz)
0
27
SLOPE (mV/dB)
28
29
30
31
32
33
24135
5583 G03
6
85°C
–40°C
25°C
FREQUENCY (GHz)
0
–83
INTERCEPT (dBm)
–79
–75
–71
–67
–63
–59
24135
5583 G04
6
–40°C
25°C 85°C
SLOPE (mV/dB)
0
PERCENTAGE DISTRIBUTION (%)
10
20
5
15
25
30
35
40
45
29.728.5 29.1
5583 G05
30.3 30.9
85°C
25°C
–40°C
LOGARITHMIC INTERCEPT (dBm)
0
PERCENTAGE DISTRIBUTION (%)
10
20
5
15
25
30
35
–79–83 –81
5583 G06
–77 –75 –73 –71
85°C
25°C
–40°C
LTC5583
7
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TYPICAL PERFORMANCE CHARACTERISTICS
Modulation Deviation vs RF Input
Power, 880MHz Inputs,
Single-Ended Drive
Channel Matching vs RF Input
Power, 880MHz CW Inputs,
Single-Ended Drive, 5 Devices
Input A to Output B Isolation,
Input B to Output A Isolation,
880MHz CW Inputs, Single-Ended Drive
Output Voltage and Linearity Error
vs RF Input Power, 880MHz CW
Inputs, Single-Ended Drive
Output Voltage and Linearity Error
vs RF Input Power, 880MHz CW Inputs,
Single-Ended Drive, 5 Devices
VCC = 3.3V, EN = 3.3V, TA = 25°C, unless otherwise noted. For temperature compensation of logarithmic intercept at 880MHz,
set RP1 = Open, RP2 = 0, RT1 = 11.5kΩ, RT2 = 1.13kΩ. See Figure 1.
Difference Output and Linearity
Error vs RF Input Power, 880MHz
CW Inputs, Single-Ended Drive
INPUT POWER (dBm)
–65
0
VOA, VOB (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 G07
5
85°C, CH A
85°C, CH B
25°C, CH A
25°C, CH B
–40°C, CH A
–40°C, CH B
INPUT POWER (dBm)
–65
0
VODF (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 G08
5
SWEEP CH A INPUT
HOLD CH B
INPUT = –26dBm
85°C
25°C
–40°C
SWEEP CH B INPUT
HOLD CH A INPUT = –26dBm
VOS = 1.2V, INV = 0V
INPUT POWER (dBm)
–65
0
VOA, VOB (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 G09
5
85°C
25°C
–40°C
INPUT POWER (dBm)
–65
–3
LINEARITY ERROR (dB)
–2
–1
0
1
2
3
–35 –15 –5–45–55 –25
5583 G10
5
3-CARRIER CDMA2K
DEVIATION MEASURED
FROM LINEAR REFERENCE
GENERATED WITH CW INPUT.
4-CARRIER WCDMA
CW
INPUT POWER (dBm)
–65
–3
VOA – VOB (dB)
VOA – VOB (V)
–2
–1
1
0
2
3
–0.09
–0.06
–0.03
0
0.03
0.06
0.09
–45 –25 –5–55 –35 –15
5583 G11
5
85°C
25°C
–40°C
INTERFERING CHANNEL
INPUT POWER (dBm)
–45
0
INTERFERED CHANNEL OUTPUT DEVIATION (dB)
0.5
1.5
1.0
2.0
2.5
–25 –5–35 –15
5583 G12
5
A m B INDICATES:
CH A = INTERFERING CHANNEL
CH B = INTERFERED CHANNEL
B m A INDICATES:
CH B = INTERFERING CHANNEL
CH A = INTERFERED CHANNEL
INTERFERED CHANNEL
INPUT = –45dBm,
INTERFERING CHANNEL
INPUT SWEPT
FREQ SEP = FREQUENCY
SEPARATION BETWEEN
CH A INPUT AND CH B INPUT
A m B, FREQ SEP = 0Hz
B m A, FREQ SEP = 0Hz
A m B, FREQ SEP = 1MHz
B m A, FREQ SEP = 1MHz
A m B, FREQ SEP = 10MHz
B m A, FREQ SEP = 10MHz
NOTE 7
LTC5583
8
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TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage and Linearity Error
vs RF Input Power, 2140MHz CW
Inputs, Single-Ended Drive
Difference Output and Linearity
Error vs RF Input Power, 2140MHz
CW Inputs, Single-Ended Drive
Output Voltage and Linearity Error
vs RF Input Power, 2140MHz CW Inputs,
Single-Ended Drive, 5 Devices
Modulation Deviation
vs RF Input Power, 2140MHz
Inputs, Single-Ended Drive
Channel Matching vs RF Input
Power, 2140MHz CW Inputs,
Single-Ended Drive, 5 Devices
Input A to Output B Isolation,
Input B to Output A Isolation,
2140MHz CW Inputs, Single-Ended Drive
VCC = 3.3V, EN = 3.3V, TA = 25°C, unless otherwise noted. For temperature compensation of logarithmic intercept at 2140MHz,
set RP1 = Open, RP2 = 0, RT1 = 9.76kΩ, RT2 = 1.1kΩ. See Figure 1.
INPUT POWER (dBm)
–65
0
VOA, VOB (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 G13
5
85°C, CH A
85°C, CH B
25°C, CH A
25°C, CH B
–40°C, CH A
–40°C, CH B
INPUT POWER (dBm)
–65
0
VODF (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 G14
5
SWEEP CH A INPUT
HOLD CH B
INPUT = –26dBm
85°C
25°C
–40°C
SWEEP CH B INPUT
HOLD CH A INPUT = –26dBm
VOS = 1.2V, INV = 0V
INPUT POWER (dBm)
–65
0
VOA, VOB (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 G15
5
85°C
25°C
–40°C
INPUT POWER (dBm)
–65
–3
LINEARITY ERROR (dB)
–2
–1
0
1
2
3
–35 –15 –5–45–55 –25
5583 G16
5
CW
3-CARRIER CDMA2K
4-CARRIER WCDMA
DEVIATION MEASURED
FROM LINEAR REFERENCE
GENERATED WITH CW INPUT.
INPUT POWER (dBm)
–65
–3
VOA – VOB (dB)
VOA – VOB (V)
–2
–1
1
0
2
3
–0.09
–0.06
–0.03
0
0.03
0.06
0.09
–45 –25 –5–55 –35 –15
5583 G17
5
85°C
25°C
–40°C
INTERFERING CHANNEL
INPUT POWER (dBm)
–45
0
INTERFERED CHANNEL OUTPUT DEVIATION (dB)
0.5
1.5
1.0
2.0
2.5
–25 –5–35 –15
5583 G18
5
A m B INDICATES:
CH A = INTERFERING CHANNEL
CH B = INTERFERED CHANNEL
B m A INDICATES:
CH B = INTERFERING CHANNEL
CH A = INTERFERED CHANNEL
INTERFERED CHANNEL
INPUT = –45dBm,
INTERFERING CHANNEL
INPUT SWEPT
FREQ SEP = FREQUENCY
SEPARATION BETWEEN
CH A INPUT AND CH B INPUT
NOTE 7
A m B, FREQ SEP = 0Hz
B m A, FREQ SEP = 0Hz
A m B, FREQ SEP = 1MHz
B m A, FREQ SEP = 1MHz
A m B, FREQ SEP = 10MHz
B m A, FREQ SEP = 10MHz
LTC5583
9
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TYPICAL PERFORMANCE CHARACTERISTICS
Modulation Deviation
vs RF Input Power, 2700MHz
Inputs, Single-Ended Drive
Channel Matching vs RF Input
Power, 2700MHz CW Inputs,
Single-Ended Drive, 5 Devices
Input A to Output B Isolation,
Input B to Output A Isolation,
2700MHz CW Inputs, Single-Ended Drive
Output Voltage and Linearity Error
vs RF Input Power, 2700MHz CW
Inputs, Single-Ended Drive
Difference Output and Linearity
Error vs RF Input Power, 2700MHz
CW Inputs, Single-Ended Drive
Output Voltage and Linearity Error
vs RF Input Power, 2700MHz CW Inputs,
Single-Ended Drive, 5 Devices
VCC = 3.3V, EN = 3.3V, TA = 25°C, unless otherwise noted. For temperature compensation of logarithmic intercept at 2700MHz,
set RP1 = Open, RP2 = 0, RT1 = 8.87kΩ, RT2 = 1.21kΩ. See Figure 1.
INPUT POWER (dBm)
–65
0
VOA, VOB (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 G19
5
85°C, CH A
85°C, CH B
25°C, CH A
25°C, CH B
–40°C, CH A
–40°C, CH B
INPUT POWER (dBm)
–65
0
VODF (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 G20
5
85°C
25°C
–40°C
SWEEP CH A INPUT
HOLD CH B
INPUT = –25dBm
SWEEP CH B INPUT
HOLD CH A INPUT = –25dBm
VOS = 1.2V, INV = 0V
INPUT POWER (dBm)
–65
0
VOA, VOB (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 G21
5
85°C
25°C
–40°C
INPUT POWER (dBm)
–65
–3
LINEARITY ERROR (dB)
–2
–1
0
1
2
3
–35 –15 –5–45–55 –25
5583 G22
5
CW
WiMAX
DEVIATION MEASURED
FROM LINEAR REFERENCE
GENERATED WITH CW INPUT.
INPUT POWER (dBm)
–65
–3
VOA – VOB (dB)
VOA – VOB (V)
–2
–1
1
0
2
3
–0.09
–0.06
–0.03
0
0.03
0.06
0.09
–45 –25 –5–55 –35 –15
5583 G23
5
85°C
25°C
–40°C
INTERFERING CHANNEL
INPUT POWER (dBm)
–45
0
INTERFERED CHANNEL OUTPUT DEVIATION (dB)
0.5
1.5
1.0
2.0
2.5
3.5
3.0
4.0
4.5
5.0
–25 –5–35 –15
5583 G24
5
A m B INDICATES:
CH A = INTERFERING CHANNEL
CH B = INTERFERED CHANNEL
B m A INDICATES:
CH B = INTERFERING CHANNEL
CH A = INTERFERED CHANNEL
INTERFERED CHANNEL
INPUT = –45dBm,
INTERFERING CHANNEL
INPUT SWEPT
FREQ SEP = FREQUENCY
SEPARATION BETWEEN
CH A INPUT AND CH B INPUT
A m B, FREQ SEP = 0Hz
B m A, FREQ SEP = 0Hz
A m B, FREQ SEP = 1MHz
B m A, FREQ SEP = 1MHz
A m B, FREQ SEP = 10MHz
B m A, FREQ SEP = 10MHz
NOTE 7
LTC5583
10
5583fa
TYPICAL PERFORMANCE CHARACTERISTICS
Modulation Deviation vs RF
Input Power, 3600MHz Inputs,
Differential Drive
Channel Matching vs RF Input
Power, 3600MHz CW Inputs,
Differential Drive, 3 Devices
Input A to Output B Isolation,
Input B to Output A Isolation,
3600MHz CW Inputs, Differential Drive
Output Voltage and Linearity Error
vs RF Input Power, 3600MHz CW
Inputs, Differential Drive
Difference Output and Linearity
Error vs RF Input Power, 3600MHz
CW Inputs, Differential Drive
Output Voltage and Linearity Error
vs RF Input Power, 3600MHz CW
Inputs, Differential Drive, 3 Devices
VCC = 3.3V, EN = 3.3V, TA = 25°C, unless otherwise noted. For temperature compensation of logarithmic intercept at 3600MHz,
set RP1 = Open, RP2 = 0, RT1 = 10.2kΩ, RT2 = 1.65kΩ. See Figure 2.
INPUT POWER (dBm)
–65
0
VOA, VOB (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 G25
5
85°C, CH A
85°C, CH B
25°C, CH A
25°C, CH B
–40°C, CH A
–40°C, CH B
INPUT POWER (dBm)
–65
0
VODF (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 G26
5
SWEEP CH B INPUT
HOLD CH A INPUT = –25dBm
SWEEP CH A INPUT
HOLD CH B
INPUT = –25dBm
85°C
25°C
–40°C
VOS = 1.2V, INV = 0V
INPUT POWER (dBm)
–65
0
VOA, VOB (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–55 –35 –15
5583 G27
5
85°C
25°C
–40°C
INPUT POWER (dBm)
–65
–3
LINEARITY ERROR (dB)
–2
–1
0
1
2
3
–35 –15 –5–45–55 –25
5583 G28
5
CW
WiMAX
DEVIATION MEASURED
FROM LINEAR REFERENCE
GENERATED WITH CW INPUT.
INPUT POWER (dBm)
–65
–3
VOA – VOB (dB)
VOA – VOB (V)
–2
–1
1
0
2
3
–0.09
–0.06
–0.03
0
0.03
0.06
0.09
–45 –25 –5–55 –35 –15
5583 G29
5
85°C
25°C
–40°C
INTERFERING CHANNEL
INPUT POWER (dBm)
–45
0
INTERFERED CHANNEL OUTPUT DEVIATION (dB)
0.5
1.5
1.0
2.0
2.5
–25 –5–35 –15
5583 G30
5
A m B INDICATES:
CH A = INTERFERING CHANNEL
CH B = INTERFERED CHANNEL
B m A INDICATES:
CH B = INTERFERING CHANNEL
CH A = INTERFERED CHANNEL
INTERFERED CHANNEL
INPUT = –45dBm,
INTERFERING CHANNEL
INPUT SWEPT
FREQ SEP = FREQUENCY
SEPARATION BETWEEN
CH A INPUT AND CH B INPUT
NOTE 7
A m B, FREQ SEP = 0Hz
B m A, FREQ SEP = 0Hz
A m B, FREQ SEP = 1MHz
B m A, FREQ SEP = 1MHz
A m B, FREQ SEP = 10MHz
B m A, FREQ SEP = 10MHz
LTC5583
11
5583fa
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage and Linearity Error
vs RF Input Power, 5800MHz CW
Inputs, Differential Drive
Difference Output and Linearity
Error vs RF Input Power, 5800MHz
CW Inputs, Differential Drive
Output Voltage and Linearity Error
vs RF Input Power, 5800MHz CW
Inputs, Differential Drive, 3 Devices
Modulation Deviation vs RF
Input Power, 5800MHz Inputs,
Differential Drive
Channel Matching vs RF Input
Power, 5800MHz CW Inputs,
Differential Drive, 3 Devices
Input A to Output B Isolation,
Input B to Output A Isolation,
5800MHz CW Inputs, Differential Drive
VCC = 3.3V, EN = 3.3V, TA = 25°C, unless otherwise noted. For temperature compensation of logarithmic intercept at 5800MHz,
set RP1 = Open, RP2 = 0, RT1 = 10kΩ, RT2 = 1.47kΩ. See Figure 2.
INPUT POWER (dBm)
–55
0
VOA, VOB (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
5583 G31
10–45 –25 –5–35 –15 5
85°C, CH A
85°C, CH B
25°C, CH A
25°C, CH B
–40°C, CH A
–40°C, CH B
INPUT POWER (dBm)
–55
0
VODF (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–35 –15
5583 G32
105
SWEEP CH A INPUT
HOLD CH B
INPUT = –20dBm
85°C
25°C
–40°C
SWEEP CH B INPUT
HOLD CH A INPUT = –20dBm
VOS = 1.2V, INV = 0V
INPUT POWER (dBm)
–55
0
VOA, VOB (V)
LINEARITY ERROR (dB)
0.5
1.0
1.5
2.0
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
1.0
0.5
0
1.5
2.0
2.5
–45 –25 –5–35 –15
5583 G33
105
85°C
25°C
–40°C
INPUT POWER (dBm)
–55
–3
LINEARITY ERROR (dB)
–2
–1
0
1
2
3
–35 –15 –5–45 –25
5583 G34
105
WiMAX
CW
DEVIATION MEASURED
FROM LINEAR REFERENCE
GENERATED WITH CW INPUT.
INPUT POWER (dBm)
–55
–3
VOA – VOB (dB)
VOA – VOB (V)
–2
–1
1
0
2
3
–0.09
–0.06
–0.03
0
0.03
0.06
0.09
–45 –25 –5–35 –15
5583 G35
105
85°C
25°C
–40°C
INTERFERING CHANNEL
INPUT POWER (dBm)
–35
0
INTERFERED CHANNEL OUTPUT DEVIATION (dB)
0.5
1.5
1.0
2.0
2.5
–25 –5–30 –15–20 –10
5583 G36
1050
A m B INDICATES:
CH A = INTERFERING CHANNEL
CH B = INTERFERED CHANNEL
B m A INDICATES:
CH B = INTERFERING CHANNEL
CH A = INTERFERED CHANNEL
INTERFERED CHANNEL
INPUT = –35dBm,
INTERFERING CHANNEL
INPUT SWEPT
FREQ SEP = FREQUENCY
SEPARATION BETWEEN
CH A INPUT AND CH B INPUT
A m B, FREQ SEP = 0Hz
B m A, FREQ SEP = 0Hz
A m B, FREQ SEP = 1MHz
B m A, FREQ SEP = 1MHz
A m B, FREQ SEP = 10MHz
B m A, FREQ SEP = 10MHz
NOTE 7
LTC5583
12
5583fa
TYPICAL PERFORMANCE CHARACTERISTICS
Output Response to RF Burst
Input, 100MHz CW Input,
CFLTRA = CFLTRB = 1μF
Supply Current vs Supply Voltage
Envelope Detectors Disabled
Supply Current vs Supply Voltage
Envelope Detectors Enabled
Input A to Input B Isolation,
Single-Ended Inputs
Input A to Input B Isolation,
Differential Inputs
Output Response to RF Burst
Input, 100MHz CW Input,
CFLTRA = CFLTRB = 8.2nF
FREQUENCY (GHz)
0
–90
ISOLATION (dB)
–80
–70
–60
–50
–40
120.5 1.5 2.5
5583 G37
3
FREQUENCY (GHz)
2
–90
ISOLATION (dB)
–80
–70
–60
–50
–40
4352.5 4.53.5 5.5
5583 G38
6
TIME (µs)
0
0.2
VOA (V)
0.6
1.0
1.4
1.8
2.6
2.2
3.0
3.4
426153789
5583 G39
10
RF BURST OFF
INPUT = 0dBm
INPUT = –10dBm
INPUT = –20dBm
INPUT = –30dBm
INPUT = –40dBm
INPUT = –50dBm
RF BURST ON
TIME (ms)
0
0.2
VOA (V)
0.6
1.0
1.4
1.8
2.6
2.2
3.0
3.4
0.40.2 0.60.1 0.50.3 0.7 0.8 0.9
5583 G40
1
INPUT = 0dBm
INPUT = –10dBm
INPUT = –20dBm
INPUT = –30dBm
INPUT = –40dBm
INPUT = –50dBm
RF BURST OFF
RF BURST ON
VCC (V)
3.1
50
ICC (mA)
60
70
80
90
100
3.33.2 3.4
5583 G41
3.5
85°C
25°C
–40°C
VCC (V)
3.1
60
ICC (mA)
70
80
90
100
65
75
85
95
105
110
3.33.2 3.4
5583 G42
3.5
85°C
–40°C
25°C
VCC = 3.3V, EN = 3.3V, TA = 25°C, unless otherwise noted. Test circuits shown in Figures 1 and 2.
LTC5583
13
5583fa
TYPICAL PERFORMANCE CHARACTERISTICS
Envelope Detector Output Over
Temperature, 2140MHz Input
Average Power = –30dBm
Envelope Detector Output Over
Temperature, 2140MHz Input
Average Power = –30dBm
Envelope Detector Peak Output
Voltage vs Crest Factor,
2140MHz Input
Supply Current vs RF Input Power,
2140MHz CW Inputs to Both Channels
Envelope Detector Output and
Input Signal Envelope, 100MHz
Input Average Power = –30dBm
Envelope Detector Output and
Input Signal Envelope, 100MHz
Input Average Power = –30dBm
INPUT POWER (dBm)
–70
50
ICC (mA)
60
80
70
90
100
–50–60 –40 –20 –10–30 0
5583 G43
5
ENVELOPE DETECTORS DISABLED
ENVELOPE DETECTORS ENABLED
TIME (µs)
0
1.2
ENVA (V)
INPUT SIGNAL (V)
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
–0.06
–0.04
–0.02
0
0.02
0.08
0.06
0.04
0.10
0.12
0.14
2413
5583 G45
5
CREST FACTOR = 6
OSCILLOSCOPE WAVEFORM ACQUIRED IN
AVERAGE MODE
TIME (µs)
0
1.2
ENVA (V)
INPUT SIGNAL (V)
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
–0.06
–0.04
–0.02
0
0.02
0.08
0.06
0.04
0.10
0.12
0.14
2413
5583 G46
5
CREST FACTOR = 10,
OSCILLOSCOPE WAVEFORM ACQUIRED IN
AVERAGE MODE
TIME (µs)
0
1.80
ENVA (V)
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2413
5583 G47
5
85°C
25°C
–40°C
PEAK
CREST FACTOR = 6
OSCILLOSCOPE
WAVEFORM
ACQUIRED IN
AVERAGE MODE
TIME (µs)
0
1.80
ENVA (V)
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2413
5583 G48
5
85°C
25°C
–40°C
CREST FACTOR = 10
OSCILLOSCOPE
WAVEFORM
ACQUIRED IN
AVERAGE MODE
PEAK
PEAK TO AVERAGE POWER RATIO
(CREST FACTOR)
1
1.75
ENVA PEAK VALUE (V)
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
321145 768910
5583 G44
12
–10dBm
–20dBm
–30dBm
–40dBm
AVERAGE INPUT POWER
VCC = 3.3V, EN = 3.3V, TA = 25°C, unless otherwise noted. Test circuits shown in Figures 1 and 2.
LTC5583
14
5583fa
PIN FUNCTIONS
DECA, DECB (Pins 1, 6): Input Common Mode Decou-
pling Pins for Channel A and Channel B. These pins are
internally biased to 1.6V. The input impedance is 1.75k
in parallel with a 40pF internal shunt capacitor to ground.
The impedance between DECA and IN+A (or IN–A) is 200.
The pin can be connected to the center tap of an external
balun or to a capacitor to ground.
VCCA, VCCB, VCCR (Pins 2, 5, 3): Power Supply Pins for
Channel A, Channel B, and Bias Circuits. Typical total cur-
rent consumption of these pins is 81mA. Each of these
pins should be bypassed with 1nF and 1µF capacitors,
placed as close to the IC as possible.
EN (Pin 4): Enable Input Pin. An applied voltage above
2V will activate the bias for the IC. For an applied voltage
below 0.3V, the circuit will be shut down (disabled) with
a corresponding reduction in power supply current. If
the enable function is not required, then this pin can be
connected to VCC. The applied voltage to this pin should
not exceed VCC by more than 0.3V.
RP2 (Pin 9): Pin for Setting Polarity of Second Order Output
Temperature Compensation. Connect this pin to ground
to change the output voltage inversely proportional to
ambient temperature. Float this pin to change the output
voltage proportional to ambient temperature.
INV (Pin 12): Control Input Pin to Invert the Polarity of
the Difference Output VODF.
RT2 (Pin 14): Second Order Output Temperature Compen-
sation Pin for Both Channels. Connect this pin to ground
to disable. The output voltage will increase or decrease
with the ambient temperature by connecting this pin to
ground via an off-chip resistor, depending on the polarity
set by RP2 pin.
VOS (Pin 15): Input Pin for Setting the DC Offset of the
Difference Output VODF. It is recommended to set this DC
offset such that V
ODF
does not fall below 100mV.
VODF (Pin 16): DC Difference Output. This voltage is equal
to the difference of the two channels’ output voltages,
plus a DC offset:
V
ODF = (VOA – VOB) + VOS, if INV pin is held low, (<1V)
V
ODF = (VOB – VOA) + VOS, if INV pin is held high, (>2V)
RT1 (Pin 17): First Order Output Temperature Compen-
sation Pin for Both Channels. Connect this pin to ground
to disable. The output voltage will increase or decrease
with the ambient temperature by connecting this pin to
ground via an off-chip resistor, depending on the polarity
set by RP1 pin.
VOA, VOB (Pins 18, 13): DC Output of Channel A and
Channel B, respectively.
VCCN (Pin 19): Power Supply Pin for the Envelope Detec-
tors in Both Channels. Typical total current consumption
of this pin is 9.6mA. This pin should be bypassed with 1nF
and 1µF capacitors. Connect this pin to ground to disable
the envelope detectors.
ENVA, ENVB (Pins 20, 11): Envelope Detector Output Pins
for Channel A and Channel B, respectively. Each output
tracks the input signal’s RF envelope and outputs a DC
voltage directly proportional to the signal power, normal-
ized to the average power.
FLTA, FLTB (Pins 21, 10): Connection for an External Filter-
ing Capacitor for Channel A and Channel B, respectively. A
minimum 8nF capacitor is required for stable AC average
power measurement. Each capacitor should be connected
between FLTA and VCCA, and between FLTB and VCCB.
RP1 (Pin 22): Pin for Setting Polarity of First Order Output
Temperature Compensation. Connect this pin to ground
to change the output voltage proportional to ambient
temperature. Float this pin to change the output voltage
inversely proportional to ambient temperature.
IN+A, IN–A, IN+B, IN–B (Pins 24, 23, 7, 8): Differential
RF Input Signal Pins for Channel A and Channel B. Each
channel can be driven with a single-ended or differential
signal. These pins are internally biased to 1.6V and should
be DC-blocked externally. The differential impedance is
400.
GND (Exposed Pad Pin 25): Circuit Ground Return for
the Entire IC. This must be soldered to the printed circuit
board ground plane.
LTC5583
15
5583fa
5583 F01
FLTA ENVA
IN+A
LTC5583
EXPOSED PAD
25
DECA
DECB
RT1
RP1
EN
VCCR
IN–A
IN+BIN
–B
VCCA
VCCN
VCCB
ENVB
RT2
RP2 INV
VOUTA
VODF
VOUTB
VOS
FLTB
1nF
1nF
1nF
CFLTRB
100nF
1nF
1nF
1nF
1nF
1nF
1µF
0.3pF
0.3pF
RF INPUT A
3.3V
R1
1Ω
1nF
1nF
RF INPUT B 1nF
VCC
VCC
VCC
20pF
20pF
1nF
75Ω
RP2
RP1
20pF
1nF
100pF
CFLTRA
100nF
20pF
1
2
3
4
5
6
18
17
16
15
14
13
789101112
24 23 22 21 20 19
VCC
75Ω
RT2
RT1
100pF
TEST CIRCUITS
COMP VALUE SIZE PART NUMBER
C 20pF 0402 Murata GRM1555CIH200JB01
C 100pF 0402 Murata GRM1555CIH101JDO1B
C 1nF 0402 Murata GRM155R71H102KA01D
C 100nF 0402 Murata GRM155R61A104KA01
C 1µF 0402 Murata GRM155R60J105KE19
R 75 0402 Vishay CRCW040275R0FKED
FREQUENCY RP1 RP2 RT1 RT2 INPUT RETURN LOSS
450MHz Open 0 11.5k 1.13k 21dB
880MHz Open 0 11.5k 1.13k 14dB
2140MHz Open 0 9.76k 1.10k 14dB
2700MHz Open 0 8.87k 1.21k 14dB
Figure 1. Test Circuit Optimized for 40MHz to 3GHz Operation in Single-Ended Input Configuration
LTC5583
16
5583fa
TEST CIRCUITS
COMP VALUE SIZE PART NUMBER
C 20pF 0402 Murata GRM1555CIH200JB01
C 100pF 0402 Murata GRM1555CIH101JD01B
C 1nF 0402 Murata GRM155R71H102KA01D
C 100nF 0402 Murata GRM155R61A104KA01
C 1µF 0402 Murata GRM155R60J105KE19
R 62 0402 Vishay CRCW040262R0FKED
Figure 2. Test Circuit Optimized for 2GHz to 6GHz Operation in Differential Input Configuration
5583 F02
FLTA ENVA
IN+A
LTC5583
EXPOSED PAD
25
DECA
DECB
RT1
RP1
EN
VCCR
IN–A
IN+BIN
–B
VCCA
VCCN
VCCB
ENVB
RT2
RP2 INV
VOUTA
VODF
VOUTB
VOS
FLTB
1nF
1nF
1nF
CFLTRB
100nF
1nF
1nF 100pF
1nF
VCC
VCC
VCC
3.3V
1nF 1µF
CFLTRA
100nF
RF INPUT A L1
T2
1:1
T1
1:1
RF INPUT B L2
20pF 1nF
62Ω
62Ω
20pF
C2
C1
1nF
R1
1
1
2
3
4
5
6
18
17
16
15
14
13
789101112
24 23 22 21 20 19
TDK HHM17XX
TDK HHM17XX
1
5
3
2
4
1
5
3
2
4
RP2
RT2
RT1
RP1
VCC
100pF
FREQUENCY L1, L2 C1, C2 T1, T2 RP1 RP2 RT1 RT2 INPUT RETURN LOSS
2140MHz 2.7nH 1pF Murata LDB212G1005C-001 Open 0 9.76k 1.10k 15dB
2700MHz 1.5nH X TDK_HHM1710J1 Open 0 8.87k 1.21k 15dB
3600MHz 1.2nH 0.3pF TDK_HHM1727D1 Open 0 10.2k 1.65k 17dB
5800MHz Short 0.3pF TDK_HHM1733B1 Open 0 10.0k 1.47k 11dB
LTC5583
17
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TEST CIRCUITS
Figure 3. Top Side of Evaluation Board for Single-Ended Input Configuration
LTC5583
18
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APPLICATIONS INFORMATION
The LTC5583 is a dual-channel true RMS power detector,
capable of measuring two RF signals over the frequency
range from 40MHz to 6GHz, independent of input wave-
forms with different crest factors such as CW, CDMA2K,
WCDMA, LTE and WiMAX signals. Up to 60dB dynamic
range is achieved with very stable output over the full
temperature range from –40°C to 85°C. Input sensitivity
can be as low as –56dBm up to 2.7GHz even with single-
ended 50 input termination.
RF Inputs
The differential RF inputs are internally biased at 1.6V.
The differential impedance is about 400. These pins
should be DC blocked when connected to ground or other
matching components.
The LTC5583 can be driven in a single-ended configuration.
The single-ended input impedance vs frequency is given
in Table 1. Figure 4 shows the simplified circuit of this
single-ended configuration for each channel. The DECA
pin can be either left floating or AC-coupled to ground
via an external capacitor. While the RF signal is applied
to the IN+A (or IN–A) pin, the other pin, IN–A (or IN+A),
should be AC-coupled to ground. By simply terminating
the signal side of the inputs with a 75 resistor in front
of the AC-blocking capacitor and coupling the other side
to ground using a 1nF capacitor, a broadband 50 input
match can be achieved with typical input return loss better
than 14dB from 40MHz to 2.7GHz. At higher RF frequen-
cies, additional matching components may be needed.
Contact LTC Applications for more information.
Table 1. Single-Ended Input Impedance
FREQUENCY
(MHz)
INPUT
IMPEDANCE (Ω)
S11
MAG ANGLE (°)
40 207.4 – j15.5 0.613 –2.2
100 193.0 – j34.0 0.599 –5.4
200 188.9 – j56.8 0.611 –8.9
400 151.6 – j68.7 0.576 –15.2
600 127.8 – j62.8 0.530 –19.5
800 107.6 – j66.0 0.513 –26.2
1000 96.1 – j61.5 0.485 –30.3
1200 85.6 – j59.2 0.467 –35.4
1400 76.2 – j57.4 0.455 –41.0
1600 67.7 – j55.0 0.445 –47.1
1800 60.4 – j52.0 0.435 –53.5
2000 54.9 – j48.7 0.423 –59.4
2200 50.3 – j45.6 0.414 –65.2
2400 46.5 – j42.7 0.406 –70.8
2600 43.7 – j39.8 0.396 –76.0
2800 41.6 – j37.0 0.384 –80.8
3000 40.2 – j34.5 0.371 –84.9
3200 39.3 – j32.0 0.356 –88.8
3400 37.8 – j30.1 0.350 –93.1
3600 35.6 – j26.4 0.336 –101.5
3800 35.0 – j23.3 0.314 –107.4
4000 34.4 – j19.8 0.291 –115.0
4200 33.6 – j16.7 0.275 –123.2
4400 32.9 – j14.2 0.264 –130.6
4600 31.7 – j11.1 0.260 –141.0
4800 30.5 – j8.0 0.261 –152.0
5000 29.3 – j5.1 0.268 –162.5
5200 28.0 – j2.1 0.283 –173.0
5400 26.7 + j0.5 0.304 178.4
5600 25.4 + j2.7 0.328 171.7
5800 24.2 + j4.8 0.353 165.8
6000 23.1 + j6.6 0.377 161.1
LTC5583
19
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APPLICATIONS INFORMATION
Figure 4. Single-Ended Input Configuration
5583 F04
LTC5583
IN+A
DECA
IN–A
1nF
24
23
1
200Ω
200Ω
40pF
20pF
0.3pF R1
75Ω
1nF
20pF1nF
RF INPUT
5583 F05
LTC5583
IN+A
DECA
IN–A
L1
J1
24
23
1
200Ω
200Ω
40pF
C5
3
2
4
1
5
C4
1nF
R1
62Ω
C6
20pF
RF INPUT
T1
1:1
TDK HHM17xx
Figure 5. Differential Input Configuration
5583 F06
MATCHING NETWORK
CS1
CS1 LM
TO IN+
RF
INPUT
TO IN–
Figure 6. Single-Ended to Differential Conversion
LTC5583
20
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APPLICATIONS INFORMATION
The LTC5583 differential inputs can also be driven from a
fully balanced source as shown in Figure 5. When the two
input sources are single-ended, conversion to differential
signals can improve channel-to-channel isolation to obtain
accurate outputs from the dual channels, particularly at
very high frequencies (i.e. 3.6GHz and above). This can
be achieved using a 1:1 balun to match the chip’s internal
400 input impedance to the 50 source by adding a
62 resistor (R1) at the differential inputs as shown in
Figure 5. Since there is no voltage conversion gain from
impedance transformation in this case, the sensitivity of
the detector is similar to the one using single-ended inputs
as shown in Figure 4.
If better sensitivity is needed, a 1:4 balun can be used
and R1 should be increased to 400 correspondingly to
match 200 input impedance to the 50 source. This
impedance transformation results in 6dB voltage gain,
thus 6dB improvement in sensitivity is obtained while
the overall dynamic range remains the same. At high
frequency, additional LC elements may be needed for
input impedance matching due to the parasitics of the
transformer and PCB traces.
Alternatively, a narrowband LC matching network can
be used for the conversion of a single-ended signal to a
balanced signal. Such a matching network is shown in
Figure 6. By this means, the sensitivity and overall linear
dynamic range of the detector can be similar to the one
using a 1:4 RF input balun, as described above.
For a 50 input termination, the approximate RF input
power range of the LTC5583 is from –58dBm to 4dBm,
even with high crest factor signals such as a 4-carrier W-
CDMA waveform, but the minimum detectable RF power
level varies as the input RF frequency increases. The linear
dynamic range can also be shifted to tailor to a particular
application. By simply inserting an attenuator in front of
the RF input, the power range is shifted higher by the
amount of the attenuation.
The sensitivity of LTC5583 is dictated by the broadband
input noise power, which also determines the output DC
offset voltage. When the inputs are terminated differently,
the DC output voltage may vary slightly. When the input
noise power is minimized, the DC offset voltage is also
reduced to a minimum, and the sensitivity and dynamic
range are improved accordingly.
External Filtering Capacitors at FLTA and FLTB Pins
These pins are internally biased at VCC – 0.43V via a 1.2k
resistor from the VCCA and VCCB voltage supply. To ensure
stable operation of the LTC5583, an external capacitor
with a value of 8nF or higher is required to connect the
FLTA pin to VCCA, and the FLTB pin to VCCB, respectively.
Do not connect these filter capacitors to ground or any
other low voltage reference to prevent an abnormal start-
up condition.
The value of these two filtering capacitors has a dominant
effect on the output transient response. The lower the
capacitance, the faster the output rise and fall times. For
signals with AM content such as W-CDMA, ripple can be
observed when the loop bandwidth set by the filtering
capacitors is close to the modulation bandwidth of the
signal.
In general, the LTC5583 output ripple remains relatively
constant regardless of the RF input power level for a fixed
filtering capacitor and modulation format of the RF signal.
Typically, this capacitor must be selected to average out
the ripple to achieve the desired accuracy of RF power
measurement.
LTC5583
21
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Figure 7. Simplified Circuit Schematic of the RMS
Power Detector Output Interface
5583 F07
LTC5583
RSS
50Ω
VOA
OR
VOB
INPUT
VCC
CLOAD
VOUT
RMS Power Detector Output: VOA, VOB
The output buffer amplifier of the LTC5583 is shown in
Figure 7. This Class-AB buffer amplifier can output ±5mA
current to the load. The output impedance is determined
primarily by the 50 series resistor connected to the buffer
amplifier inside the chip. This will prevent any overstress
on the internal devices in the event that the output is
shorted to ground.
The –3dB small-signal bandwidth of the buffer amplifier
is about 22.4MHz and the full-scale rise/fall time can be
as fast as 140ns, limited by the slew rate of the internal
circuit instead. When the output is resistively terminated
or open, the fastest output transient response is achieved
when a large signal is applied to the RF input. The rise time
of the LTC5583 is about 140ns and the fall time is 3.5s,
respectively, for full-scale pulsed RF input power with
8.2nF filtering capacitors. The speed of the output transient
response is dictated mainly by the filtering capacitors (at
least 8nF) at the FLTA and FLTB pins. See the detailed output
transient response in the Typical Performance Character-
istics section. When the RF input has AM content, residual
ripple may be present at the output depending upon the
low frequency content of the modulated RF signal. This
ripple can be reduced with a larger filtering capacitor at
the expense of a slower transient response.
APPLICATIONS INFORMATION
Since the output buffer amplifier of the LTC5583 is capable
of driving an arbitrary capacitive load, the residual ripple
can be further filtered at the output with a series resistor
RSS and a large shunt capacitor CLOAD (see Figure 7). This
lowpass filter also reduces the output noise by limiting the
output noise bandwidth. When this RC network is designed
properly, a fast output transient response can be maintained
with reduced residual ripple. For example, we can estimate
CLOAD with an output voltage swing of 1.7V at 2140MHz.
In order to not allow the maximum 5mA sourcing current
to limit the fall time (about 5s), the maximum value of
CLOAD can be chosen as follows:
C
LOAD ≤ 5mA • Allowable Additional Time/1.7V
= 5mA • 0.25s/1.7V = 735pF
Once CLOAD is determined, RSS can be chosen properly
to form an RC low-pass filter with a corner frequency of
1/[2π • (RSS + 50) • CLOAD].
In general, the rise time of the LTC5583 is much shorter
than the fall time. However, when the output RC filter is
used, the rise time may be dominated by the time constant
of this filter. Accordingly, the rise time becomes very similar
to the fall time. Although the maximum sinking capability
of the LTC5583 is 5mA, it is recommended that the output
load resistance should be greater than 1.2k in order to
achieve the full output voltage swing.
LTC5583
22
5583fa
APPLICATIONS INFORMATION
where TC1 and TC2 are the first order and second order
temperature compensation coefficients, respectively; TA is
the actual ambient temperature; and tNOM is the reference
room temperature 25°C; detV1 and detV2 are the output
voltage variation when RT1 and RT2 are not set to zero.
Temperature Compensation of Logarithmic Intercept
The simplified interface schematics of the intercept tem-
perature compensation are shown in Figure 8 and Figure 9.
The adjustment of the output voltage can be described
by the following equation with respect to the ambient
temperature:
∆VOUT = TC1 • (TA – tNOM) + TC2 • (TA – tNOM)2
+ detV1 + detV2
Figure 9. Simplified Interface Circuit Schematic of
the Control Pins RT1 and RT2
Figure 8. Simplified Interface Circuit Schematic
of the Polarity Pins RP1 and RP2
5583 F08
LTC5583
22.2k
RP1 OR RP2
VCC
OPEN OR
SHORT
5583 F09
LTC5583
RT1 OR
RT2
VCC
250k
LTC5583
23
5583fa
The temperature coefficients TC1 and TC2 are shown as
functions of the tuning resistors RT1 and RT2 in Figure 10
and Figure 11.
APPLICATIONS INFORMATION
RT1 (kΩ)
5
TC1 (mV/°C)
detV1 (mV)
1.6
1.2
0.4
0.8
0
–0.4
–0.8
–1.2
–1.6
40
30
10
0
20
–10
–20
–30
–40
5583 F10
352015 302510
RP1 = 0
RP1 = 0PEN
detV1
detV1
TC1
TC1
Figure 10. First Order Temperature Compensation
Coefficient TC1 vs External RT1 Value
Figure 11. Second Order Temperature Compensation
Coefficient TC2 vs External RT2 Value
RT2 (kΩ)
0
TC2 (µV/°C2)
detV2 (mV)
16
12
4
8
0
–4
–8
–12
–16
200
150
50
0
100
–50
–100
–150
–200
5583 F11
10729856143
RP2 = OPEN
RP2 = 0
detV2
detV2
TC2
TC2
When pins RT1 and RT2 are shorted to ground, the tem-
perature compensation circuit is disabled automatically.
Polarity of the temperature coefficient TC1 (or TC2), can
be selected by either shorting the RP1 pin (or RP2 pin)
to ground or leaving it open, while the coefficients’ values
can be controlled by external resistors RT1 and RT2 inde-
pendently, according to Figures 10 and 11. At a given RF
frequency, the polarities and optimal values of TC1 and TC2
can be chosen to ensure a stable output over the operating
temperature range. Table 2 lists the suggested RP1, RP2,
RT1 and RT2 values at various RF frequencies for the best
output performance over temperature.
Table 2. Suggested RP and RT Values for Optimal Temperature
Performance vs RF Frequency
Frequency (MHz) RP1 RT1 (kΩ) RP2 RT2 (kΩ)
450 Open 11.5 0 1.13
880 Open 11.5 0 1.13
2140 Open 9.76 0 1.10
2700 Open 8.87 0 1.21
3600 Open 10.2 0 1.65
5800 Open 10.0 0 1.47
LTC5583
24
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APPLICATIONS INFORMATION
Envelope Detector Output: ENVA, ENVB
Each envelope detector output linearly follows the instan-
taneous input power level, tracking the input signal’s RF
envelope. ENVA and ENVB also indicate the peak-to-av-
erage power ratio (crest factor). Thus, reading both VOA
and ENVA provides the average power, peak-to-average
power ratio, peak power, and RF envelope of the input
signal to Channel A. Reading VOB and ENVB provides the
same information for Channel B.
Enable: EN
A simplified schematic of the EN pin interface is shown
in Figure 13. The enable voltage necessary to turn on the
LTC5583 is 2V. To disable or turn off the chip, set this volt-
age below 0.3V. It is important that the voltage applied to
the EN pin should never exceed VCC by more than 0.3V.
Otherwise, the supply current may be sourced through
the upper ESD protection diode connected at the EN pin.
Under no circumstances should voltage be applied to the
EN pin before the supply pins (VCCA, VCCB, VCCR, VCCN).
If this occurs, damage to the IC may result.
5583 F12
LTC5583 VCC
ENVA OR
ENVB
Figure 12. Simplified Schematic of the ENVA and ENVB Pin
Figure 13. Simplified Schematic of the Enable Pin
5583 F13
LTC5583
VCC
49k
EN
49k
LTC5583
25
5583fa
APPLICATIONS INFORMATION
Difference Output: VODF
This voltage is equal to the difference of the two channels’
output voltages, plus a DC offset:
V
ODF = (VOA – VOB) + VOS
if INV voltage < 1V.
V
ODF = (VOB – VOA) + VOS
if INV voltage > 2V.
A simplified schematic of the VODF interface is shown in
Figure 14. The low 5Ω output impedance at this pin is due
to internal feedback circuitry.
A simplified schematic of the VOS pin interface is shown
in Figure 16. The output range of VODF is from 50mV to
VCC – 50mV; it cannot go below 50mV. If VOA – VOB is
negative (for INV = low), a positive offset voltage VOS is
needed. Similarly, if VOB – VOA is negative (for INV = high),
a positive offset voltage VOS is needed.
Figure 14. Simplified Schematic of the VODF Pin
Figure 15. Simplified Schematic of the INV Pin
Figure 16. Simplified Schematic of the VOS Pin
5583 F15
LTC5583
VCC
10k
INV
5583 F16
LTC5583
VCC
30k
VOS
* VOA IF INV = LOW
V
OB IF INV = HIGH
*
5583 F14
LTC5583
15k
–
+
VCC
VODF
Supply Voltage Ramping
Fast ramping of the supply voltage can cause a current
glitch in the internal ESD protection circuits. Depending
on the supply inductance, this could result in a supply
voltage overshoot at initial turn-on that exceeds the maxi-
mum rating. A supply voltage ramp time of greater than
1ms is recommended. In case this voltage ramp time is
not controllable, a small (i.e. 1Ω) series resistor can be
inserted between VCC pin and the supply voltage source
to mitigate the problem and protect the IC. The R1 shown
in Figures 1 and 2 serves this purpose.
Figure 15 shows a simplified schematic of the INV pin
interface. INV determines the sign of the difference func-
tion at the VODF output.
LTC5583
26
5583fa
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
4.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
2423
1
2
BOTTOM VIEW—EXPOSED PAD
2.45 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF24) QFN 0105
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.45 ± 0.05
(4 SIDES)
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
LTC5583
27
5583fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/10 Revised the maximum Shutdown Current value in the Electrical Characteristics section. 5
LTC5583
28
5583fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
LT 1210 REV A • PRINTED IN USA
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LTC5583
RMS
DETECT
OUTA INA INB
OUTB
RMS
DETECT
ENVELOPE
DETECT
DIRECTIONAL
COUPLER
Tx PA
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