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LMH6572 Triple 2:1 High Speed Video Multiplexer
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1FEATURES DESCRIPTION
The LMH™ 6572 is a high performance analog
23• 350 MHz, 250 mV −3 dB Bandwidth multiplexer optimized for professional grade video
• 290 MHz, 2 VPP −3 dB Bandwidth and other high fidelity, high bandwidth analog
• 10 ns Channel Switching Time applications. The LMH6572 provides a 290MHz
bandwidth at 2 VPP output signal levels. The 140 MHz
• 90 dB Channel to Channel Isolation @ 5 MHz of .1 dB bandwidth and a 1500 V/µs slew rate make
• 0.02%, 0.02° Diff. Gain, Phase this part suitable for High Definition Television
• 0.1 dB Gain Flatness to 140 MHz (HDTV) and High Resolution Multimedia Video
applications.
• 1400 V/μs Slew Rate
• Wide Supply Voltage Range: 6V (±3V) to 12V The LMH6572 supports composite video applications
(±6V) with its 0.02% and 0.02° differential gain and phase
errors for NTSC and PAL video signals while driving
•−78 dB HD2 @ 10 MHz a single, back terminated 75Ωload. The LM6572 can
•−75 dB HD3 @ 10 MHz deliver 80 mA linear output current for driving multiple
video load applications.
APPLICATIONS The LMH6572 has an internal gain of 2 V/V (+6 dBv)
• RGB Video Router for driving back terminated transmission lines at a net
• Multi Input Video Monitor gain of 1 V/V (0 dBv).
• Fault Tolerant Data Switch The LMH6572 is available in the SSOP package.
Truth Table
Connection Diagram SEL EN OUT
0 0 CH 1
1 0 CH 0
X 1 Disable
Figure 1. 16-Pin SSOP Package
See Package Number DBQ0016A
Top View
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2LMH is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the Copyright © 2005–2013, Texas Instruments Incorporated
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Human Body Model 2000V
ESD Tolerance(3) Machine Model 200V
Supply Voltage (V+−V−) 13.2V
IOUT(4) 130 mA
Input Voltage Range ±(VS)
Maximum Junction Temperature +150°C(3)
Storage Temperature Range −65°C to +150°C
Infrared or Convection (20 sec) 235°C
Soldering Information Wave Soldering (10 sec) 260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, 1.5 kΩin series with 100 pF. Machine Model 0ΩIn series with 200 pF.
(4) The maximum output current (IOUT) is determined by the device power dissipation limitations. See the Power Dissipation section of the
Application Section for more details. A short circuit condition should be limited to 5 seconds or less.
Operating Ratings(1)
Operating Temperature −40 °C to 85 °C
Supply Voltage Range 6V to 12V
Thermal Resistance (θJA) 125°C/W
Package 16-Pin SSOP (θJC) 36°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
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±5V Electrical Characteristics
Unless otherwise specified, VS= ±5V, RL= 100Ω.
Symbol Parameter Conditions(1) Min Typ Max Units
Frequency Domain Performance
SSBW −3 dB Bandwidth VOUT = 0.25 VPP 350 MHz
LSBW –3 dB Bandwidth(2) VOUT = 2 VPP 250 290 MHz
.1 dBBW 0.1 dB Bandwidth VOUT = 0.25 VPP 140 MHz
DG Differential Gain RL= 150Ω, f = 4.43 MHz 0.02 %
DP Differential Phase RL= 150Ω, f = 4.43MHz 0.02 deg
Time Domain Response
TRS Channel to Channel Switching Time Logic Transition to 90% Output 10 ns
Enable and Disable Times Logic Transition to 90% or 10% Output 11 ns
TRL Rise and Fall Time 2V Step 1.5 ns
TSS Settling Time to 0.05% 2V Step 17 ns
OS Overshoot 4V Step 5 %
SR Slew Rate(2) 4V Step 1200 1400 V/μs
Distortion
HD2 2nd Harmonic Distortion 2 VPP , 10 MHz −78 dBc
HD3 3rd Harmonic Distortion 2 VPP , 10 MHz −75 dBc
IMD 3rd Order Intermodulation Products 10 MHz, Two tones 2 VPP at Output −80 dBc
Equivalent Input Noise
VN Voltage >1 MHz, Input Referred 5 nV√Hz
ICN Current >1 MHz, Input Referred 5 pA/√Hz
Static, DC Performance
GAIN Voltage Gain 2.0 V/V
Gain Error(3) No load, with respect to nominal gain of ±0.3 ±0.5 %
2.00 V/V. ±0.7
Gain Error RL= 50Ω, with respect to nominal gain 0.3 %
of 2.00 V/V
VIO Output Offset Voltage(3) VIN = 0V 1 ±14 mV
±17.5
DVIO Average Drift 27 µV/°C
IBN Input Bias Current(3) (4) VIN = 0V −1.4 ±5.0 µA
±5.6
DIBN Average Drift 7 nA/°C
PSRR Power Supply Rejection Ratio(3) DC, Input referred 50 54 dB
48
ICC Supply Current(3) No load 20 23 25 mA
28.5
Supply Current Disabled(3) No load 2.0 2.2 mA
2.3
VIH Logic High Threshold(3) Select & Enable Pins 2.0 V
VIL Logic Low Threshold(3) Select & Enable Pins 0.8 V
IiL Logic Pin Input Current Low(4) Logic Input = 0V −1 ±5.0 µA
±15
IiH Logic Pin Input Current High(4) Logic Input = 2.0V 112 150 200 µA
100 210
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ> TA. See Applications Section for information on temperature de-rating of this device.
Min/Max ratings are based on product testing, characterization and simulation. Individual parameters are tested as noted.
(2) Parameters ensured by design.
(3) Parameters ensured by electrical testing at 25° C.
(4) Positive Value is current into device.
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±5V Electrical Characteristics (continued)
Unless otherwise specified, VS= ±5V, RL= 100Ω.
Symbol Parameter Conditions(1) Min Typ Max Units
Miscellaneous Performance
RF Internal Feedback and Gain Set 650 800 940 Ω
Resistor Values 620 1010
RODIS Disabled Output Resistance Internal Feedback and Gain Set 1.3 1.6 1.88 kΩ
Resistors in Series to Ground
RIN+ Input Resistance 100 kΩ
CIN Input Capacitance 0.9 pF
ROUT Output Resistance 0.26 Ω
VO Output Voltage Range No Load ±3.83 ±3.9 V
±3.80
VOL RL= 100Ω±3.52 ±3.53 V
±3.5
CMIR Input Voltage Range ±2 ±2.5 V
IO Linear Output Current(3)(4) VIN = 0V +70 ±80 mA
40
ISC Short Circuit Current(5) VIN = ±2V, Output Shorted to Ground ±230 mA
XTLK Channel to Channel Crosstalk VIN = 2 VPP @5 MHz -90 dBc
XTLK Channel to Channel Crosstalk VIN = 2 VPP @ 100 MHz -54 dBc
XTLK All Hostile Crosstalk In A, C. Out B, VIN = 2 VPP @ 5 MHz -95 dBc
(5) The maximum output current (IOUT) is determined by the device power dissipation limitations. See the Power Dissipation section of the
Application Section for more details. A short circuit condition should be limited to 5 seconds or less.
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±3.3V Electrical Characteristics
Unless otherwise specified, VS= ±3.3V, RL= 100Ω.
Symbol Parameter Conditions(1) Min Typ Max Units
Frequency Domain Performance
SSBW −3 dB Bandwidth VOUT = 0.25 VPP 360 MHz
LSBW −3 dB Bandwidth VOUT = 2.0 VPP 270 MHz
0.1 dBBW 0.1 dB Bandwidth VOUT = 0.5 VPP 80 MHz
GFP Peaking DC to 200 MHz 0.3 dB
DG Differential Gain RL= 150Ω, f=4.43 MHz 0.02 %
DP Differential Phase RL= 150Ω, f=4.43 MHz 0.03 deg
Time Domain Response
TRL Rise and Fall Time 2V Step 2.0 ns
TSS Settling Time to 0.05% 2V Step 15 ns
OS Overshoot 2V Step 5 %
SR Slew Rate 2V Step 1000 V/μs
Distortion
HD2 2nd Harmonic Distortion 2 VPP, 10 MHz −70 dBc
HD3 3rd Harmonic Distortion 2 VPP, 10 MHz −74 dBc
IMD 3rd Order Intermodulation Products 10 MHz, Two tones 2 VPP at Output -79 dBc
Static, DC Performance
GAIN Voltage Gain 2.0 V/V
VIO Output Offset Voltage VIN = 0V 1 mV
DVIO Average Drift 36 µV/°C
IBN Input Bias Current(2) VIN = 0V 2 μA
DIBN Average Drift 24 nA/°C
PSRR Power Supply Rejection Ratio DC, Input Referred 54 dB
ICC Supply Current RL = ∞20 mA
VIH Logic High Threshold Select & Enable Pins 1.3 V
VIL Logic Low Threshold Select & Enable Pins 0.4 V
Miscellaneous Performance
RIN+ Input Resistance 100 kΩ
CIN Input Capacitance 0.9 pF
ROUT Output Resistance 0.27 Ω
VO Output Voltage Range No Load ±2.5 V
VOL RL= 100Ω±2.2 V
CMIR Input Voltage Range ±1.2 V
IO Linear Output Current VIN = 0V ±60 mA
ISC Short Circuit Current VIN = ±1V, Output Shorted to Ground ±150 mA
XTLK Channel to Channel Crosstalk 5 MHz -90 dBc
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ> TA. See Applications Section for information on temperature de-rating of this device.
Min/Max ratings are based on product testing, characterization and simulation. Individual parameters are tested as noted.
(2) Positive Value is current into device.
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Typical Performance Characteristics
Unless otherwise specified, VS= ±5V, RL= 100Ω.
Frequency Response vs. VOUT Frequency Response vs. VOUT
Figure 2. Figure 3.
Suggested RSvs. Capacitative Load
Frequency Response vs. Capacitive Load Load = 1kΩ|| CL
Figure 4. Figure 5.
Harmonic Distortion vs. Output Voltage Harmonic Distortion vs. Output Voltage
Figure 6. Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise specified, VS= ±5V, RL= 100Ω.
Harmonic Distortion vs. Frequency Harmonic Distortion vs. Frequency
Figure 8. Figure 9.
Harmonic Distortion vs. Supply Voltage Channel Switching Time
Figure 10. Figure 11.
Disable Time Pulse Response
Figure 12. Figure 13.
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Typical Performance Characteristics (continued)
Unless otherwise specified, VS= ±5V, RL= 100Ω.
Crosstalk PSRR
Figure . Figure 14.
PSRR Closed Loop Output Impedance
Figure 15. Figure 16.
Closed Loop Output Impedance
Figure 17.
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APPLICATION NOTES
General Information
The LMH6572 is a high-speed triple 2:1 analog multiplexer, optimized for very high speed and low distortion.
With a fixed gain of 2 and excellent AC performance, the LMH6572 is ideally suited for switching high resolution,
presentation grade video signals. The LMH6572 has no internal ground reference. Single or split supply
configurations are both possible. The LMH6572 features very high speed channel switching and disable times.
When disabled the LMH6572 output is high impedance, making multiplexer expansion possible by combining
multiple devices.
Single Supply Operation
The LMH6572 uses mid-supply referenced circuits for the select and disable pins. In order to use the LMH6572
in single supply configuration, it is necessary to use a circuit similar to Figure 19. In this configuration the logical
inputs are compatible with high breakdown open collector TTL, or open drain CMOS logic. In addition, the default
logic state is reversed since there is a pull-up resistor on those pins. Single supply operation also requires the
input to be biased to within the common mode input range of roughly ±2V from the mid-supply point.
Figure 18. Typical Application Figure 19. Single Supply Application
Video Performance
The LMH6572 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. Best performance will be obtained with back-
terminated loads. The back termination reduces reflections from the transmission line and effectively masks
transmission line and other parasitic capacitances from the amplifier output stage. Figure 18 shows a typical
configuration for driving a 75Ωcable. The output buffer is configured for a gain of 2, so using back terminated
loads will give a net gain of 1.
Gain Accuracy
The gain accuracy of the LMH6572 is accurate to ±0.5% (0.3% typical) and stable over temperature. The internal
gain setting resistors, RF and RG, match very well; however, over process and temperature their absolute value
will change.
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Expanding the Multiplexer
It is possible to build higher density multiplexers by paralleling several LMH6572s. Figure 20 shows a 4:1 RGB
MUX using two LMH6572s:
Figure 20. RGB MUX Using Two LMH6572's
If it is important in the end application to make sure that no two inputs are presented to the output at the same
time, an optional delay block can be added prior to the ENABLE(EN) pin of each device, as shown. Figure 21
shows one possible approach to this delay circuit. The delay circuit shown will delay ENABLE’s H to L transitions
(R1and C1decay) but will not delay its L to H transition.
Figure 21. Delay Circuit Implementation
R2should be kept small compared to R1in order to not reduce the ENABLE voltage and to produce little or no
delay to the ENABLE L to H transition.
With the ENABLE pin putting the output stage into a high impedance state, several LMH6572’s can be tied
together to form a larger input MUX. However, there is a slight loading effect on the active output caused by the
off-channel feedback and gain set resistors, as shown in Figure 21.Figure 22 is assuming there are four
LMH6572 devices tied together to form a triple 8:1 MUX. With the internal resistors valued at approximately
800Ω, the gain error is about -0.57 dB, or about −6%.
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Figure 22. Multiplexer Input Expansion by Combining Outputs
An alternate approach would be to tie the outputs directly together and let all devices share a common back
termination resistor in order to alleviate the gain error issue above.
The drawback in this case is the increased capacitive load presented to the output of each LMH6572 due to the
offstate capacitance of the LMH6572.
Other Applications
The LMH6572 may be utilized in systems that involve a single RGB channel as well whenever there is a need to
switch between different “flavors” of a single RGB input.
Here are some examples:
1. RGB positive polarity, negative polarity switch
2. RGB full resolution, high-pass filter switch
In each of these applications, the same RGB input occupies one set of inputs to the LMH6572 and the other
“flavor” would be tied to the other input set.
Driving Capacitive Loads
Capacitive output loading applications will benefit from the use of a series output resistor. Figure 23 shows the
use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive loads of
5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. Figure 24
gives a recommended value for selecting a series output resistor for mitigating capacitive loads. The values
suggested in the charts are selected for .5 dB or less of peaking in the frequency response. This gives a good
compromise between settling time and bandwidth. For applications where maximum frequency response is
needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the recommended values.
Figure 23. Decoupling Capacitive Loads
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Figure 24. Recommended ROUT vs. Capacitive Load Figure 25. Frequency Response vs. Capacitive
Load
Layout Considerations
Whenever questions about layout arise, use the LMH730151 evaluation board as a guide. To reduce parasitic
capacitances, ground and power planes should be removed near the input and output pins. For long signal paths
controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass
capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are
applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device; however, the
smaller ceramic capacitors should be placed as close to the device as possible. In Figure 18 and Figure 19, the
capacitor between V+and V−is optional, but is recommended for best second harmonic distortion. Another way
to enhance performance is to use pairs of .01 μF and 0.1 μF ceramic capacitors for each supply bypass.
Power Dissipation
The LMH6572 is optimized for maximum speed and performance in the small form factor of the standard SSOP
package. To achieve its high level of performance, the LMH6572 consumes 23 mA of quiescent current, which
cannot be neglected when considering the total package power dissipation limit. To ensure maximum output
drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make
sure that the TJMAX is never exceeded due to the overall power dissipation.
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Follow these steps to determine the Maximum power dissipation for the LMH6572:
1. Calculate the quiescent (no-load) power:
PAMP = ICC* (VS)
where
• VS= V+- V−(1)
2. Calculate the RMS power dissipated in the output stage:
PD(rms) = rms ((VS- VOUT) * IOUT)
where
• VOUT and IOUT are the voltage across and the current through the external load
• VSis the total supply voltage (2)
3. Calculate the total RMS power:
PT= PAMP + PD(3)
The maximum power that the LMH6572 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150° – TAMB)/ θJA
where
• TAMB = Ambient temperature (°C)
•θJA = Thermal resistance, from junction to ambient, for a given package (°C/W)
• For the SSOP package θJA is 125 °C/W (4)
ESD Protection
The LMH6572 is protected against electrostatic discharge (ESD) on all pins. The LMH6572 will survive 2000V
Human Body model and 200V Machine model events. Under normal operation the ESD diodes have no effect on
circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6572 is
driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows
through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is
possible to power up a chip with a large signal applied to the input pins. Shorting the power pins to each other
will prevent the chip from being powered up through the input.
Evaluation Boards
Texas Instruments provides the following evaluation boards as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the datasheet plots were measured with these boards.
Device Package Evaluation Board Part Number
LMH6572 SSOP LMH730151
An evaluation board can be shipped when a device sample request is placed with Texas Instruments.
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REVISION HISTORY
Changes from Revision E (April 2013) to Revision F Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6572MQ/NOPB ACTIVE SSOP DBQ 16 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LH65
72MQ
LMH6572MQX/NOPB ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LH65
72MQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
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regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
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Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
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DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
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Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
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Wireless Connectivity www.ti.com/wirelessconnectivity
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