PowerSSO-36
exposed pad up
PowerSSO-36 with
exposed pad down
Features
• 20 W + 20 W continuous output power:
– RL = 8 Ω, THD = 10% at VCC = 18 V
• Wide-range single-supply operation (5 - 18 V)
• High efficiency (η = 90%)
• Four selectable, fixed gain settings of nominally 20 dB, 26 dB, 30 dB and 32 dB
• Differential input minimize common-mode noise
• No ‘pop’ at turn-on/off
• Standby and mute features
• Short-circuit protection
• Thermal overload protection
• External synchronisation
Description
The TDA7491HV is a dual BTL class-D audio amplifier with single power supply
designed for LCD TVs and monitors.
Thanks to the high efficiency and exposed-pad-up (EPU) and down (EPD) packages,
no separate heatsink is required.
The TDA7491HV is pin-to-pin compatible with the TDA7491P and TDA7491LP.
Product status link
TDA7491HV
Product summary
Order code TDA7491HV13TR
Package PowerSSO-36 EPD
Order code TDA7491HVU13TR
Package PowerSSO-36 EPU
Packing Tape and reel
Temperature
range -40 to 85 °C
20 W + 20 W dual BTL class-D audio amplifier
TDA7491HV
Datasheet
DS5624 - Rev 9 - October 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
2Pin description
2.1 Pinout (EPD)
Figure 2. Pin connections (top view, PCB view)
S UB_GND
OUTP B
OUTP B
P GNDB
P GNDB
P VC CB
P VC CB
OUTNB
OUTNB
OUTNA
OUTNA
P VC CA
INNB
P VC CA
P GNDA
P GNDA
OUTP A
OUTP A
P GND
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
VS S
S VCC
VR E F
INP B
GAIN
P LIMIT
S VR
DIAG
S GND
VDDS
S YNCLK
13
14
15
16
17
18
24 R OS C
23 INNA
22 INP A
21 MUTE
20 S TBY
19 VDDP W
Exposed pad down
(Connected to ground )
EP
TDA7491HV
Pin description
DS5624 - Rev 9 page 3/50
2.2 Pin list (EPD)
Table 1. Pin description list
Number Name Type Description
1 SUB_GND PWR Connect to the frame
2,3 OUTPB O Positive PWM for right channel
4,5 PGNDB PWR Power stage ground for right channel
6,7 PVCCB PWR Power supply for right channel
8,9 OUTNB O Negative PWM output for right channel
10,11 OUTNA O Negative PWM output for left channel
12,13 PVCCA PWR Power supply for left channel
14,15 PGNDA PWR Power stage ground for left channel
16,17 OUTPA O Positive PWM output for left channel
18 PGND PWR Power stage ground
19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage
20 STBY I Standby mode control
21 MUTE I Mute mode control
22 INPA I Positive differential input of left channel
23 INNA I Negative differential input of left channel
24 ROSC O Master oscillator frequency-setting pin
25 SYNCLK I/O Clock in/out for external oscillator
26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks
27 SGND PWR Signal ground
28 DIAG O Open-drain diagnostic output
29 SVR O Supply voltage rejection
30 GAIN0 I Gain setting input 1
31 GAIN1 I Gain setting input 2
32 INPB I Positive differential input of right channel
33 INNB I Negative differential input of right channel
34 VREF O Half VDDS (nominal) referred to ground
35 SVCC PWR Signal power supply
36 VSS O 3.3-V (nominal) regulator output referred to power supply
- EP - Exposed pad for heatsink, to be connected to GND
TDA7491HV
Pin list (EPD)
DS5624 - Rev 9 page 4/50
2.3 Pinout (EPU)
Figure 3. Pin connections (top view, PCB view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
28
29
30
31
32
33
34
35
36
19
20
21
22
23
24
25
26
27
VSS SUB GN D
OUTPB
OUTPB
PGNDB
PGNDB
PVCCB
PVCCB
OUTNB
OUTNB
OUTNA
OUTNA
PVCCA
PVCCA
PGNDA
PGNDA
OUTPA
OUTPA
PGNDVDDPW
STBY
MUTE
IN PA
IN NA
ROSC
SYNCLK
VDDS
SGND
DIAG
SVR
PLIMIT
GAIN
IN PB
IN NB
VREF
SVCC
EP
exposed pad up
Connect to ground
TDA7491HV
Pinout (EPU)
DS5624 - Rev 9 page 5/50
2.4 Pin list (EPU)
Table 2. Pin description list
Number Name Type Description
1 SUB_GND PWR Connect to the frame
2, 3 OUTPB O Positive PWM for right channel
4, 5 PGNDB PWR Power stage ground for right channel
6, 7 PVCCB PWR Power supply for right channel
8, 9 OUTNB O Negative PWM output for right channel
10, 11 OUTNA O Negative PWM output for left channel
12, 13 PVCCA PWR Power supply for left channel
14, 15 PGNDA PWR Power stage ground for left channel
16, 17 OUTPA O Positive PWM output for left channel
18 PGND PWR Power stage ground
19 VDDPW O 3.3 V (nominal) regulator output referred to ground for power stage
20 STBY I Standby mode control
21 MUTE I Mute mode control
22 INPA I Positive differential input of left channel
23 INNA I Negative differential input of left channel
24 ROSC O Master oscillator frequency-setting pin
25 SYNCLK I/O Clock in/out for external oscillator
26 VDDS O 3.3 V (nominal) regulator output referred to ground for signal blocks
27 SGND PWR Signal ground
28 DIAG O Open-drain diagnostic output
29 SVR O Supply voltage rejection
30 PLIMIT I Output voltage level setting
31 GAIN I Gain setting input
32 INPB I Positive differential input of right channel
33 INNB I Negative differential input of right channel
34 VREF O Half VDDS (nominal) referred to ground
35 SVCC PWR Signal power supply
36 VSS O 3.3 V (nominal) regulator output referred to power supply
- EP - Exposed pad for heatsink, to be connected to GND
TDA7491HV
Pin list (EPU)
DS5624 - Rev 9 page 6/50
3Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage for pins PVCCA, PVCCB 23 V
VI Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN0,
GAIN1 -0.3 - 3.6 V
Top Operating temperature -40 to 85 °C
TjJunction temperature -40 to 150 °C
Tstg Storage temperature -40 to 150 °C
Table 4. Thermal data
Symbol Parameter Min. Typ. Max. Unit
Rth j-case Thermal resistance, junction-to-case 2 3
°C/W
Rth j-amb Thermal resistance, junction-to-ambient (mounted on a recommended
PCB)(1).24
1. FR4 with vias to copper area of 9 cm2
TDA7491HV
Absolute maximum ratings
DS5624 - Rev 9 page 7/50
4Electrical specifications
Unless otherwise stated, the results in Table 1 below are given for the conditions: VCC = 18 V, RL (load) = 8 Ω,
ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 20 dB and Tamb = 25 °C.
Table 5. Electrical specifications
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Supply voltage 5 - 18 V
IqTotal quiescent current - 26 35 mA
IqSTBY Quiescent current in standby 2.5 5.0 µA
VOS Output offset voltage
Play mode -100 +100
mV
Mute mode -60 +60
IOCP Overcurrent protection threshold RL = 0 Ω 3 5 - A
TjJunction temperature at thermal
shutdown 150 °C
RiInput resistance Differential input 54 60 kΩ
VUVP Undervoltage protection threshold - 4.5 V
RDS(on) Power transistor on resistance
High-side 0.2
Ω
Low-side 0.2
PoOutput power
THD = 10% 20
W
THD = 1% 16
PoOutput power
RL = 8 Ω, THD = 10%, VCC = 12
V7.2
W
RL = 6 Ω, THD = 1% VCC = 25
V4.0
PDDissipated power
Po =20W +20 W,
THD = 10%
4.0 W
η Efficiency Po = 20 W + 20W 80 90 %
THD Total harmonic distortion Po = 1 W 0.1 %
GVClosed-loop gain
GAIN0 = L, GAIN1 = L 18 20 22
dB
GAIN0 = L, GAIN1 = H 24 26 28
GAIN0 = H, GAIN1 = L 28 30 32
GAIN0 = H, GAIN1 = H 30 32 34
ΔGVGain matching -1 +1 dB
CT Cross-talk f = 1 kHz, Po=1 W 70 dB
eN Total input noise
A curve, GV = 20 dB 20
µV
f = 22 Hz to 22 kHz - 25 35
SVRR Supply voltage rejection ratio fr = 100 Hz, Vr = 1 Vpp, CSVR =
10 µF 50 dB
Tr, TfRise and fall times 40 ns
fSW Switching frequency Internal oscillator, master mode 290 320 350 kHz
TDA7491HV
Electrical specifications
DS5624 - Rev 9 page 8/50
Symbol Parameter Test conditions Min. Typ. Max. Unit
fSWR Switching frequency range (1) 250 - 400 kHz
VinH Digital input high (H)
-
2.3
V
VinL Digital input low (L) 0.8
AMUTE Mute attenuation VMUTE = low, VSTBY= high 80 dB
Function
mode
Standby mode
VSTBY < 0.5 V
VMUTE = X
Mute mode
VSTBY > 2.9 V
VMUTE < 0.8 V
Play mode
VSTBY > 2.9 V
VMUTE > 2.9 V
1. Refer to Section 8.4 Internal and external clocks.
TDA7491HV
Electrical specifications
DS5624 - Rev 9 page 9/50
5Characterization curves
The following characterization curves have been produced by using the TDA7491HV evaluation board.
The LC filter for 4 Ω load uses components of 15 μH and 470 nF, whilst that for 6 Ω load uses 22 μH and 220 nF
and that for 8 Ω load uses 33 μH and 220 nF.
5.1 4 Ω loads at VCC = 14 V
Figure 4. Output power vs. supply voltage
Test Condition :
Vcc = 5~14V,
RL = 4 ohm,
Rosc = 39k , Cosc =100nF,
f =1kHz,
Gv = 30dB,
Tamb = 25
Specification Limit:
Typical:
Vs =14V,Rl = 4 ohm
Po = 20W @THD =10%
Po =16W @THD =1%
Supply voltage
Output power (W)
Figure 5. THD vs. output power (1 kHz)
THD (%)
Output Power (W)
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
100m 20200m 500m 1 2 5 10
Test Condition:
Vcc=14V,
RL=4 ohm,
Rosc=39k , Cosc=100nF,
f =1kHz,
Gv=30dB,
Tamb=25
Specification Limit:
Typical:
Po=20W @ THD=10%
TDA7491HV
Characterization curves
DS5624 - Rev 9 page 10/50
Figure 6. THD vs. output power (100 Hz)
THD (%)
Output Power (W)
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
100m 20200m 500m 1 2 5 10
Test Condition:
Vcc=14V,
RL=4 ohm,
Rosc=39k , Cosc=100nF,
f =100Hz,
Gv=30dB,
Tamb=25
Specification Limit:
Typical:
20W @ THD=10%
Figure 7. THD vs. frequency
THD (%)
Frequency (Hz)
0.01
0.5
0.02
0.03
0.04
0.05
0.06
0.07
0.1
0.2
0.3
0.4
20 20k50 100 200 500 1k 2k 5k 10k
Test Condition:
Vcc=14V,
RL=4 ohm,
Rosc=39k , Cosc=100nF,
f = 1kHz,
Gv=30dB,
Po=1W
Tamb=25
Specification Limit:
Typical: THD <0.5%
TDA7491HV
4 Ω loads at VCC = 14 V
DS5624 - Rev 9 page 11/50
Figure 8. Frequency response
Ampl (dB)
Frequency (Hz)
-5
+2
-4
-3
-2
-1
-0
+1
10 30k20 50 100 200 500 1k 2k 5k 10k
Specification Limit:
Max: +/-3dB
@20Hz to 20kHz
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc=39k , Cosc=100nF,
f = 1kHz,
Gv = 30dB,
Po =1W
Tamb = 25
Figure 9. Crosstalk vs. frequency
Crosstalk (dB)
-120
-40
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
20 20k50 100 200 500 1k 2k 5k 10k
Specification Limit:
Typical: >50dB (@ f = 1kHz)
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc= 39k , Cosc = 100nF,
f = 1kHz,
Gv = 30dB,
Po = 1W
Tamb = 25
Frequency (Hz)
Figure 10. FFT performance (0 dB)
Frequency (Hz)
FFT (dB)
-150
+10
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
20 20k50 100 200 500 1k 2k 5k 10k
Specification Limit:
Typical: >60dB
for the harmonic frequency
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc = 39k , Cosc =100nF,
f =1kHz,
Gv = 30dB,
Po = 1W
Tamb = 25
TDA7491HV
4 Ω loads at VCC = 14 V
DS5624 - Rev 9 page 12/50
Figure 11. FFT performance (-60 dB)
Frequency (Hz)
FFT (dB)
-150
+0
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
Specification Limit:
Typical: > 90dB
for the harmonic frequency
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc = 39k , Cosc = 100nF,
f = 1kHz,
Gv=30dB,
Po= -60dB (@ 1W =0dB)
Tamb=25
Figure 12. Power supply rejection ratio vs. frequency
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc = 39k , Cosc = 100nF,
Vin=0,
Gv=30dB,
0dB refers to 500mV,100Hz
Tamb=25
Ripple frequency=100Hz
Ripple voltage=500mV
Figure 13. Power dissipation and efficiency vs. output power
Test Condition:
Vcc=14V,
RL=4 ohm,
Rosc=39k , Cosc=100nF,
f =1kHz,
Gv=30dB,
Tamb=25
Vcc=14V
Rload=4ohm
Gain=30dB
f=1kHz
TDA7491HV
4 Ω loads at VCC = 14 V
DS5624 - Rev 9 page 13/50
Figure 14. Closed-loop gain vs. frequency
-5
+2
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
-0
+0.5
+1
+1.5
d
B
r
A
20 30k50 100 200 500 1k 2k 5k 10k 20k
Hz
Test Conditions:
Vcc =14V,
RL= 4 ohm,
Rosc = 39k , Cosc = 100nF,
F=1kHz,
0dB@f=1kHz,,Po=1w,
Gain=32dB
Tamb=25
Gain=32dB
Gain=32dBGain=22dB
Gain=26dB
Figure 15. Current consumption vs. voltage on pin MUTE
Vcc=14V
Rload=4ohm
Gain=30dB
Vin=0
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc = 39k , Cosc = 100nF,
Vin=0,
Ta mb=25
Figure 16. Attenuation vs. voltage on pin MUTE
Vcc=14V
Rload=4ohm
Gain=30dB
0dB@f=1kHz, Po=1w
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc = 39k , Cosc = 100nF,
0dB@f=1kHz, Po=1w,
Gain=30dB,
Ta mb=25
TDA7491HV
4 Ω loads at VCC = 14 V
DS5624 - Rev 9 page 14/50
Figure 17. Current consumption vs. voltage on pin STBY
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc = 39k , Cosc = 100nF,
Vin=0,
Ta mb=25
Vcc=14V
Rload=4ohm
Gain=30dB
Vin=0
Figure 18. Attenuation vs. voltage on pin STBY
Test Condition:
Vcc =14V,
RL= 4 ohm,
Rosc = 39k , Cosc = 100nF,
0dB@f=1kHz,Po=1w,
Gain=30dB.
Tamb=25
Vcc=14V
Rload=4ohm
Gain=30dB
0dB@f=1kHz, Po=1w
TDA7491HV
4 Ω loads at VCC = 14 V
DS5624 - Rev 9 page 15/50
5.2 6 Ω loads at VCC = 16 V
Figure 19. Output power vs. supply voltage
Test Condition :
f =1kHz
Specification Limit:
Typical:
Vs =16V,R l =6 ohm
Po=20W @THD=10%
Po=16W @THD=1%
Figure 20. THD vs. output power (1 kHz)
THD (%)
Output Power (W)
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
200m 20500m 1 2 5 10
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
f =1kHz,
Gv =30dB,
Tamb =25
Specification Limit:
Typical:
Po=20W @ THD=10%
TDA7491HV
6 Ω loads at VCC = 16 V
DS5624 - Rev 9 page 16/50
Figure 21. THD vs. output power (100 Hz)
THD (%)
Output Power (W)
0.005
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
200m 20500m 1 2 5 10
Test Condition:
Vcc =16V,
RL = 6 ohm,
Rosc =39k , Cosc =100nF,
f =100Hz,
Gv =30dB,
Tamb =25
Specification Limit:
Typical:
20W @ THD =10%
Figure 22. THD vs. frequency
THD (%)
Frequency (Hz)
0.01
2
0.02
0.05
0.1
0.2
0.5
1
20 20k50 100 200 500 1k 2k 5k 10k
Test Condition:
Vcc =16V,
RL= 6 ohm,
Ros c=39k , Cosc =100nF,
f =1kHz,
Gv =30dB,
Po =1W
Tamb =25
Specification Limit:
Typical: THD<0.5%
TDA7491HV
6 Ω loads at VCC = 16 V
DS5624 - Rev 9 page 17/50
Figure 23. Frequency response
Ampl (dB)
Frequency (Hz)
-5
+2
-4
-3
-2
-1
-0
+1
10 30k20 50 100 200 500 1k 2k 5k 10k
Specification Limit:
Max: +/-3dB
@20Hz to 20kHz
Test Condition:
Vcc=16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
f = 1kHz,
Gv =30dB,
Po =1W
Tamb =25
Figure 24. Crosstalk vs. frequency
Crosstalk (dB)
Frequency (Hz)
-120
-40
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
20 20k50 100 200 500 1k 2k 5k 10k
Specification Limit:
Typical: >50dB (@ f =1kHz)
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
f = 1kHz,
Gv =30dB,
Po =1W
Tamb=25
TDA7491HV
6 Ω loads at VCC = 16 V
DS5624 - Rev 9 page 18/50
Figure 25. FFT performance (0 dB)
FFT (dB)
-150
+10
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
20 20k50 100 200 500 1k 2k 5k 10k
Specification Limit:
Typical: >60dB
for the harmonic frequency
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
f =1kHz,
Gv =30dB,
Po =1W
Tamb =25
Frequency (Hz)
Figure 26. FFT performance (-60 dB)
Frequency (Hz)
FFT (dB)
-150
+0
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
Specification Limit:
Typical: > 90dB
for the harmonic frequency
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
f =1kHz,
Gv =30dB,
Po = -60dB (@ 1W =0dB)
Tamb =25
TDA7491HV
6 Ω loads at VCC = 16 V
DS5624 - Rev 9 page 19/50
Figure 27. Power supply rejection ratio vs. frequency
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
Vin=0,
Gv =30dB,
Tamb =25 ,
0dB refers to 500mV, 100Hz
Ripple frequency=100Hz
Ripple voltage=500mV
Figure 28. Power dissipation and efficiency vs. output power
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
f =1kHz,
Gv =30dB,
Tamb =25
Vcc=16V
Rload=6ohm
Gain=30dB
f=1kHz
Figure 29. Closed-loop gain vs. frequency
-5
+2
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
-0
+0.5
+1
+1.5
d
B
r
A
20 30k50 100 200 500 1k 2k 5k 10k 20k
Hz
Gain=32dB
Gain=22dB
Gain=30dB
Gain=26dB
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
0dB@f=1kHz,Po=1w,
Gv=32dB,
Tamb =25
TDA7491HV
6 Ω loads at VCC = 16 V
DS5624 - Rev 9 page 20/50
Figure 30. Current consumption vs. voltage on pin MUTE
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
Vin=0,
Gain=30dB,
Tamb =25
Vcc=16V
Rload=6ohm
Gain=30dB
Vin=0
Mute voltage (V)
Figure 31. Attenuation vs. voltage on pin MUTE
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
0dB@f=1kHz,Po=1w,
Gain=30dB,
Tamb =25
Vcc=16V
Rload=6ohm
Gain=30dB
0dB@f=1kHz, Po=1w
Mute voltage
TDA7491HV
6 Ω loads at VCC = 16 V
DS5624 - Rev 9 page 21/50
Figure 32. Current consumption vs. voltage on pin STBY
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
Vin=0,
Gain=30dB,
Tamb =25
Vcc=16V
Rload=6ohm
Gain=30dB
Vin=0
Figure 33. Attenuation vs. voltage on pin STBY
Test Condition:
Vcc =16V,
RL= 6 ohm,
Rosc =39k , Cosc =100nF,
0dB@f=1kHz,Po=1w,
Gain=30dB,
Tamb =25
Vcc=16V
Rload=6ohm
Gain=30dB
0dB@f=1kHz, Po=1w
Standby voltage
Iquiescent (mA)
TDA7491HV
6 Ω loads at VCC = 16 V
DS5624 - Rev 9 page 22/50
5.3 8 Ω loads at VCC = 18 V
Figure 34. Output power vs. supply voltage
Test conditions :
Vcc = 5~18V,
RL = 8 ohm,
Rosc =39k , Cosc =100nF
f =1kHz,
Gv =30dB,
Tamb =25
Specification limit:
Typical:
Vs =18V,Rl = 8 ohm
Po =20W @THD =10%
Po =16W @THD =1%
Supply voltage
Output power (W)
Figure 35. THD vs. output power (1 kHz)
THD (%)
Output Power (W)
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
100m 20200m 500m 1 2 5 10
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
f =1kHz,
Gv =30dB,
Tamb =25
Specification Limit:
Typical:
Po =20W @ THD =10%
TDA7491HV
8 Ω loads at VCC = 18 V
DS5624 - Rev 9 page 23/50
Figure 36. THD vs. output power (100 Hz)
THD (%)
Output Power (W)
0.005
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
100m 20200m 500m 1 2 5 10
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
f =100Hz,
Gv =30dB,
Tamb =25
Specification Limit:
Typical:
20W @ THD =10%
Figure 37. THD vs. frequency
Frequency (Hz)
THD (%)
0.005
2
0.01
0.02
0.05
0.1
0.2
0.5
1
20 20k50 100 200 500 1k 2k 5k 10k
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
f =1kHz,
Gv =30dB,
Po =1W
Tamb =25
Specification Limit:
Typical: THD<0.5%
TDA7491HV
8 Ω loads at VCC = 18 V
DS5624 - Rev 9 page 24/50
Figure 38. Frequency response
Ampl (dB)
Frequency (Hz)
-5
+2
-4
-3
-2
-1
-0
+1
10 30k20 50 100 200 500 1k 2k 5k 10k
Specification Limit:
Max: +/-3dB
@20Hz to 20kHz
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
f =1kHz,
Gv =30dB,
Po =1W
Tamb =25
Figure 39. Crosstalk vs. frequency
Crosstalk (dB)
Frequency (Hz)
-120
-40
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
20 20k50 100 200 500 1k 2k 5k 10k
Specification Limit:
Typical: >50dB (@ f =1kHz)
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
f = 1kHz,
Gv=30dB,
Po=1W
Tamb=25
TDA7491HV
8 Ω loads at VCC = 18 V
DS5624 - Rev 9 page 25/50
Figure 40. FFT performance (0 dB)
FFT (dB)
-150
+10
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
20 20k50 100 200 500 1k 2k 5k 10k
Specification Limit:
Typical: >60dB
for the harmonic frequency
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
f = 1kHz,
Gv =30dB,
Po =1W
Tamb =25
Frequency (Hz)
Figure 41. FFT performance (-60 dB)
Frequency (Hz)
FFT (dB)
-150
+0
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
Specification Limit:
Typical: > 90dB
for the harmonic frequency
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
f =1kHz,
Gv =30dB,
Po = -60dB (@ 1W =0dB)
Tamb =25
TDA7491HV
8 Ω loads at VCC = 18 V
DS5624 - Rev 9 page 26/50
Figure 42. Power supply rejection ratio vs. frequency
8ohm 18v PSRR.at27
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
Vin=0,
Gv =30dB,
Tamb =25
0dB refers to 500mV, 100Hz
Ripple frequency=100Hz
Ripple voltage=500mV
Figure 43. Power dissipation and efficiency vs. output power
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
f=1kHz,
Gv =30dB,
Tamb =25
Vcc=18V
Rload=8ohm
Gain=30dB
f=1kHz
Output power per channel (W)
Efficiency %
Power dissipation (W)
TDA7491HV
8 Ω loads at VCC = 18 V
DS5624 - Rev 9 page 27/50
Figure 44. Closed-loop gain vs. frequency
-5
+2
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
-0
+0.5
+1
+1.5
d
B
r
A
20 30k50 100 200 500 1k 2k 5k 10k 20k
Hz
Gain=32dB
Gain=22dB
Gain=30dB
Gain=26dB
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
0dB@f=1kHz,Po=1w,
Gain=32dB,
Tamb =25
Figure 45. Current consumption vs. voltage on pin MUTE
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
Vin=0,
Gain=30dB,
Tamb =25
Vcc=18V
Rload=8ohm
Gain=30dB
Vin=0
Mute voltage
Iquiescent (mA)
TDA7491HV
8 Ω loads at VCC = 18 V
DS5624 - Rev 9 page 28/50
Figure 46. Attenuation vs. voltage on pin MUTE
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
0dB@f=1kHz,Po=1w,
Gain=30dB,
Tamb =25
Vcc=18V
Rload=8ohm
Gain=30dB
0dB@f=1kHz, Po=1w
Iquiescent (mA)
Mute voltage
Figure 47. Current consumption vs. voltage on pin STBY
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
Vin=0,
Gain=30dB,
Tamb =25
Vcc=18V
Rload=8ohm
Gain=30dB
Vin=0
Iquiescent (mA)
Standby voltage (V)
TDA7491HV
8 Ω loads at VCC = 18 V
DS5624 - Rev 9 page 29/50
Figure 48. Attenuation vs. voltage on pin STBY
Test Condition:
Vcc =18V,
RL= 8 ohm,
Rosc =39k , Cosc =100nF,
0dB@f=1kHz,Po=1w,
Gain=30dB,
Tamb =25
Vcc=18V
Rload=8ohm
Gain=30dB
0dB@f=1kHz, Po=1w
Attenuation (dB)
Standby voltage (V)
TDA7491HV
8 Ω loads at VCC = 18 V
DS5624 - Rev 9 page 30/50
6Test board
Figure 49. Test board (TDA7491HV) layout
TDA7491HV
Test board
DS5624 - Rev 9 page 31/50
7Application circuit
Figure 50. Application circuit for class-D amplifier
TDA7491HV
TDA7491HV
Application circuit
DS5624 - Rev 9 page 32/50
8Application information
8.1 Mode selection
The three operating modes of the TDA7491HV are set by the two inputs, STBY (pin 20) and MUTE (pin 21).
• Standby mode: all circuits are turned off, very low current consumption.
• Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty
cycle.
• Play mode: the amplifiers are active.
The protection functions of the TDA7491HV are enabled by pulling down the voltages of the STBY and MUTE
inputs shown in figure below. The input current of the corresponding pins must be limited to 200 µA.
Table 6. Mode settings
Mode STBY MUTE
Standby L(1).X (do not care)
Mute H(1) L
Play H H
1. Refer to VSTBY and VMUTE in Section 4 Electrical specifications
Figure 51. Standby and mute circuits
STBY
MUTE
0 V
3.3 V C7
2.2 µF
R2
30 k
Standby
0 V
3.3 V C15
2.2 µF
R4
30 k
Mute
TDA7491HV
TDA7491HV
Application information
DS5624 - Rev 9 page 33/50
Figure 52. Turn-on/off sequence for minimizing speaker “pop”
8.2 Gain setting
The gain of the TDA7491HV is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31). Internally, the gain is set
by changing the feedback resistors of the amplifier.
Table 7. Gain settings
GAIN0 GAIN1 Nominal gain, Gv (dB)
L(1) H(1) 20
L H 26
H L 30
H H 32
1. Refer to Section 4 Electrical specifications for L and H drive levels.
TDA7491HV
Gain setting
DS5624 - Rev 9 page 34/50
8.3 Input resistance and capacitance
The input impedance is set by an internal resistor Ri = 68 kΩ (typical). An input capacitor (Ci) is required to couple
the AC input signal.
The equivalent circuit and frequency response of the input components are shown in figure below. For Ci = 220
nF, the high-pass filter cut-off frequency is below 20 Hz:
fc = 1 / (2 * π * Ri * Ci)
Figure 53. Device input circuit and frequency response
8.4 Internal and external clocks
The clock of the class-D amplifier can be generated internally or can be driven by an external source.
If two or more class-D amplifiers are used in the same system, it is recommended that all the devices operate at
the same clock frequency. This can be implemented by using one TDA7491HV as master clock, while the other
devices are in slave mode, that is, externally clocked. The clock interconnect is via pin SYNCLK of each device.
As explained below, SYNCLK is an output in master mode and an output in master mode and an input in slave
mode.
8.4.1 Master mode (internal clock)
Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, ROSC, connected to
pin ROSC:
fSW = 106 / ((16* ROSC+ 182) * 4) kHz
where ROSC is in kΩ.
In master mode, pin SYNCLK is used as a clock output pin whose frequency is:
fSYNCLK = 2 * fSW
For master mode to operate correctly, then resistor ROSC must be less than 60 kΩ as given below in Table 8. How
to set up SYNCLK.
TDA7491HV
Input resistance and capacitance
DS5624 - Rev 9 page 35/50
8.4.2 Slave mode (external clock)
In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin
SYNCLK to be internally configured as an input as given in table below.
The output switching frequency of the slave devices is:
fSW = fSYNCLK / 2
Table 8. How to set up SYNCLK
Mode ROSC SYNCLK
Master ROSC < 60 kΩ Output
Slave Floating (not connected) Input
Figure 54. Master and slave connection
SYNCLK ROSC
Rosc
Cosc
ROSC SYNCLK
39 k
100 nF
Output Input
evalSretsaM
TDA7491HV TDA7491HV
8.5 Modulation
The output modulation scheme of the BTL is called unipolar pulse width modulation (PWM).
The differential output voltages change between 0 V and +VCC and between 0 V and -VCC.
This is in contrast to the traditional bipolar PWM outputs which change between +VCC
and -VCC. An advantage of this scheme is that it effectively doubles the switching frequency of the differential
output waveform on the load then reducing the current ripple accordingly. The OUTP and OUTN are in the same
phase almost overlapped when the input is zero under this condition, then the switching current is low and the
related losses in the load are low.
In practice, a short delay is introduced between these two outputs in order to avoid the BTL output switching
simultaneously when the input is zero.
Figure below shows the resulting differential output voltage and current when a positive, zero and negative input
signal is applied. The resulting differential voltage on the load has a double frequency with respect to outputs
OUTP and OUTN, resulting in reduced current ripple.
TDA7491HV
Modulation
DS5624 - Rev 9 page 36/50
Figure 55. Unipolar PWM output
8.6 Reconstruction low-pass filter
Standard applications use a low-pass filter before the speaker. The cut-off frequency should be higher than 22
kHz and much lower than the output switching frequency. It is necessary to choose the L-C component values
depending on the loud speaker impedance. Some typical values, which give a cut-off frequency of 27 kHz, are
shown in figures below.
Figure 56. Typical LC filter for an 8 Ω speaker
TDA7491HV
Reconstruction low-pass filter
DS5624 - Rev 9 page 37/50
Figure 57. Typical LC filter for an 4 Ω speaker
8.7 Protection functions
The TDA7491HV is fully protected against undervoltage, overcurrent and thermal overloads as explained here.
Undervoltage protection (UVP)
If the supply voltage drops below the value of VUVP given in Section 4 Electrical specifications the undervoltage
protection is active and forces the outputs to the high-impedance state. When the supply voltage recovers, the
device restarts.
Overcurrent protection (OCP)
If the output current exceeds the value for IOCP given in Section 4 Electrical specifications, the overcurrent
protection is active and forces the outputs to the high-impedance state. Periodically, the device tries to restart. If
the overcurrent condition is still present then the OCP remains active. The restart time, TOC, is determined by the
R-C components connected to pin STBY.
Thermal protection (OTP)
If the junction temperature, Tj, reaches 145 °C (nominal), the device goes to mute mode and the positive and
negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for Tj, given in
Section 4 Electrical specifications, the device shuts down and the output is forced to the high-impedance state.
When the device cools sufficiently the device restarts.
8.8 Diagnostic output
The output pin DIAG is an open-drain transistor. When the protection is activated it is in the high-impedance state.
The pin can be connected to a power supply (<18 V) by a pull-up resistor whose value is limited by the maximum
sinking current (200 µA) of the pin.
Figure 58. Behavior of pin DIAG for various protection conditions
TDA7491HV
Protection logic
R1
DIAG
VDD
VDD
Overcurrent
protection
Restart Restart
OV, UV, OT
protection
TDA7491HV
Protection functions
DS5624 - Rev 9 page 38/50
8.9 Heatsink requirements
Due to the high efficiency of the class-D amplifier a 2-layer PCB can easily provide the heatsinking capability for
low to medium power outputs. Using such a PCB with a copper ground layer of 3x3 cm2 and 16 vias connecting it
to the contact area for the exposed pad, a thermal resistance, junction-to-ambient (in natural air convection), of 24
°C/W can be achieved.
The dissipated power within the device depends primarily on the supply voltage, load impedance and output
modulation level. With the TDA7491HV driving 2 x 8 Ω with a supply of 18 V then the device dissipation is
approximately 4 W that gives with the above mentioned PCB a junction temperature rise of about 90 °C.
With a musical program, the dissipated power is about 40% less than the above maximum value. This leads to a
junction temperature increase of around 60 °C. So even at the maximum recommended ambient temperature
there is a margin of safety before the maximum junction temperature is reached.
Figure below shows the derating curves for copper areas of 4 cm2 and 9 cm2.
Figure 59. Power derating curves for PCB used as heatsink
0
1
2
3
4
5
6
7
8
0 20 40 60 80 100 120 140 160
Pd (W)
Tamb ( °C)
Copper Area 2x2 cm
and via holes
TDA7491HV
PSSO-36
Copper Area 3x3 cm
and via holes
TDA7491HV
Heatsink requirements
DS5624 - Rev 9 page 39/50
9Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
9.1 PowerSSO-36 EPD
Figure 60. PowerSSO-36 EPD package outline
TDA7491HV
Package information
DS5624 - Rev 9 page 40/50
Table 9. PowerSSO-36 EPD package dimensions
Symbol
mm Inches
Min. Typ. Max. Min. Typ.
A 2.15 2.47 0.085 0.097
A2 2.15 2.40 0.085 0.094
a1 0.00 0.10 0.000 0.004
b 0.18 0.36 0.007 0.014
c 0.23 0.32 0.009 0.013
D 10.10 10.50 0.398 0.413
E 7.40 7.60 0.291 0.299
e 0.5 0.020
e3 8.5 0.335
F 2.3 0.091
G 0.10 0.004
H 10.10 10.50 0.398 0.413
h 0.40 0.016
k 0 8 degrees 0 8 degrees
L 0.60 1.00 0.024 0.039
M 4.30 0.169
N 10 degrees 10 degrees
O 1.20 0.047
Q 0.80 0.031
S 2.90 0.114
T 3.65 0.144
U 1.00 0.039
X 4.10 4.70 0.161 0.185
Y 4.90 7.10 0.193 0.280
TDA7491HV
PowerSSO-36 EPD
DS5624 - Rev 9 page 41/50
9.2 PowerSSO-36 with exposed pad up
Figure 61. PowerSSO-36 EPU package outline
7618147_6
TDA7491HV
PowerSSO-36 with exposed pad up
DS5624 - Rev 9 page 42/50
Table 10. PowerSSO-36 EPU package mechanical data
Symbol
mm Inches
Min. Typ. Max. Min. Typ. Max.
A 2.15 - 2.45 0.085 - 0.096
A2 2.15 - 2.35 0.085 - 0.093
a1 0 - 0.10 0 - 0.004
b 0.18 - 0.36 0.007 - 0.014
c 0.23 - 0.32 0.009 - 0.013
D 10.10 - 10.50 0.398 - 0.413
E 7.40 - 7.60 0.291 - 0.299
e - 0.5 - - 0.020 -
e3 - 8.5 - - 0.335 -
F - 2.3 - - 0.091 -
G - - 0.10 - - 0.004
H 10.10 - 10.50 0.398 - 0.413
h - - 0.40 - - 0.016
k 0 - 8 degrees - - 8 degrees
L 0.60 - 1.00 0.024 - 0.039
M - 4.30 - - 0.169 -
N - - 10 degrees - - 10 degrees
O - 1.20 - - 0.047 -
Q - 0.80 - - 0.031 -
S - 2.90 - - 0.114 -
T - 3.65 - - 0.144 -
U - 1.00 - - 0.039 -
X 4.10 - 4.70 0.161 - 0.185
Y 6.50 - 7.10 0.256 - 0.280
TDA7491HV
PowerSSO-36 with exposed pad up
DS5624 - Rev 9 page 43/50
Revision history
Table 11. Document revision history
Date Revision Changes
02-Jul-2008 1 Initial release.
03-Oct-2008 2
Updated AMR table
Updated Chapter 4: Characterization curves on page 12
Added Figure 48: Test board (TDA7491HV) layout on page 29
Updated Figure 49: PowerSSO-36 EPD outline drawing on page 30 and Table 6:
PowerSSO-36 EPD dimensions on page 31
Updated Figure 50: Applications circuit for class-D amplifier on page 32
29-Jun-2009 3
Updated text concerning oscillator R and C in Section 3.3: Electrical specifications on
page 10
Updated VOVP minimum value, added VUVP maximum value, updated STBY and MUTE
voltages in Table 5: Electrical specifications on page 10
Updated equation for fSW Table 5 on page 10
Updated Figure 50: Applications circuit for class-D amplifier on page 32
03-Sep-2009 4
Added text for exposed pad in Figure 2 on page 8
Added text for exposed pad in Table 2 on page 9
Updated exposed pad Y (Min) dimension in Table 6 on page 31
Updated supply voltage for pin DIAG pull-up resistor in Section 7.8 on page 40.
24-Mar-2011 5
Updated Features
Updated Section 3: Electrical specifications
Removed filter less operation
Extended the temperature range to -40 to +85°C.
12Sep-2011 6 Updated OUTNA in Table 2: Pin description list
20-Feb-2014 7 Updated order code Table 1 on page 1
04-Jul-2018 8 Added PowerSSO-36 EPU silhouette in cover page, Section 2.3 Pinout (EPU), Section
2.4 Pin list (EPU) and Section 9.2 PowerSSO-36 with exposed pad up.
05-Oct-2018 9 Updated product summary table in cover page.
TDA7491HV
DS5624 - Rev 9 page 44/50
Contents
1Device block diagram..............................................................2
2Pin description ....................................................................3
2.1 Pinout (EPD) ..................................................................3
2.2 Pin list (EPD) ..................................................................4
2.3 Pinout (EPU) ..................................................................5
2.4 Pin list (EPU) ..................................................................6
3Absolute maximum ratings ........................................................7
4Electrical specifications ...........................................................8
5Characterization curves...........................................................10
5.1 4 Ω load at VCC = 14 V ........................................................10
5.2 6 Ω load at VCC = 16 V ........................................................15
5.3 8 Ω load at VCC = 18 V ........................................................22
6Test board ........................................................................31
7Application circuit ................................................................32
8Application information...........................................................33
8.1 Mode selection ...............................................................33
8.2 Gain setting ..................................................................34
8.3 Input resistance and capacitance ................................................35
8.4 Internal and external clocks .....................................................35
8.4.1 Master mode (internal clock) ...............................................35
8.4.2 Slave mode (external clock) ...............................................36
8.5 Modulation ...................................................................36
8.6 Reconstruction low-pass filter ...................................................37
8.7 Protection functions ...........................................................38
8.8 Diagnostic output..............................................................38
8.9 Heatsink requirements .........................................................38
9Package information..............................................................40
9.1 PowerSSO-36 exposed pad down ...............................................40
9.2 PowerSSO36 EPU package information ..........................................41
TDA7491HV
Contents
DS5624 - Rev 9 page 45/50
List of tables
Table 1. Pin description list ...................................................................4
Table 2. Pin description list ...................................................................6
Table 3. Absolute maximum ratings .............................................................7
Table 4. Thermal data.......................................................................7
Table 5. Electrical specifications ...............................................................8
Table 6. Mode settings ..................................................................... 33
Table 7. Gain settings ...................................................................... 34
Table 8. How to set up SYNCLK............................................................... 36
Table 9. PowerSSO-36 EPD package dimensions .................................................. 41
Table 10. PowerSSO-36 EPU package mechanical data ............................................... 43
Table 11. Document revision history ............................................................. 44
TDA7491HV
List of tables
DS5624 - Rev 9 page 47/50
List of figures
Figure 1. Internal block diagram (showing one channel only) ...........................................2
Figure 2. Pin connections (top view, PCB view) ...................................................3
Figure 3. Pin connections (top view, PCB view) ...................................................5
Figure 4. Output power vs. supply voltage ....................................................... 10
Figure 5. THD vs. output power (1 kHz)......................................................... 10
Figure 6. THD vs. output power (100 Hz)........................................................ 11
Figure 7. THD vs. frequency ................................................................ 11
Figure 8. Frequency response ............................................................... 12
Figure 9. Crosstalk vs. frequency ............................................................. 12
Figure 10. FFT performance (0 dB) ............................................................ 12
Figure 11. FFT performance (-60 dB) ........................................................... 13
Figure 12. Power supply rejection ratio vs. frequency ................................................ 13
Figure 13. Power dissipation and efficiency vs. output power ........................................... 13
Figure 14. Closed-loop gain vs. frequency ........................................................ 14
Figure 15. Current consumption vs. voltage on pin MUTE ............................................. 14
Figure 16. Attenuation vs. voltage on pin MUTE .................................................... 14
Figure 17. Current consumption vs. voltage on pin STBY ............................................. 15
Figure 18. Attenuation vs. voltage on pin STBY .................................................... 15
Figure 19. Output power vs. supply voltage ....................................................... 16
Figure 20. THD vs. output power (1 kHz)......................................................... 16
Figure 21. THD vs. output power (100 Hz)........................................................ 17
Figure 22. THD vs. frequency ................................................................ 17
Figure 23. Frequency response ............................................................... 18
Figure 24. Crosstalk vs. frequency ............................................................. 18
Figure 25. FFT performance (0 dB) ............................................................ 19
Figure 26. FFT performance (-60 dB) ........................................................... 19
Figure 27. Power supply rejection ratio vs. frequency ................................................ 20
Figure 28. Power dissipation and efficiency vs. output power ........................................... 20
Figure 29. Closed-loop gain vs. frequency ........................................................ 20
Figure 30. Current consumption vs. voltage on pin MUTE ............................................. 21
Figure 31. Attenuation vs. voltage on pin MUTE .................................................... 21
Figure 32. Current consumption vs. voltage on pin STBY ............................................. 22
Figure 33. Attenuation vs. voltage on pin STBY .................................................... 22
Figure 34. Output power vs. supply voltage ....................................................... 23
Figure 35. THD vs. output power (1 kHz)......................................................... 23
Figure 36. THD vs. output power (100 Hz)........................................................ 24
Figure 37. THD vs. frequency ................................................................ 24
Figure 38. Frequency response ............................................................... 25
Figure 39. Crosstalk vs. frequency ............................................................. 25
Figure 40. FFT performance (0 dB) ............................................................ 26
Figure 41. FFT performance (-60 dB) ........................................................... 26
Figure 42. Power supply rejection ratio vs. frequency ................................................ 27
Figure 43. Power dissipation and efficiency vs. output power ........................................... 27
Figure 44. Closed-loop gain vs. frequency ........................................................ 28
Figure 45. Current consumption vs. voltage on pin MUTE ............................................. 28
Figure 46. Attenuation vs. voltage on pin MUTE .................................................... 29
Figure 47. Current consumption vs. voltage on pin STBY ............................................. 29
Figure 48. Attenuation vs. voltage on pin STBY .................................................... 30
Figure 49. Test board (TDA7491HV) layout ....................................................... 31
Figure 50. Application circuit for class-D amplifier................................................... 32
Figure 51. Standby and mute circuits ........................................................... 33
Figure 52. Turn-on/off sequence for minimizing speaker “pop” .......................................... 34
TDA7491HV
List of figures
DS5624 - Rev 9 page 48/50
Figure 53. Device input circuit and frequency response ............................................... 35
Figure 54. Master and slave connection ......................................................... 36
Figure 55. Unipolar PWM output .............................................................. 37
Figure 56. Typical LC filter for an 8 Ω speaker ..................................................... 37
Figure 57. Typical LC filter for an 4 Ω speaker ..................................................... 38
Figure 58. Behavior of pin DIAG for various protection conditions ........................................ 38
Figure 59. Power derating curves for PCB used as heatsink ........................................... 39
Figure 60. PowerSSO-36 EPD package outline .................................................... 40
Figure 61. PowerSSO-36 EPU package outline .................................................... 42
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