DACx578
Data Buffer A DAC Register A
Buffer Control Register Control
Control Logic
Input Control Logic
Power-Down
Control Logic
AVDD VREFIN
8-/10-/12-Bit
DAC
CLRLDACADDR0
SDA
SCL
Data Buffer B DAC Register B
Data Buffer C
Data Buffer D
Data Buffer E
Data Buffer F
Data Buffer G
DAC Register C
DAC Register D
DAC Register E
DAC Register F
DAC Register G
V H
OUT
Data Buffer H DAC Register H
V G
OUT
V F
OUT
V E
OUT
V D
OUT
V C
OUT
V B
OUT
V A
OUT
GNDADDR1
8-/10-/12-Bit
DAC
8-/10-/12-Bit
DAC
8-/10-/12-Bit
DAC
8-/10-/12-Bit
DAC
8-/10-/12-Bit
DAC
8-/10-/12-Bit
DAC
8-/10-/12-Bit
DAC
RSTSEL
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
8-/10-/12-Bit, Octal-Channel, Ultra-Low Glitch, Voltage Output, Two-Wire Interface
Digital-to-Analog Converters
Check for Samples: DAC5578,DAC6578,DAC7578
1FEATURES DESCRIPTION
23• Relative Accuracy: The DAC5578 (8 bit), DAC6578 (10 bit), and
DAC7578 (12 bit) are low-power, voltage-output, octal
– DAC5578 (8 bit): 0.25LSB INL channel, digital-to-analog converters (DACs). The
– DAC6578 (10 bit): 0.5LSB INL devices are monolithic, provide good linearity,and
– DAC7578 (12 bit): 1LSB INL minimize undesired code-to-code transient voltages
• Glitch Energy: 0.15nV-s (glitch).
• Power-On Reset to Zero Scale or Midscale The devices use a versatile, 2-wire serial interface
that is I2C-compatible and operates at clock rates of
– Devices in the TSSOP Package Reset to up to 3.4MHz. Multiple devices can share the same
Zero Scale bus.
– Devices in the QFN Package Reset to Zero The devices incorporate a power-on-reset (POR)
Scale or Midscale circuit that ensures the DAC output powers up to
• Ultra-Low Power Operation: 0.13mA/ch at 5V zero-scale or midscale until a valid code is written to
• Wide Power-Supply Range: +2.7V to +5.5V the device. These devices also contain a power-down
• 2-Wire Serial Interface ( I2C™ compatible) feature, accessed through the serial interface, that
reduces the current consumption of the devices to
• Temperature Range: –40°C to +125°C typically 0.42mA at 5V. Power consumption is typically
2.32mW at 3V, reducing to 0.68mW in power-down
APPLICATIONS mode. The low power consumption and small
• Portable Instrumentation footprint make these devices ideal for portable,
• Closed-Loop Servo Control battery-operated equipment.
• Process Control The DAC5578,DAC6578, and DAC7578 are drop-in
• Data Acquisition Systems and functionally-compatible with the DAC7678. All
devices are available in a 4x4, QFN-24 package and
a TSSOP-16 package.
RELATED DEVICES 8-BIT 10-BIT 12-BIT
Pin- and Function-Compatible — — DAC7678
(w/internal reference)
Pin- and Function-Compatible DAC5578 DAC6578 DAC7578
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2I2C is a trademark of NXP Semiconductors.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
MAXIMUM
MAXIMUM RELATIVE SPECIFIED
DIFFERENTIAL PACKAGE- PACKAGE PACKAGE
PRODUCT ACCURACY TEMPERATURE
NONLINEARITY LEAD DESIGNATOR MARKING
(LSB) RANGE
(LSB)
TSSOP-16 PW DAC7578
DAC7578 ±1 ±0.25 –40°C to +125°C
QFN-24 RGE DAC7578
TSSOP-16 PW DAC6578
DAC6578 ±0.5 ±0.5 –40°C to +125°C
QFN-24 RGE DAC6578
TSSOP-16 PW DAC5578
DAC5578 ±0.25 ±0.25 –40°C to +125°C
QFN-24 RGE DAC5578
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted. DAC5578, DAC6578, DAC7578 UNIT
AVDD to GND –0.3 to +6 V
Digital input voltage to GND –0.3 to +AVDD + 0.3 V
VOUT to GND –0.3 to +AVDD + 0.3 V
VREFIN to GND –0.3 to +AVDD + 0.3 V
Operating temperature range –40 to +125 °C
Storage temperature range –65 to +150 °C
Junction temperature range (TJmax) +150 °C
Power dissipation (TJmax – TA)/qJA W
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
THERMAL INFORMATION DACx578
THERMAL METRIC(1) UNITS
PW (16 Pins) RGE (24 PINS)
qJA Junction-to-ambient thermal resistance 111.9 33.7
qJCtop Junction-to-case (top) thermal resistance 33.3 16.9
qJB Junction-to-board thermal resistance 52.4 7.4 °C/W
yJT Junction-to-top characterization parameter 2 0.5
yJB Junction-to-board characterization parameter 51.2 7.1
qJCbot Junction-to-case (bottom) thermal resistance n/a 1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
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DAC6578
DAC7578
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SBAS496A –MARCH 2010–REVISED AUGUST 2010
ELECTRICAL CHARACTERISTICS
At AVDD = 2.7V to 5.5V and over –40°C to +125°C, unless otherwise noted. DAC5578, DAC6578, DAC7578
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
STATIC PERFORMANCE(1)
Resolution 8 Bits
DAC5578 Relative accuracy Measured by the line passing through codes 4 and 250 ±0.01 ±0.25 LSB
Differential nonlinearity ±0.01 ±0.25 LSB
Resolution 10 Bits
Measured by the line passing through codes 12 and
DAC6578 Relative accuracy ±0.06 ±0.5 LSB
1012
Differential nonlinearity ±0.03 ±0.5 LSB
Resolution 12 Bits
Measured by the line passing through codes 30 and
DAC7578 Relative accuracy ±0.3 ±1 LSB
4050
Differential nonlinearity ±0.1 ±0.25 LSB
Extrapolated from two-point line passing through two
Offset error 0.5 ±4 mV
codes(2), unloaded
Offset error drift 3 mV/°C
Full-scale error DAC register loaded with all '1's ±0.03 ±0.2 % of FSR
Full-scale error drift 2 mV/°C
Zero-code error DAC register loaded with all '0's 1 4 mV
Zero-code error drift 2 mV/°C
Extrapolated from two-point line passing through two
Gain error ±0.01 ±0.15 % of FSR
codes(2), unloaded
ppm of
Gain temperature coefficient ±1 FSR/°C
OUTPUT CHARACTERISTICS(3)
Output voltage range 0 AVDD V
DACs unloaded, 1/4 scale to 3/4 scale 7 ms
Output voltage settling time RL= 1MΩand CL= 470pF 12 ms
Slew rate 0.75 V/ms
RL=∞470 pF
Capacitive load stability RL= 2kΩ1000 pF
Code change glitch impulse 1LSB change around major carry 0.15 nV-s
Digital feedthrough SCL toggling 1.5 nV-s
Power-on glitch RL=∞3 mV
Channel-to-channel dc crosstalk Full-scale swing on adjacent channel 0.1 LSB
DC output impedance At midscale input 4.5 Ω
Short-circuit current DAC outputs shorted to GND 25 mA
Power-up time (including settling time) Coming out of power-down mode, AVDD = 5V 50 ms
(1) Linearity calculated using a reduced code range; output unloaded.
(2) 12-bit: 30 and 4050; 10-bit: 12 and 1012; 8-bit: 4 and 250
(3) Specified by design or characterization; not production tested.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): DAC5578 DAC6578 DAC7578
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At AVDD = 2.7V to 5.5V and over –40°C to +125°C, unless otherwise noted. DAC5578, DAC6578, DAC7578
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
AC PERFORMANCE(4)
DAC output noise density TA= +25°C, at zero-code input, fOUT = 1kHz 20 nV/√Hz
DAC output noise TA= +25°C, at midscale input, f = 0.1Hz to 10Hz 3 mVPP
EXTERNAL REFERENCE
External reference current AVDD = 2.7V to 5.5V 60 µA
LOGIC INPUTS(4)
Input current ±1 mA
VINL Logic input LOW voltage 2.7V ≤AVDD ≤5.5V GND-0.3 0.3xAVDD V
VINH Logic input HIGH voltage 2.7V ≤AVDD ≤5.5V 0.7xAVDD AVDD+0.3 V
Pin capacitance 1.5 3 pF
POWER REQUIREMENTS
AVDD Analog power supply 2.7 5.5 V
AVDD = 3.6V to 5.5V 1.02 1.4 mA
VINH = AVDD and VINL = GND
Normal mode AVDD = 2.7V to 3.6V 0.86 1.3 mA
VINH = AVDD and VINL = GND
IDD (5) AVDD = 3.6V to 5.5V 0.42 6 mA
VINH = AVDD and VINL = GND
All power-down modes AVDD = 2.7V to 3.6V 0.25 4.7 mA
VINH = AVDD and VINL = GND
AVDD = 3.6V to 5.5V 3.67 7.7 mW
VINH = AVDD and VINL = GND
Normal mode AVDD = 2.7V to 3.6V 2.32 4.68 mW
VINH = AVDD and VINL = GND
Power
dissipation(5) AVDD = 3.6V to 5.5V 1.51 33 mW
VINH = AVDD and VINL = GND
All power-down modes AVDD = 2.7V to 3.6V 0.68 16.92 mW
VINH = AVDD and VINL = GND
TEMPERATURE RANGE
Specified performance –40 +125 °C
(4) Specified by design or characterization; not production tested.
(5) Input code = mid scale, no load.
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Product Folder Link(s): DAC5578 DAC6578 DAC7578
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCL
SDA
GND
V B
OUT
V D
OUT
V F
OUT
V H
OUT
CLR
LDAC
ADDR0
AVDD
V A
OUT
V C
OUT
V E
OUT
V G
OUT
VREFIN
DACx578
NC
AVDD
V A
OUT
V C
OUT
V E
OUT
V G
OUT
NC
GND
V B
OUT
V D
OUT
V F
OUT
V H
OUT
1
2
3
4
5
6
18
17
16
15
14
13
DACx578
7 8 9 10 11 12
24 23 22 21 20 19
NC
VREFIN
RSTSEL
ADDR1
ADDR0
CLR
NC
NC
LDAC
TWOC
SCL
SDA
(Thermal pad) 1
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
PIN CONFIGURATIONS
PW PACKAGE RGE PACKAGE
TSSOP-16 QFN-24
(TOP VIEW) (TOP VIEW)
(1) It is recommended to connect the thermal
pad to GND for better thermal dissipation.
PIN DESCRIPTIONS
PACKAGE NAME DESCRIPTION
16-Pin 24-PIN
1 22 LDAC Load DACs
2 11 ADDR0 3-state address input
3 2 AVDD Power-supply input, 2.7V to 5.5V
4 3 VOUTA Analog output voltage from DAC A
5 4 VOUTC Analog output voltage from DAC C
6 5 VOUTE Analog output voltage from DAC E
7 6 VOUTG Analog output voltage from DAC G
8 8 VREFIN Positive reference input
9 12 CLR Asynchronous clear input
10 13 VOUTH Analog output voltage from DAC H
11 14 VOUTF Analog output voltage from DAC F
12 15 VOUTD Analog output voltage from DAC D
13 16 VOUTB Analog output voltage from DAC B
14 17 GND Ground reference point for all circuitry on the device
Serial data input. Data are clocked into or out of the input register. This pin is a bidirectional,
15 19 SDA open-drain data line that should be connected to the supply voltage with an external pull-up resistor.
16 20 SCL Serial clock input. Data can be transferred at rates up to 3.4MHz. Schmitt-trigger logic input.
— 1 NC Not internally connected
— 7 NC Not internally connected
— 9 RSTSEL Reset select pin. RSTSEL high resets device to mid-scale; RSTSEL low resets device to zero-scale.
— 10 ADDR1 3-state address input
— 18 NC Not internally connected
Twos complement select. If the TWOC pin is pulled high, the DAC registers use twos complement
— 21 TWOC format; if TWOC is pulled low, the DAC registers use straight binary format.
— 23 NC Not internally connected
— 24 NC Not internally connected
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): DAC5578 DAC6578 DAC7578
LDAC1
LDAC2
CLR
Low Byte Ack Cycle
P S
tHD:STA
tHD:DAT tSU:DAT
tSU:STA
tHD:STA
S P
SCL
SDA
tLOW
tRtF
tBUF
tSU:STO
t1
t2
t3
t4
tHIGH
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
TIMING DIAGRAM
(1) Asynchronous LDAC update mode. For more information and details, see the LDAC Functionality section.
(2) Synchronous LDAC update mode. For more information and details, see the LDAC Functionality section.
Figure 1. Serial Write Operation
TIMING REQUIREMENTS(1)
At AVDD = 2.7 V to 5.5 V and –40°C to +125°C range (unless otherwise noted).
STANDARD FAST HIGH SPEED
MODE MODE MODE
PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
SCL frequency, fSCL 0.1 0.4 3.4 MHz
Bus free time between STOP and START conditions, tBUF 4.7 1.3 µs
Hold time after repeated start, tHDSTA 4 0.6 0.16 µs
Repeated Start setup time, tSUSTA 4.7 0.6 0.16 µs
STOP condition setup time, tSUSTO 4 0.6 0.16 µs
Data hold time, tHDDAT 0 0 0 ns
Data setup time, tSUDAT 250 100 10 ns
SCL clock LOW period, tLOW 4700 1300 160 ns
SCL clock HIGH period, tHIGH 4000 600 60 ns
Clock/Data fall time, tF300 300 160 ns
Clock/Data rise time, tR1000 300 160 ns
LDAC pulse width LOW time, t140 10 1.2 µs
SCL falling edge to LDAC falling edge for asynchronous LDAC update, t220 5 0.6 µs
LDAC falling edge to SCL falling edge for synchronous LDAC update, t3360 90 10.5 µs
CLR pulse width LOW time, t440 10 1.2 µs
(1) See the Serial Write Operation timing diagram.
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Digital Input Code
INL Error (LSB)
0 512 1024 1536 2048 2560 3072 3584 4096
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-0.8
-0.4
0.4
0.8 All Eight Channels Shown
External Reference = 5V
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
Digital Input Code
DNL Error (LSB)
0 512 1024 1536 2048 2560 3072 3584 4096
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 5V
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
Digital Input Code
INL Error (LSB)
0 512 1024 1536 2048 2560 3072 3584 4096
-1.0
-0.8
-0.6
-0.4
-0.2
0.2
0.4
0.6
0.8
1.0
-0.8
-0.4
0.0
0.4
0.8 All Eight Channels Shown
External Reference = 5V
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
Digital Input Code
DNL Error (LSB)
0 512 1024 1536 2048 2560 3072 3584 4096
-0.25
-0.20
-0.15
-0.05
0.05
0.15
0.25
-0.10
0.00
0.10
0.20 All Eight Channels Shown
External Reference = 5V
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
Digital Input Code
INL Error (LSB)
0 512 1024 1536 2048 2560 3072 3584 4096
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-0.8
-0.4
0.4
0.8 All Eight Channels Shown
External Reference = 5V
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
Digital Input Code
DNL Error (LSB)
0 512 1024 1536 2048 2560 3072 3584 4096
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 5V
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC7578, 12-Bit, –40°C) vs DIGITAL INPUT CODE (DAC7578, 12-Bit, –40°C)
Figure 2. Figure 3.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC7578, 12-Bit, +25°C) vs DIGITAL INPUT CODE (DAC7578, 12-Bit, +25°C)
Figure 4. Figure 5.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC7578, 12-Bit, +125°C) vs DIGITAL INPUT CODE (DAC7578, 12-Bit, +125°C)
Figure 6. Figure 7.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Digital Input Code
INL Error (LSB)
0 128 256 384 512 640 768 896 1024
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 All Eight Channels Shown
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
DNL Error (LSB)
0 128 256 384 512 640 768 896 1024
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 All Eight Channels Shown
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
INL Error (LSB)
0 128 256 384 512 640 768 896 1024
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 All Eight Channels Shown
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
DNL Error (LSB)
0 128 256 384 512 640 768 896 1024
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 All Eight Channels Shown
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
INL Error (LSB)
0 128 256 384 512 640 768 896 1024
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 All Eight Channels Shown
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
DNL Error (LSB)
0 128 256 384 512 640 768 896 1024
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 All Eight Channels Shown
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC6578, 10-Bit, -40°C) vs DIGITAL INPUT CODE (DAC6578, 10-Bit, -40°C)
Figure 8. Figure 9.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC6578, 10-Bit, +25°C) vs DIGITAL INPUT CODE (DAC6578, 10-Bit, +25°C)
Figure 10. Figure 11.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC6578, 10-Bit, +125°C) vs DIGITAL INPUT CODE (DAC6578, 10-Bit, +125°C)
Figure 12. Figure 13.
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Product Folder Link(s): DAC5578 DAC6578 DAC7578
Digital Input Code
INL Error (LSB)
0 32 64 96 128 160 192 224 256
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
DNL Error (LSB)
0 32 64 96 128 160 192 224 256
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
INL Error (LSB)
0 32 64 96 128 160 192 224 256
-0.25
-0.20
-0.15
-0.10
-0.05
0.05
0.10
0.15
0.20
0.25
0.00
All Eight Channels Shown
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
DNL Error (LSB)
0 32 64 96 128 160 192 224 256
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
INL Error (LSB)
0 32 64 96 128 160 192 224 256
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
DNL Error (LSB)
0 32 64 96 128 160 192 224 256
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC5578, 8-Bit, -40°C) vs DIGITAL INPUT CODE (DAC5578, 8-Bit, -40°C)
Figure 14. Figure 15.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC5578, 8-Bit, +25°C) vs DIGITAL INPUT CODE (DAC5578, 8-Bit, +25°C)
Figure 16. Figure 17.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC5578, 8-Bit, +125°C) vs DIGITAL INPUT CODE (DAC5578, 8-Bit, +125°C)
Figure 18. Figure 19.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Temperature ( C)°
INL Error (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-0.8
-0.4
0.4
0.8 External Reference = 5V
INL MIN
INL MAX
Temperature ( C)°
DNL Error (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
External Reference = 5V
DNL MAX
DNL MIN
Temperature ( C)°
INL Error (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 External Reference = 5V
INL MIN
INL MAX
Temperature ( C)°
DNL Error (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 External Reference = 5V
DNL MIN
DNL MAX
Temperature ( C)°
INL Error (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
External Reference = 5V
INL MIN
INL MAX
Temperature ( C)°
DNL Error (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
External Reference = 5V
DNL MIN
DNL MAX
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE (DAC7578, 12-Bit) vs TEMPERATURE (DAC7578, 12-Bit)
Figure 20. Figure 21.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE (DAC6578, 10-Bit) vs TEMPERATURE (DAC6578, 10-Bit)
Figure 22. Figure 23.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE (DAC5578, 8-Bit) vs TEMPERATURE (DAC5578, 8-Bit)
Figure 24. Figure 25.
10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Temperature ( C)°
Offset Error (mV)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-4
-3
-2
-1
0
1
2
3
4
External Reference = 5V
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
Temperature ( C)°
Power Supply Current (μA)
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
1
2
3
4
5
6
External Reference = 5V
Temperature ( C)°
Full-Scale Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Temperature ( C)°
Gain Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
External Reference = 5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
POWER SUPPLY CURRENT OFFSET ERROR
vs TEMPERATURE vs TEMPERATURE
Figure 26. Figure 27.
POWER-DOWN CURRENT FULL-SCALE ERROR
vs TEMPERATURE vs TEMPERATURE
Figure 28. Figure 29.
GAIN ERROR
vs TEMPERATURE
Figure 30.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Source Current (mA)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
4.80
4.85
4.90
4.95
5.00
Channel C
DAC Loaded With FFFh
Sink Current (mA)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Channel C
DAC Loaded With 000h
Source Current (mA)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
4.80
4.85
4.90
4.95
5.00
Channel D
DAC Loaded With FFFh
Sink Current (mA)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Channel D
DAC Loaded With 000h
Source Current (mA)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
4.80
4.85
4.90
4.95
5.00
Channel H
DAC Loaded With FFFh
Sink Current (mA)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Channel H
DAC Loaded With 000h
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
SOURCE CURRENT SINK CURRENT
AT POSITIVE RAIL AT NEGATIVE RAIL
Figure 31. Figure 32.
SOURCE CURRENT SINK CURRENT
AT POSITIVE RAIL AT NEGATIVE RAIL
Figure 33. Figure 34.
SOURCE CURRENT SINK CURRENT
AT POSITIVE RAIL AT NEGATIVE RAIL
Figure 35. Figure 36.
12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Digital Input Code
Power Supply Current (mA)
0 512 1024 1536 2048 2560 3072 3584 4096
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.0
0.4
0.8
External Reference = 5V
Code Loaded to all Eight DAC Channels
Power Supply Voltage (V)
Power Supply Current ( A)m
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
AV = 2.7V to 5.5V
DD
% of Population
0
2
4
6
8
10
12
14
0.90
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
1.11
1.12
1.13
1.14
1.15
External Reference = 5V
Supply Current (mA)
Zoomed Rising Edge
100 V/divm
Rising Edge
2 V/div
Trigger Pulse
5 V/div
Time (5 s/div)m
From Code 000h to FFFh
Zoomed Falling Edge
100 V/divm
Falling Edge
2 V/div
Trigger Pulse
5 V/div
Time (5 s/div)m
From Code FFFh to 000h
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
POWER SUPPLY CURRENT POWER SUPPLY CURRENT
vs DIGITAL INPUT CODE vs POWER SUPPLY VOLTAGE
Figure 37. Figure 38.
POWER-SUPPLY CURRENT
POWER DOWN CURRENT
vs POWER SUPPLY VOLTAGE HISTOGRAM
Figure 39. Figure 40.
FULL-SCALE SETTLING TIME: FULL-SCALE SETTLING TIME:
5V RISING EDGE 5V FALLING EDGE
Figure 41. Figure 42.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Zoomed Rising Edge
100 V/divm
Rising Edge
2 V/div
Trigger Pulse
5 V/div
Time (5 s/div)m
From Code 400h to C00h
Zoomed Falling Edge
100 V/divm
Falling Edge
2 V/div
Trigger Pulse
5 V/div
Time (5 s/div)m
From Code C00h to 400h
V - 2 mV/div
OUT
AV - 2 V/div
DD
Time (10 ms/div)
~2 mVPP
DAC Unloaded
DAC at Zero Scale
G045
AV = 5.5 V,
Clock Feedthrough Impulse ~1.5 nV-s
DD
t - Time - 1 s/divm
V - 5 mV/div
OUT
SCL - 5 V/div
V - 2 V/div
OUT
AV - 2 V/div
DD
Time (20 ms/div)
DAC Unloaded
DAC at Zero Scale
V - 1 mV/div
OUT
AV - 2 V/div
DD
Time (10 ms/div)
DAC Unloaded
DAC at Zero Scale
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
HALF-SCALE SETTLING TIME: HALF-SCALE SETTLING TIME:
5V RISING EDGE 5V FALLING EDGE
Figure 43. Figure 44.
CLOCK FEEDTHROUGH POWER-ON GLITCH
400 kHz MIDSCALE RESET TO ZERO SCALE
Figure 45. Figure 46.
POWER-ON GLITCH
RESET-TO-MID SCALE POWER-OFF GLITCH
Figure 47. Figure 48.
14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5578 DAC6578 DAC7578
LDAC Clock
Feed-Through
V - 500 V/div
OUT m
LDAC - Trigger Pulse
5 V/div
Time (2 s/div)m
From Code 801h to 800h
V - 500 V/div
OUT m
LDAC - Trigger Pulse
5 V/div
From Code 800h to 801h
Time (2 s/div)m
LDAC Clock
Feed-Through
Time (2 s/div)m
V - 2 mV/div
OUT
LDAC Clock
Feed-Through
From Code 200h to 201h
LDAC - Trigger Pulse
5 V/div
LDAC Clock
Feed-Through
LDAC - Trigger Pulse
5 V/div
From Code 201h to 200h
Time (2 s/div)m
V - 2 mV/div
OUT
Time (2 s/div)m
V - 5 mV/div
OUT
LDAC Clock
Feed-Through
From Code 80h to 81h
LDAC - Trigger Pulse
5 V/div
Time (2 s/div)m
V - 5 mV/div
OUT
LDAC Clock
Feed-Through
From Code 81h to 801h
LDAC - Trigger Pulse
5 V/div
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
GLITCH ENERGY: GLITCH ENERGY:
5V, 12-BIT, 1LSB STEP, RISING EDGE 5V, 12-BIT, 1LSB STEP, FALLING EDGE
Figure 49. Figure 50.
GLITCH ENERGY: GLITCH ENERGY:
5V, 10-BIT, 1LSB STEP, RISING EDGE 5V, 10-BIT, 1LSB STEP, FALLING EDGE
Figure 51. Figure 52.
GLITCH ENERGY: GLITCH ENERGY:
5V, 8-BIT, 1LSB STEP, RISING EDGE 5V, 8-BIT, 1LSB STEP, FALLING EDGE
Figure 53. Figure 54.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Frequency (Hz)
Voltage Noise (nV/√Hz)
0
50
100
150
200
250
300
20 100 100k
Zero Scale
Mid Scale
Full Scale
DAC Output Unloaded
External Reference = 5V
1k 10k
~3 VmPP
V (1 V/div)
OUT m
Time (2 s/div)
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted). DAC OUTPUT NOISE
DAC OUTPUT NOISE DENSITY
vs FREQUENCY 0.1 Hz to 10 Hz
Figure 55. Figure 56.
16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Power Supply Current - mA
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
0 512 1024 1536 2048 2560 3072 3584 4096
Digital Input Code
AV = 3.6 V,
External Reference = 3.3 V,
Code Loaded to all Eight DAC Channels
DD
0.765
0.775
0.785
0.795
0.805
0.815
0.825
0.835
0.845
0.855
0.865
0.875
0.885
0.895
0.905
0.915
0.925
0.935
0.945
0.955
0.965
0.975
AV = 3.6 V,
External Reference = 3.3 V
DD
0
2
8
14
4
6
10
12
% of Population
I - Supply Current - mA
DD
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS: DAC AT AVDD = 3.6 V
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
POWER SUPPLY CURRENT POWER SUPPLY CURRENT
vs TEMPERATURE vs DIGITAL INPUT CODE
Figure 57. Figure 58.
POWER SUPPLY CURRENT HISTOGRAM
Figure 59.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Digital Input Code
INL Error (LSB)
0 512 1024 1536 2048 2560 3072 3584 4096
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-0.8
-0.4
0.4
0.8 All Eight Channels Shown
External Reference = 2.5V
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
Digital Input Code
DNL Error (LSB)
0 512 1024 1536 2048 2560 3072 3584 4096
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 2.5V
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
Digital Input Code
INL Error (LSB)
0 512 1024 1536 2048 2560 3072 3584 4096
-1.0
-0.8
-0.6
-0.4
-0.2
0.2
0.4
0.6
0.8
1.0
-0.8
-0.4
0.0
0.4
0.8
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
Digital Input Code
DNL Error (LSB)
0 512 1024 1536 2048 2560 3072 3584 4096
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.15
0.25
0.10
0.20
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
Digital Input Code
INL Error (LSB)
0 512 1024 1536 2048 2560 3072 3584 4096
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-0.8
-0.4
0.4
0.8 All Eight Channels Shown
External Reference = 2.5V
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
Digital Input Code
DNL Error (LSB)
0 512 1024 1536 2048 2560 3072 3584 4096
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 2.5V
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC7578, 12-Bit, –40°C) vs DIGITAL INPUT CODE (DAC7578, 12-Bit, –40°C)
Figure 60. Figure 61.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC7578, 12-Bit, +25°C) vs DIGITAL INPUT CODE (DAC7578, 12-Bit, +25°C)
Figure 62. Figure 63.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC7578, 12-Bit, +125°C) vs DIGITAL INPUT CODE (DAC7578, 12-Bit, +125°C)
Figure 64. Figure 65.
18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Digital Input Code
INL Error (LSB)
0 128 256 384 512 640 768 896 1024
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 All Eight Channels Shown
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
DNL Error (LSB)
0 128 256 384 512 640 768 896 1024
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 All Eight Channels Shown
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
INL Error (LSB)
0 128 256 384 512 640 768 896 1024
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 All Eight Channels Shown
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
DNL Error (LSB)
0 128 256 384 512 640 768 896 1024
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 All Eight Channels Shown
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
INL Error (LSB)
0 128 256 384 512 640 768 896 1024
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 All Eight Channels Shown
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
DNL Error (LSB)
0 128 256 384 512 640 768 896 1024
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 All Eight Channels Shown
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC6578, 10-Bit, –40°C) vs DIGITAL INPUT CODE (DAC6578, 10-Bit, –40°C)
Figure 66. Figure 67.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC6578, 10-Bit, +25°C) vs DIGITAL INPUT CODE (DAC6578, 10-Bit, +25°C)
Figure 68. Figure 69.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC6578, 10-Bit, +125°C) vs DIGITAL INPUT CODE (DAC6578, 10-Bit, +125°C)
Figure 70. Figure 71.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Digital Input Code
INL Error (LSB)
0 32 64 96 128 160 192 224 256
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
DNL Error (LSB)
0 32 64 96 128 160 192 224 256
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
INL Error (LSB)
0 32 64 96 128 160 192 224 256
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
DNL Error (LSB)
0 32 64 96 128 160 192 224 256
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
INL Error (LSB)
0 32 64 96 128 160 192 224 256
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Digital Input Code
DNL Error (LSB)
0 32 64 96 128 160 192 224 256
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
All Eight Channels Shown
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC5578, 8-Bit, –40°C) vs DIGITAL INPUT CODE (DAC5578, 8-Bit, –40°C)
Figure 72. Figure 73.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC5578, 8-Bit, +25°C) vs DIGITAL INPUT CODE (DAC5578, 8-Bit, +25°C)
Figure 74. Figure 75.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (DAC5578, 8-Bit, +125°C) vs DIGITAL INPUT CODE (DAC5578, 8-Bit, +125°C)
Figure 76. Figure 77.
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Product Folder Link(s): DAC5578 DAC6578 DAC7578
Temperature ( C)°
DNL Error (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
External Reference = 2.5V
DNL MIN
DNL MAX
-1.00
-0.80
-0.60
-0.40
-0.20
0.00
0.20
0.40
0.60
0.80
1.00
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature ( C)°
INL Error (LSB)
External Reference = 2.5V
INL MIN
INL MAX
Temperature ( C)°
INL Error (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 External Reference = 2.5V
INL MIN
INL MAX
Temperature ( C)°
DNL Error (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.4
-0.2
0.2
0.4 External Reference = 2.5V
DNL MIN
DNL MAX
Temperature ( C)°
INL Error (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
External Reference = 2.5V
INL MIN
INL MAX
Temperature ( C)°
DNL Error (LSB)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
External Reference = 2.5V
DNL MIN
DNL MAX
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE (DAC7578, 12-BIT) vs TEMPERATURE (DAC7578, 12-BIT)
Figure 78. Figure 79.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE (DAC6578, 10-Bit) vs TEMPERATURE (DAC6578, 10-Bit)
Figure 80. Figure 81.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE (DAC5578, 8-Bit) vs TEMPERATURE (DAC5578, 8-Bit)
Figure 82. Figure 83.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Temperature ( C)°
Offset Error (mV)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-4
-3
-2
-1
0
1
2
3
4
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Temperature ( C)°
Full-Scale Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
0.00
0.60
0.90
1.50
2.10
2.70
3.00
3.90
4.50
4.70
Power Supply Current - Am
-40 -25 -10 5 20 35 50 65 80 95 110 125
T - Temperature -°C
0.30
1.20
1.80
2.40
3.30
3.60
4.20 AV = 2.7 V,
External Reference = 2.5 V
DD
Temperature ( C)°
Gain Error (%FSR)
-40 -25 -10 5 20 35 50 65 80 95 110 125
-0.15
-0.10
-0.05
0.0
0.05
0.10
0.15
External Reference = 2.5V
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
POWER-SUPPLY CURRENT OFFSET ERROR
vs TEMPERATURE vs TEMPERATURE
Figure 84. Figure 85.
POWER-DOWN CURRENT FULL-SCALE ERROR
vs TEMPERATURE vs TEMPERATURE
Figure 86. Figure 87.
GAIN ERROR
vs TEMPERATURE
Figure 88.
22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Source Current (mA)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
2.450
2.455
2.460
2.465
2.470
2.475
2.480
2.485
2.490
2.495
2.500
2.455
2.465
2.475
2.485
2.495 Channel A
DAC Loaded With FFFh
External Reference = 2.5V
Sink Current (mA)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Channel A
DAC Loaded With 000h
External Reference = 2.5V
Source Current (mA)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
2.450
2.455
2.460
2.465
2.470
2.475
2.480
2.485
2.490
2.495
2.500
2.455
2.465
2.475
2.485
2.495 Channel B
DAC Loaded With FFFh
External Reference = 2.5V
Sink Current (mA)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Channel B
DAC Loaded With 000h
External Reference = 2.5V
Source Current (mA)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
2.450
2.455
2.460
2.465
2.470
2.475
2.480
2.485
2.490
2.495
2.500
2.455
2.465
2.475
2.485
2.495 Channel G
DAC Loaded With FFFh
External Reference = 2.5V
Sink Current (mA)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Channel G
DAC Loaded With 000h
External Reference = 2.5V
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
SOURCE CURRENT SINK CURRENT
AT POSITIVE RAIL AT NEGATIVE RAIL
Figure 89. Figure 90.
SOURCE CURRENT SINK CURRENT
AT POSITIVE RAIL AT NEGATIVE RAIL
Figure 91. Figure 92.
SOURCE CURRENT SINK CURRENT
AT POSITIVE RAIL AT NEGATIVE RAIL
Figure 93. Figure 94.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Power Supply Current (mA)
Digital Input Code
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
0 512 1024 1536 2048 2560 3072 3584 4096
AV = 2.7 V,
External Reference = 2.5 V,
Code Loaded to all Eight DAC Channels
DD
% of Population
0
2
4
6
8
10
12
14
16
18
0.70
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
External Reference = 2.5V
Supply Current (mA)
Zoomed Rising Edge
100 V/divm
From Code 000h to FFFh
External Reference = 2.5 V
Rising Edge
2 V/div
Trigger Pulse
5 V/div
Time (5 s/div)m
Falling Edge
2 V/div
From Code FFFh to 000h
External Reference = 2.5 V
Time (5 s/div)m
Zoomed Falling Edge
100 V/divm
Trigger Pulse
5 V/div
Falling Edge
2 V/div
Time (5 s/div)m
Zoomed Falling Edge
100 V/divm
Trigger Pulse
5 V/div
From Code C00h to 400h
External Reference = 2.5 V
Rising Edge
2 V/div
Time (5 s/div)m
Zoomed Rising Edge
100 V/divm
Trigger Pulse
5 V/div
From Code 400h to C00h
External Reference = 2.5 V
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
POWER SUPPLY CURRENT POWER SUPPLY CURRENT
DIGITAL INPUT CODE HISTOGRAM
Figure 95. Figure 96.
FULL-SCALE SETTLING TIME: FULL-SCALE SETTLING TIME:
2.7V RISING EDGE 2.7V FALLING EDGE
Figure 97. Figure 98.
HALF-SCALE SETTLING EDGE: HALF-SCALE SETTLING TIME:
2.7V RISING EDGE 2.7V FALLING EDGE
Figure 99. Figure 100.
24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5578 DAC6578 DAC7578
V - 5 mV/div
OUT
SCL - 5 V/div
Time (1 s/div)m
Clock Feedthrough Impulse ~ 0.5n V-s
External Reference = 2.5 V
V - 2 mV/div
OUT
AV - 2 V/div
DD
~ 1.8 mVPP
Time (10 ms/div)
External Reference = 2.5 V
DAC = Zero Scale
DACs Unloaded
V - 2 mV/div
OUT
AV - 2 V/div
DD
Time (20 ms/div)
External Reference = 2.5 V
DAC = Mid Scale
DACs Unloaded
V - 1 mV/div
OUT
AV - 2 V/div
DD
Time (10 ms/div)
DAC = Zero Scale
V - 500 V/div
OUT m
Time (2 s/div)m
LDAC Clock
Feed-Through
LDAC - Trigger Pulse
5 V/div
From Code 800h to 801h
External Reference = 2.5 V
LDAC Clock
Feed-Through
V - 500 V/div
OUT m
LDAC - Trigger Pulse
5 V/div
Time (2 s/div)m
From Code 801h to 800h
External Reference = 2.5 V
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
CLOCK FEEDTHROUGH POWER-ON GLITCH
400 kHz, MIDSCALE RESET TO ZERO SCALE
Figure 101. Figure 102.
POWER-ON GLITCH
RESET TO MIDSCALE POWER-OFF GLITCH
Figure 103. Figure 104.
GLITCH ENERGY: GLITCH ENERGY:
2.7V, 12-BIT, 1LSB STEP, RISING EDGE 2.7V, 12-BIT, 1LSB STEP, FALLING EDGE
Figure 105. Figure 106.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): DAC5578 DAC6578 DAC7578
Time (2 s/div)m
V - 1 mV/div
OUT
LDAC Clock
Feed-Through
External Reference = 2.5 V
From Code 200h to 201h
LDAC - Trigger Pulse
5 V/div
Time (2 s/div)m
V - 1 mV/div
OUT
LDAC Clock
Feed-Through
External Reference = 2.5 V
From Code 201h to 200h
LDAC - Trigger Pulse
5 V/div
Time (2 s/div)m
V - 5 mV/div
OUT
LDAC Clock
Feed-Through
External Reference = 2.5 V
From Code 80h to 81h
LDAC - Trigger Pulse
5 V/div
LDAC Clock
Feed-Through
V - 5 mV/div
OUT
LDAC - Trigger Pulse
5 V/div
External Reference = 2.5 V
From Code 81h to 80h
Time (2 s/div)m
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued)
At TA= 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, DAC7578
graphs shown (unless otherwise noted).
GLITCH ENERGY: GLITCH ENERGY:
2.7V, 10-BIT, 1LSB STEP, FALLING EDGE 2.7V, 10-BIT, 1LSB STEP, FALLING EDGE
Figure 107. Figure 108.
GLITCH ENERGY: GLITCH ENERGY:
2.7V, 8-BIT, 1LSB STEP, RISING EDGE 2.7V, 8-BIT, 1LSB STEP, FALLING EDGE
Figure 109. Figure 110.
26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5578 DAC6578 DAC7578
DAC
Register
REF(+)
Resistor String
REF( )-
VREFIN
VOUTX
178kW
150kW150kW
V =
OUT x VREFIN
DIN
2n
VREF
R
R
R
R
VREF
2
RDIVIDER
To Output Amplifier
(2x Gain)
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
The DAC5578, DAC6578, and DAC7578 (DACx578)
architecture consists of eight string DACs each
followed by an output buffer amplifier. Figure 111
shows a principal block diagram of the DAC
architecture.
Figure 111. Device Architecture
For the TSSOP package, the input coding is straight
binary. For the QFN package, the TWOC pin controls
the code format.
When using an external reference, the ideal output
voltage is given by Equation 1:
(1)
Where:
DIN = decimal equivalent of the binary code that
is loaded to the DAC register. The code can
range from 0 to 255 for the 8-bit DAC5578, 0 to Figure 112. Resistor String
1023 (DAC6578) and 0 to 4095 (DAC7578).
VREFIN = external reference voltage of 0V to 5V,
supplied at the VREFIN pin. OUTPUT AMPLIFIER
n = resolution on bits; 8 (DAC5578), 10 The output buffer amplifier is capable of generating
(DAC6578), or 12 (DAC7578) rail-to-rail voltages on its output, giving a maximum
output range of 0V to AVDD. It is capable of driving a
RESISTOR STRING load of 2kΩin parallel with 1000pF to GND. The
The resistor string circuitry is shown in Figure 112. It source and sink capabilities of the output amplifier
is a string of resistors, each of value R. The code can be seen in the Typical Characteristics. The
loaded into the DAC register determines at which typical slew rate is 0.75V/ms, with a typical full-scale
node on the string the voltage is tapped off to be fed settling time of 7ms with the output unloaded.
into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors. The
overall gain is one and allows the user to provide an
external reference value of 0 to AVDD.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): DAC5578 DAC6578 DAC7578
NotAcknowledge
Acknowledge
1 2 8 9
ClockPulsefor
Acknowledgement
S
START
Condition
DataOutput
byTransmitter
DataOutput
byReceiver
SCLfrom
Master
Start
Condition
SDA
Stop
Condition
SDA
SCL
S P
SCL
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
TWO-WIRE, I2C-COMPATIBLE INTERFACE Other than specific timing signals, the I2C interface
works with serial bytes. At the end of each byte, a
The two-wire serial interface used by the DACx578 is ninth clock cycle is used to generate/detect an
I2C-compatible (refer to the I2C Bus Specification). acknowledge signal, as shown in Figure 114. An
The bus consists of a data line (SDA) and a clock line acknowledge is when the SDA line is pulled low
(SCL) with pull-up resistors. When the bus is idle, during the high period of the ninth clock cycle. A
both SDA and SCL lines are pulled high. All not-acknowledge is when the SDA line is left high
I2C-compatible devices connect to the I2C bus during the high period of the ninth clock cycle.
through open-drain I/O pins SDA and SCL.
The I2C specification states that the device that
controls communication is called a master, and the
devices that are controlled by the master are called
slaves. The master device generates the SCL signal.
The master device also generates special timing
conditions (start, repeated start, and stop) on the bus
to indicate the start or stop of a data transfer, as
shown in Figure 113. Device addressing is also
performed by the master. The master device on an
I2C bus is usually a microcontroller or a digital signal Figure 114. Acknowledge and Not Acknowledge
processor (DSP). The DACx578 operates as a slave Signals on the I2C Bus
device on the I2C bus. A slave device acknowledges
the master commands, and upon the direction of the F/S Mode Protocol
master, either receives or transmits data. • The master initiates data transfer by generating a
start condition, defined as when a high-to-low
transition occurs on the SDA line while SCL is
high, as shown in Figure 114. All I2C-compatible
devices recognize a start condition.
• The master then generates the SCL pulses, and
transmits the 7-bit address and the read/write
direction bit (R/W) on the SDA line. During all
Figure 113. transmissions, the master ensures that data are
valid. A valid data condition requires the SDA line
Although the DACx578 normally operates as a slave to be stable during the entire high period of the
receiver, when a master device acquires the clock pulse, as shown in Figure 115. All devices
DACx578 internal register data, the DACx578 also recognize the address sent by the master and
operates as a slave transmitter. In this case, the compare it to the internal fixed addresses. Only
master device reads from the DACx578 (the slave the slave device with a matching address
transmitter). According to I2C terminology, read and generates an acknowledge by pulling the SDA line
write operations are always performed with respect to low during the entire high period of the ninth SCL
the master device. cycle, as shown in Figure 114. Upon detecting this
acknowledge, the master recognizes the
The DACx578 supports the following data transfer communication link with a slave has been
modes, as defined in the I2C Bus Specification: established.
• Standard mode (100kbps) • The master generates additional SCL cycles to
• Fast mode (400kbps) either transmit data to the slave (R/W bit = '0') or
• Fast mode plus (1.0Mbps)(1) receive data from the slave (R/W bit = '1'). In
• High-Speed mode (3.4Mbps) either case, the receiver must acknowledge the
data sent by the transmitter. So the acknowledge
The data transfer protocols for Standard and Fast signal can either be generated by the master or by
modes are exactly the same; therefore, these modes the slave, depending on which one is the receiver.
are referred to as F/S mode in this document. The The 9-bit valid data sequences, consisting of eight
protocol for High-Speed mode is different from the data bits and one acknowledge bit, can continue
F/S mode, and it is referred to as HS mode. The as long as necessary.
DACx578 supports 7-bit addressing. Note that 10-bit • To signal the end of the data transfer, the master
addressing and a general call address are not generates a stop condition by pulling the SDA line
supported. from low to high while the SCL line is high (see
Figure 115). This action releases the bus and
(1) The DACx578 supports Fast mode plus speed and timing
specifications only. These devices cannot support the 20mA stops the communication link with the addressed
low-level output current specification.
28 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5578 DAC6578 DAC7578
ChangeofDataAllowed
DataLineStable;
DataValid
SDA
SCL
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
slave. All I2C-compatible devices recognize the DACx578 I2C UPDATE SEQUENCE
stop condition. Upon receipt of a stop condition, For a single update, the DACx578 requires a start
the bus is released, and all slave devices then condition, a valid I2C address (A) byte, a command
wait for a start condition followed by a matching and access (CA) byte, and two data bytes, the most
address. significant data byte (MSDB) and least significant
data byte (LSDB), as shown in Table 1.
After each byte is received, the DACx578
acknowledges by pulling the SDA line low during the
high period of a single clock pulse, as shown in
Figure 116. These four bytes and acknowledge
cycles make up the 36 clock cycles required for a
single update to occur. A valid I2C address selects
the corresponding slave device (for example,
Figure 115. I2C Bus Bit Transfer DACx578).
The CA byte sets the operational mode of the
HS Mode Protocol selected DACx578. When the operational mode is
• When the bus is idle, both the SDA and SCL lines selected by this byte, the DACx578 must receive two
are pulled high by the pull-up resistors. data bytes, the most significant data byte (MSDB)
• The master generates a start condition followed and least significant data byte (LSDB), for data
by a valid serial byte containing HS mode master update to occur. The DACx578 performs an update
code 00001XXX. This transmission is made in F/S on the falling edge of the acknowledge signal that
mode at no more than 1.0Mbps. No device is follows the LSDB.
allowed to acknowledge the HS mode master The CA byte does not have to be re-sent until a
code, but all devices must recognize it and switch change in operational mode is required. The bits of
the respective internal settings to support 3.4Mbps the control byte continuously determine the type of
operation. update performed. Thus, for the first update, the
• The master then generates a repeated start DACx578 requires a start condition, a valid I2C
condition (a repeated start condition has the same address, the CA byte, and two data bytes (MSDB and
timing as the start condition). After this repeated LSDB). For all consecutive updates, the DACx578
start condition, the protocol is the same as F/S needs only an MSDB and LSDB, as long as the CA
mode, except that transmission speeds up to byte command remains the same.
3.4Mbps are allowed. A stop condition ends HS When using the I2C HS mode (clock = 3.4MHz), each
mode and switches all the internal settings of the 12-bit DAC update other than the first update can be
slave devices to support F/S mode. Instead of done within 18 clock cycles (MSDB, acknowledge
using a stop condition, repeated start conditions signal, LSDB, acknowledge signal) at 188.88kSPS.
should be used to secure the bus in HS mode. When using Fast mode (clock = 400kHz), the
maximum DAC update rate is limited to 22.22kSPS.
Using the Fast mode plus (clock = 1MHz), the
maximum DAC update rate is limited to 55.55kSPS.
When a stop condition is received, the DACx578
releases the I2C bus and awaits a new start condition.
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Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
SDA
SCL
MSB
P
Sr
Sr
or
P
S
or
Sr
START or
REPEATED START
Condition
Clock Line Held Low While
Interrupts are Serviced
1 2 7 8 9
ACK
1 2 3 - 8 9
ACK
Address
R/W
Recognize START or
REPEATED START
Condition
REPEATED START
STOP
or
Condition
Recognize STOP or
REPEATED START
Condition
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Figure 116. I2C Bus Protocol
Table 1. Update Sequence
MSB ··· LSB MSB ··· LSB MSB ··· LSB MSB ··· LSB
ACK ACK ACK ACK
Address (A) Byte Command/Access Byte MSDB LSDB
DB[32:24] DB[23:16] DB[15:8] DB[7:0]
AVDD, GND, or left floating. The device address can
Address (A) Byte be updated dynamically between serial commands.
When using the QFN package (DAC5578RGE,
The address byte, shown in Table 2, is the first byte DAC6578RGE, and DAC7578RGE), up to eight
received following the start condition from the master devices can be connected to the same I2C bus. When
device. The first four most significant bits (MSBs) of using the TSSOP package (DAC5578PW.
the address are factory preset to '1001'. The next DAC6578PW, and DAC7578PW), up to three devices
three bits of the address are controlled by the ADDR can be connected to the same I2C bus.
pin(s). The ADDR pin(s) inputs can be connected to
Table 2. Address Byte
MSB LSB
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W
1 0 0 1 See Table 3 or Table 4 Slave Address column 0 or 1
Table 3. Address Format For QFN-24 (RGE) Package
SLAVE ADDRESS ADDR1 ADDR0
1001 000 0 0
1001 001 0 1
1001 010 1 0
1001 011 1 1
1001 100 Float 0
1001 101 Float 1
1001 110 0 Float
1001 111 1 Float
Not supported Float Float
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Table 4. Address Format For TSSOP-16 (PW) Package
SLAVE ADDRESS ADDR0
1001 000 0
1001 010 1
1001 100 Float
register is being accessed when writing to or reading
Command and Access (CA) Byte from the DACx578. See Table 6 for a list of write and
The command and access byte, as shown in Table 5,read commands.
controls which command is executed and which
Table 5. Command and Access Byte
MSB LSB
C3 C2 C1 C0 A3 A2 A1 A0
Command bits(1) Access bits(1)
(1) See Table 6 for bit selection.
Table 6. Command and Access Byte Format(1)
C3 C2 C1 C0 A3 A2 A1 A0 DESCRIPTION
Write Sequences
0 0 0 0 A3 A2 A1 A0 Write to DAC input register channel n
0 0 0 1 A3 A2 A1 A0 Select to update DAC register channel n
Write to DAC input register channel n, and update all DAC registers
0 0 1 0 A3 A2 A1 A0 (global software LDAC)
0 0 1 1 A3 A2 A1 A0 Write to DAC input register channel n, and update DAC register channel n
0 1 0 0 X X X X Power down/on DAC
0 1 0 1 X X X X Write to clear code register
0 1 1 0 X X X X Write to LDAC register
0 1 1 1 X X X X Software reset
Read Sequences
0 0 0 0 A3 A2 A1 A0 Read from DAC input register channel n
0 0 0 1 A3 A2 A1 A0 Read from DAC register channel n
0 1 0 0 X X X X Read from DAC power down register
0 1 0 1 X X X X Read from clear code register
0 1 1 0 X X X X Read from LDAC register
Access Sequences
C3 C2 C1 C0 0 0 0 0 DAC channel A
C3 C2 C1 C0 0 0 0 1 DAC channel B
C3 C2 C1 C0 0 0 1 0 DAC channel C
C3 C2 C1 C0 0 0 1 1 DAC channel D
C3 C2 C1 C0 0 1 0 0 DAC channel E
C3 C2 C1 C0 0 1 0 1 DAC channel F
C3 C2 C1 C0 0 1 1 0 DAC channel G
C3 C2 C1 C0 0 1 1 1 DAC channel H
C3 C2 C1 C0 1 1 1 1 All DAC channels, broadcast update
(1) Any sequences other than the ones listed are invalid; improper use can cause incorrect device operation.
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Most Significant Data Byte (MSDB) and Least I2C Read Sequence
Significant Data Byte (LSDB) To read any register, use the following command
The MSDB and LSDB contain the data that are sequence:
passed to the register(s) specified by the CA byte, as 1. Send a start or repeated start command with a
shown in Table 7 and Table 8. See Table 14 for a slave address and the R/W bit set to '0' for
complete list of write sequences and Table 15 for a writing. The device acknowledges this event.
complete list of read sequences. The DACx578 2. Then send a command byte for the register to be
updates at the falling edge of the acknowledge signal read. The device acknowledges this event again.
that follows the LSDB[0] bit. 3. Then send a repeated start with the slave
address and the R/W bit set to '1' for reading.
Broadcast Addressing The device also acknowledges this event.
Broadcast addressing, as shown in Table 9, is also 4. Then the device writes the MSDB of the register.
supported by the DACx578. Broadcast addressing The master should acknowledge this byte.
can be used for synchronously updating or powering 5. Finally, the device writes out the LSDB.
down multiple DACx578 devices. These devices are
designed to work with each other, and with the An alternative reading method allows for reading back
DAC7678, to support multichannel synchronous of the last register written to. The sequence is a
updates. Using the broadcast address command, the start/repeated start with slave address and the R/W
DACx578 responds regardless of the state of the bit set to '1', and the two bytes of the last register are
address pins. Note that broadcast addressing is read out, as shown in Table 13.
supported only in write mode (master writes to the
DACx578). Note that it is not possible to use the broadcast
address for reading.
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Table 7. Most Significant Data Byte (MSDB)
MSB LSB
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
Table 8. Least Significant Data Byte (LSDB)
MSB LSB
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Table 9. Broadcast Address Command
MSB LSB
10001110
Table 10. DAC5578 Data Input Register Format
DB23 DB15 DB8 DB0
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X
|--------- Command and Address Bits ---------| |---------------------- Data Bits ----------------------| |--------------------- Don't Care ---------------------|
Table 11. DAC6578 Data Input Register Format
DB23 DB15 DB6 DB0
C3 C2 C1 C0 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X
|--------- Command and Address Bits ---------| |------------------------------ Data Bits ------------------------------| |------------- Don't Care -------------|
Table 12. DAC7578 Data Input Register Format
DB23 DB15 DB4 DB0
C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
|--------- Command and Address Bits ---------| |-------------------------------------- Data Bits --------------------------------------| |----- Don't Care -----|
Table 13. Read Sequence
S MSB … R/W(0) ACK MSB … LSB ACK Sr MSB … R/W(1) ACK MSB … LSB ACK MSB … LSB ACK
Address Byte Command/Access Byte Sr Address Byte MSDB LSDB
From master Slave From master Slave From master slave From Slave Master From Slave Master
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Table 14. Control Matrix for Write Commands (see Table 10,Table 11, and Table 12 for 8-bit, 10-bit, and 12-bit mapping)
COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DESCRIPTION
C3 C2 C1 C0 A3 A2 A1 A0 DATA[7:0] X X X X X X X X General data format for 8-bit DAC5578
C3 C2 C1 C0 A3 A2 A1 A0 DATA[9:2] D1 D0 X X X X X X General data format for 10-bit DAC6578
C3 C2 C1 C0 A3 A2 A1 A0 DATA[11:4] D3 D2 D1 D0 X X X X General data format for 12-bit DAC7578
Write to DAC Input Register
0 0 0 0 0 0 0 0 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel A
0 0 0 0 0 0 0 1 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel B
0 0 0 0 0 0 1 0 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel C
0 0 0 0 0 0 1 1 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel D
0 0 0 0 0 1 0 0 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel E
0 0 0 0 0 1 0 1 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel F
0 0 0 0 0 1 1 0 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel G
0 0 0 0 0 1 1 1 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel H
0 0 0 0 1 X X X X X X X X X X X X X X X X X X X Invalid code, no action performed
0 0 0 0 1 1 1 1 Data[11:4] Data[3:0] X X X X Broadcast mode, write to all DAC channels
Select DAC Register to Update
0 0 0 1 0 0 0 0 X X X X X X X X X X X X X X X X Selects DAC channel A to be updated
0 0 0 1 0 0 0 1 X X X X X X X X X X X X X X X X Selects DAC channel B to be updated
0 0 0 1 0 0 1 0 X X X X X X X X X X X X X X X X Selects DAC channel C to be updated
0 0 0 1 0 0 1 1 X X X X X X X X X X X X X X X X Selects DAC channel D to be updated
0 0 0 1 0 1 0 0 X X X X X X X X X X X X X X X X Selects DAC channel E to be updated
0 0 0 1 0 1 0 1 X X X X X X X X X X X X X X X X Selects DAC channel F to be updated
0 0 0 1 0 1 1 0 X X X X X X X X X X X X X X X X Selects DAC channel G to be updated
0 0 0 1 0 1 1 1 X X X X X X X X X X X X X X X X Selects DAC channel H to be updated
0 0 0 1 1 X X X X X X X X X X X X X X X X X X X Invalid code, no action performed
Broadcast mode, selects all DAC channels to be
0 0 0 1 1 1 1 1 X X X X X X X X X X X X X X X X updated
Write to Selected DAC Input Register and Update Corresponding DAC Register (Individual Software LDAC)
Write to DAC input register for channel A and update
0 0 1 1 0 0 0 0 Data[11:4] Data[3:0] X X X X channel A DAC register
Write to DAC input register for channel B and update
0 0 1 1 0 0 0 1 Data[11:4] Data[3:0] X X X X channel B DAC register
Write to DAC input register for channel C and update
0 0 1 1 0 0 1 0 Data[11:4] Data[3:0] X X X X channel C DAC register
Write to DAC input register for channel D and update
0 0 1 1 0 0 1 1 Data[11:4] Data[3:0] X X X X channel D DAC register
Write to DAC input register for channel E and update
0 0 1 1 0 1 0 0 Data[11:4] Data[3:0] X X X X channel E DAC register
Write to DAC input register for channel F and update
0 0 1 1 0 1 0 1 Data[11:4] Data[3:0] X X X X channel F DAC register
Write to DAC input register for channel G and update
0 0 1 1 0 1 1 0 Data[11:4] Data[3:0] X X X X channel G DAC register
Write to DAC input register for channel H and update
0 0 1 1 0 1 1 1 Data[11:4] Data[3:0] X X X X channel H DAC register
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Table 14. Control Matrix for Write Commands (see Table 10,Table 11, and Table 12 for 8-bit, 10-bit, and 12-bit mapping) (continued)
COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DESCRIPTION
C3 C2 C1 C0 A3 A2 A1 A0 DATA[7:0] X X X X X X X X General data format for 8-bit DAC5578
C3 C2 C1 C0 A3 A2 A1 A0 DATA[9:2] D1 D0 X X X X X X General data format for 10-bit DAC6578
C3 C2 C1 C0 A3 A2 A1 A0 DATA[11:4] D3 D2 D1 D0 X X X X General data format for 12-bit DAC7578
0 0 1 1 1 X X X X X X X X X X X X X X X X X X X Invalid code, no action performed
Broadcast mode, write to all input registers and update
0 0 1 1 1 1 1 1 Data[11:4] Data[3:0] X X X X all DAC registers
Write to Selected DAC Input Register and Update All DAC Registers (Global Software LDAC)
Write to DAC input register for channel A and update all
0 0 1 0 0 0 0 0 Data[11:4] Data[3:0] X X X X DAC registers
Write to DAC input register for channel B and update all
0 0 1 0 0 0 0 1 Data[11:4] Data[3:0] X X X X DAC registers
Write to DAC input register for channel C and update all
0 0 1 0 0 0 1 0 Data[11:4] Data[3:0] X X X X DAC registers
Write to DAC input register for channel D and update all
0 0 1 0 0 0 1 1 Data[11:4] Data[3:0] X X X X DAC registers
Write to DAC input register for channel E and update all
0 0 1 0 0 1 0 0 Data[11:4] Data[3:0] X X X X DAC registers
Write to DAC input register for channel F and update all
0 0 1 0 0 1 0 1 Data[11:4] Data[3:0] X X X X DAC registers
Write to DAC input register for channel G and update all
0 0 1 0 0 1 1 0 Data[11:4] Data[3:0] X X X X DAC registers
Write to DAC input register for channel H and update all
0 0 1 0 0 1 1 1 Data[11:4] Data[3:0] X X X X DAC registers
0 0 1 0 1 X X X X X X X X X X X X X X X X X X X Invalid code, no action performed
Broadcast mode, write to all input registers and update
0 0 1 0 1 1 1 1 Data[11:4] Data[3:0] X X X X all DAC registers
Power-Down Register
0 1 0 0 X X X X X PD1 PD0 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H X X X X X
0 1 0 0 X X X X X 0 0 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H X X X X X Each DAC bit set to '1' powers on selected DACs
Each DAC bit set to '1' powers down selected DACs.
0 1 0 0 X X X X X 0 1 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H X X X X X VOUT connected to GND through 1kΩpull-down resistor
Each DAC bit set to '1' powers down selected DACs.
0 1 0 0 X X X X X 1 0 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H X X X X X VOUT connected to GND through 100kΩpull-down
resistor
Each DAC bit set to '1' powers down selected DACs.
0 1 0 0 X X X X X 1 1 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H X X X X X VOUT is High Z
Clear Code Register
0 1 0 1 X X X X X X X X X X X X X X CL1 CL0 X X X X
0 1 0 1 X X X X X X X X X X X X X X 0 0 X X X X Write to clear code register, CLR pin clears to zero scale
0 1 0 1 X X X X X X X X X X X X X X 0 1 X X X X Write to clear code register, CLR pin clears to midscale
0 1 0 1 X X X X X X X X X X X X X X 1 0 X X X X Write to clear code register, CLR pin clears to full scale
0 1 0 1 X X X X X X X X X X X X X X 1 1 X X X X Write to clear code register disables CLR pin
LDAC Register
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Table 14. Control Matrix for Write Commands (see Table 10,Table 11, and Table 12 for 8-bit, 10-bit, and 12-bit mapping) (continued)
COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DESCRIPTION
C3 C2 C1 C0 A3 A2 A1 A0 DATA[7:0] X X X X X X X X General data format for 8-bit DAC5578
C3 C2 C1 C0 A3 A2 A1 A0 DATA[9:2] D1 D0 X X X X X X General data format for 10-bit DAC6578
C3 C2 C1 C0 A3 A2 A1 A0 DATA[11:4] D3 D2 D1 D0 X X X X General data format for 12-bit DAC7578
When all DAC bits are set to '1', selected DACs ignore
the LDAC pin.
0 1 1 0 X X X X DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X X X X When all DAC bits are set to '0', selected DAC registers
update according to the LDAC pin.
Software Reset
0 1 1 1 X X X X 0 0 X X X X X X X X X X X X X X Software reset (default). Same as power-on reset (POR).
0 1 1 1 X X X X 0 1 X X X X X X X X X X X X X X Software reset that sets device into High-Speed mode
0 1 1 1 X X X X 1 0 X X X X X X X X X X X X X X Software reset that maintains High-Speed mode state
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Table 15. Control Matrix for Read Commands (see Table 10,Table 11, and Table 12 for 8-bit, 10-bit, and 12-bit mapping)
COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DESCRIPTION
C3 C2 C1 C0 A3 A2 A1 A0 DATA [7:0] X X X X X X X X General data format for 8-bit DAC5578
C3 C2 C1 C0 A3 A2 A1 A0 DATA [9:2] D1 D0 X X X X X X General data format for 10-bit DAC6578
C3 C2 C1 C0 A3 A2 A1 A0 DATA [11:4] D3 D2 D1 D0 X X X X General data format for 12-bit DAC7578
Input Register
0 0 0 0 0 0 0 0 Data[11:4] Data[3:0] 0 0 0 0 Read from DAC input register channel A
0 0 0 0 0 0 0 1 Data[11:4] Data[3:0] 0 0 0 0 Read from DAC input register channel B
0 0 0 0 0 0 1 0 Data[11:4] Data[3:0] 0 0 0 0 Read from DAC input register channel C
0 0 0 0 0 0 1 1 Data[11:4] Data[3:0] 0 0 0 0 Read from DAC input register channel D
0 0 0 0 0 1 0 0 Data[11:4] Data[3:0] 0 0 0 0 Read from DAC input register channel E
0 0 0 0 0 1 0 1 Data[11:4] Data[3:0] 0 0 0 0 Read from DAC input register channel F
0 0 0 0 0 1 1 0 Data[11:4] Data[3:0] 0 0 0 0 Read from DAC input register channel G
0 0 0 0 0 1 1 1 Data[11:4] Data[3:0] 0 0 0 0 Read from DAC input register channel H
0 0 0 0 1 X X X X X X X X X X X X X X X X X X X Invalid code
DAC Register
0 0 0 1 0 0 0 0 Data[11:4] Data[3:0] 0 0 0 0 Read DAC A DAC register
0 0 0 1 0 0 0 1 Data[11:4] Data[3:0] 0 0 0 0 Read DAC B DAC register
0 0 0 1 0 0 1 0 Data[11:4] Data[3:0] 0 0 0 0 Read DAC C DAC register
0 0 0 1 0 0 1 1 Data[11:4] Data[3:0] 0 0 0 0 Read DAC D DAC register
0 0 0 1 0 1 0 0 Data[11:4] Data[3:0] 0 0 0 0 Read DAC E DAC register
0 0 0 1 0 1 0 1 Data[11:4] Data[3:0] 0 0 0 0 Read DAC F DAC register
0 0 0 1 0 1 1 0 Data[11:4] Data[3:0] 0 0 0 0 Read DAC G DAC register
0 0 0 1 0 1 1 1 Data[11:4] Data[3:0] 0 0 0 0 Read DAC H DAC register
0 0 0 1 1 X X X X X X X X X X X X X X X X X X X Invalid code
Power Down Register
0 1 0 0 X X X X 0 0 0 0 0 0 PD1 PD0 DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H Read power down register
Clear Code Register
0 1 0 1 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL1 CL0 Read clear code register
LDAC Register
0 1 1 0 X X X X 0 0 0 0 0 0 0 0 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A Read LDAC register
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POWER-ON RESET TO ZERO-SCALE OR hardware LDAC pin is being brought low. The LDAC
MIDSCALE register is loaded with an 8-bit word (DB15 to DB8)
using control bits C3, C2, C1, and C0. The default
The DACx578 contains a power-on reset (POR) value for each bit, and therefore each DAC channel,
circuit that controls the output voltage during is zero and the external LDAC pin operates in normal
power-on. For devices in the TSSOP package, at mode. If the LDAC register bit for a selected DAC
power-on, all DAC registers are filled with zeros and channel is set to '1', that DAC channel ignores the
the output voltages of all DAC channels are set to external LDAC pin and updates only through the
zero-scale. For devices in the QFN package, all DAC software LDAC command. If, however, the LDAC
registers are set to have all DAC channels power on register bit is set to '0', the DAC channel is controlled
depending of the state of the RSTSEL pin. by the external LDAC pin (default).
The RSTSEL pin value is read at power-on and This combination of both software and hardware
should be set prior to or simultaneously with AVDD.simultaneous update functions is particularly useful in
For RSTSEL set to AVDD, the DAC channels are applications where only selective DAC channels are
loaded with midscale code. If RSTSEL is set to to be updated simultaneously, while the other
ground, the DAC channels are loaded with zero-scale channels remain unaffected and have synchronous
code. All DAC channels remain in this state until a channel updates.
valid write sequence and load command are sent to
the respective DAC channel. The power-on reset POWER-DOWN COMMANDS
function is useful in applications where it is important
to know the output state of each DAC while the The DACx578 uses four modes of operation. These
device is in the process of powering on. modes are accessed by using control bits C3, C2,
C1, and C0. The control bits must be set to '0100'.
LDAC FUNCTIONALITY When the control bits are set correctly, the four
different power-down modes are software
The DACx578 offers both software and hardware programmable by setting bits PD0 (DB13) and PD1
simultaneous updates and control functions. The (DB14) in the control register. Table 16 shows how to
DAC double-buffered architecture is designed so that control the operating mode with data bits PD0
new data can be entered for each DAC without (DB13), and PD1 (DB14). The DACx578 treats the
disturbing the analog outputs. power-down condition as data; all the operational
modes are still valid for power down. It is possible to
The DACx578 data updates can be performed either broadcast a power-down condition to all the
in Synchronous or Asynchronous mode. DACx578s in a system. It is also possible to
In Synchronous mode, data are updated on the falling power-down a channel and update data on other
edge of the acknowledge signal that follows LSDB. channels. Further, it is possible to write to the DAC
For Synchronous mode updates, the LDAC pin is not register/buffer of the DAC channel that is powered
required and must be connected to GND down. When the DAC channel is then powered on, it
permanently. contains the new value.
In Asynchronous mode, the LDAC pin is used as a When both the PD0 and PD1 bits are set to '0', the
negative-edge-triggered timing signal for device works normally with its typical consumption of
asynchronous DAC updates. Multiple single-channel 1.02 mA at 5.5V. However, for the three power-down
updates can be performed in order to set different modes, the supply current falls to 0.42µA at 5.5V
channel buffers to desired values and then make a (0.25µA at 2.7V). Not only does the supply current
falling edge on the LDAC pin. The data buffers of all fall, but the output stage also switches internally from
the channels must be loaded with the desired data the output amplifier to a resistor network of known
before an LDAC falling edge. After a high-to-low values as shown in Figure 117.
LDAC transition, all DACs simultaneously update with The advantage of this switching is that the output
the last contents of the corresponding data buffers. If impedance of the device is known while it is in
the contents of a data buffer are not changed by the power-down mode. As described in Table 16, there
serial interface, the corresponding DAC output are three different power-down options. VOUT can be
remains unchanged after the LDAC trigger. connected internally to GND through a 1kΩresistor, a
Alternatively, all DAC outputs can be updated 100kΩresistor, or open circuited (High-Z).
simultaneously using the built-in LDAC software
function. The LDAC register offers additional flexibility
and control, giving the ability to select which DAC
channel(s) should update simultaneously when the
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For example: C3, C2, C1, and C0 = '0100' and DB14 CLR pin low clears the contents of all DAC registers
and DB13 = '11' represent a power-down condition and all DAC buffers and replaces the code with the
with High-Z output impedance for a selected channel. code determined by the clear code register. The clear
DB14 and DB13 = '01' represents a power-down code register can be written to by applying the
condition with 1kΩoutput impedance, while DB14 commands showed in Table 14. The default setting of
and DB13 = '10' represents a power-down condition the clear code register sets the output of all DAC
with 100kΩoutput impedance. channels to 0V when the CLR pin is brought low. The
CLR pin is falling-edge triggered; therefore, the
Table 16. DAC Operating Modes device exits clear code mode on the falling edge of
the acknowledge signal that follows LSDB of the next
PD1 PD0 write sequence. If the CLR pin is executed (brought
(DB14) (DB13) DAC OPERATING MODES low) during a write sequence, this write sequence is
0 0 Power on selected DACs aborted and the DAC registers and DAC buffers are
0 1 Power down selected DACs, 1kΩto GND cleared as described above.
1 0 Power down selected DACs, 100kΩto GND When performing a software reset of the device, the
1 1 Power down selected DACs, High-Z to GND clear code register is reset to the default mode (DB5
= '0', DB4 = '0'). Setting the clear code register to
Spacer DB4 = '1' and DB5 = '1' ignores any activity on the
external CLR pin.
SOFTWARE RESET FUNCTION
The DACx578 contains a software reset feature.
When the software reset feature is executed, the
device (all DAC channels) are reset to the power-on
reset code. All registers inside the device are reset to
the respective default settings. The DACx578 has an
additional feature of switching straight to high speed
mode after reset. Table 17 shows all the different
modes of the software reset function.
Table 17. Software Reset Modes
Figure 117. Output Stage During Power-Down DB15 DB14 OPERATING MODES
Default Software reset. Equivalent to
0 0 Power-on-Reset
CLEAR CODE REGISTER AND CLR PIN Software reset and set part in High Speed
x 1
The DACx578 contains a clear code register. The Mode
clear code register can be accessed via the serial Software reset and maintain High Speed
1 0
interface (I2C) and is user configurable. Bringing the Mode state
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 39
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DAC7578
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OPERATING EXAMPLES: DAC7578
For the following examples X = don’t care; value can be either '0' or '1'.
I2C Standard and Fast mode examples (ADDR0 and LDAC pin tied low) (TSSOP package)
Example 1: Write Mid Scale to Data Buffer A and Update Channel A Output
Command and
Start Address MSDB LSDB Stop
Access Byte
ACK ACK ACK ACK
S 1001 0000 0000 0000 1000 0000 0000 XXXX P
Channel A updates to Mid Scale after the falling edge of the last ACK cycle
SPACER
Example 2: Power-Down Channel B, C, and H with Hi-Z Output
Command and
Start Address MSDB LSDB Stop
Access Byte
ACK ACK ACK ACK
S 1001 0000 0100 XXXX X111 0000 110X XXXX P
SPACER
Example 3: Read-back the value of the input register of DAC Channel G
Command and Repeated MSDB (from LSDB (from
Start Address Address
Access Byte Start DAC7578) DAC7578)
ACK ACK ACK ACK
S 1001 0000 0000 0110 Sr 1001 0001 XXXX XXXX XXXX 0000
SPACER
Example 4: Write multiple bytes of data to Channel F.
Write Full Scale and then Quarter Scale to Channel F
Command and
Start Address MSDB LSDB MSDB LSDB Stop
Access Byte
ACK ACK ACK ACK* ACK ACK**
S 1001 0000 0000 0101 1111 1111 1111 XXXX 0100 0000 0000 XXXX P
Channel F updates to Full Scale after the falling edge of the 4th ACK* cycle and then Channel F updates to
quarter scale after falling edge of the last ACK** cycle.
SPACER
I2C High Speed mode example (ADDR0 and LDAC pin tied low) (TSSOP package)
SPACER
Example 5: Write Mid Scale and then Full Scale to all DAC channels.
HS Command
NOT Repeated
Start Master Address ACK and Access ACK MSDB ACK LSDB ACK MSDB ACK LSDB ACK Stop
ACK Start
Code Byte
S 0000 1000 Sr 1001 0000 0011 1111 1000 0000 0000 XXXX 1111 1111 1111 XXXX P
All Channels update to Mid Scale after the falling edge of the 4th ACK cycle and then all Channels update to Full
scale after falling edge of the last ACK cycle.
40 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5578 DAC6578 DAC7578
IN 1 2
O UT REF REF
n
1
D R + R R2
V = V Gain V
R R1
2
æ ö
æ ö
æ ö æ ö
´ ´ ´ - ´
ç ÷
ç ÷ ç ÷ç ÷
ç ÷
è øè ø è ø
è ø
IN
OUT n
10 D
V = 5V
2
´
æ ö -
ç ÷
è ø
Pull-Up Resistors
1k to 10k (typ)W W
Microcontroller or
Microprocessor
with I C Port
2
VDD
5
6
7
8
12
11
10
9
V D
OUT
V F
OUT
V H
OUT
CLR
V C
OUT
V E
OUT
V G
OUT
VREFIN
DACx578
Top
View
1
2
3
4
16
15
14
13
SCL
SDA
GND
V B
OUT
LDAC
ADDR0
AVDD
V A
OUT
SCL
SDA
VOUT
VREFIN/
VREFOUT
VREFEXT
+6V
±5V
-6V
OPA703
DACx578
10 Fm0.1 Fm
R1
10kW
R2
10kW
Serial Interface
GND
AVDD
AVDD
DAC5578
DAC6578
DAC7578
www.ti.com
SBAS496A –MARCH 2010–REVISED AUGUST 2010
APPLICATION INFORMATION
DAC NOISE PERFORMANCE MICROPROCESSOR INTERFACING
Output noise spectral density at the VOUTX pin versus A basic connection diagram to the SCL and SDA pins
frequency is depicted in Figure 55 for full-scale, of the DACx578 is shown in Figure 119. The
midscale, and zero-scale input codes. The typical DACx578 interfaces directly to standard mode, fast
noise density reduces to 104nV/√Hz at 1kHz for mid mode and high speed mode of 2-Wire compatible
scale code with external reference as shown in serial interfaces. The DACx578 does not perform
Figure 55. Integrated output noise between 0.1Hz clock stretching (pulling SCL low), as a result it is not
and 10Hz is close to 3µVPP (midscale), as shown in necessary to provide for this function unless other
Figure 56.devices on the same bus require this function. Pull-up
resistors are required on both the SDA and SCL lines
BIPOLAR OPERATION USING THE DACx578 as the bus-drivers are open-drain. The size of these
The DACx578 family of products is designed for pull-up resistors depends on the operating speed and
single-supply operation, but a bipolar output range is capacitance of the bus lines. Higher value resistors
also possible using the circuit in either Figure 118.consume less power but increase transition time on
Rail-to-rail operation at the amplifier output is the bus limiting the bus speed. Long bus lines have
achievable using an OPA703 as the output amplifier. higher capacitance and require smaller pull-up
resistors to compensate. The resistors should not be
The output voltage for any input code can be too small; if they are, bus drivers may not be able to
calculated with Equation 2.pull the bus lines low.
(2)
Where:
DIN = decimal equivalent of the binary code that
is loaded to the DAC register. It can range from 0
to 4095 (12 bit), 0 to 1023 (10 bit), and 0 to 255
(8 bit)
n = resolution in bits
Gain = 1
(3)
This result has an output voltage range of ±5V with
000h corresponding to a -5V output and FFFh
corresponding to a +5V output for the 12 bit
DAC7578.
Figure 119. Typical Connections of the DACx578
Figure 118. Bipolar Output Range Using External
Reference at 5V
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 41
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Pull-Up Resistors
1k to 10k (typ)W W
Microcontroller or
Microprocessor
with I C Port
2
VDD
5
6
7
8
12
11
10
9
V D
OUT
V F
OUT
V H
OUT
CLR
V C
OUT
V E
OUT
V G
OUT
VREFIN
DACx578
Top
View
1
2
3
4
16
15
14
13
SCL
SDA
GND
V B
OUT
LDAC
ADDR0
AVDD
V A
OUT
SCL
SDA
VDD
5
6
7
8
12
11
10
9
V D
OUT
V F
OUT
V H
OUT
CLR
V C
OUT
V E
OUT
V G
OUT
VREFIN
DACx578
Top
View
1
2
3
4
16
15
14
13
SCL
SDA
GND
V B
OUT
LDAC
ADDR0
AVDD
V A
OUT
5
6
7
8
12
11
10
9
V D
OUT
V F
OUT
V H
OUT
CLR
V C
OUT
V E
OUT
V G
OUT
VREFIN
DACx578
Top
View
1
2
3
4
16
15
14
13
SCL
SDA
GND
V B
OUT
LDAC
ADDR0
AVDD
V A
OUT
Leave
Floating
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
CONNECTING MULTIPLE DEVICES
Multiple devices of DACx578 family can be connected
on the same bus. Using the address pin, the
DACx578 can be set to one of three different I2C
addresses for the TSSOP package and one of eight
addresses for the QFN package. An example
showing three DACx578 devices in TSSOP package
is shown if Figure 120. Note that only one set of
pull-up resistors is needed per bus. The pull-up
resistor values may need to be lowered slightly to
compensate for the additional bus capacitance due to
multiple devices and increased bus length.
Figure 120. Typical Connections of the Multiple
DACx578 on the Same Bus
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SBAS496A –MARCH 2010–REVISED AUGUST 2010
PARAMETER DEFINITIONS
With the increased complexity of many different Full-Scale Error
specifications listed in product data sheets, this Full-scale error is defined as the deviation of the real
section summarizes selected specifications related to full-scale output voltage from the ideal output voltage
digital-to-analog converters. while the DAC register is loaded with the full-scale
code (for example, for 12 bit resolution 0xFFF).
STATIC PERFORMANCE Ideally, the output should be AVDD – 1 LSB. The
full-scale error is expressed in percent of full-scale
Static performance parameters are specifications range (%FSR).
such as differential nonlinearity (DNL) or integral
nonlinearity (INL). These are dc specifications and Offset Error
provide information on the accuracy of the DAC. They The offset error is defined as the difference between
are most important in applications where the signal actual output voltage and the ideal output voltage in
changes slowly and accuracy is required. the linear region of the transfer function. This
difference is calculated by using a straight line
Resolution defined by two codes (for example, for 12 bit
Generally, the DAC resolution can be expressed in resolution code 30 and 4050). Since the offset error is
different forms. Specifications such as IEC 60748-4 defined by a straight line, it can have a negative or
recognize the numerical, analog, and relative positive value. Offset error is measured in mV.
resolution. The numerical resolution is defined as the
number of digits in the chosen numbering system Zero-Code Error
necessary to express the total number of steps of the The zero-code error is defined as the DAC output
transfer characteristic, where a step represents both voltage, when all '0's are loaded into the DAC
a digital input code and the corresponding discrete register. Zero-scale error is a measure of the
analogue output value. The most commonly-used difference between actual output voltage and ideal
definition of resolution provided in data sheets is the output voltage (0V). It is expressed in mV. It is
numerical resolution expressed in bits. primarily caused by offsets in the output amplifier.
Least Significant Bit (LSB) Gain Error
The least significant bit (LSB) is defined as the Gain error is defined as the deviation in the slope of
smallest value in a binary coded system. The value of the real DAC transfer characteristic from the ideal
the LSB can be calculated by dividing the full-scale transfer function. Gain error is expressed as a
output voltage by 2n, where nis the resolution of the percentage of full-scale range (%FSR).
converter. Full-Scale Error Drift
Most Significant Bit (MSB) Full-scale error drift is defined as the change in
The most significant bit (MSB) is defined as the full-scale error with a change in temperature.
largest value in a binary coded system. The value of Full-scale error drift is expressed in units of µV/°C.
the MSB can be calculated by dividing the full-scale Offset Error Drift
output voltage by 2. Its value is one-half of full-scale. Offset error drift is defined as the change in offset
Relative Accuracy or Integral Nonlinearity (INL) error with a change in temperature. Offset error drift
Relative accuracy or integral nonlinearity (INL) is is expressed in µV/°C.
defined as the maximum deviation between the real Zero-Code Error Drift
transfer function and a straight line passing through Zero-code error drift is defined as the change in
the endpoints of the ideal DAC transfer function. INL zero-code error with a change in temperature.
is measured in LSBs. Zero-code error drift is expressed in µV/°C.
Differential Nonlinearity (DNL) Gain Temperature Coefficient
Differential nonlinearity (DNL) is defined as the The gain temperature coefficient is defined as the
maximum deviation of the real LSB step from the change in gain error with changes in temperature.
ideal 1LSB step. Ideally, any two adjacent digital The gain temperature coefficient is expressed in ppm
codes correspond to output analog voltages that are of FSR/°C.
exactly one LSB apart. If the DNL is less than 1LSB,
the DAC is said to be monotonic. Power-Supply Rejection Ratio (PSRR)
Power-supply rejection ratio (PSRR) is defined as the
empty para to force Full-Scale Error to next col ratio of change in output voltage to a change in
empty para to force Full-Scale Error to next col supply voltage for a full-scale output of the DAC. The
PSRR of a device indicates how the output of the
DAC is affected by changes in the supply voltage.
PSRR is measured in decibels (dB).
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 43
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OUT
V ( )
SR max t
t
æ ö
D
=ç ÷
D
è ø
DAC5578
DAC6578
DAC7578
SBAS496A –MARCH 2010–REVISED AUGUST 2010
www.ti.com
Monotonicity Digital Feed-through
Monotonicity is defined as a slope whose sign does Digital feed-through is defined as impulse seen at the
not change. If a DAC is monotonic, the output output of the DAC from the digital inputs of the DAC.
changes in the same direction or remains at least It is measured when the DAC output is not updated. It
constant for each step increase (or decrease) in the is specified in nV-s, and measured with a full-scale
input code. code change on the data bus; that is, from all '0's to
all '1's and vice versa.
DYNAMIC PERFORMANCE Channel-to-Channel DC Crosstalk
Dynamic performance parameters are specifications Channel-to-channel dc crosstalk is defined as the dc
such as settling time or slew rate, which are important change in the output level of one DAC channel in
in applications where the signal rapidly changes response to a change in the output of another DAC
and/or high frequency signals are present. channel. It is measured with a full-scale output
change on one DAC channel while monitoring
Slew Rate another DAC channel remains at midscale. It is
The output slew rate (SR) of an amplifier or other expressed in LSB.
electronic circuit is defined as the maximum rate of DAC Output Noise Density
change of the output voltage for all possible input
signals. Output noise density is defined as
internally-generated random noise. Random noise is
characterized as a spectral density (nV/√Hz). It is
measured by loading the DAC to midscale and
measuring noise at the output.
Where ΔVOUT(t) is the output produced by the DAC Output Noise
amplifier as a function of time t.DAC output noise is defined as any voltage deviation
Output Voltage Settling Time of DAC output from the desired value (within a
Settling time is the total time (including slew time) for particular frequency band). It is measured with a DAC
the DAC output to settle within an error band around channel kept at midscale while filtering the output
its final value after a change in input. Settling times voltage within a band of 0.1Hz to 10Hz and
are specified to within ±0.003% (or whatever value is measuring its amplitude peaks. It is expressed in
specified) of full-scale range (FSR). terms of peak-to-peak voltage (Vpp).
Code Change/Digital-to-Analog Glitch Energy Full-Scale Range (FSR)
Digital-to-analog glitch impulse is the impulse injected Full-scale range (FSR) is the difference between the
into the analog output when the input code in the maximum and minimum analog output values that the
DAC register changes state. It is normally specified DAC is specified to provide; typically, the maximum
as the area of the glitch in nanovolt-seconds (nV-s), and minimum values are also specified. For an n-bit
and is measured when the digital input code is DAC, these values are usually given as the values
changed by 1LSB at the major carry transition. matching with code 0 and 2n–1.
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SBAS496A –MARCH 2010–REVISED AUGUST 2010
LAYOUT The power applied to AVDD should be well-regulated
and low noise. Switching power supplies and dc/dc
A precision analog component requires careful layout, converters often have high-frequency glitches or
adequate bypassing, and clean, well-regulated power spikes riding on the output voltage. In addition, digital
supplies. The DACx578 offers single-supply components can create similar high-frequency spikes
operation, and is often used in close proximity with as their internal logic switches states. This noise can
digital logic, microcontrollers, microprocessors, and easily couple into the DAC output voltage through
digital signal processors. The more digital logic various paths between the power connections and
present in the design and the higher the switching analog output. As with the GND connection, AVDD
speed, the more difficult it is to keep digital noise should be connected to a power-supply plane or trace
from appearing at the output. As a result of the single that is separate from the connection for digital logic
ground pin of the DACx578, all return until they are connected at the power-entry point. In
currents(including digital and analog return currents addition, a 1µF to 10µF capacitor and 0.1µF bypass
for the DAC) must flow through a single point. Ideally, capacitor are strongly recommended. In some
GND would be connected directly to an analog situations, additional bypassing may be required,
ground plane. This plane would be separate from the such as a 100µF electrolytic capacitor or even a Pi
ground connection for the digital components until filter made up of inductors and capacitors – all
they were connected at the power-entry point of the designed to essentially low-pass filter the supply and
system. remove the high-frequency noise.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 45
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REVISION HISTORY
Changes from Original (March 2010) to Revision A Page
• Changed Changed the data sheet From: Product Preview To: Production Data. ................................................................ 1
46 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC5578SPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DAC5578SPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DAC5578SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DAC5578SRGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DAC6578SPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DAC6578SPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DAC6578SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DAC6578SRGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DAC7578SPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DAC7578SPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DAC7578SRGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DAC7578SRGET ACTIVE VQFN RGE 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2010
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC5578SPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
DAC5578SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
DAC5578SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
DAC6578SPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
DAC6578SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
DAC6578SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
DAC7578SPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
DAC7578SRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
DAC7578SRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC5578SPWR TSSOP PW 16 2000 367.0 367.0 35.0
DAC5578SRGER VQFN RGE 24 3000 367.0 367.0 35.0
DAC5578SRGET VQFN RGE 24 250 210.0 185.0 35.0
DAC6578SPWR TSSOP PW 16 2000 367.0 367.0 35.0
DAC6578SRGER VQFN RGE 24 3000 367.0 367.0 35.0
DAC6578SRGET VQFN RGE 24 250 210.0 185.0 35.0
DAC7578SPWR TSSOP PW 16 2000 367.0 367.0 35.0
DAC7578SRGER VQFN RGE 24 3000 367.0 367.0 35.0
DAC7578SRGET VQFN RGE 24 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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