THC63LVD824A _Rev1.20_E THC63LVD824A Single(112MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description Features The THC63LVD824A receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA resolutions and Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions. The THC63LVD824A converts the LVDS data streams back into 48bits of CMOS/TTL data with falling edge or rising edge clock for convenient with a variety of LCD panel controllers. In Single Link, data transmit clock frequency of 112MHz, 48bits of RGB data are transmitted at an effective rate of 784Mbps per LVDS channel. Using a 112MHz clock, the data throughput is 392Mbytes per second. In Dual Link, data transmit clock frequency of 85MHz, 48bits of RGB data are transmitted at an effective rate of 595Mbps per LVDS channel. Using a 85MHz clock, the data throughput is 595Mbytes per second. * Wide dot clock range: 25-170MHz suited for VGA, SVGA, XGA, SXGA, SXGA+ and UXGA * PLL requires No external components * Supports Single Link up to 112MHz dot clock for * * * * * * * * * SXGA Supports Dual Link up to 170MHz dot clock for UXGA 50% output clock duty cycle TTL clock edge programmable TTL output driverbility selectable for lower EMI Power down mode Low power single 3.3V CMOS design 100pin TQFP THC63LVDF84B compatible Pin compatible with THC63LVD824 Block Diagram RA1 +/RB1 +/1st Link RC1 +/RD1 +/- CMOS/TTL OUTPUT SERIAL TO PARALLEL LVDS INPUT 8 8 28 8 RED1 GREEN1 1st DATA BLUE1 HSYNC VSYNC RA2 +/RB2 +/2nd Link RC2 +/RD2 +/RCLK2 +/(25 to 85MHz) DE DEMUX PLL SERIAL TO PARALLEL RCLK1 +/(25 to 112MHz) RECEIVER CLOCK OUT (12.5 to 85MHz) 8 28 8 8 RED2 GREEN2 2nd DATA BLUE2 PLL R/F /PDWN Copyright(c)2014 THine Electronics, Inc. 1/14 THine Electronics, Inc. THC63LVD824A _Rev1.20_E DE VSYNC HSYNC B17 B16 GND VCC B15 B14 B13 B12 B11 B10 G17 G16 G15 G14 G13 GND VCC G12 G11 G10 R17 R16 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Pin Out GND VCC R14 R13 R12 R11 R10 GND VCC CLKOUT B27 B26 B25 B24 B23 GND VCC B22 B21 B20 G27 GND VCC G26 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 R15 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 50 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PLL VCC GND /PDWN MODE0 MODE1 GND R/F DRVSEL R20 R21 R22 R23 R24 VCC GND R25 R26 R27 G20 G21 G22 G23 G24 G25 76 RA1RA1+ RB1RB1+ LVDS VCC RC1RC1+ RCLK1RCLK1+ RD1RD1+ LVDS GND RA2RA2+ RB2RB2+ LVDS VCC RC2RC2+ RCLK2RCLK2+ RD2RD2+ LVDS GND PLL GND LVDS GND Copyright(c)2014 THine Electronics, Inc. 2/14 THine Electronics, Inc. THC63LVD824A _Rev1.20_E Pin Description Pin Name Pin # Type Description RA1+, RA1- 78, 77 LVDS IN RB1+, RB1- 80, 79 LVDS IN RC1+, RC1- 83, 82 LVDS IN RD1+, RD1- 87, 86 LVDS IN RCLK1+, RCLK1- 85, 84 LVDS IN RA2+, RA2- 90, 89 LVDS IN RB2+, RB2- 92, 91 LVDS IN RC2+, RC2- 95, 94 LVDS IN RD2+, RD2- 99, 98 LVDS IN RCLK2+, RCLK2- 97, 96 LVDS IN R17 ~ R10 52, 51, 50, 47, 46, 45, 44, 43 OUT G17 ~ G10 62, 61, 60, 59, 58, 55, 54, 53 OUT B17 ~ B10 72, 71, 68, 67, 66, 65, 64, 63 OUT R27 ~ R20 19, 18, 17, 14, 13, 12, 11, 10 OUT G27 ~ G20 29, 26, 25, 24, 23, 22, 21, 20 OUT B27 ~ B20 39, 38, 37, 36, 35, 32, 31, 30 OUT DE 75 OUT Data Enable Output. VSYNC 74 OUT Vsync Output. HSYNC 73 OUT Hsync Output. CLKOUT 40 OUT Clock Output. The 1st Link. The 1st pixel input data when Dual Link. LVDS Clock Input for 1st Link. The 2nd Link. These pins are disabled when Single Link. LVDS Clock Input for 2nd Link. The 1st Pixel Data Outputs. The 2nd Pixel Data Outputs. Output Driverbility Select. DRVSEL 9 IN R/F 8 IN DRVSEL H L clock 8mA 4mA data 4mA 2mA Output Clock Triggering Edge Select. H: Rising edge, L: Falling edge. Pixel Data Mode. MODE1 MODE0 L L L H other Mode Dual Link (Dual-in/Dual-out) Single Link(Single-in/Dual-out) Not Available MODE1, MODE0 6, 5 IN /PDWN 4 IN VCC 15, 27, 33, 41, 48, 56, 69 Power Power Supply Pins for TTL outputs and digital circuitry. GND 3, 7, 16, 28, 34, 42, 49, 57, 70 Ground Ground Pins for TTL outputs and digital circuitry. LVDS VCC 81,93 Power Power Supply Pins for LVDS inputs. LVDS GND 76, 88, 100 Ground Ground Pins for LVDS inputs. Copyright(c)2014 THine Electronics, Inc. H: Normal operation, L: Power down (all outputs are pulled to ground) 3/14 THine Electronics, Inc. THC63LVD824A _Rev1.20_E Pin Name Pin # Type Description PLL VCC 2 Power Power Supply Pin for PLL circuitry. PLL GND 1 Ground Ground Pin for PLL circuitry. Absolute Maximum Ratings 1 Supply Voltage (VCC) -0.3V ~ +4.0V CMOS/TTL Input Voltage -0.3V ~ (VCC + 0.3V) ( 4.0V) CMOS/TTL Output Voltage -0.3V ~ (VCC + 0.3V) ( 4.0V) LVDS Receiver Input Voltage -0.3V ~ (VCC + 0.3V) ( 4.0V) Output Current -15mA ~ 15mA Junction Temperature +125 C Storage Temperature Range -55 C ~ +125 C Maximum Power Dissipation @+25 C 1.7W Electrical Characteristics CMOS/TTL DC Specifications VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol Parameter Conditions Min. Typ. Max. Units VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VOH High Level Output Voltage VOL Low Level Output Voltage IINC Input Current IOH= -2mA, -4mA (data) IOH= -4mA, -8mA (clock) 2.4 V IOL= 2mA, 4mA (data) IOL= 4mA, 8mA (clock) 0V V IN V CC 0.4 V 10 A LVDS Receiver DC Specifications VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol Parameter Conditions VTH Differential Input High Threshold VIC= 1.2V VTL Differential Input Low Threshold VIC= 1.2V IINL Input Current Min. Typ. Max. 100 -100 VIN= 2.4V / 0V mV mV 20 VCC= 3.6V Units A 1. "Absolute Maximum Ratings" are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Copyright(c)2014 THine Electronics, Inc. 4/14 THine Electronics, Inc. THC63LVD824A _Rev1.20_E Supply Current VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol Parameter Condition(*) Receiver Supply IRCCW Max. Units MODE<1:0>=LL fCLKOUT = 85MHz Current CL=8pF, Vcc=3.6V (Worst Case Pattern) IRCCS Typ. Receiver Power Down Supply Current /PDWN = L 225 mA 10 A Switching Characteristics VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol Parameter Min. Typ. Max. Units Dual-in / Dual-out 11.76 tRCIP 40.0 ns Single-in / Dual-out 17.85 2tRCIP 80.0 ns tRCP CLKOUT Period tRCH CLKOUT High Time t RCP ----------2 ns tRCL CKLOUT Low Time t RCP ----------2 ns tRS TTL Data Setup to CLKOUT 0.3tRCP-0.5 ns tRH TTL Data Hold from CKLOUT 0.3tRCP-0.5 ns tTLH TTL Low to High Transition Time 2.5 4.0 ns tTHL TTL High to Low Transition Time 2.5 4.0 ns tSK Receiver Skew Margin CLKIN=85MHz -0.40 +0.40 ns CLKIN=112MHz -0.25 +0.25 ns +tSK ns tRIP1 Input Data Position0 tRIP0 Input Data Position1 t RCIP ------------- - t SK 7 t RCIP -----------7 t RCIP ------------- + t SK 7 ns tRIP6 Input Data Position2 t RCIP - - t SK 2 -----------7 t RCIP 2 -----------7 t RCIP 2 ------------ + t SK 7 ns tRIP5 Input Data Position3 t RCIP 3 ------------ - t SK 7 t RCIP 3 -----------7 t RCIP 3 ------------ + t SK 7 ns tRIP4 Input Data Position4 t RCIP - - t SK 4 -----------7 t RCIP 4 -----------7 t RCIP 4 ------------ + t SK 7 ns tRIP3 Input Data Position5 t RCIP 5 ------------ - t SK 7 t RCIP 5 -----------7 t RCIP 5 ------------ + t SK 7 ns tRIP2 Input Data Position6 t RCIP 6 ------------ - t SK 7 t RCIP 6 -----------7 t RCIP 6 ------------ + t SK 7 ns tRPLL Phase Lock Loop Set tRCIP CLKIN Period tCK12 Skew Time between RCLK1 and RCLK2 Copyright(c)2014 THine Electronics, Inc. -tSK 8.92 0.0 10.0 ms 40.0 ns 0.3t RCIP 5/14 ns THine Electronics, Inc. THC63LVD824A _Rev1.20_E AC Timing Diagrams TTL Outputs TTL Output 80% 80% 8pF 20% 20% TTL Output Load tTHL tTLH tRCH tRCL R/F = L CLKOUT VCC/2 VCC/2 VCC/2 R/F = H tRCP tRS Rxn Gxn Bxn tRH VCC/2 VCC/2 x = 1,2 n = 0~7 Phase Lock Loop Set Time VCC 3.0V RCLKx+/- /PDWN 2.0V tRPLL 2.0V CLKOUT Copyright(c)2014 THine Electronics, Inc. 6/14 THine Electronics, Inc. THC63LVD824A _Rev1.20_E Pixel Map Table for Single/Dual Link 1st Pixel Data 824A TTLOutputPin R10 2nd Pixel Data TFT Panel Data LSB 24Bit R10 824A TTLOutputPin 18Bit - R20 TFT Panel Data LSB 24Bit R20 18Bit - R11 R11 - R21 R21 - R12 R12 R10 R22 R22 R20 R13 R13 R11 R23 R23 R21 R14 R14 R12 R24 R24 R22 R15 R15 R13 R25 R25 R23 R16 R16 R14 R26 R26 R24 R27 R25 R17 MSB R17 R15 R27 MSB G10 LSB LSB G10 - G20 G20 - G11 G11 - G21 G21 - G12 G12 G10 G22 G22 G20 G13 G13 G11 G23 G23 G21 G14 G14 G12 G24 G24 G22 G15 G15 G13 G25 G25 G23 G16 G16 G14 G26 G26 G24 G17 MSB G17 G15 G27 MSB G27 G25 B10 LSB LSB B20 - B10 - B20 B11 B11 - B21 B21 - B12 B12 B10 B22 B22 B20 B13 B13 B11 B23 B23 B21 B14 B14 B12 B24 B24 B22 B15 B15 B13 B25 B25 B23 B16 B16 B14 B26 B26 B24 B17 B15 B27 B27 B25 B17 MSB Copyright(c)2014 THine Electronics, Inc. MSB 7/14 THine Electronics, Inc. THC63LVD824A _Rev1.20_E 824A TTL Data Output Timing for Single/Dual Link Example : SXGA(1280 x 1024) HSYNC DE CLKOUT R1x/G1x/B1x #1 #3 #5 #7 1275 #1277 #1279 R2x/G2x/B2x #2 #4 #6 #8 1276 #1278 #1280 #1 #2 n = 0~7 #1279 #1280 TFT Panel (1280 x 1024) Copyright(c)2014 THine Electronics, Inc. 8/14 THine Electronics, Inc. THC63LVD824A _Rev1.20_E AC Timing Diagrams LVDS Inputs tRIP2 tRIP3 tRIP4 tRIP5 tRIP6 tRIP0 tRIP1 Ryx+/- Ryx6 Ryx5 Ryx4 RCLKx+ Ryx3 Ryx2 Ryx1 Ryx0 Ryx6 Ryx5 Vdiff = 0V Ryx4 Ryx3 Ryx2 Ryx1 Vdiff = 0V x = 1,2 y = A,B,C,D tRCIP RCLK1+ Vdiff = 0V tCK12 RCLK2+ Vdiff = 0V Note: Vdiff = (Ryx+) - (Ryx-), (RCLKx+) - (RCLKx-) Copyright(c)2014 THine Electronics, Inc. 9/14 THine Electronics, Inc. THC63LVD824A _Rev1.20_E LVDS Data Inputs Timing Diagrams in Single Link Previous Cycle (2nd pixel data) Current Cycle (1st pixel data) RCLK1+ RA1+/- R26' R25' R24' R23' R22' G12 R17 R16 R15 R14 R13 R12 G22'' RB1+/- G27' G26' G25' G24' G23' B13 B12 G17 G16 G15 G14 G13 B23'' RC1+/- HSYNC' B27' B26' B25' B24' DE B17 B16 B15 B14 DE'' RD1+/- B20' G21' G20' R21' R20' x G11 G10 R11 R10 x'' Copyright(c)2014 THine Electronics, Inc. VSYNC HSYNC B11 B10 10/14 THine Electronics, Inc. THC63LVD824A _Rev1.20_E LVDS Data Inputs Timing Diagrams in Dual Link Previous Cycle Current Cycle RCLK1+ RA1+/- R16' R15' R14' R13' R12' G12 R17 R16 R15 R14 R13 R12 G12'' RB1+/- G17' G16' G15' G14' G13' B13 B12 G17 G16 G15 G14 G13 B13'' RC1+/- HSYNC' B17' B16' B15' B14' DE B17 B16 B15 B14 DE'' RD1+/- B10' G11' G10' R11' R10' x G11 G10 R11 R10 x'' VSYNC HSYNC B11 B10 RCLK2+ RA2+/- R26' R25' R24' R23' R22' G22 R27 R26 R25 R24 R23 R22 G22'' RB2+/- G27' G26' G25' G24' G23' B23 B22 G27 G26 G25 G24 G23 B23'' RC2+/- x' B27' B26' B25' B24' x x x B27 B26 B25 B24 x'' RD2+/- B20' G21' G20' R21' R20' x B21 B20 G21 G20 R21 R20 x'' Copyright(c)2014 THine Electronics, Inc. 11/14 THine Electronics, Inc. THC63LVD824A _Rev1.20_E Note 1)Power On Sequence Power on LVDS-Tx after THC63LVD824A. If it is not avoidable, please contact to mspsupport@thine.co.jp (for FAE mailing list) 2)Cable Connection and Disconnection Don't connect and disconnect the LVDS cable , when the power is supplied to the system. 3)GND Connection Connect the each GND of the PCB which LVDS-Tx and THC63LVD824A on it. It is better for EMI reduction to place GND cable as close to LVDS cable as possible. 4)Multi Drop Connection Multi drop connection is not recommended. TCLK+ LVDS-Tx THC63LVD824A TCLKTHC63LVD824A 5)Asynchronous use Asynchronous use such as following systems are not recommended. If it is not avoidable, please contact to mspsupport@thine.co.jp (for FAE mailing list) CLKOUT DATA IC LVDS-Tx CLKOUT DATA CLKOUT TCLK+ TCLK- THC63LVD824A IC TCLK+ LVDS-Tx TCLK- THC63LVD824A TCLK+ TCLKIC Copyright(c)2014 THine Electronics, Inc. DATA CLKOUT THC63LVD824A DATA IC TCLK+ TCLK- DATA THC63LVD824A 12/14 DATA THine Electronics, Inc. THC63LVD824A _Rev1.20_E Package INDEX 100 76 PIN No.1 75 16.0SQ TYP 14.0SQ TYP 0.5TYP 0.20 51 25 50 1.2MAX 26 UNITS:mm Copyright(c)2014 THine Electronics, Inc. 13/14 THine Electronics, Inc. THC63LVD824A _Rev1.20_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. This product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the product. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. E-mail : sales@thine.co.jp Copyright(c)2014 THine Electronics, Inc. 14/14 THine Electronics, Inc.