Teledyne e2v Semiconductors SAS 2018
EV12DS130AG
EV12DS130BG
LowPower12‐bit3GspsDigitaltoAnalog
Converterwith4/2:1Multiplexer
DatasheetDS1080
Whilst Teledyne e2v Semiconductors SAS has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the
consequences of any use thereof and also reserves the right to change the specification of goods without notice. Teledyne e2v Semiconductors SAS accepts no
liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of the devices in accordance with
information contained herein.
Teledyne e2v Semiconducto rs SAS, avenue de Rochepleine 381 20 Saint-Egrève, Fran ce Holding Company: Tele dyne e2v Semico nductors SAS
Telephone: +33 (0 )4 76 58 30 00
Contact Teledyne e2v by e-mail: hotline-b dc@teledyne-e2v.com or visit www.teledyne-e2v.com for global sales and operations centres
MAINFEATURES
•12‐bitResolution
•3GspsGuaranteedConversionRate
•7GHzAnalogOutputBandwidth
•4:1or2:1integratedParallelMUX(Selectable)
•SelectableOutputModesforperformanceoptimization:
ReturntoZero,NonReturntoZero,NarrowReturntoZero,RF
•LowLatencyTime:3.5ClockCycles
•1.4WattPowerDissipationinMUX4:1Mode
•Functions
– SelectableMUXRatio4:1(FullSpeed),2:1(HalfSpeed)
–TripleMajorityVoting
–User‐friendlyFunctions:
‐GainAdjustment
‐InputDataCheckBit(FPGATimingCheck)
‐SetupTimeandHoldTimeViolationFlags(STVF,HTVF)
‐ClockPhaseShiftSelectforSynchronizationwithDSP
(PSS[2:0])
‐OutputClockDivisionSelection(PossibilitytoChange
theDivisionRatiooftheDSPClock)
‐InputUnderClockingMode
‐DiodeforDiejunctionTemperatureMonitoring
•LVDSDifferentialDatainputandDSPClockOutput
•AnalogOutputSwing:1VppDifferential(100Differential
Impedance)
•ExternalResetforSynchronizationofMultipleMuxDACs
•PowerSupplies:3.3V(Digital),3.3V&5.0V(Analog)
•LGA255,CCGA255,Ci‐CGA255Package(21×21mmBody
Size,1.27mmPitch)
PERFORMANCES
Broadband:NPRat–14dBLoadingFactor,(SeeSection7.2.7
”NPRPerformance”onpage62)
•1stNyquist(NRTZ): NPR=51.3dB 10.0Bit
EquivalentatFs=3Gsps
•1stNyquist(NRTZ): NPR=55.7dB 10.8Bit
EquivalentatFs=1.5Gsps
•2ndNyquist(NRTZorRTZ): NPR=44.6dB 8.9Bit
EquivalentatFs=3Gsps
•3rdNyquist(RF): NPR=42.5dB8.6Bit
EquivalentatFs=3Gsps
SingleTone:(seeSection5.”FunctionalDescription”on
page17)
•PerformancesCharacterizedforFoutfrom100MHzto
4500MHzandfrom2Gspsto3.2Gsps
•PerformanceIndustriallyScreenedOver3NyquistZones
at3GspsforSelectedFout.
StepResponse
•FullScaleRise/FallTime60ps
APPLICATIONS
•DirectDigitalSynthesisforBroadbandApplications(L‐S
andLowerCBand)
•AutomaticTest Equipment(ATE)
•ArbitraryWaveformGenerators
•RadarWaveformSignalSynthesis
•DOCSISV3.0Systems
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1. BLOCKDIAGRAM
Figure1‐1. SimplifiedBlockDiagram
2. DESCRIPTION
TheEV12DS130A/Bisa12‐bit3GspsDACwithanintegrated4:1or2:1multiplexer,allowingeasy
interfacewithstandardLVDSFPGAsthankstouserfriendlyfeaturesasOCDS,PSS.
Itembedsdifferentoutputmodes(RTZ,NRZ,narrowRTZ,RF)thatallowperformanceoptimizations
dependingontheworkingNyquistzone.
TheNoisePowerRatio(NPR)performance,overmorethan900 MHzinstantaneousbandwidth,andthe
highlinearity(SFDR,IMD)overfull1stNyquistzoneat3Gsps(NRZfeature),makethisproductwell
suitedforhigh‐endapplicationssuchasarbitrarywaveformgeneratorsandbroadbandDDSsystems.
1st
M/S
2:1 or
4:1
MUX
2nd M/S
DAC
Core
(NRZ,
NRTZ,
RTZ,
RF)
DSP CLOCK
PHASE SHIFT
CLOCK
DIV/X
CLOCK
BUFFER
PSS[2:0]
DSP
DSPN
24
2
24
24
24
2
CLK, CLKN
Port Select
24 2
Latches Latches
MODE
[1:0]
MUX
STVF
HTVF
SYNC,
SYNCN
FPGA
GA
A
B
C
D
24
24
24
24
OUT,
OUTN
DIODE
4 data
ports (12-
bit
differential)
IDC_P
IDC_N
OCDS[1:0]
FPGA
TIMING
2
2
3
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3. ELECTRICALCHARACTERISTICS
3.1 AbsoluteMaximumRatings
Notes: 1. Absolutemaximumratingsarelimitingvalues(referencedtoGND=0V),tobeappliedindividually,whileotherparame‐
tersarewithinspecifiedoperatingconditions.Longexposuretomaximumratingmayaffectdevicereliability.
2. AllintegratedcircuitshavetobehandledwithappropriatecaretoavoiddamagesduetoESD.Damagecausedby
inappropriatehandlingorstoragecouldrangefromperformancedegradationtocompletefailure.
3. MaximumratingsenableactiveinputswithDACpoweredoff.
4. MaximumratingsenablefloatinginputswithDACpoweredon.
5. DSPclockandSTVF,HTVFoutputbuffersmustnotbeshortedtogroundnorpositivepowersupply.
Table 3-1. Absolute Maximum Ratings
Parameter Symbol Value Unit
PositiveAnalogsupplyvoltage VCCA5 6.0 V
PositiveAnalogsupplyvoltage VCCA3 4.0 V
PositiveDigitalsupplyvoltage VCCD 4.0 V
Digitalinputs(oneachsingle‐endedinput)andIDC,SYNC,signal
PortP=A,B,C,D[P0..P11],
[P0N..P11N]
IDC_P,IDC_N
SYNC,SYNCN
VIL
VIH
DigitalInputmaximumDifferentialmodeswing
GND–0.3
VCCA3
2.0
V
V
Vpp
Masterclockinput(oneachsingle‐endedinput)
VIL
VIH
MasterClockMaximumDifferentialmodeswing
CLK,CLKN 1.5
3.5
2.5
V
V
Vpp
Controlfunctionsinputs
VIL
VIH
MUX,
MODE[0..1],
PSS[0..2],
OCDS[0..1]
–0.4V
VCCD+0.4
V
V
GainAdjustmentfunction GA –0.3V,VCCA3+0.3 V
MaximumJunctionTemperature Tj 170 °C
StorageTemperature Tstg –65to150 °C
Electrostaticdischargeimmunity
ESDClassification
ESDHBM 1000
Class1B
V
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3.2 RecommendedConditionsofUse
Notes: 1. Forlowtemperatureitisrecommendedtooperateatmaximumanalogsupplies(VCCA3)level.
2. Therisetimeofanypowersupplies(Vccd,Vcca5,Vcca3)shallbe<10ms.
ForEV12DS130A,inordertoobtaintheguaranteedperformancesandfunctionality,thefollowingrulesshallbefollowed
whenpoweringthedevices(SeeSection8.9”PowerUpSequencing”onpage75)
ForEV12DS130B,nospecificpowerupsequencenorpowersuppliesrelationshipsarerequired.
3. Analogoutputisindifferential.Single‐endedoperationisnotrecommended.Guaranteedperformanceisonlyindifferen‐
tialconfiguration.
4. Nopower‐downsequencingisrequired.
Table 3-2. Recommended Conditions of Use
Parameter Symbol Comments RecommendedValue Unit Note
Positiveanalogsupplyvoltage VCCA5 5.0 V (2)(4)
Positiveanalogsupplyvoltage VCCA3 3.3 V (1)(2)(4)
Positivedigitalsupplyvoltage VCCD 3.3 V (2)(4)
Digitalinputs(oneachsingle‐endedinput)
andIDC,SYNC,signal
PortP=A,B,C,D
VIL
VIH
Differentialmodeswing
[P0..P11],
[P0N..P11N]
IDC_P,IDC_N
SYNC,SYNCN
1.075
1.425
700
V
V
mVpp
(3)
Masterclockinputpowerlevel
(Differentialmode) PCLK 3dBm
(3)
Controlfunctionsinputs MUX,OCDS,PSS,
MODE,PSS
VIL
VIH
0
VCCD
V
V
GainAdjustmentfunction GA Range 0
VCCA3
V
OperatingTemperatureRange Tc=Tcase
Tj=Tjunction
Military"M"&
spacegrade–55°C<Tc,Tj<125°C °C
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3.3 ElectricalCharacteristics
Valuesinthetablesbelowarebasedonourconditionsofmeasurementandvalidovertemperature
rangerespectivelyforM,andSpacequalitylevelandfortypicalpowersupplies(VCCA5=5.0V,
VCCA3 =3.3V,VCCD=3.3V),typicalswing,unlessspecifiedandinMUX4:1mode.
Table3‐3. ElectricalCharacteristics
Parameter Symbol Min Typ Max Unit Note
Test
Level(2)
RESOLUTION 12 bit 1,6
POWERREQUIREMENTS
PowerSupplyvoltage
‐Analog
‐Analog
‐Digital
VCCA5
VCCA3
VCCD
4.75
3.15
3.15
5
3.3
3.3
5.25
3.45
3.45
V
V
(7)(8) 1,6
PowerSupplycurrent(4:1MUX)
‐Analog
‐Analog
‐Digital
ICCA5
ICCA3
ICCD
84
106
187
92
125
213
mA
mA
mA
1,6
PowerSupplycurrent(2:1MUX)
‐Analog
‐Analog
‐Digital
ICCA5
ICCA3
ICCD
84
106
160
92
125
185
mA
mA
mA
1,6
Powerdissipation(4:1MUX) PD1.41.6W1,6
Powerdissipation(2:1DMUX) PD1.31.5W1,6
DIGITALDATAINPUTS,SYNCandIDCINPUTS
Logiccompatibility LVDS
Digitalinputvoltages:
‐Differentialinputvoltage
‐Commonmode
VID
VICM
100 350
1.25
500 mVp
V
1,6
4
Inputcapacitancefromeachsingleinputtoground 2pF5
DifferentialInputresistance801001201,6
CLOCKINPUTS
Inputvoltages(Differentialoperationswing) 0.56 12.24 Vpp4
Powerlevel(Differentialoperation)–4 1 8 dBm(1) 4
Commonmode2.42.5 2.6V4
Inputcapacitancefromeachsingleinputtoground
(atdielevel) 2pF5
DifferentialInputresistance 801001201,6
6
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Notes: 1. ForuseinhigherNyquistzone,itisrecommendedtousehigherpowerclockwithinthelimit.
DSPCLOCKOUTPUT
Logiccompatibility LVDS
Digitaloutputvoltages:
‐Differentialoutputvoltage
‐Commonmode
VOD
VOCM
240 350
1.30
450 mVp
V
1,6
4
ANALOGOUTPUT
Full‐scaleDifferentialoutputvoltage
(100differentiallyterminated)0.9211.08Vpp1,6
Full‐scaleoutputpower(differentialoutput) 0.25 1 1.64 dBm1,6
Single‐endedmid‐scaleoutputvoltage(50terminated) VCCA5–0.43 V(4)
Outputcapacitance 1.5pF5
Outputinternaldifferentialresistance 90 100110 1,6
OutputVSWR(usinge2vevaluationboard)
1.5GHz
3GHz
4.5GHz
1.17
1.54
1.64
4
Outputbandwidth6GHz4
FUNCTIONS
Digitalfunctions:MODE,OCDS,PSS,MUX
‐Logic0
‐Logic1
‐InputCurrent
VIL
VIH
IIN
1.6
0
VCCD
0.8
150
V
V
µA (6)
GainAdjustmentfunction GA 0 0
VCCA3
1,6
Digitaloutputfunction(HTVF,STVF)
‐Logic0
‐Logic1
‐OutputCurrent
VOL
VOH
IO
–
2.1
–
–
0.8
80
V
V
µA
(5)
(6)
1,6
DCACCURACY
DifferentialNon‐LinearityDNL+0.95LSB1,6
DifferentialNon‐Linearity DNL‐–0.95LSB1,6
IntegralNon‐LinearityINL+ 3LSB1,6
IntegralNon‐Linearity INL‐–3LSB 1,6
DCgain:
‐Initialgainerror
‐DCgainadjustment
‐DCgainsensitivitytopowersupplies
‐DCgaindriftovertemperature
–8 0
±11
±2
+8
+6
%
%
%
%
(3)
1,6
4
1,6
4
Table3‐3. ElectricalCharacteristics(Continued)
Parameter Symbol Min Typ Max Unit Note
Test
Level(2)
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2. SeeSection3.6onpage14forexplanationoftestlevels.
3. InitialgainerrorcorrespondstothedeviationoftheDCgaincentervaluefromunitygain.TheDCgainadjustment(GA
function)ensuresthattheinitialgaindeviationcanbecancelled.
TheDCgainsensitivitytopowersuppliesisgivenaccordingtherule:
GainSensVsSupply=|Gain@VccMin–Gain@VccMax|/Gain@Vccnom
4. Single‐endedoperationisnotrecommended,thislineisgivenforbetterunderstandingofwhatisoutputbytheDAC.
5. InordertomodifytheVOL/VOHvalue,potentialdividercouldbeused.
6. Sinkorsource.
7. OnlyforEV12DS130Adependencybetweenpowersupplies:
Withintheapplicablepowersuppliesrange,thefollowingrelationshipshallalwaysbesatisfiedVCCA3 VCCD,takinginto
accountAGNDandDGNDplanesaremergedandpowersuppliesaccuracy.
8. PleasereferSection8.9”PowerUpSequencing”onpage75.
3.4 ACElectricalCharacteristics
Valuesinthetablesbelowarebasedonourconditionsofmeasurementandvalidovertemperature
rangerespectivelyforM,andSpacequalitylevelandfortypicalpowersupplies(VCCA5=5.0V,
VCCA3 =3.3V,VCCD=3.3V),typicalswing,unlessspecifiedandinMUX4:1mode.
Table3‐4. ACElectricalCharacteristicsNRZMode(FirstNyquistZone)
Parameter Symbol Min Typ Max Unit Note
Test
level(1)
Single‐toneSpuriousFreeDynamicRange
FirstNyquist
Fs=3GSps@Fout=100MHz0dBFS
Fs=3GSps@Fout=400MHz0dBFS
Fs=3GSps@Fout=100MHz–3dBFS
|SFDR| 57
59
68
63
70
dBc 1,6
4
1,6
Highestspurlevel
FirstNyquist
Fs=3GSps@Fout=100MHz0dBFS
Fs=3GSps@Fout=400MHz0dBFS
Fs=3GSps@Fout=100MHz–3dBFS
–68
–61
–72
–56
–60
dBm
1,6
4
1,6
SFDRsensitivity&highspurlevelvariationoverpower
supplies ±2dB 4
SignalindependentSpur(clock‐relatedspur)
Fc/2 –82 dBm 4
Fc/4 –85 dBm 4
NoisePowerRatio
–14dBFSpeaktormsloadingfactor
Fs=3GSps
20MHzto900MHzbroadbandpattern,
25MHznotchcenteredon450MHz
NPR 45 49 dB (2) 1,6
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Notes: 1. SeeSection3.6onpage14forexplanationoftestlevels.
2. Figuresintablesarederivedfromindustrialscreening;forpracticalreasons(necessitytocoveralso2ndand3rdNyquist
Zones)thebalunusedforindustrialtestisnotoptimumforfirstNyquistperformances,andresultswhenFoutorfolded
loworderhamonicsarebetweenDCto400MHzareverypessimistic.ForfurtherdetailspleaserefertoSection7.2on
page42foreffectofthebalunonperformances.
EquivalentENOB
ComputedfromNPRfigureat3GSps ENOB 9 9.6 Bit (2) 1,6
SignaltoNoiseRatio
ComputedfromNPRfigureat3GSps SNR 56 58 dB (2) 1,6
DACselfnoisedensityatcode0or4095 –163 –154 dBm/H
z1,6
Table3‐4. ACElectricalCharacteristicsNRZMode(FirstNyquistZone)(Continued)
Parameter Symbol Min Typ Max Unit Note
Test
level(1)
Table3‐5. ACElectricalCharacteristicsNRTZMode(First&SecondNyquistZone)
Parameter Symbol Min Typ Max Unit Note
Test
level(1)
Single‐toneSpuriousFreeDynamicRange
MUX4:1
Fs=3GSps@Fout=100MHz0dBFS
Fs=3GSps@Fout=700MHz0dBFS
Fs=3GSps@Fout=1800MHz0dBFS
Fs=3GSps@Fout=700MHz–3dBFS
MUX2:1
Fs=1.5GSps@Fout=700MHz0dBFS
|SFDR|
60
55
52
57
51
68
62
61
66
65
dBc
1,6
1,6
1,6
1,6
1,6
Highestspurlevel
MUX4:1
Fs=3GSps@Fout=100MHz0dBFS
Fs=3GSps@Fout=700MHz0dBFS
Fs=3GSps@Fout=1800MHz0dBFS
Fs=3GSps@Fout=700MHz–3dBFS
MUX2:1
Fs=1.5GSps@Fout=700MHz0dBFS
–70
–64
–67
–70
–68
–62
–56
–57
–62
–53
dBm
1,6
1,6
1,6
1,6
1,6
SFDRsensitivity&highspurlevelvariationoverpower
supplies ±2dB4
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Notes: 1. SeeSection3.6onpage14forexplanationoftestlevels.
2. Figuresintablesarederivedfromindustrialscreening;forpracticalreasons(necessitytocoveralso2ndand3rdNyquist
Zones)thebalunusedforindustrialtestisnotoptimumforfirstNyquistperformances,andresultswhenFoutorfolded
loworderhamonicsarebetweenDCto400MHzareverypessimistic.ForfurtherdetailspleaserefertoSection7.2on
page42foreffectofthebalunonperformances.
SignalindependentSpur(clock‐relatedspur)
Fc –29 dBm 4
Fc/2 –80 dBm 4
Fc/4 –80 dBm 4
DACselfnoisedensityatcode0or4095 –149 –143 dBm/Hz 1,6
NoisePowerRatio
–14dBFSpeaktormsloadingfactor
Fs=3GSps
20MHzto900MHzbroadbandpattern,
25MHznotchcenteredon450MHz
NPR 45.5 50.2 dB (2) 1,6
EquivalentENOB
ComputedfromNPRfigureat3GSps ENOB 9.1 9.9 Bit (2) 1,6
SignaltoNoiseRatio
ComputedfromNPRfigureat3GSps SNR 56.5 61.2 dB (2) 1,6
NoisePowerRatio
–14dBFSpeaktormsloadingfactor
Fs=1.5GSps
10MHzto450MHzbroadbandpattern,
12.5MHznotchcenteredon225MHz
NPR 55.7 dB (2) 4
EquivalentENOB
ComputedfromNPRfigureat1.5GSps ENOB 10.8 Bit (2) 4
SignaltoNoiseRatio
ComputedfromNPRfigureat1.5GSps SNR 66.7 dB (2) 4
Table3‐5. ACElectricalCharacteristicsNRTZMode(First&SecondNyquistZone)(Continued)
Parameter Symbol Min Typ Max Unit Note
Test
level(1)
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Notes: 1. SeeSection3.6onpage14forexplanationoftestlevels.
2. PleaserefertoSection7.2”ACPerformances”onpage42tohavedetailedcharacterizationresults.
Table3‐6. ACElectricalCharacteristicsRTZMode(SecondNyquistZone)(2)
Parameter Symbol Min Typ Max Unit Note
Test
level(1)
Single‐toneSpuriousFreeDynamicRange
MUX4:1
Fs=3GSps@Fout=1600MHz0dBFS
Fs=3GSps@Fout=2900MHz0dBFS
|SFDR|
49
60
57
dBc 4
1,6
Highestspurlevel
MUX4:1
Fs=3GSps@Fout=1600MHz0dBFS
Fs=3GSps@Fout=2900MHz0dBFS
–67
–66 –59
dBm 4
1,6
SFDRsensitivity&highspurlevelvariationover
powersupplies ±2dB4
SignalindependentSpur(clock‐relatedspur)
Fc –25 dBm 4
Fc/2 –80 dBm 4
Fc/4 –80 dBm 4
DACselfnoisedensityatcode0or4095 –143 –139 dBm/Hz 1,6
NoisePowerRatio
–14dBFSpeaktormsloadingfactor
Fs=3GSps
1520MHzto2200MHzbroadbandpattern,
25MHznotchcenteredon1850MHz
NPR 39.5 44.0 dB 1,6
EquivalentENOB
ComputedfromNPRfigureat3GSps ENOB 8.1 8.8 Bit 1,6
SignaltoNoiseRatio
ComputedfromNPRfigureat3GSps SNR 50.5 55.0 dB 1,6
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Table3‐7. ACElectricalCharacteristicsRFMode(SecondandThirdNyquistZones)(2)
Parameter Symbol Min Typ Max Unit Note
Test
level(1)
Single‐toneSpuriousFreeDynamicRange
2ndNyquist
Fs=3GSps@Fout=1600MHz0dBFS
Fs=3GSps@Fout=2900MHz0dBFS
3rdNyquist
Fs=3GSps@Fout=3800MHz0dBFS
Fs=3GSps@Fout=4400MHz0dBFS
|SFDR|
44
45
45
52
60
53
54
dBc
1,6
4
1,6
1,6
Highestspurlevel
2ndNyquist
Fs=3GSps@Fout=1600MHz0dBFS
Fs=3GSps@Fout=2900MHz0dBFS
3rdNyquist
Fs=3GSps@Fout=3800MHz0dBFS
Fs=3GSps@Fout=4400MHz0dBFS
–58
–58
–60
–62
–50
–52
–55
dBm
1,6
4
1,6
1,6
SFDRsensitivity&highspurlevelvariationoverpowersupplies ±2dB 4
SignalindependentSpur(clock‐relatedspur)
Fc –28 dBm 4
Fc/2 –80 dBm 4
Fc/4 –80 dBm 4
DACselfnoisedensityatcode0or4095 –141 –138 dBm/Hz 1,6
NoisePowerRatio(2ndNyquist)
–14dBFSpeaktormsloadingfactor
Fs=3GSps
1520MHzto2200MHzbroadbandpattern,
25MHznotchcenteredon1850MHz
NPR 38 42 dB 1,6
EquivalentENOB
ComputedfromNPRfigureat3GSps ENOB 7.8 8.5 Bit 1,6
SignaltoNoiseRatio
ComputedfromNPRfigureat3GSps SNR 49 53 dB 1,6
NoisePowerRatio
–14dBFSpeaktormsloadingfactor
Fs=3GSps
2200MHzto2880MHzbroadbandpattern,
25MHznotchcenteredon2550MHz
NPR 38 42 dB 1,6
12
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Notes: 1. SeeSection3.6onpage14forexplanationoftestlevels.
2. Figuresintablesarederivedfromindustrialscreeningwithoutanycorrectiontotakeinaccountthebaluneffect,butfor
practicalreasons(necessitytocoveralso2ndand3rdNyquistZones)thebalunusedforindustrialtestisnotoptimumfor
firstNyquistperformances,andresultswhenFoutorfoldedloworderhamonicsarebetweenDCto400MHzarevery
pessimistic.
3.5 TimingCharacteristicsandSwitchingPerformances
EquivalentENOB
ComputedfromNPRfigureat3GSps ENOB 7.8 8.5 Bit 1,6
SignaltoNoiseRatio
ComputedfromNPRfigureat3GSps SNR 49 53 dB 1,6
NoisePowerRatio
–14dBFSpeaktormsloadingfactor
Fs=3GSps
3050MHzto3700MHzbroadbandpattern,
25MHznotchcenteredon3375MHz
NPR 38 40 dB (2) 1,6
EquivalentENOB
ComputedfromNPRfigureat3GSps ENOB 7.8 8.2 Bit (2) 1,6
SignaltoNoiseRatio
ComputedfromNPRfigureat3GSps SNR 49 51 dB (2) 1,6
Table3‐7. ACElectricalCharacteristicsRFMode(SecondandThirdNyquistZones)(2)(Continued)
Parameter Symbol Min Typ Max Unit Note
Test
level(1)
Table3‐8. TimingCharacteristicsandSwitchingPerformances
Parameter Symbol Min Typ Max Unit Note
Test
level(1)
SWITCHINGPERFORMANCEANDCHARACTERISTICS
Operatingclockfrequency
4:1MUXmode
2:1MUXmode
300
300
3000
1500
MHz 4
TIMINGCHARACTERISTICS
Analogoutputrise/falltime TOR
TOF
60 ps (2) 4
DataTsetup(Fc=3Gsps) 250 ps (3) 4
DataThold(Fc=3Gsps) 100 ps (3) 4
MaxInputdatarate(Mux4:1) 75 750 MSps 4
MaxInputdatarate(Mux2:1) 150 750 MSps 4
Masterclockinputjitter 100 fsrms (4) 5
DSPclockphasetuningsteps 0.5 Clockperiod 5
MasterclocktoDSP,DSPNdelay TDSP 1.6 ns 4
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Notes: 1. SeeSection3.6onpage14forexplanationofthetestlevel.
2. Analogoutputrise/falltimemeasuredfrom20%to80%ofafullscalejump,afterprobede‐embedding.
3. Exclusiveofperiod(pp)jitteronData.SetupandholdtimeforDATAatinputrelativetoDSPclockatoutputofthe
component,atPSS=000;alsoapplicableforIDCsignal.
4. Masterclockinputjitterdefinedover5GHzbandwidth.
5. TCrepresentsthemasterclockperiod.SeeFigure3‐3.
6. ForEV12DS130A,pleaserefertoerratasheet1125
Figure3‐1. TimingDiagramfor4:1MUXPrincipleofOperationOCDS[00]
SYNCforbiddenarealowerbound(Fc=3Gsps) T1200 ps (5)(6) 4
SYNCforbiddenareaupperbound(Fc=3Gsps) T2180 ps (5)(6) 4
SYNCtoDSP,DSPN
MUX2:1
MUX4:1
880
1600
ps 4
DataPipelineDelay
MUX4:1
MUX2:1
TPD 3.5
3.5
Clockperiod 4
DataOutputDelay TOD 160 ps 4
Table3‐8. TimingCharacteristicsandSwitchingPerformances(Continued)
Parameter Symbol Min Typ Max Unit Note
Test
level(1)
External CLK
Data input A
Data input B
Data input C
Data input D
Internal CLK/4 is used to clock the Data input A, B, C, D into DAC
Internal CLK/4
DSP clock is internal CLK/ 4 delay by the DAC (by step of 0,5 CLK vi a the PSS function) to be used as DDR clock fo r the FPGA
DSP with PSS[000]
DSP with PSS[001]
Pipeline delay 3,5 CLK + T OD Output dela y TOD
OUT
NN+1xxx
Nxxx
xxx
xxx
N+1
N+2
N+3
xxx
N+12
N+5 N+9 N+13
N+4 N+8
N+10 N+14
N+7 N+11 N+14
N+6
N+2 N+3 N+4 N+5 N+10N+6 N+7 N+8 N+9
SSS
SS
SS
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Figure3‐2. TimingDiagramfor2:1MUXPrincipleofOperationOCDS[00]
Figure3‐3. SYNCTimingDiagram
PleaserefertoSection5.9”Synchronizationfunctionsformulti‐DACoperation”onpage31.
3.6 ExplanationofTestLevels
OnlyMINandMAXvaluesareguaranteed.
Notes: 1. Unlessotherwisespecified.
2. Ifapplicable,pleasereferto“OrderingInformation”
External CLK
Data inp ut A
Data inp ut B
Internal CLK/2 is used to clock the Data input A, B into DAC
Internal CLK /2
DSP clock is internal CLK/2 delay by the DAC (by step of 0,5 CLK via the PSS function) to be used as DDR clock for the FPGA
DSP with PSS[001]
DSP with PSS[000]
Pipeline delay 3,5 CLK + TOD Output delay TOD
OUT
N+10N+8N+2 N+4 N+6
N N+1 N+2 N+8N+3N+4N+5N+6
xxx XXX N+1
xxx
N+3
xxx XXX N
N+7
N+12
N+5 N+7 N+9 N+11 N+13
SS
SS
SYNC OK OK
NOK NOK
t1
t2
SYNC OK
SYNC NOK
SYNC NOK
Master Clk
t2
t1
1100%productiontestedat+25°C(1)
2100%productiontestedat+25°C(1),andsampletestedatspecifiedtemperatures.
3Sampletestedonlyatspecifiedtemperatures
4Parameterisguaranteedbydesignand/orcharacterizationtesting(thermalsteady‐stateconditionsatspecified
temperature)
5Parametervalueisguaranteedbydesign
6100%productiontestedoverspecifiedtemperaturerange(forSpace/Milgrade(2))
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3.7 DigitalInputCodingTable
Table3‐9. CodingTable(Theoricalvalues)
Digitaloutput
msb………..lsb
Differential
analogoutput
000000000000 –500mV
010000000000 –250mV
011000000000 –125mV
011111111111 –0.122mV
100000000000 0.122mV
101000000000 +125mV
110000000000 +250mV
111111111111 +500mV
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4. DEFINITIONOFTERMS
Abbreviation Term Definition
(Fsmax) Maximumconversion
Frequency Maximumconversionfrequency
(Fsmin) Minimumconversionfrequency MinimumconversionFrequency
(SFDR) Spuriousfreedynamicrange
RatioexpressedindBoftheRMSsignalamplitude,setatFullScale,totheRMSvalueofthe
highestspectralcomponent(peakspuriousspectralcomponent).Thepeakspurious
componentmayormaynotbeaharmonic.ItmaybereportedindB(i.e.,relatedto
converter0dBFullScale),orindBc(i.e,relatedtoinputsignallevel).
(HSL) HighSpurLevel PowerofhighestspuriousspectralcomponentexpressedindBm.
(ENOB) EffectiveNumberOfBits
ENOBisdeterminatedfromNPRmeasurementwiththeformula:
ENOB=(NPR[dB]+ILF[dB]I–3–1.76)/6.02
WhereLF“Loadingfactor”istheratiobetweentheGaussiannoisestandarddeviation
versusamplitudefullscale.
(SNR) Signaltonoiseratio
SNRisdeterminatedfromNPRmeasurementwiththeformula:
SNR[dB]=NPR[dB]+ILF[dB]I–3
WhereLF“Loadingfactor”istheratiobetweentheGaussiannoisestandarddeviation
versusamplitudefullscale.
(DNL) Differentialnonlinearity
TheDifferentialNonLinearityforangivencodeiisthedifferencebetweenthemeasured
stepsizeofcodeiandtheidealLSBstepsize.DNL(i)isexpressedinLSBs.DNListhe
maximumvalueofallDNL(i).DNLerrorspecificationoflessthan1LSBguaranteesthat
therearenomissingpointandthatthetransferfunctionismonotonic.
(INL) Integralnonlinearity
TheIntegralNonLinearityforagivencodeiisthedifferencebetweenthemeasuredvoltage
atwhichthetransitionoccursandtheidealvalueofthistransition.
INL(i)isexpressedinLSBs,andisthemaximumvalueofall|INL(i)|
(TPD/TOD) Outputdelay
Theanalogoutputpropagationdelaymeasuredbetweentherisingedgeofthedifferential
CLK,CLKNclockinput(zerocrossingpoint)andthezerocrossingpointofafull‐scaleanalog
outputvoltagestep.TPDcorrespondstothepipelinedelayplusaninternalpropagation
delay(TOD)includingpackageaccesspropagationdelayandinternal(on‐chip)delayssuch
asclockinputbuffersandDACconversiontime.
(NPR) NoisePowerRatio
TheNPRismeasuredtocharacterizetheDACperformanceinresponsetobroadbandwidth
signals.Whenapplyinganotch‐filteredbroadbandwhite‐noisepatternattheinputtothe
DACundertest,theNoisePowerRatioisdefinedastheratiooftheaveragenoisemeasured
ontheshoulderofthenotchandinsidethenotchonthesameintegrationbandwidth.
(VSWR) VoltageStandingWaveRatio TheVSWRcorrespondstotheinsertionlosslinkedtopowerreflection.ForexampleaVSWR
of1:2correspondstoa20dBreturnloss(ie.99%powertransmittedand1%reflected).
(IUCM) Inputunderclockingmode TheIUCMprincipleistoapplyaselectabledivisionratiobetweenDACsectionclockandthe
MUXsectionclock.
(PSS) PhaseShiftSelect ThePhaseShiftSelectfunctionallowtotunethephaseoftheDSPclock.
(OCDS) OutputClockDivisionSelectt ItallowstodividetheDSPclockfrequencybytheOCDScodedvaluefactor
(NRZ) NonReturntoZeromode NonReturntoZeromodeonanalogoutput
(RF) RadioFrequencymode RFmodeonanalogoutput
(RTZ) Returntozero Returntozeromodeonanalogoutput
(NRTZ) Narrowreturntozero Narrowreturntozeromodeonanalogoutput
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5. FUNCTIONALDESCRIPTION
Figure5‐1. DACFunctionalDiagram
Table5‐1. FunctionsDescription
Name Function Name Function
VCCD 3.3VDigitalPowerSupply CLK In‐phaseMasterclock
VCCA5 5.0VAnalogPowerSupply CLKN InvertedphaseMasterclock
VCCA3 3.3VAnalogPowerSupply DSP_CK In‐phaseOutputclock
DGND DigitalGround DSP_CKN InvertedphaseOutputclock
AGND Analogground(foranalogsupply
reference) PSS[0..2] Phaseshiftselect
A[11…0] In‐phasedigitalinputPortAGAGainAdjust
A[11..0]N InvertedphasedigitalinputPortA MUX MultiplexerSelection
B[11…0] In‐phasedigitalinputPortBMODE[0..1]DACMode:NRZ,RTZ,NRTZ,RF
B[11..0]N InvertedphasedigitalinputPortBSTVF SetuptimeViolationflag
C[11…0] In‐phasedigitalinputPortCHTVFHoldtimeViolationflag
C[11..0]N InvertedphasedigitalinputPortCIDC_P,IDC_N Inputdatacheck
D[11…0] In‐phasedigitalinputPortD OCDS[0..1] OutputClockDivisionfactorSelection
D[11..0]N InvertedphasedigitalinputPortDDiode Diodefortemperaturemonitoring
OUT In‐phaseanalogoutput SYNC/SYNCN Synchronizationsignal(ActiveHigh)
OUTN Invertedphaseanalogoutput IUCM InputUnderClockingMode
AGND
DAC 12-bit
2x12
2x12
2x12
2x12
A
0…A11
A
0N…A11N
B0…B11
B0N…B11N
C0…C11
C0N…C11N
CLK, CLKN
SYNC
2 OUT, OUTN
2 DSP_CK,
DSP_CKN
MUX
MODE
GA
PSS 3
D0…D11
D0N…D11N
IUCM
DIODE
2
DGND
2
2
OCDS 2
IDC_P
IDC_N
2
STVF
HTVF
V
CCD
V
CCA5
V
CCA3
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5.1 DSPOutputClock
TheDSPoutputclockDSP,DSPNisanLVDSsignalwhichisusedtosynchronizetheFPGAgeneratingthe
digitalpatternswiththeDACsamplingclock.
TheDSPclockfrequencyisafractionofthesamplingclockfrequency.Thedivisionfactordependson
OCDSsettings.TheDSPclockfrequencyisequalto(samplingfrequency/[2N*X])whereNistheMUX
ratioandXistheoutputclockdivisionfactor,determinedbyOCDS[0..1]bits.
Forexample,ina4:1MUXratioapplicationwithasamplingclockof3GHzandOCDSsetto“00”(ie.
Factorof1),theinputdatarateis750MSpsandtheDSPclockfrequencyis375MHz.
ThisDSPclockisusedintheFPGAtocontrolthedigitaldatasequencing.Itsphasecanbeadjusted
usingthePSS[2:0]bits(refertoSection5.5onpage26)inordertoensureapropersynchronization
betweenthedatacomingtotheDACandthesamplingclock.
TheHTVFandSTVFbitsshouldbeusedtocheckwhetherthetimingbetweentheFPGAandtheDACis
correct.HTVFandSTVFbitswillindicatewhethertheDACandFPGAarealignedornot.PSSbitsshould
thenbeusedtoshifttheDSPclockandthustheinputdataoftheDAC,sothatacorrecttimingis
achievedbetweentheFPGAandtheDAC.
Importantnote:MaximumsupportedsamplingfrequencywhenusingDSPtoclockdigitaldatais2.1
GspsonEV12DS130B.PleaserefertoapplicationnoteAN1141touseEV12DS130Batsampling
frequencybeyond2.1GHz.
5.2 Multiplexer
Twomultiplexerratioareallowed:
•4:1whichallowsoperationatfullsamplingrate(ie.3GHz)
•2:1whichcanonlybeusedupto1.5GHzsamplingrate,exceptinIUCMmode
In2:1MUXratio,theunuseddataports(portsCandD)canbeleftopen.
5.3 MODEFunction
TheMODEfunctionallowschoosingbetweenNRZ,NRTZ,RTZandRFfunctions.NRZandnarrowRTZ
shouldbechosenforusein1stNyquistzonewhileRTZshouldbechosenforusein2ndandRFfor3rd
Nyquistzones.
Label Value Description
MUX
04:1mode
12:1mode
Label Value Description DefaultSetting(NotConnected)
MODE[1:0]
00 NRZmode
11
RFmode
01 NarrowRTZ(a.k.a.NRTZ)mode
10 RTZMode(50%)
11 RFmode
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Theoryofoperation:seefollowingsubsectionsfortimedomainwaveformofthedifferentmodes.
IdealequationsdescribingmaxavailablePoutforfrequencydomaininthefourmodesaregiven
hereafter,withX=normalizedoutputfrequency(thatisFout/Fclock,edgesofNyquistzonesarethen
atX=01/213/22…).Duetolimitedbandwidth,anextratermmustbeaddedtotakeinaccountafirst
orderlowpassfilter.
NRZmode:
wheresinc(x)=sin(x)/x,andk=1
NRTZmode:
whereTiswidthofreshapingpulse,Tisabout75ps.
RTZmode:
wherekisthedutycycleoftheclockpresentedattheDACinput,pleasenotethatduetophase
mismatchinbalunusedtoconvertsingleendedclocktodifferentialclockthefirstzeromaymove
aroundthelimitofthe4thandthe5thNyquistzones.Ideallyk=1/2.
RFmode:
wherekisasperinNRTZmode.
Asaconsequence:
•NRZmodeoffersmaxpowerfor1stNyquistoperation
•RTZmodeoffersslowrollofffor2ndNyquistor3rdNyquistoperation
•RFmodeoffersmaximumpowerover2ndand3rdNyquistoperation
•NRTZmodeoffersoptimumpoweroverfull1standfirsthalfof2ndNyquistzones.Thisisthemost
relevantintermofperformanceforoperationover1standbeginningof2ndNyquistzone.Depending
onthesamplingratethezerooftransmissionmovesinthe3rdNyquistzonefrombegintoendwhen
samplingrateincreases.
Pout(X) 20 log10
ksinckX
0.893
---------------------------------------------
=
Pout(X) 20 log10
ksinckX
0.893
---------------------------------------------
=
kTclk T–
Tclk
-----------------------=
Pout(X) 20 log10
ksinckX
0.893
---------------------------------------------
=
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Noteinthetwofollowingfigures:Pinklineisidealequation’sresult,andgreenlineincludesafirst
order6GHzcut‐offlowpassfiltertotakeintoaccountfinitebandwidtheffectduetodieandpackage.
Figure5‐2. MaxAvailablePout[dBm]atNominalGainvsFout[GHz]intheFourOutputModesat3Gsps,overfour
NyquistZones,ComputedforT=75ps
1s
t
Nyquist 2n
d
Nyquist 3r
d
Nyquist 4
th
Nyquist 1s
t
Nyquist 2n
d
Nyquist 3r
d
Nyquist 4
th
Nyquist
1s
t
Nyquist 2n
d
Nyquist 3r
d
Nyquist 4
th
Nyquist 1s
t
Nyquist 2n
d
Nyquist 3r
d
Nyquist 4
th
Nyquist
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Figure5‐3. MaxavailablePout[dBm]atNominalGainvsFout[GHz]intheFourOutputModesat2Gsps,overfour
NyquistZones,ComputedforT=75ps
5.3.1 NRZOutputMode
Thismodedoesnotallowforoperationinthe2ndNyquistzonebecauseoftheSinx/xnotch.
Theadvantageisthatitgivesgoodresultsatthebeginningofthe1stNyquistzone(lessattenuation
thaninRTZarchitecture),itremovestheparasiticspurattheclockfrequency(indifferential).
Figure5‐4. NRZTimingDiagram
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist 1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
Mux OUT
External CLK
T=TOD
T=T
clk
N N+1 N+2 N+3
Analog Output signal 0V
N+3 N+4XXX N N+1 N+2
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5.3.2 NarrowRTZMode(NRTZMode)
Thismodehasthefollowingadvantages:
• Optimizedpowerin1stNyquistzone
• Extendeddynamicthrougheliminationofnoiseontransitionedges
•Improvedspectralpurity(seeSection7.2.3onpage50)
•TradeoffbetweenNRZandRTZ
Figure5‐5. NarrowRTZTimingDiagram
Note: TisindependentofFclock.
5.3.3 RTZMode
TheadvantageoftheRTZmodeistoenabletheoperationinthe2ndzonebutthedrawbackisclearlyto
attenuatemorethesignalinthefirstNyquistzone.
Advantages:
• Extendedrolloffofsinc
• Extendeddynamicthrougheliminationofhazardoustransitions
Weakness:
•ByconstructionclockspuratFs.
Figure5‐6. RTZTimingDiagram
Mux OUT
External CLK
T=TOD+Tτ/2
T=Tclk-Tτ
N N+1 N+2 N+3
Analog Output signal
N+4 0V
TτTτTτTτTτ
N+3 N+4XXX N N+1 N+2
Mux OUT
External CLK
T=TOD
T=0,5xTclk
N N+ 1 N+2 N+3
N+4
A
nalog Output signal 0V
N+3 N+4XXX N N+1 N+2
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5.3.4 RFMode
RFmodeisoptimalforoperationathighoutputfrequency,sincethedecaywithfrequencyoccursat
higherfrequencythanforRTZ.UnlikeNRZorRTZmodes,RFmodepresentsanotchatDCand2N*Fs,
andminimumattenuationforFout=Fs.
Advantages:
• Optimizedfor2ndand3rdNyquistoperation
• Extendeddynamicrangethrougheliminationofhazardoustransitions.
•Clockspurpushedto2.Fs
Figure5‐7. RFTimingDiagram
Note: Thecentraltransitionisnothazardousbutitseliminationallowstopushclockspurto2.Fs
TisindependentofFclock.
5.4 InputUnderClockingMode(IUCM),PrincipleandSpectralResponse
AnInputUnderClockingModehasbeenaddedtotheDACinordertoallowtheDACinputdatarateto
beathalfthenominalratewithrespectoftheDACsamplingrate.
Whentheunderclockingmodeisactivated,theDACexpectsdataathalfthenominalrate:iftheDAC
worksatFssamplingrate,thenin4:1MUXmode,theinputdatarateshouldbeFs/4andtheDSPclock
shouldbeFs/(2N*OCDS),withN=MUXratioandOCDS=OCDSRatio.
WhentheIUCMisactive,theinputdataratecanbeFs/8andtheDSPclockfrequencyis
Fs/(2N*OCDS*2),withN=MUXratioandOCDS=OCDSRatio.Thismeansthatininputunderclocking
mode,theDACiscapabletotreatdataathalfthenominalrate.Inthiscase,theDSPclockisalsohalfits
nominalspeed.
Mux OUT
External CLK
T=TOD+Tτ
/2
T=Tclk-Tτ
N N+1 N+2 N+3
N+4
A
nalog Output signal
0V
TτTτTτTτTτ
N+3 N+4XXX N N+1 N+2
Label LogicValue Description
IUCM
0 InputUnderClockingModeinactive
1 InputUnderClockingModeactive
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Todisablethismode,theIUCMpinmustbeconnectedtoGND.
Toenablethismode,IUCMmustbeconnectedtoVCCDorleftunconnected
TheIUCMmodeaffectsspectralresponseofthedifferentmodes.
ThefirsteffectisthatNyquistzoneedgesarenotanymoreatn*Fclock/2butatn*/Fclock/4(direct
consequenceofthedivisionby2ofthedatarate).
Thesecondeffectisthemodificationoftheequationsrulingthespectralresponsesinthedifferent
modes.
IdealequationsdescribingmaxavailablePoutforfrequencydomaininthefouroutputmodeswhen
IUCMmodeisactivatedaregivenhereafter,withX=normalisedoutputfrequency(thatisFout/Fclock,
edgesofNyquistZonesarethenatX=0,1/4,1/2,3/4,1,…)
Infactduetolimitedbandwidth,anextratermmustbeaddedtotakeinaccountafirstorderlowpass
filterwitha6GHzcut‐offfrequency.
NRZmode:
wheresinc(x)=sin(x)/x,andk=1
NRTZmode:
whereTiswidthofreshapingpulse,Tisabout75ps.
RTZmode:
wherekisthedutycycleoftheclockpresentedattheDACinput,pleasenotethatduetophase
mismatchinbalunusedtoconvertsingleendedclocktodifferentialclockthefirstzeromaymove
aroundthelimitofthe4thandthe5thNyquistzones.Ideallyk=1/2.
RFmode:
wherekisasperinNRTZmode.
Pout(X) 20 log10
ksinckX.Xcos
0.893
----------------------------------------------------------------------------
=
Pout(X) 20 log10
ksinckX.Xcos
0.893
----------------------------------------------------------------------------
=
kTclk T–
Tclk
-----------------------=
Pout(X) 20 log10
ksinckX.Xcos
0.893
---------------------------------------------------------------------------
=
Pout(X) 20 log10
ksinc
kX
2
-------------------


kX
2
-------------------


. .Xcossin
0.893
-------------------------------------------------------------------------------------------------------------------
=
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Figure5‐8. MaxavailablePout[dBm]atnominalgainvsFout[GHz]inthefouroutputmodesat3GSps,combinedwith
IUCM,overfournyquistzones,computedforT=75ps.
NZ1 NZ2 NZ3 NZ4 NZ5 NZ6 NZ7 NZ8
NZ1 NZ2 NZ3 NZ4 NZ5 NZ6 NZ7 NZ8 NZ1 NZ2 NZ3 NZ4 NZ5 NZ6 NZ7 NZ8
NZ1 NZ2 NZ3 NZ4 NZ5 NZ6 NZ7 NZ8
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Figure5‐9. MaxavailablePout[dBm]atnominalgainvsFout[GHz]inthefouroutputmodesat2GSps,combinedwith
IUCM,overfournyquistzones,computedforT=75ps
5.5 PSS(PhaseShiftSelectFunction)
ItispossibletoadjustthetimingsbetweenthesamplingclockandtheDSPoutputclock(which
frequencyisgivenbythefollowingformula:Samplingclock/2NXwhereNistheMUXratio,Xthe
outputclockdivisionfactor).
TheDSPclockoutputphasecanbetunedoverarangeof3.5inputclockcycles(7stepsofhalfaclock
cycle)inadditiontotheintrinsicpropagationdelaybetweentheDSPclock(DSP,DSPN)andthe
samplingclock(CLK,CLKN).
Threebitsareprovidedforthephaseshiftfunction:PSS[2:0].
Bysettingthese3bitsto0or1,onecanaddadelayontheDSPclockinordertoproperlysynchronize
theinputdataoftheDACandthesamplingclock(theDSPclockshouldbeappliedtotheFPGAand
shouldbeusedtoclocktheDACdigitalinputdata).
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InordertodeterminehowmuchdelayneedstobeaddedontheDSPclocktoensurethe
synchronizationbetweentheinputdataandthesamplingclockwithintheDAC,theHTVFandSTVFbits
shouldbemonitored.RefertoSection5.7onpage29.
Note: InMUX4:1modethe8settingsarerelevant,inMUX2:1onlythefourfirstsettingsarerelevantsincethe
fourlastoneswillyieldexactlythesameresults.
Figure5‐10. PSSTimingDiagramfor4:1MUX,OCDS[00]
Table5‐2. PSSCodingTable
Label Value Description
PSS[2:0]
000 NoadditionaldelayonDSPclock
001 0.5inputclockcycledelayonDSPclock
010 1inputclockcycledelayonDSPclock
011 1.5inputclockcycledelayonDSPclock
100 2inputclockcycledelayonDSPclock
101 2.5inputclockcycledelayonDSPclock
110 3inputclockcycledelayonDSPclock
111 3.5inputclockcycledelayonDSPclock
Extern al CLK
Internal CLK/4 is used to clock the Data input A, B, C, D into DAC
Internal CLK/4
DSP with PSS[000]
T=0.5xTclk
DSP with PSS[001]
DSP with PSS[010]
DSP with PSS[011]
DSP with PSS[110]
DSP with PSS[111]
.
.
.
DSP clock is a ratio of internal clock delayed by step of 0.5 Tclk via the PSS function and outputed in DDR mode.
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Figure5‐11. PSSTimingDiagramfor2:1MUX,OCDS[00]
5.6 OutputClockDivisionSelectFunction
ItispossibletochangetheDSPclockinternaldivisionfactorfrom1to2withrespecttothesampling
clock/2NwhereNistheMUXratio.ThisispossibleviatheOCDS"OutputClockDivisionSelect"bits.
OCDSisusedtoobtainasynchronizationclockfortheFPGAslowenoughtoallowtheFPGAtooperate
withnofurtherinternaldivisionofthisclock,thusitsinternalphaseisdeterminedbytheDSPclock
phase.ThisisusefulinasystemwithmultipleDACsandmultipleFPGAstoguaranteedeterministic
phaserelationshipbetweentheFPGAsafterasynchronizationofalltheDACs.
Figure5‐12. OCDSTimingDiagramfor4:1MUX
External CLK
Internal C LK/2 is us e d to cloc k the Data input A, B into DAC
Internal CLK/2
DSP with PSS[000]
T=0.5xTclk
DSP with PSS[001]
DSP wi th PSS[ 010]
DSP wi th PSS[ 011]
DSP wi th PSS[ 110]
DSP wi th PSS[ 111]
.
.
.
DSP clock is a ratio of internal clock delayed by step of 0.5 Tclk via the PSS function and outputed in DDR mode.
Table5‐3. OCDS[1:0]CodingTable
Label Value Description
OCDS[1:0]
00 DSPclockfrequencyisequaltothesamplingclockdividedby2N
01 DSPclockfrequencyisequaltothesamplingclockdividedby2N*2
10 Notallowed
11 Notallowed
External CLK
Internal CLK/4 is used to clock the Data input A, B, C, D into DAC
Internal CLK/4
DSP clock is internal CLK/4 divided by OCDS selection. This clock could be used as DDR clock for the FPGA
DSP with OCDS[00]
DSP with OCDS[01]
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Figure5‐13. OCDSTimingDiagramfor2:1MUX
5.7 SynchronizationFPGA‐DAC:IDC_P,IDC_N,HTVFandSTVFFunctions
IDC_P,IDC_N:InputDatacheckfunction(LVDSsignal).
HTVF:HoldTimeViolationFlag.(cmos3.3Vsignal)
STVF:SetupTimeViolationFlag.(cmos3.3Vsignal)
IDCsignalistogglingateachcyclesynchronouslywithotherdatabits.ItshouldbeconsideredasaDAC
inputdatathattogglesateachcycle.
ThissignalshouldbegeneratedbytheFPGAinorderfortheDACtocheckinreal‐timeifthetimings
betweentheFPGAandtheDACarecorrect.
Figure5‐14. IDCTimingvsDataInput
TheinformationonthetimingsisthengivenbyHTVF,STVFsignals(flags).
DuringmonitoringSTVFindicatessetuptimeofdataviolation(Low‐>OK,High‐>Violation),HTVF
indicatesholdtimeofdataviolation(Low‐>OK,High‐>Violation).
External CLK
Internal CLK/2 is used to clock the Data input A, B into DAC
Internal CLK/2
DSP clock is int ernal CLK/2 divided by OCDS selection. This clock c oul d be u sed as DDR clock for the FPGA
DSP with OCDS[00]
DSP with OCDS[01]
Table5‐4. HTVF,STVFCodingTable
Label Value Description
HTVF
0SYNCHROOK
1DataHoldtimeviolationdetected
STVF
0SYNCHROOK
1DataSetuptimeviolationdetected
IDC_P,
IDC_N
Data
Xi, XiN
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Figure5‐15. FPGAtoDACSynoptic
PrincipleofOperation:
TheInputDataCheckpair(IDC_P,IDC_N)willbesampledthreetimeswithhalfamasterclockperiod
shift(thesecondsamplebeingsynchronouswithallthedatasamplinginstant),thesethreesamples
willbecompared,anddependingontheresultsofthecomparisonaviolationmaybesignalled.
•Violationofsetuptime‐>STVFishighlevel
•Violationofholdtime‐>HTVFishighlevel
Incaseofviolationoftiming(setuporhold)theuserhastwosolutions:
•ShiftphaseintheFPGAPLL(ifthisfunctionalityisavailableinFPGA)forchangingtheinternaltiming
ofDATAandDataChecksignalinsideFPGA.
•ShifttheDSPclocktiming(OutputclockoftheDACwhichcanbeusedforFPGAsynchronization–
refertoSection5.5onpage26),inthiscasethisshiftalsoshifttheinternaltimingofFPGAclock.
Note: Whenused,itshouldberoutedasthedatasignals(samelayoutrulesandsamelength).ifnotused,it
shouldbedriventoanLVDSloworhighlevel.
Forfurtherdetails,refertoapplicationnoteAN1087.
FPGA DAC
IDC
Port A
Port B
Port C
Port D
HTVF, STVF
OCDS
2
2
24
24
24
24
2
2
DSP
3
PSS
CLK DIV 2
τ
OUT
2
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5.8 OCDS,MUXCombinationsSummary
Note: Behaviour according to MUX, OCDS and PSS combination is independent of output mode (MODE).
5.9 Synchronizationfunctionsformulti‐DACoperation
Inordertosynchronizethetimings,aSYNCoperationcanbegenerated.
AftertheapplicationoftheSYNCsignaltheDSPclockfromtheDACwillstopforaperiodandaftera
constantandknowntimetheDSPclockwillstartupagain.
TherearetwoSYNCfunctionsintegratedinthisDAC:
•apowerupreset,whichistriggeredbythepowersuppliesifthededicatedpowerupsequenceis
appliedVccd=>Vcca3=>Vcca5;
•ExternalSYNCpulseappliedon(SYNC,SYNCN).
TheexternalSYNCisLVDScompatible(samebufferasforthedigitalinputdata).Itisactivehigh.
DependingonthesettingsforOCDS,PSSandalsotheMUXratiothewidthoftheSYNCpulsemustbe
greaterthanacertainnumberofexternalclockpulses.Itisalsonecessarythatthesyncpulsebe
synchronizedwiththesystemclockandisanintegernumberofclockpulses.Seeapplicationnote
(ref 1087)forfurtherdetails.
Table5‐5. OCDS,IUCM,MUX,PSSCombinationsSummary
MUX IUCM OCDS PSSrange Datarate Comments
0
4:1
1
ON
00 DSPclockdivisionfactor16
0to7/ ( 2 F s ) by
1/(2Fs)steps Fs/8 RefertoSection
5.6
0 1 01 DSPclockdivisionfactor32
01 10Notallowed
01 11Notallowed
00
OFF,normalmode
00 DSPclockdivisionfactor8
0to7/ ( 2 F s ) by
1/(2Fs)steps Fs/4 RefertoSection
5.6
0 0 01 DSPclockdivisionfactor16
00 10Notallowed
00 11Notallowed
1
2:1
1
ON
00 DSPclockdivisionfactor8
0to7/ ( 2 F s ) by
1/(2Fs)steps Fs/4
Not
recommended
mode,not
guaranteed
1 1 01 DSPclockdivisionfactor16
11 10Notallowed
11 11Notallowed
10
OFF,normalmode
00 DSPclockdivisionfactor4
0to7/ ( 2 F s ) by
1/(2Fs)steps Fs/2 RefertoSection
5.6
10 01DSPclockdivisionfactor8
10 10Notallowed
10 11Notallowed
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Figure5‐16. ResetTimingDiagram(4:1MUX)
Figure5‐17. ResetTimingDiagram(2:1MUX)
Importantnote:
ForEV12DS130A:
•Seeerratasheet(ref1125)forSYNCconditionofuse.
•SYNC,SYNCNpinshavetobedriven.
ForEV12DS130B:
•SYNC,SYNCNpinscanbeleftfloatingifunused.
•Nospecifictimingconstraints(otherthanT1andT2)arerequired.
5.10 GainAdjustGAFunction
ThisfunctionallowstoadjusttheinternalgainoftheDACtocanceltheinitialgaindeviation.
ThegainoftheDACcanbeadjustedby±11%bytuningthevoltageappliedonGAbyvaryingGA
potentialfrom0to VCCA3.
GAmaxisgivenforGA=0andGAminforGA=VCCA3
DSP,
DSPN
CLK,
CLKN
3 GHz
SYNC,
SYNCN 3 clock
cycles min Pipeline +
TDSP
DSP,
DSPN
CLK,
CLKN
1.5 GHz
SYNC,
SYNCN 3 clock
cycles min Pipeline +
TDSP
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5.11 DiodeFunction
AdiodeisavailabletomonitorthediejunctiontemperatureoftheDAC.
Forthemeasurementofdiejunctiontemperature,youmayuseatemperaturesensor.
Figure5‐18. TemperatureDIODEImplementation
Incharacterizationmeasurementacurrentof1mAisappliedontheDIODEpin.Thevoltageacrossthe
DIODEpinandtheDGNDpingivesthejunctiontemperatureusingtheintrinsicdiodecharacteristics
belowFigure5‐19.
Figure5‐19. DiodeCharacteristicsforDieJunctionMonitoring
Diode
DGND
DAC Temperature sensor
D+
D-
Junction Temperature Versus Diode voltage for I=1mA
y = -1.13x + 915
750
770
790
810
830
850
870
890
910
930
950
970
-35 -15 5 25 45 65 85 105 125
Junction temperature (°C)
Diode voltage (mV)
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6. PINDESCRIPTION
Figure6‐1. PinoutView(TopView)
12345678910111213141516
A VCCD B4 B5 B8 B10 B9 B11 C11 C9 C10 C8 C5 C4 VCCD DGND A
B DGND VCCD B4N B5N B8N B10N B9N B11N C11N C9N C10N C8N C5N C4N VCCD DGND B
CB3 B3N VCCD DGND B7N B7 B6 B6N C6N C6 C7 C7N DGND VCCD C3N C3 C
D B2 B2N DGND VCCD VCCD DGND DGND DGND DGND DGND DGND VCCD VCCD DGND C2N C2 D
E B1 B1N B0 DGND DGND DGND VCCD VCCD VCCD VCCD DGND DGND DGND C0 C1N C1 E
F A10 A10N B0N DGND VCCD DGND DGND VCCD VCCD DGND DGND VCCD DGND C0N D10N D10 F
GA11 A11N A9N DGND VCCD VCCD AGND AGND AGND AGND VCCD VCCD DGND D9N D11N D11 G
H A8 A8N A9 DGND DGND VCCD AGND AGND AGND AGND VCCD DGND DGND D9 D8N D8 H
J A6 A6N A1N DGND DGND VCCA3 AGND AGND AGND AGND VCCA3 DGND DGND D1N D6N D6 J
K A3 A3N A1 VCCA3 VCCA3 VCCA3 AGND AGND AGND AGND VCCA3 VCCA3 VCCA3 D1 D3N D3 K
L A7 A7N A2 DGND DGND DGND VCCA5 VCCA5 VCCA5 VCCA5 DGND DGND DGND D2 D7N D7 L
M A5 A5N A2N DGND DGND DIODE AGND VCCA5 AGND VCCA5 NC or
DGND IUCM DGND D2N D5N D5 M
N A0 A0N DSPN HTVF DGND STVF AGND VCCA5 AGND VCCA5 DGND DGND DGND OCDS
0D0N D0 N
P A4 A4N DSP GA DGND AGND AGND AGND AGND AGND AGND DGND DGND OCDS
1D4N D4 P
R DGND DGND DGND IDC_P SYNCN CLKN AGND AGND AGND AGND AGND MODE
1PSS1 PSS2 DGND DGND R
T DGND DGND DGND IDC_N SYNC CLK AGND AGND OUT OUTN AGND MODE
0PSS0 MUX DGND DGND T
12345678910111213141516
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Table6‐1. PinoutTable
SignalName Pinnumber Description Direction Equivalentsimplifiedschematics
Powersupplies
VCCA5 L7,L8,L9,L10,M8,M10,
N8,N10
5.0Vanalogpowersupplies
ReferencedtoAGND
VCCA3 J6,J11,K4,K5,K6,K11,
K12,K13
3.3Vanalogpowersupply
ReferencedtoAGND NA
VCCD
A2,A15,B2,B15,C3,C14,
D4,D5,D12,D13,E7,E8,
E9,E10,F5,F8,F9,F12,
G5,G6,G11,G12,H6,
H11
3.3Vdigitalpowersupply
ReferencedtoDGND NA
AGND
G7,G8,G9,G10,H7,H8,
H9,H10,J7,J8,J9,J10,
K7,K8,K9,K10,M7,M9,
N7,N9,P6,P7,P8,P9,
P10,P11,R7,R8,R9,R10,
R11,T7,T8,T11
AnalogGround NA
DGND
A16,B1,B16,C4,C13,D3,
D6,D7,D8,D9,D10,D11,
D14,E4,E5,E6,E11,E12,
E13,F4,F6,F7,F10,F11,
F13,G4,G13,H4,H5,
H12,H13,J4,J5,J12,J13,
L4,L5,L6,L11,L12,L13,
M4,M5,M13,N5,N11,
N12,N13,P5,P12,P13,
R1,R2,R3,R15,R16,T1,
T2,T3,T15,T16
DigitalGround NA
ClockSignals
CLK,CLKN T6,R6 Samplingclocksignalinput(In‐phaseand
invertedphase) I
50Ω
50Ω
AGND
3.75 pF
2.5 V
CLKN
CLK
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DSP,DSPN P3,N3 Outputclock(in‐phaseandinvertedphase) O
AnalogOutputSignal
OUT,OUTN T9,T10 Inphaseandinvertedphaseanalogoutput
signal(differentialterminationrequired) O
DigitalInputSignals
A0,A0N
A1,A1N
A2,A2N
A3,A3N
A4,A4N
A5,A5N
A6,A6N
A7,A7N
A8,A8N
A9,A9N
A10,A10N
A11,A11N
N1,N2
K3,J3
L3,M3
K1,K2
P1,P2
M1,M2
J1,J2
L1,L2
H1,H2
H3,G3
F1,F2
G1,G2
In‐phase,invertedphaseDigitalinput
PortA
DataA0,A0NistheLSB
DataA11,A11NistheMSB
I
Table6‐1. PinoutTable(Continued)
SignalName Pinnumber Description Direction Equivalentsimplifiedschematics
VCCD
DGND
145Ω
DSP,
DSPN
OUT
OUTN
VCCA5
Current
Switches and
sources
50Ω
AGND
In
InN
50Ω
50ΩDGND3.75 pF
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B0,B0N
B1,B1N
B2,B2N
B3,B3N
B4,B4N
B5,B5N
B6,B6N
B7,B7N
B8,B8N
B9,B9N
B10,B10N
B11,B11N
E3,F3
E1,E2
D1,D2
C1,C2
A3,B3
A4,B4
C7,C8
C6,C5
A5,B5
A7,B7
A6,B6
A8,B8
In‐phase,invertedphaseDigitalinput
PortB
DataB0,B0NistheLSB
DataB11,B11NistheMSB
I
C0,C0N
C1,C1N
C2,C2N
C3,C3N
C4,C4N
C5,C5N
C6,C6N
C7,C7N
C8,C8N
C9,C9N
C10,C10N
C11,C11N
E14,F14
E16,E15
D16,D15
C16,C15
A14,B14
A13,B13
C10,C9
C11,C12
A12,B12
A10,B10
A11,B11
A9,B9
In‐phase,invertedphaseDigitalinput
PortD
DataD0,D0NistheLSB
DataD11,D11NistheMSB
I
D0,D0N
D1,D1N
D2,D2N
D3,D3N
D4,D4N
D5,D5N
D6,D6N
D7,D7N
D8,D8N
D9,D9N
D10,D10N
D11,D11N
N16,N15
K14,J14
L14,M14
K16,K15
P16,P15
M16,M15
J16,J15
L16,L15
H16,H15
H14,G14
F16,F15
G16,G15
In‐phase,invertedphaseDigitalinput
PortD
DataD0,D0NistheLSB
DataD11,D11NistheMSB
I
IDC_P
IDC_N
R4
T4 Inputdatacheck I
SYNC,
SYNCN
T5
R5 InphaseandInvertedphaseresetsignal I
Table6‐1. PinoutTable(Continued)
SignalName Pinnumber Description Direction Equivalentsimplifiedschematics
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ControlSignals
HTVF N4 Holdtimeviolationflag O
STVF N6 Setuptimeviolationflag O
PSS0
PSS1
PSS2
T13
R13
R14
PhaseShiftSelect(PSS2istheMSB) I
MODE0
MODE1
T12
R12
DACModeselectionbits:
- RTZ
- NRZ
- NarrowRTZ
- RF
I
OCDS0
OCDS1
N14
P14
OutputClockDivisionSelect=thesebits
allowtoselecttheclockdivisionfactor
appliedontheDSP,DSPNsignal.
I
MUX T14 MUXselection: I
IUCM M12 Inputunderclockingmodeenable I
GA P4 Gainadjust I
Table6‐1. PinoutTable(Continued)
SignalName Pinnumber Description Direction Equivalentsimplifiedschematics
HTVF or STVF
100Ω
400Ω
20Ω
VCCD
DGND
13 kΩ
33 kΩ
200Ω
VCCD
20 kΩ
DGND
Input
2.5 kΩ
300Ω
2.5 kΩ
1 kΩ
26.6 pF
AGND
4 pF
GA
VCCA3
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7. CHARACTERIZATIONRESULTS
Unlessotherwisespecifiedresultsaregivenatroomtemperature(Tj~60°C),nominalpowersupply,in
4:1MUXmode,gainatnominalsetting.
7.1 StaticPerformances
7.1.1 DCGainCharacterization
Figure7‐1. DACDCGainvsGainAdjust(MeasuredinNRZMode)
Diode M6 Diodefordiejunctiontemperature
monitoringfunction I
NC M11 Reservedpin,NC,canbeconnectedto
DGND
Table6‐1. PinoutTable(Continued)
SignalName Pinnumber Description Direction Equivalentsimplifiedschematics
SUB
Diode
DGND_DIODE
DAC 12 bit 3 Gsps : Gain DC versus Gain Adjust
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-0.5 0 0.5 1 1 .5 2 2.5 3 3.5
Gain Adjust (V)
Gain (V)
part 2
part 4
part 5
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Figure 7-2. DACDCGainDriftfromUnityGainvsTemperature(MeasuredinNRZMode)
Figure 7-3. DCGainSensitivitytoPowerSupply(MeasuredinNRZOutputMode)
DAC 12 bit 3 Gsps : DC gain sensitivity to temperature
0.95
0.96
0.97
0.98
0.99
1.00
1.01
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140
Temperature junction(°C)
Gain (%)
part 2
part 4
part 5
Ga : 1.64V
Tamb = 66.5°C
Conditions: room temperature, supply levels:
- Min: VCCA: 4.75V // VCCA3 = VCCD = 3.15V
- Typ: VCCA: 5V // VCCA3 = VCCD = 3.3V
- Max: VCCA: 5.25V // VCCA3 = VCCD = 3.45V
DAC 12 bit 3 Gsps : DC gain sensitivity to power supplies
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
Min Typ Max
Power supplies
Gain (V)
part 2
part 4
part 5
Ga : 1.64V
Ga : 0V
Ga : 3.3V
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7.1.2 Static Linearity
Figure 7-4. INL/DNL Measurement at Fout = 100 kHz and 3 Gsps
INL reflects a true 12 bit DAC.
Low DNL values reflect a strictly monotonous 12 bit DAC.
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7.2 AC Performances
7.2.1 Available Output Power vs Fout.
The following plots summarize characterization results, for a Fout sweep from 98 MHz to 4498 MHz
(step 100 MHz).
Figure 7-5. Available Pout vs Fout from 98 MHz to 4498 MHz in the 4 Output Modes at 3 Gsps
Figure 7-6. Available Pout vs Fout from 98 MHz to 4498 MHz and from 2 Gsps to 3.2 Gsps in NRZ Mode
-70
-60
-50
-40
-30
-20
-10
0
10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
Mux4:1_Mode_NRZ
Mux4:1_Mode_NRTZ
Mux4:1_Mode_RTZ
Mux4:1_Mode_RF
Pout_dBm
Output frequency (MHz)
NRZ mode offers max power for 1st Nyquist operation.
RTZ mode offer slow roll off for 2nd Nyquist operation.
RF mode offers maximum power over 2nd
and 3rd Nyquits operation.
NRTZ mode offers optimum power over full 1st and first half
of 2nd Nyquist zones.
This is the most relevant in term of performance for operation
over 1st and beginning of 2nd Nyquist zone.
1st Nyquist 2nd Nyquist 3rd Nyquist
First notch at F= Fclock,
second notch at 2xFclock
Pout_dBm
Output frequency (MHz)
-80
-70
-60
-50
-40
-30
-20
-10
0
10
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
0 - 2000 - Mux4:1_Mode_NRZ
0 - 2199 - Mux4:1_Mode_NRZ
0 - 2399 - Mux4:1_Mode_NRZ
0 - 2599 - Mux4:1_Mode_NRZ
0 - 2799 - Mux4:1_Mode_NRZ
0 - 2999 - Mux4:1_Mode_NRZ
0 - 3200 - Mux4:1_Mode_NRZ
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Figure 7-7. Available Pout vs Fout from 98 MHz to 4498 MHz and from 2 Gsps to 3.2 Gsps in NRTZ Mode
Figure 7-8. Available Pout vs Fout from 98 MHz to 4498 MHz and from 2 Gsps to 3.2 Gsps in RTZ Mode
Figure 7-9. Available Pout vs Fout from 98 MHz to 4498 MHz and from 2 Gsps to 3.2 Gsps in RF Mode
-60
-50
-40
-30
-20
-10
0
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
2000 - Mux4:1_Mode_NRTZ
2199 - Mux4:1_Mode_NRTZ
2399 - Mux4:1_Mode_NRTZ
2599 - Mux4:1_Mode_NRTZ
2799 - Mux4:1_Mode_NRTZ
2999 - Mux4:1_Mode_NRTZ
3200 - Mux4:1_Mode_NRTZ
First notch at F=1/((1/Fclock) - 75ps),
second notch at 2xF
Pout_dBm
Output frequency (MHz)
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
2000 - Mux4:1_Mode_RTZ
2199 - Mux4:1_Mode_RTZ
2399 - Mux4:1_Mode_RTZ
2599 - Mux4:1_Mode_RTZ
2799 - Mux4:1_Mode_RTZ
2999 - Mux4:1_Mode_RTZ
3200 - Mux4:1_Mode_RTZ
First notch at F = 2 x Fclock
Pout_dBm
Output frequency (MHz)
-35
-30
-25
-20
-15
-10
-5
0
98
198
298
398
498
598
698
798
898
998
1098
1198
1298
1398
1498
1598
1698
1798
1898
1998
2098
2198
2298
2398
2498
2598
2698
2798
2898
2998
3098
3198
3298
3398
3498
3598
3698
3798
3898
3998
4098
4198
4298
4398
4498
2000 - Mux4:1_Mode_RF
2199 - Mux4:1_Mode_RF
2399 - Mux4:1_Mode_RF
2599 - Mux4:1_Mode_RF
2799 - Mux4:1_Mode_RF
2999 - Mux4:1_Mode_RF
3200 - Mux4:1_Mode_RF
First notch at DC
Pout_dBm
Output frequency (MHz)
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7.2.2 Single Tone Measurements
The following plots summarize characterization results in MUX4:1 mode, for an Fout sweep from 98
MHz to 4498 MHz (step 100 MHz).
The left side of the plot gives SFDR expressed in dBc and the right side gives HSL (Highest Spur Level
excluding Fclock spur) expressed in dBm.
Figure 7-10. SFDR and HSL in NRZ mode at –3 dBFS for Sampling Rate from 2000 MSps to 3200 MSps
NRZ mode is only relevant for Fout below 400 MHz.
The spikes in the SFDR are caused by normalization artefacts due to the Sinc(x) null.
Figure 7-11. SFDR and HSL in NRTZ mode at –3 dBFS for Sampling Rate from 2000 MSps to 3200 MSps
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
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-3 - 2199 - Mux4:1_NRZ
-3 - 2399 - Mux4:1_NRZ
-3 - 2599 - Mux4:1_NRZ
-3 - 2799 - Mux4:1_NRZ
-3 - 2999 - Mux4:1_NRZ
-3 - 3200 - Mux4:1_NRZ
Highest Spur Level (excl. Fclock)[dBm]Spurious Free Dynamic Range (excl. Fclock) [dBc]
Output frequency (MHz)
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-3 - 2000 - Mux4:1_NRTZ
-3 - 2199 - Mux4:1_NRTZ
-3 - 2399 - Mux4:1_NRTZ
-3 - 2599 - Mux4:1_NRTZ
-3 - 2799 - Mux4:1_NRTZ
-3 - 2999 - Mux4:1_NRTZ
-3 - 3200 - Mux4:1_NRTZ
Highest Spur Level (excl. Fclock)[dBm]
Spurious Free Dynamic Range (excl. Fclock) [dBc]
Output frequency (MHz)
45
1080K–BDC–01/18
Teledyne e2v Semiconductors SAS 2018
NRTZ mode brings significant improvement regarding NRZ mode. This mode concentrates the benefits
of both NRZ mode (high power available) and RTZ mode (extended available dynamic range).
The spikes in the SFDR are caused by normalization artefacts due to the Sinc(x) null.
Figure 7-12. SFDR and HSL in RTZ Mode at –3 dBFS for Sampling Rate from 2000 MSps to 3200 MSps
RTZ mode allows for operation over the 3 first Nyquist zones.
In first and beginning of second Nyquist zone NRTZ mode is mode relevant. The spikes in the SFDR are
caused by normalization artefacts due to the Sinc(x) null.
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Somme de SFDR_dBc Somme de SFDR_dBm
-3 - 2000 - Mux4:1_RTZ
-3 - 2199 - Mux4:1_RTZ
-3 - 2399 - Mux4:1_RTZ
-3 - 2599 - Mux4:1_RTZ
-3 - 2799 - Mux4:1_RTZ
-3 - 2999 - Mux4:1_RTZ
-3 - 3200 - Mux4:1_RTZ
Spurious Free Dynamic Range (excl. Fclock) [dBc] Highest Spur Level (excl. Fclock) [dBm]
Output frequency (MHz)
46
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Teledyne e2v Semiconductors SAS 2018
Figure 7-13. SFDR and HSL in RF Mode at –3 dBFS for Sampling Rate from 2000 MSps to 3200 MSps
RF mode allows for operation over 3rd Nyquist zones. Performances are not sensitive to output level.
Performance roll off occurs beyond 3000 MSps.
Figure 7-14. Comparison of the 4 Output Modes at 2999 MSps and at –3 dBFS: SFDR and HSL
NRZ is interesting only at the very beginning of the first Nyquist zone.
NRTZ is relevant over 1st 2nd and 4th Nyquist zones.
RTZ is relevant over 2nd and 3rd Nyquist zones.
RF mode displays a good behavior over 2nd and 3rd Nyquist Zones.
The spikes in the SFDR are caused by normalization artefacts due to the Sinc(x) null
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-3 - 2000 - Mux4:1_RF
-3 - 2199 - Mux4:1_RF
-3 - 2399 - Mux4:1_RF
-3 - 2599 - Mux4:1_RF
-3 - 2799 - Mux4:1_RF
-3 - 2999 - Mux4:1_RF
-3 - 3200 - Mux4:1_RF
Output Frequency (MHz)
Spurious Free Dynamic Range (excl. Fclock) [dBc] Highest spur level (excl. Fclock) [dBm]
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Somme de SFDR_dBc Somme de SFDR_dBm
-3 - 2999 - Mux4:1_NRZ
-3 - 2999 - Mux4:1_RTZ
-3 - 2999 - Mux4:1_RF
-3 - 2999 - Mux4:1_NRTZ
Spurious Free Dynamic Range (excl. Fclock) [dBc] Highest Spur Level (excl. Fclock) [dBm]
1st Nyquist 2nd Nyquist 3rd Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist
Output frequency (MHz)
47
1080K–BDC–01/18
Teledyne e2v Semiconductors SAS 2018
Figure 7-15. Comparison of the 4 Output Modes at 2000 MSps and –3 dBFS: SFDR and HSL
NRTZ is the most relevant over 1st Nyquist zone, 1st half of 2nd Nyquits zone and 4th Nyquist zone.
RF mode is the best choice for 2nd half of 2nd Nyquist Zone and 3rd Nyquist zone.
RTZ gives relevant performances over the three first Nyquist zones.
The spikes in the SFDR are caused by normalization artefacts due to the Sinc(x) null
Figure 7-16. Comparison of NRZ and NRTZ Modes at Full Scale and –3 dBFS at 2999 MSps: SFDR and HSL (Excluding
Fclock)
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Somme de SFDR_dBc Somme de SFDR_dBm
-3 - 2000 - Mux4:1_NRZ
-3 - 2000 - Mux4:1_RTZ
-3 - 2000 - Mux4:1_RF
-3 - 2000 - Mux4:1_NRTZ
Spurious Free Dynamic Range (excl. Fclock) [dBc] Highest Spur Level (excl. Fclock) [dBm]
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
Output frequency (MHz)
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-3 - 2999 - Mux4:1_NRZ
-3 - 2999 - Mux4:1_NRTZ
0 - 2999 - Mux4:1_NRZ
0 - 2999 - Mux4:1_NRTZ
1st Nyquist 2nd Nyquist 3rd Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist
Output frequency (MHz)
Highest Spur Level (excl. Fclock)[dBm]Spurious Free Dynamic Range (excl. Fclock) [dBc]
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NRTZ gives better performances over 1st and 2nd Nyquist zone, and is much less sensitive to output
level.
Figure 7-17. Comparison of NRTZ and RTZ Modes at Full Scale and –3 dBFS at 2999 MSps: SFDR and HSL
NRTZ is more relevant for 1st Nyquist zone and 1st half of 2nd Nyquist zone. Beyond middle of second
Nyquist zone RTZ mode is more relevant.
Figure 7-18. Comparison of RTZ and RF Modes at Full Scale and –3 dBFS at 2999 MSps: SFDR and HSL
RF mode gives better performance over 3rd Nyquist zone.
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-3 - 2999 - Mux4:1_RTZ
-3 - 2999 - Mux4:1_NRTZ
0 - 2999 - Mux4:1_RTZ
0 - 2999 - Mux4:1_NRTZ
1st Nyquist 2nd Nyquist 3rd Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist
Output frequency (MHz)
Highest Spur Level (excl. Fclock)[dBm]Spurious Free Dynamic Range (excl. Fclock) [dBc]
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-3 - 2999 - Mux4:1_RF
0 - 2999 - Mux4:1_RTZ
0 - 2999 - Mux4:1_RF
1st Nyquist 2nd Nyquist 3rd Nyquist
1st Nyquist 2nd Nyquist 3rd Nyquist
Output frequency (MHz)
Highest Spur Level (excl. Fclock)[dBm]Spurious Free Dynamic Range (excl. Fclock) [dBc]
49
1080K–BDC–01/18
Teledyne e2v Semiconductors SAS 2018
Figure 7-19. Comparison of NRZ and NRTZ Modes at Full Scale and –3 dBFS at 2000 MSps: SFDR and HSL (Excluding
Fclock)
NRTZ linearity is slightly improved reducing the sampling rate to 2000 MSps, possibility of operation
over the 4th Nyquist zone is demonstrated.
Figure 7-20. Comparison of NTRZ and RTZ Modes at Full Scale and –3 dBFS at 2000 MSps: SFDR and HSL
(Excluding Fclock)
NRTZ mode is relevant in 1st, 2nd Nyquist zones and is still usable over 4th Nyquist zone with SFDR in
excess of 50 dBc.
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Somme de SFDR_dBc Somme de SFDR_dBm
-3 - 2000 - Mux4:1_NRZ
-3 - 2000 - Mux4:1_NRTZ
0 - 2000 - Mux4:1_NRZ
0 - 2000 - Mux4:1_NRTZ
Spurious Free Dynamic Range (excl. Fclock) [dBc] Highest Spur Level (excl. Fclock) [dBm]
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist 1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
Output frequency (MHz)
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Somme de SFDR_dBc Somme de SFDR_dBm
-3 - 2000 - Mux4:1_RTZ
-3 - 2000 - Mux4:1_NRTZ
0 - 2000 - Mux4:1_RTZ
0 - 2000 - Mux4:1_NRTZ
Spurious Free Dynamic Range (excl. Fclock) [dBc] Highest Spur Level (excl. Fclock) [dBm]
1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist 1st Nyquist 2nd Nyquist 3rd Nyquist 4th Nyquist
Output frequency (MHz)
50
1080K–BDC–01/18
Teledyne e2v Semiconductors SAS 2018
7.2.3 Single tone measurements: typical spectra at 3Gsps
The following figures show typical SFDR spectra obtained for the four DAC modes on an EV12DS130A/B
device.
Conditions: typical power supplies, ambient temperature, MUX4:1, Fs = 3 Gsps.
Figure 7-21. Typical SFDR spectrum in NRZ mode. Fout = 100MHz (1st Nyquist), MUX4:1, Fs = 3Gsps. SFDR = 67dBc
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Figure 7-22. Typical SFDR spectrum in NRTZ mode. Fout = 1800MHz (2nd Nyquist), MUX4:1, Fs = 3Gsps.
SFDR = 61dBc
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Teledyne e2v Semiconductors SAS 2018
Figure 7-23. Typical SFDR spectrum in RTZ mode. Fout = 2900MHz (2nd Nyquist), MUX4:1, Fs = 3Gsps.
SFDR = 59dBc.
Figure 7-24. Typical SFDR spectrum in RF mode. Fout = 4400MHz (3rd Nyquist), MUX4:1, Fs = 3Gsps. SFDR = 56 dBc
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7.2.4 Multi Tone Measurements
A five tones pattern (400 MHz, 500 MHz, 600 MHz, 700 MHz and 800 MHz) is applied to the DAC
operating at 3 Gsps and results are observed in the 2nd, 3rd, 4th and 5th Nyquist zones.
Results are given in the most relevant mode considering the Nyquist zone observed.
Figure 7-25. Observation of the 2nd Nyquist Zone (Tones are pushed from 2.2 GHz to 2.6 GHz): NRTZ, RF and RTZ Modes
NRTZ mode: RF mode:
RTZ mode:
Fout (MH z) Pout (dBm) SFDR (freq) SFDR (dBc)
N R TZ 2200 -23,99 1800 -51,28
RTZ 2200 -24,53 1800 -55,97
RF 2200 -21,76 2700 -57,25
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1080K–BDC–01/18
Teledyne e2v Semiconductors SAS 2018
Figure 7-26. Observation of the 3rd Nyquist Zone (Tones are pushed from 3.4GHz to 3.8GHz): RF and RTZ Modes
NRTZ performances are degraded because of the sinc attenuation (first notch in the first half of the 3rd
Nyquist zone).
Figure 7-27. Observation of the 4th Nyquist Zone (Tones are pushed from 5.2 GHz to 5.6 GHz): NRTZ and RF Modes
RF mode: RTZ mode:
Fout (MHz) Pout (dBm) SFDR (freq) SFDR (dBc)
NRTZ 3400 –39.43 4000 –44.48
RTZ 3400 –28.77 3100 –55.14
RF 3400 –23.03 3100 –58.33
NRTZ mode RF mode
55
1080K–BDC–01/18
Teledyne e2v Semiconductors SAS 2018
RTZ mode is degraded because of the sinc attenuation (first notch at the end of the 4th Nyquist zone).
RF mode offers significantly more power than RTZ mode, this is why we still have acceptable
performances.
NRTZ operation is possible because the 4th Nyquist zone is fully included in the secondary spectral lobe.
Figure 7-28. Observation of the 5th Nyquist Zone (Tones are pushed from 6.4 GHz to 6.8 GHz): NRTZ Mode
NRTZ mode is still usable in the 5th Nyquist zone (SFDR in excess of 46 dB).
Fout (MHz) Pout (dBm) SFDR (freq) SFDR (dBc)
NRTZ 5200 –34.72 5000 –50.34
RTZ 5200 –40.37 4700 –45
RF 5200 –31.87 4700 –49.49
Fout (MHz) Pout (dBm) SFDR (freq) SFDR (dBc)
N RTZ 6400 -38,64 7000 -46,92
RTZ 6800 -46,69 7000 -39,25
RF 6400 -46,89 7000 -38,01
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7.2.5 Direct Microwave Synthesis Capability Measurements: ACPR
Measurements given hereafter are performed on the DAC at 3 Gsps with a 10 MHz wide QPSK pattern
centered on 800 MHz.
Results are observed in 2nd, 3rd, 4th and 5th Nyquist zones and are given only for the most relevant
modes (that is RF and/or NRTZ modes).
Figure 7-29. NRTZ Mode, 2nd Nyquist: Center Frequency is pushed to 3 GHz – 800 MHz = 2.2 GHz
ACPR is in excess of 62 dB. DMWS capability is proven for second Nyquist in NRTZ mode.
Figure 7-30. RF Mode, 2nd Nyquist: Center Frequency is pushed to 3 GHz – 800 MHz = 2.2 GHz
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ACPR is in excess of 60 dB. DMWS capability is proven for the second Nyquist zone in RF mode with
slightly reduced dynamic range regarding NRTZ mode but with increased output power.
Figure 7-31. RF Mode, 3rd Nyquist Zone: Center Frequency is pushed to 3 GHz+ 800 MHz = 3.8 GHz
ACPR is in excess of 59 dB. DMWS capability is proven for the third Nyquist zone in RF mode.
Note: due to the notch of available Pout near the middle of the third Nyquist zone, the NRTZ mode is not rele-
vant for DMWS in the third Nyquist zone.
Figure 7-32. NRTZ Mode, 4th Nyquist Zone: Center Frequency is pushed to 6 GHz – 800 MHz = 5.2 GHz
ACPR is in excess of 54 dB. DMWS capability is proven for the fourth Nyquist zone in NRTZ mode.
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Figure 7-33. RF Mode, 4th Nyquist Zone: Center Frequency is pushed to 6 GHz – 800 MHz = 5.2 GHz
ACPR is in excess of 53 dB. DMWS capability is proven for the fourth Nyquist zone in RF mode.
Note due to a notch of available Pout near the end of the 4th Nyquist zone in RF output mode, for
DMWS beyond middle of 4th Nyquist zone it is recommended to use the NRTZ output mode instead of
the RF output mode.
Figure 7-34. NRTZ Mode, 5th Nyquist Zone: Center Frequency is pushed to 6 GHz + 800 MHz = 6.8 GHz
ACPR is still in excess of 47 dB. DMWS capability if proven for the fifth Nyquist zone in NRTZ mode with
reduced available dynamic range.
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7.2.6 DOCSIS v3.0 Capability Measurements
Measurements hereafter have been carried out on a soldered device EV12DS130A/B, in NRTZ mode at
3 GSps.
Note: Results illustrated hereafter (spectrum and zoom on notch) come from measurement on a
EV12DS130A/B device (CI-CGA255 package). Measurements have been carried out using the ACP
treatment of the spectrum analyzer Rhode & Schwarz FSU8, in RMS detection mode.
Figure 7-35. ACPR 1 Channel Centered on 300 MHz, Output Mode NRTZ
Figure 7-36. ACPR 1 Channel Centered on 900 MHz, Output Mode NRTZ
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Figure 7-37. ACPR 1 channel centered on 300 MHz, Output Mode NRTZ
Figure 7-38. ACPR 4 Channels Centered on 300 MHz, Output Mode NRTZ
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Figure 7-39. ACPR 1 Channel Centered on 900 MHz, Output Mode NRTZ
Figure 7-40. ACPR 4 Channels Centered on 900 MHz, Output Mode NRTZ
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7.2.7 NPR Performance
NPR measurements have been carried out at optimum loading factor (LF) for a 12 bit DAC, that is –
14 dBFS, with the DAC operating at 3 Gsps.
SNR can be computed from SNR measurement with the formula: SNR[dB] = NPR[dB] + ILF[dB]I – 3.
ENOB can be computed with the formula: ENOB = (SNR[dB] – 1.76) / 6.02.
Note: Results illustrated hereafter (spectrum and zoom on notch) come from measurement on a
EV12DS130A/B device (CI-CGA255 package). Measurements have been carried out using the ACP
treatment of the spectrum analyzer Rhode & Schwarz FSU8, in RMS detection mode.
Figure 7-41. NPR in First Nyquist Zone, 20 MHz to 900 MHz Noise Pattern with a 25 MHz Notch Centered on 450 MHz,
NRZ mode
Measured average NPR: 50.02 dB, therefore SNR = 61.02 dB and ENOB = 9.84 bit
Effects at low frequency are due to balun and pattern.
Figure 7-42. NPR in First Nyquist Zone, 20 MHz to 900 MHz Noise Pattern with a 25 MHz Notch Centered on 450 MHz,
NRTZ Mode
Measured average NPR: 51.36 dB, therefore SNR = 62.36 dB and ENOB = 10.07 bit.
Effects at low frequency are due to balun and pattern.
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Figure 7-43. NPR in First Nyquist Zone, 10 MHz to 450 MHz Noise Pattern with a 12.5 MHz Notch centered on 225 MHz,
NRTZ Mode at Fs = 1.5 Gsps
Measured average NPR: 55.7 dB, therefore SNR = 66.7 dB and ENOB = 10.8 bit.
Effects at low frequency are due to balun and pattern.
Figure 7-44. NPR in second Nyquist Zone, 1520 MHz to 2200 MHz Noise Pattern with a 25 MHz Notch centered on
1850 MHz, RTZ mode
Measured average NPR: 44.6 dB, therefore SNR = 55.6 dB and ENOB = 8.94 bit
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Figure 7-45. NPR in second Nyquist Zone, 1520 MHz to 2200 MHz noise pattern with a 25 MHz notch centered on
1850 MHz, RF Mode
Measured average NPR: 42.78 dB, therefore SNR = 53.78 dB and ENOB = 8.64 bit
Figure 7-46. NPR in second Nyquist Zone, 2200 MHz to 2880 MHz Noise Pattern with a 25 MHz Notch centered on
2550 MHz, RF Mode
Measured average NPR: 42.56 dB, therefore SNR = 53.56 dB and ENOB = 8.6 bit.
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Figure 7-47. NPR in Third Nyquist Zone, 3050 MHz to 3700 MHz Noise Pattern with a 25 MHz Notch Centered on
3375 MHz, RF Mode
Measured average NPR: 40.08 dB, therefore SNR = 51.08 dB and ENOB = 8.19 bit
The following figures reflect the stability of NPR in first Nyquist in NRTZ mode (and therefore SNR and
ENOB) versus temperature.
Measurements have been carried out at nominal power supply on an EV12DS130A/B, at 3 Gsps, with
the FSU8 spectrum analyzer in RMS detection mode.
Figure 7-48. Drift of NPR and Associated SNR and ENOB in First Nyquist in NRTZ Mode from Tj = –30°C to Tj = 125°C
NPR DAC (VN15A) / / P ack ag e : Fp BG A
N RTZ @-14dB (20MHz to 900MHz) span:25MHz notch centered : 450MHz
1st Nyquist
47.80
48.00
48.22
48.57
48.85
48.78
48.35
48.57
47.6
47.8
48.0
48.2
48.4
48.6
48.8
49.0
-40-200 20406080100120140
Tj (°C)
NPR (dB)
SNR DAC (VN15A) / / Pa ck ag e : Fp BG A
N RTZ @-14dB (20MHz to 900MHz) span:25MHz notch centered : 450MHz
1st Nyquist
59.57
59.35
59.78 59.85
59.57
59.22
59.00
58.80
58.6
58.8
59.0
59.2
59.4
59.6
59.8
60.0
-40 -20 0 20 40 60 80 100 120 140
Tj (°C)
SNR (dB)
ENO B DAC (V N1 5A) // P a ck ag e : Fp BG A
N RTZ @-14dB (20MHz to 900MHz) span:25MHz notch centered : 450MHz
1st Nyquist
9.60
9.57
9.64 9.65
9.60
9.54
9.51
9.48
9.45
9.50
9.55
9.60
9.65
9.70
-40 -20 0 20 40 60 80 100 120 140
Tj (°C)
ENOB (Bi t)
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Optimum is at Tj = 40°C, degradation over temp is within 1 dB (or 0.15 effective bit).
Measurements hereafter have been carried out on an EV12AS130AGS device at 3 Gsps, with the FSU8
spectrum analyzer in RMS detection mode.
Figure 7-49. Drift of NPR vs temperature in the 4 Output Modes at Nominal Supply
Conclusion: performances are stable in the four output modes against temperature.
Figure 7-50. NPR vs Power Supply Level in the 4 Output Modes at Room Temperature
Conditions: Typical, excepted: power supplies
Min: VCCA: 4.75V // VCCA3 = VCCD = 3.15V
Typ: VCCA: 5.0V // VCCA3 = VCCD = 3.3V
Max: VCCA: 5.25V // VCCA3 = VCCD = 3.45V.
Conclusion: performances are fairly stable against power supply.
Note: NPR performance at lower clock frequencies is affected by power up sequence. See application
note 1087 for further details.
NPR vs. temperature
38
40
42
44
46
48
50
52
54
Tj = -30˚C Tj = +44.5˚C Tj = +125˚C
Temperature (˚C)
NPR (dB)
NRZ @-14dB (20MHz to 900MHz)
span:25MHz notch centered :
450MHz
NRTZ @-14dB (20MHz to 900MHz)
span:25MHz notch centered :
450MHz
RTZ @-14dB (1520MHz to 2200MHz)
span:25MHz notch centered :
1850MHz
RF @-14dB (1520MHz to 2200MHz)
span:25MHz notch centered :
1850MHz
RF @-14dB (2200MHz to 2880MHz)
span:25MHz notch centered :
2550MHz
RF @-14dB (3050MHz to 3700MHz)
span:25MHz notch centered :
3375MHz
NPR vs. power supplies
38
40
42
44
46
48
50
52
54
Min Typ Max
Power supplies
NPR (dB)
NRZ @-14dB (20MHz to 900MHz)
span:25MHz notch centered :
450MHz
NRTZ @-14dB (20MHz to 900MHz)
span:25MHz notch centered :
450MHz
RTZ @-14dB (1520MHz to 2200MHz)
span:25MHz notch centered :
1850MHz
RF @-14dB (1520MHz to 2200MHz)
span:25MHz notch centered :
1850MHz
RF @-14dB (2200MHz to 2880MHz)
span:25MHz notch centered :
2550MHz
RF @-14dB (3050MHz to 3700MHz)
span:25MHz notch centered :
3375MHz
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7.2.8 Spectrum over 4 Nyquist Zones in the Four Output Modes
Observation of a 1GHz broadband pattern with a 25 MHz notch centered on 500 MHz spectrum over
4 Nyquist zones at 3 Gsps (that is from DC to 6 GHz), measurements performed on an EV12DS130A/B
device (CI-CGA 255 package, with an overall 6 GHz bandwidth limitation).
By periodisation of a sampled system each tone Fi of the pattern in the 1st Nyquist zone is duplicated as
follows:
•2
nd Nyquist Zone: tone at Fclock - Fi
•3
rd Nyquist Zone: tone at Fclock + Fi
•4
th Nyquist Zone: tone at 2*Fclock - Fi
Figure 7-51. Spectrum over 4 Nyquist Zones at 3 Gsps in NRZ Output Mode
First Zero of the sinc() function is at Fclock.
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Figure 7-52. Spectrum over 4 Nyquist Zones at 3 Gsps in NRTZ Output Mode
Figure 7-53. Spectrum over 4 Nyquist Zones at 3 Gsps in RTZ Output Mode
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First Zero of the sinc() function is slightly before 2*Fclock which indicates that the duty cycle of RTZ
function is a little bit more than 50%, this is due to the balun which introduced some phase error
beyond the 180 degrees between CLK and CLKN thus creating a duty cycle on the clock actually seen by
the DAC.
Figure 7-54. Spectrum over 4 Nyquist Zones at 3 Gsps in RF Output Mode
Measurements are showing a pretty good fit with theory, see Section 5.3 on page 18.
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8. APPLICATION INFORMATION
For further details, please refer to application note 1087.
8.1 Analog Output (OUT/OUTN)
The analog output should be used in differential way as described in the figures below.
If the application requires a single-ended analog output, then a balun is necessary to generate a single-
ended signal from the differential output of the DAC.
Figure 8-1. Analog Output Differential Termination
Figure 8-2. Analog Output Using a 1/ 2 Balun
Note: The AC coupling capacitors should be chosen as broadband capacitors with a value depending on the
application.
MUXDAC
VCCA5
100nF
100nF
OUT
OUTN
Current
Switches and
sources
AGND
50Ω
50Ω
50Ω lines
OUT
OUTN
AGND
MUXDAC
AGND
50Ω termination
50Ω line OUT
50Ω line
1/sqrt2
50Ω line
100nF
100nF
OUT
OUTN
VCCA5
Current
Switches and
sources
50Ω
AGND
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8.2 Clock Input (CLK/CLKN)
The DAC input clock (sampling clock) should be entered in differential mode as described in Figure 5-
11.
Figure 8-3. Clock Input Differential Termination
Note: The buffer is internally pre-polarized to 2.5V (buffer between VCC5 and AGND).
Figure 8-4. Clock Input Differential with Balun
Note: The AC coupling capacitors should be chosen as broadband capacitors with a value depending on the
application.
Differential
sinewave 50Ω
Source
CLK
CLKN
DAC Clock Input Buffer
50Ω
50Ω
AGND
3.75 pF
C = 100pF
C = 100pF
2.5 V
50Ω line
50Ω line
50Ω line
50Ω line
Single
sinewave 50Ω
Source
CLK
CLKN
DAC Clock Input Buffer
50Ω
50Ω
AGND
C = 100pF
C = 100pF
2.5 V
50Ω line
50Ω line
50Ω line
1/sqrt2
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8.3 Digital Data, SYNC and IDC Inputs
LVDS buffers are used for the digital input data, the reset signal (active high) and IDC signal.
They are all internally terminated by 2 × 50 to ground via a 3.75 pF capacitor.
Figure 8-5. Digital Data, Reset and IDC Input Differential Termination
Notes: 1. In the case when only two ports are used (2:1 MUX ratio), then the unused data should be left open
(no connect).
2. Data and IDC signals should be routed on board with the same layout rules and the same length than
the data.
3. In case SYNC is not used, it is necessary to bias the SYNC to 1.1V and SYNCN to 1.4V on EV12DS130A.
8.4 DSP Clock
The DSP, DSPN output clock signals are LVDS compatible.
They have to be terminated via a differential 100 termination as described in Figure 5-13.
Figure 8-6. DSP Output Differential Termination
LVDS Output
Buffer
In
InN
DAC Data and Sync Input Buffer
50Ω
50Ω
DGND
3.75 pF
50Ω line
50Ω line
DAC Output DSP
Differential Output
buffers
Z0 = 50Ω
Z0 = 50Ω
100ΩTermination
DSP
DSPN
To Load
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8.5 Control Signal Settings
The MUX, MODE, PSS and OCDS control signals use the same static input buffer.
Logic “1” = 200 K to Ground, or tied to VCCD = 3.3V or left open
Logic “0” = 10 to Ground or Grounded
Figure 8-7. Control Signal Settings
The control signal can be driven by FPGA.
Figure 8-8. Control Signal Settings with FPGA
Logic “1” > VIH or VCCD = 3.3V
Logic “0” < VIL or 0V
8.6 HTVF and STVF Control Signal
The HTVF and STVF control signals is a 3.3V CMOS output buffer.
These signals could be acquired by FPGA.
Figure 8-9. Control Signal Settings with FPGA
In order to modify the VOL/VOH value, pull up and pull down resistances could be used, or a potential
divider.
8.7 GA Function Signal
This function allows adjustment of the internal gain of the DAC.
The gain of the DAC can be tuned with applied analog voltage from 0 to VCCA3
This analog input signal could be generated by a DAC controlled by FPGA or microcontroller.
Figure 8-10. Control Signal Settings with GA
10Ω
200 KΩ
GND GND
Control
Signal Pin
Control
Signal Pin
Control
Signal Pin
Not
Connected
Active Low Level (‘0’)
Inactive High Level (‘1’)
Control
Signal Pin
FPGA
HTVF STVF Control
Signal
FPGA
GA
DAC16b
FPGA n
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8.8 Power Supplies Decoupling and Bypassing
The DAC requires 3 distinct power supplies:
VCCA5 = 5.0V (for the analog core)
VCCA3 = 3.3V (for the analog part)
VCCD = 3.3V (for the digital part)
It is recommended to decouple all power supplies to ground as close as possible to the device balls with
100 pF in parallel to 10nF capacitors. The minimum number of decoupling pairs of capacitors can be
calculated as the minimum number of groups of neighboring pins.
4 pairs of 100pF in parallel to 10 nF capacitors are required for the decoupling of VCCA5. 4 pairs for the
VCCA3 is the minimum required and finally, 10 pairs are necessary for VCCD.
Figure 8-11. Power Supplies Decoupling Scheme
Each power supply has to be bypassed as close as possible to its source or access by 100 nF in parallel to
22 µF capacitors (value depending of DC/DC regulators).
Analog and digital ground plane should be merged.
DAC 10-bit
AGND
AGND
DGND
100 pF
10 nF
100 pF
10 nF
100 pF
10 nF
X 4 (min)
X 4 (min)
X 10 (min)
VCCA5
VCCA3
VCCD
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8.9 Power Up Sequencing
For EV12DS130B there is no forbidden power-up sequence, nor power supplies dependency
requirement.
For EV12DS130A the following instructions must be implemented:
Power-up sequence:
It is necessary to raise VCCA5 power supply within the range 5.20V up to a recommended maximum of
5.60V during at least 1ms at power up. Then the supply voltage has to settle within 500 ms to a steady
nominal supply voltage within a range of 4.75V up to 5.25V.
A power-up sequence on VCCA5 that does not comply with the above recommendation will not
compromise the functional operation of the device. Only the noise floor will be affected.
Figure 8-12. Power-up Sequence
The rise time for any of the power supplies (VCCA5, VCCA3 and VCCD) shall be 10 ms.
At power-up a SYNC pulse is internally and automatically generated when the following sequence is
satisfied: VCCD, VCCA3 and VCCA5. To cancel the SYNC pulse at power-up, it is necessary to apply the
sequence: VCCA5, VCCA3, VCCD. (It is mandatory that VCCD is the last supply to rise and always remains
behind VCCA5 and VCCA3). Any other sequence may not have a deterministic SYNC behaviour. See
erratasheet (ref 1125) for specific condition of use relative to the SYNC operation.
Relationship between power supplies:
Within the applicable power supplies range, the following relationship shall always be satisfied
VCCA3 VCCD, taking into account AGND and DGND planes are merged and power supplies accuracy.
1 ms min
10 ms max
5.6V max 5.2V min
5.25V max 4.75V min
500 ms max
Time
VCCA5
3.45V max 3.15V min
VCCA3 > VCCD
VCCA3
VCCD
3V
4.5V
0.5V
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8.10 Balun Influence
It is important to know that balun characteristic may influence significantly DAC output spectral
response. Especially harmonic distortion can dramatically be degraded when part of the band of
interest lies out of the specified domain of the balun.
As depicted in the following figure an inappropriate balun choice can result in a strong increase in
harmonic peaks amplitude, thus degrading performances. The balun used in this measurement covers
only the 500MHz to 7GHz band so that the DC to 500MHz region of the first nyquist zone is distorted.
Figure 8-13. Observation of the 1st and 2nd nyquist zones in output mode RTZ with 0.5 GHz-7 GHz Balun
On the opposite, when appropriate balun is used the real device response is measured.
Figure 8-14. Spectrum of the 1st Nyquist Zone, Output Mode RTZ with a 2 MHz to 2GHz Bandwidth Balun
As a consequence, one must be aware that optimum performances can only be reached when using a
balun optimal for the band of interest of the application. We specifically recommend selecting a balun
which frequency domain covers the whole band of interest (for instance one whole Nyquist zone).
H4 degradation due
to Balun out of band
H3
Folded H1: 1518MHz
0 1.5 GHz 3 GHz
H1 : 1482MHz
Folded H3
Folded H2
H2 degradation due
to Balun out of band
Folded H4
H2 = - 82 dBm
residual impact of balun H3= -89 dbm
Balun :
2M – 2G
Fundamental :
1482MHz , - 3dFS
Images:
Fcloc k/16 +/- Fout
Images:
Fcloc k/8 +/- F out
Start 0 Hz 150 MHz Stop 1.5 GHz
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9. PACKAGE DESCRIPTION
9.1 Ci-CGA255 Outline
21.0 +/- 0.20
Triangle
patterned
on top at A1
corner.
550 µm side
width of triangle
Top View
Bottom View
All units in mm
Side View
No column on A1 corner
SCI chamfer 1.5 mm at A1 corner
0.30
Position of array of columns / edge A and B
Position of columns within array
Chanfer 0.4 (X4)
Columns
High T˚ Solder
Pb/Sn 90/10
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9.2 CLGA255 Outline
Square dot
patterned on
top at A1 corner.
570 µm diameter
Top view Bottom view Side view
Position of array of lands / edge A and B
Position of lands within array
(1.27)
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9.3 CCGA255 Outline
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9.4 Thermal Characteristics
Assumptions:
• Die thickness = 300 µm
•No convection
• Pure conduction
• No radiation
Typical Assumptions:
• Convection according to JEDEC
• Still air
• Horizontal 2s2p board
• Board size 114.3 × 76.2 mm, 1.6 mm thickness
10. DIFFERENCES BETWEEN EV12DS130A AND EV12DS130B
EV12DS130A and EV12DS130B exhibit the same dynamic performances.
EV12DS130B requires no specific dependency between power supplies nor power up sequences while
the EV12DS130A does require specific power up sequences as described in Section 8.9 on page 75.
Maximum supported sampling frequency with DSP clock feature for EV12DS130B is 2.1GHz due to
internal jitter. It is however possible to benefit from the EV12DS130B DAC performances up to 3GHz if
specific system architecture is implemented. Please refer to application AN1141 for further
information.
RTH Heating zone Ci CGA CCGA Unit
Junction-> Bottom of columns
7.5%
die area :
4580x4580 µm
13.8 15.0 °C/W
Junction-> Board ( JEDEC JESD51-8)
Boad size = 39x39mm, 1.6 mm Thickness) 17.1 18.6 °C/W
Junction -> Top of Lid 19.3 22.0 °C/W
Tjhot spot – TJdiode 3.3 3.3 °C/W
RTH Heating zone Ci CGA CCGA Unit
Junction -> Ambient 18%
die area :
4820x4820 µm
29.5 29.4 °C/W
Tjhot spot – TJdiode 3.3 3.3 °C/W
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No SYNC timing constraints (other than T1 T2) are required on EV12DS130B.
As a summary
When using EV12DS130A, please ensure your system fulfills those specific recommendations
• Power Up Sequence (See Section 8.9 on page 75)
• Power supplies dependency (see Section 8.9 on page 75)
• SYNC pin have to be driven in any case
• Please refer to errata sheet 1125
When using EV12DS130B, please ensure your system fulfills those specific recommendations
• In case sampling frequency is above 2.1 Gsps, please read the AN1141 “Using EV1xDS130B at
sampling rate higher than 2.1GSps”
Please refer to application note AN1140 "Replacing EV1xDS130A with EV1xDS130B” for further details
11. ORDERING INFORMATION
Please refer to datasheet details and application notes before ordering.
Table 11-1. Ordering Information
Part Number SMD Number Package Temperature Range Screening Level Comments
EV12DS130AG
EVX12DS130AGS CI-CGA255 Ambient Prototype
EV12DS130AMGSD/T CI-CGA255 –55°C < Tc,Tj < 125°C EQM Grade
EV12DS130AMGS9NB1 CI-CGA255 –55°C < Tc,Tj < 125°C Space Grade
EV12DS130AGS-EB CI-CGA255 Ambient Prototype Evaluation board
EVX12DS130ALG LGA255 Ambient Prototype
EV12DS130AMLGD/T LGA255 –55°C < Tc,Tj < 125°C EQM Grade
EV12DS130AMLG9NB1 LGA255 –55°C < Tc,Tj < 125°C Space Grade
EVX12DS130AGC CCGA255 Ambient Prototype
EV12DS130AMGC CCGA255 –55°C < Tc,Tj < 125°C Engineering
model
EV12DS130AMGCD/T CCGA255 –55°C < Tc,Tj < 125°C EQM Grade
EV12DS130AMGC9NB1 CCGA255 –55°C < Tc,Tj < 125°C Space Grade
EV12DS130AMLG-V 5962-1522201VXC LGA255 –55°C < Tc,Tj < 125°C QML-V Grade
MIL PRF 38535
EV12DS130AMGS-V 5962-1522201VYF CI-CGA255 –55°C < Tc,Tj < 125°C QML-V Grade
MIL PRF 38535
EV12DS130AMGC-V 5962-1522201VZF CCGA255 –55°C < Tc,Tj < 125°C QML-V Grade
MIL PRF 38535
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EV12DS130BG
EVX12DS130BGS CI-CGA255 Ambient Prototype
EV12DS130BGS-EB CI-CGA255 Ambient Prototype Evaluation board
EVX12DS130BLG LGA255 Ambient Prototype
EV12DS130BMLG LGA255 –55°C < Tc,Tj < 125°C Engineering
model
EV12DS130BMLGD/T LGA255 –55°C < Tc,Tj < 125°C EQM Grade
EV12DS130BMLG9NB1 LGA255 –55°C < Tc,Tj < 125°C Space Grade
EVX12DS130BGC CCGA255 Ambient Prototype
EV12DS130BMGC CCGA255 –55°C < Tc,Tj < 125°C Engineering
model
EV12DS130BMGCD/T CCGA255 –55°C < Tc,Tj < 125°C EQM Grade
EV12DS130BMGC9NB1 CCGA255 –55°C < Tc,Tj < 125°C Space Grade
EV12DS130BMLG-V 5962-1522202VXC LGA255 –55°C < Tc,Tj < 125°C QML-V Grade
MIL PRF 38535
EV12DS130BMGS-V 5962-1522202VYF CI-CGA255 –55°C < Tc,Tj < 125°C QML-V Grade
MIL PRF 38535
EV12DS130BMGC-V 5962-1522202VZF CCGA255 –55°C < Tc,Tj < 125°C QML-V Grade
MIL PRF 38535
Table 11-1. Ordering Information (Continued)
Part Number SMD Number Package Temperature Range Screening Level Comments
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12. REVISION HISTORY
This table provides revision history for this document.
Table 12-1. Revision History
Rev. No Date Substantive Change(s)
1080K January 2018 Table 10-1, “Ordering Information,” on page 48: Remove “Pending qualification / contact
Marketing” in the Comments column
1080J September 2016 Table 11-1, “Ordering Information,” on page 81: Correction of EV12DS130B SMD Numbers
1522201 instead of 1522202
1080I August 2016
Table 11-1, “Ordering Information,” on page 81: Introduction of QML-V grade for
EV12DS130B
Typo correction
1080H March 2016 Introduction of QML-V grade and add EV12DS130AMGC
1080G December 2014
Section 5.6 on page 28: OCDS [10] not allowed
Introduction and description of EV12DS130B
New Section 10. ”Differences between EV12DS130A and EV12DS130B” on page 80
Table 3-6, “AC Electrical Characteristics RTZ Mode (Second Nyquist Zone)(2),” on page 10:
Limits update
Table 3-9, “Coding Table (Theorical values),” on page 15: typo error on lines (RTZ) and
(NRTZ)
Section 5.1 ”DSP Output Clock” on page 18 updated
Section 5.3 ”MODE Function” on page 18: equations updated
Section 5.5 ”PSS (Phase Shift Select Function)” on page 26 updated
Section 5.9 ”Synchronization functions for multi-DAC operation” on page 31 updated
Figure 7-5 on page 42 updated
Figure 7-13 on page 46 updated
New Section 7.2.3 ”Single tone measurements: typical spectra at 3Gsps” on page 50
New Section 8.10 ”Balun Influence” on page 76
Table 11-1, “Ordering Information,” on page 81
1080F May 2014
Table 3-3: Change max current ICCD limit (2:1 & 4:1 MUX mode)
Table 3-3: Output internal differential resistor is test level 1 & 6
Table 3-6: remove minimum limit on |SFDR| in 4:1 MUX mode
Fs = 3Gsps @ Fout = 1600MHz 0 dBFS (now test level 4)
Table 3-6: remove maximum limit on highest spur level in 4:1 MUX mode
Fs = 3Gsps @ Fout = 1600MHz 0 dBFS (now test level 4)
Table 3-8: provide min & max limits for Input data rate in 2:1 and 4:1 MUX mode.
Table 3-8: Delay TDP is renamed TPD. It is a typ value and not a max value
Section 4. ”Definition of Terms” on page 16:
- TOD definition is replace by TPD/TOD definition for clarification
- Typo correction on RTZ and NRTZ term
Figure 8-11: modification of power supplies decoupling scheme on VCCA3 and VCCD
Typo errors
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1080E December 2013
Typo errors correction in formula of Section 5.3 ”MODE Function” on page 18 and Section
5.6 ”Output Clock Division Select Function” on page 28
Section 9.3 ”CCGA255 Outline” on page 79 CCGA Outline drawing
Table 3-2, “Recommended Conditions of Use,” on page 4: typo errors on note 2:
VCCA3 VCCD
Table 3-3, “Electrical Characteristics,” on page 5: typo errors on note 7: VCCA3 VCCD
1080D July 2013
Typo errors
OCDS restrictions
HTVF STVF flag application clarification
Power sequencing modification. Sync operation clarification.
Add LGA and CCGA outline drawing
1080C July 2012
Typo errors
absolute max rating clarifications
addition of pin equivalent schematic description
Power sequencing recommendation
1080B February 2012 Typo errors
Rth adjustement.
1080A February 2012 Initial Revision
Table 12-1. Revision History (Continued)
Rev. No Date Substantive Change(s)
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Table of Contents
MAIN FEATURES ...................................................................................... 1
PERFORMANCES ..................................................................................... 1
APPLICATIONS ......................................................................................... 1
1 Block Diagram .......................................................................................... 2
2 Description ............................................................................................... 2
3 Electrical Characteristics ........................................................................ 3
3.1Absolute Maximum Ratings .......................................................................................3
3.2Recommended Conditions of Use .............................................................................4
3.3Electrical Characteristics ...........................................................................................5
3.4AC Electrical Characteristics .....................................................................................7
3.5Timing Characteristics and Switching Performances ..............................................12
3.6Explanation of Test Levels ......................................................................................14
3.7Digital Input Coding Table .......................................................................................15
4 Definition of Terms ................................................................................ 16
5 Functional Description .......................................................................... 17
5.1DSP Output Clock ...................................................................................................18
5.2Multiplexer ...............................................................................................................18
5.3MODE Function .......................................................................................................18
5.4Input Under Clocking Mode (IUCM), Principle and Spectral Response .................. 23
5.5PSS (Phase Shift Select Function) ..........................................................................26
5.6Output Clock Division Select Function .................................................................... 28
5.7Synchronization FPGA-DAC: IDC_P, IDC_N, HTVF and STVF Functions .............29
5.8OCDS, MUX Combinations Summary .....................................................................31
5.9Synchronization functions for multi-DAC operation .................................................31
5.10Gain Adjust GA Function .......................................................................................32
5.11Diode Function ......................................................................................................33
6 PIN Description ...................................................................................... 34
7 Characterization Results ....................................................................... 39
7.1Static Performances ................................................................................................39
7.2AC Performances ....................................................................................................42
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8 Application Information ........................................................................ 70
8.1Analog Output (OUT/OUTN) ...................................................................................70
8.2Clock Input (CLK/CLKN) .........................................................................................71
8.3Digital Data, SYNC and IDC Inputs .........................................................................72
8.4DSP Clock ...............................................................................................................72
8.5Control Signal Settings ............................................................................................ 73
8.6HTVF and STVF Control Signal ..............................................................................73
8.7GA Function Signal .................................................................................................73
8.8Power Supplies Decoupling and Bypassing ............................................................ 74
8.9Power Up Sequencing .............................................................................................75
8.10Balun Influence ......................................................................................................76
9 Package Description ............................................................................. 77
9.1Ci-CGA255 Outline ..................................................................................................77
9.2CLGA255 Outline ....................................................................................................78
9.3CCGA255 Outline .................................................................................................... 79
9.4Thermal Characteristics .......................................................................................... 80
10 Differences between EV12DS130A and EV12DS130B ........................ 80
11 Ordering Information ............................................................................. 81
12 Revision History .................................................................................... 83