1
®
FN6052.3
ISL83483, ISL83485, ISL83488,
ISL83490, ISL83491
3.3V, Low Power, High Speed or Slew Rate
Limited, RS-485/RS-422 Transceivers
These Intersil RS-485/RS-422 devices are BiCMOS 3.3V
powered, single transceiv ers that meet both the RS-485 and
RS-422 standards for balanced communication. Unlike
competitive devices, this Intersil family is specified for 10%
tolerance supplies (3V to 3.6V).
The ISL83483 and ISL83488 utilize slew rate limited drivers
which reduce EMI, and minimize reflections from improperly
term inated transmission lines, or unterminated stubs in
multidrop and multipoint applications.
Data rates up to 10Mbps are achievable by using the
ISL83485, ISL83490, or ISL8349 1, which feature higher
slew rates.
Logic inputs (e.g., DI and DE) accept signals in excess of
5.5V, making them compatible with 5V logic families.
Receiver (Rx) inputs feature a “fail-safe if open” design,
which ensures a logic high output if Rx inputs are floating. All
de vices present a “single unit load” to the RS-485 bus , which
allows up to 32 transceivers on the network.
Driver (Tx) outputs are short circuit protected, even for
voltages exceeding the power supply voltage. Additionally,
on-chip thermal shutdown circuitry disables the Tx outputs to
prevent damage if power dissipation becomes excessive.
The ISL83488, ISL83490, ISL83491 are configured for full
duplex (separate Rx input and Tx output pins) ap plications.
The ISL83488 and ISL83490 are offered in space saving 8
lead packages for applications not requiring Rx and Tx
output disable functions (e.g., point-to-point and RS-422).
Half duplex configurations (ISL83483, ISL83485) multiplex
the Rx inputs and Tx outputs to provide transceivers with Rx
and Tx disable functions in 8 lead packages.
Features
• Operate from a Single +3.3V Supply (10% Tolerance)
• Interoperable with 5V Logic
• High Data Rates. . . . . . . . . . . . . . . . . . . . . up to 10Mbps
• Single Unit Load Allows up to 32 Devices on the Bus
• Slew Rate Limited Versions for Error Free Data
Transmission (ISL83483, ISL83488) . . . . . .up to 250kbps
• Low Current Shutdown Mode (ISL83483, ISL83485,
ISL83491). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15nA
• -7V to +12V Common Mode Input Vol ta ge Range
• Three State Rx and Tx Outputs (Except ISL83488,
ISL83490)
• 10ns Propagation Dela y, 1ns Skew (ISL83485, ISL83490,
ISL83491)
• Full Duplex and Half Duplex Pinouts
• Current Limiting and Thermal Shutdown for driver
Overload Protection
•Pb-free available
Applications
• Factory Automation
• Security Networks
• Building Environmental Control Systems
• Industrial/Process Control Networks
• Level Translators (e.g., RS-232 to RS-422)
• RS-232 “Extension Cords”
TABLE 1. SUMMARY OF FEATURES
PART
NUMBER HALF/FULL
DUPLEX DATA RATE
(Mbps) SLEW-RATE
LIMITED? RECEIVER/DRIVER
ENABLE? QUIESCENT ICC
(mA) LOW POWE R
SHUTDOWN? PIN COUNT
ISL83483 Half 0.25 Yes Yes 0.65 Yes 8
ISL83485 Half 10 No Yes 0.65 Yes 8
ISL83488 Full 0.25 Yes No 0.65 No 8
ISL83490 Full 10 No No 0.65 No 8
ISL83491 Full 10 No Yes 0.65 Yes 14
Data Sheet August 2004
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Pinouts
ISL83483, ISL83485 (PDIP, SOIC)
TOP VIEW ISL83488, ISL83490 (PDIP, SOIC)
TOP VIEW ISL83491 (PDIP, SOIC)
TOP VIEW
RO
RE
DE
DI
1
2
3
4
8
7
6
5
VCC
B/Z
A/Y
GND
D
RVCC
RO
DI
GND
1
2
3
4
8
7
6
5
A
B
Z
Y
D
RNC
RO
RE
DE
DI
GND
GND
VCC
VCC
A
B
Z
Y
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
D
R
Ordering Information
PART NO.
(BRAND) TEMP.
RANGE (oC) PACKAGE PKG. DWG. #
ISL83483IB*
(83483IB) -40 to 85 8 Ld SOIC M8.15
ISL83483IBZ*
(83483IB) (Note) -40 to 85 8 Ld SOIC
(Pb-free) M8.15
ISL83483IP -40 to 85 8 Ld PDIP E8.3
ISL83485IB*
(83485IB) -40 to 85 8 Ld SOIC M8.15
ISL83485IBZ*
(83485IB) (Note) -40 to 85 8 Ld SOIC
(Pb-free) M8.15
ISL83485IP -40 to 85 8 Ld PDIP E8.3
ISL83488IB*
(83488IB) -40 to 85 8 Ld SOIC M8.15
ISL83488IBZ*
(83488IB) (Note) -40 to 85 8 Ld SOIC
(Pb-free) M8.15
ISL83488IP -40 to 85 8 Ld PDIP E8.3
ISL83490IB*
(83490IB) -40 to 85 8 Ld SOIC M8.15
ISL83490IBZ*
(83490IB) (Note) -40 to 85 8 Ld SOIC
(Pb-free) M8.15
ISL83490IP -40 to 85 8 Ld PDIP E8.3
ISL83491IB* -40 to 85 14 Ld SOIC M14.15
ISL83491IBZ*
(Note) -40 to 85 14 Ld SOIC
(Pb-free) M14.15
ISL83491IP -40 to 85 14 Ld PDIP E14.3
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Truth Tables
TRANSMITTING
INPUTS OUTPUTS
RE DE DI Z Y
X1101
X1010
0 0 X High-Z High-Z
1 0 X High-Z * High-Z *
NOTE: *Shutdown Mode for ISL83483, ISL83485, ISL83491
RECEIVING
INPUTS OUTPUT
RE DE
Half Duplex DE
Full Duplex A-B RO
00X≥ +0.2V 1
00X≤ -0.2V 0
0 0 X Inputs Open 1
100XHigh-Z *
111XHigh-Z
NOTE: *Shutdown Mode for ISL83483, ISL83485, ISL83491
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
3
Pin Descriptions
PIN FUNCTION
RO Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating).
RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high.
DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low.
DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low.
GND Ground connection.
A/Y Noninverting receiver input and noninverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1.
B/Z Inverting receiver input and inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1.
A Noninverting receiver input.
B Inverting receiver input.
Y Noninverting driver output.
Z Inverting driver output.
VCC System power supply input (3V to 3.6V).
NC No Connection.
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
4
Typical Operating Circuits
ISL83483, ISL83485
ISL83488, ISL83490
ISL83491
0.1µF
+
D
R
7
6
8
1
2
3
4
5
VCC
GND
RO
RE
DE
DI
A/Y
B/Z
+3.3V
0.1µF+
D
R
6
7
8
1
2
3
4
5
VCC
GND
RO
RE
DE
DI
A/Y
B/Z
+3.3V
RTRT
0.1µF
+
D
R8
7
6
5
1
2
3
4
VCC
GND
RO
DI
A
B
Y
Z
+3.3V
0.1µF+
D
R
8
7
6
5
1
2
3
4
VCC
GND
RO
DI
A
B
Y
Z
+3.3V
RT
RT
0.1µF
+
D
R12
11
10
9
13, 14
2
3
4
5
6, 7
VCC
GND
RO
RE
DE
DI
A
B
Y
Z
+3.3V
0.1µF+
D
R
12
11
10
9
13,14
2
3
4
5
6, 7
VCC
GND
RO
RE
DE
DI
A
B
Y
Z
+3.3V
RT
RT
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
5
Absolute Maximum Ratings Thermal Info rmation
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltages
DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input/Output Voltages
A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V
RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V)
Short Circuit Duration
Y, Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Operating Conditions
Temperature Range
ISL834XXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1) θJA (oC/W)
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 170
8 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . 140
14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 130
14 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 105
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC- Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Test Conditions: VCC = 3V to 3.6V; Unless Otherwise Specified. Typicals are at VCC = 3.3V, TA = 25oC,
Note 2
PARAMETER SYMBOL TEST CONDITIONS TEMP
(oC) MIN TYP MAX UNITS
DC CHARACTERISTICS
Driver Differential VOUT (no load) VOD1 Full - - VCC V
Driver Differential VOUT (with load) VOD2 RL = 100Ω (RS-422) (Figure 1A) Full 2 2.7 - V
RL = 54Ω (RS-485) (Figure 1A) Full 1.5 2.3 VCC V
RL = 60Ω, -7V ≤ VCM ≤ 12V (Figure 1B) Full 1.5 2.6 - V
Change in Magnitude of Driver
Differential VOUT for
Complementary Output States
∆VOD RL = 54Ω or 100Ω (Figure 1A) Full - 0.01 0.2 V
Driver Common-Mode VOUT VOC RL = 54Ω or 100Ω (Figure 1A) Full - 1.8 3 V
Change in Magnitude of Driver
Common-Mode VOUT for
Complementary Output States
∆VOC RL = 54Ω or 100Ω (Figure 1A) Full - 0.01 0.2 V
Logic Input High Voltage VIH DE, DI, RE Full 2 - - V
Logic Input Low Voltage VIL DE, DI, RE Full - - 0.8 V
Logic Input Current IIN1 DE, DI Full -2 - 2 µA
RE Full -25 - 25 µA
Input Current (A, B) IIN2 DE = 0V, VCC = 0V or 3.6V VIN = 12V Full - 0.6 1 mA
VIN = -7V Full - -0.3 -0.8 mA
Output Leakage Current (Y, Z)
(ISL83491) IIN3 RE = 0V, DE = 0V, VCC = 0V or 3.6V VIN = 12V Full - 14 20 µA
VIN = -7V Full -20 -11 - µA
Output Leakage Current (Y, Z)
in Shutdown Mode (ISL83491) IIN3 RE = VCC, DE = 0V, VCC = 0V or 3.6V VIN = 12V Full - 0.03 1 µA
VIN = -7V Full -1 -0.01 - µA
Receiver Differential Threshold
Voltage VTH -7V ≤ VCM ≤ 12V Full -0.2 - 0.2 V
Receiver Input Hysteresis ∆VTH VCM = 0V 25 - 50 - mV
Receiver Output High Voltage VOH IO = -4mA, VID = 200mV Full VCC -
0.4 --V
Receiver Output Low Voltage VOL IO = -4mA, VID = 200mV Full - - 0.4 V
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
6
Three-State (high impedance)
Receiver Output Current IOZR 0.4V ≤ VO ≤ 2.4V Full -1 - 1 µA
Receiver Input Resistance RIN -7V ≤ VCM ≤ 12V Full 12 19 - kΩ
No-Load Supply Current (Note 3) ICC DI = 0V or VCC DE = VCC,
RE = 0V
or VCC
Full - 0.75 1.2 mA
DE = 0V,
RE = 0V Full - 0.65 1 mA
Shutdown Supply Current
(Except ISL83488 and ISL83490) ISHDN DE = 0V, RE = VCC, DI = 0V or VCC Full - 15 100 nA
Driver Short-Circuit Current,
VO = High or Low IOSD1 DE = VCC, -7V ≤ VY or VZ ≤ 12V (Note 4) Full - - 250 mA
Receiver Short-Circuit Current IOSR 0V ≤ VO ≤ VCC Full 8 - 60 mA
DRIVER SWITCHING CHARAC TERISTICS (ISL83485, ISL83490, ISL83491)
Maximum Data Rate fMAX Full 12 15 - Mbps
Driver Differential Output Delay tDD RDIFF = 60Ω, CL = 15pF (Figure 2A) Full 1 10 35 ns
Driver Differential Rise or Fall Time t R, tFRDIFF = 60Ω, CL = 15pF (Figure 2A) Full 3 5 20 ns
Driver Input to Output Delay tPLH, tPHL RL = 27Ω, CL = 15pF (Figure 2C) Full 6 10 35 ns
Driver Output Skew tSKEW RL = 27Ω, CL = 15pF (Figure 2C) Full - 1 8 ns
Driver Enable to Output High
(Except ISL83490) tZH RL = 110Ω, CL = 50pF, SW = GND (Figure 3),
(Note 5) Full - 45 90 ns
Driver Enable to Output Low
(Except ISL83490) tZL RL = 110Ω, CL = 50pF, SW = VCC (Figure 3),
(Note 5) Full - 45 90 ns
Driver Disable from Output High
(Except ISL83490) tHZ RL = 110Ω, CL = 50pF, SW = GND (Figure 3) 25 - 65 80 ns
Full - - 110 ns
Driver Disable from Output Low
(Except ISL83490) tLZ RL = 110Ω, CL = 50pF, SW = VCC (Figure 3) 25 - 65 80 ns
Full - - 110 ns
Driver Enable from Shutdown to
Output High (Except ISL83490) tZH(SHDN) RL = 110Ω, CL = 50pF, SW = GND (Figure 3),
(Notes 7, 8) Full - 115 150 ns
Driver Enable from Shutdown to
Output Low (Except ISL83490) tZL(SHDN) RL = 110Ω, CL = 50pF, SW = VCC (Figure 3),
(Notes 7, 8) Full - 115 150 ns
DRIVER SWITCHING CHARAC TERISTICS (ISL83483, ISL83488)
Maximum Data Rate fMAX Full 250 - - kbps
Driver Differential Output Delay tDD RDIFF = 60Ω, CL = 15pF (Figure 2A) Full 600 930 1400 ns
Driver Differential Rise or Fall Time t R, tFRDIFF = 60Ω, CL = 15pF (Figure 2A) Full 400 900 1200 ns
Driver Input to Output Delay tPLH, tPHL RL = 27Ω, CL = 15pF (Figure 2C) 25 600 930 1500 ns
Full 400 - 1500 ns
Driver Output Skew tSKEW RL = 27Ω, CL = 15pF (Figure 2C) Full - 140 - ns
Driver Enable to Output High
(Except ISL83488) tZH RL = 110Ω, CL = 50pF, SW = GND (Figure 3),
(Note 5) Full - 385 800 ns
Driver Enable to Output Low
(Except ISL83488) tZL RL = 110Ω, CL = 50pF, SW = VCC (Figure 3),
(Note 5) Full - 55 800 ns
Driver Disable from Output High
(Except ISL83488) tHZ RL = 110Ω, CL = 50pF, SW = GND (Figure 3) 25 - 63 80 ns
Full - - 110 ns
Electrical Specifications Test Conditions: VCC = 3V to 3.6V; Unless Otherwise Specified. Typicals are at VCC = 3.3V, TA = 25oC,
Note 2 (Continued)
PARAMETER SYMBOL TEST CONDITIONS TEMP
(oC) MIN TYP MAX UNITS
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
7
Driver Disable from Output Low
(Except ISL83488) tLZ RL = 110Ω, CL = 50pF, SW = VCC (Figure 3) 25 - 70 80 ns
Full - - 110 ns
Driver Enable from Shutdown to
Output High (Except ISL83488) tZH(SHDN) RL = 110Ω, CL = 50pF, SW = GND (Notes 7, 8) Full - 450 2000 ns
Driver Enable from Shutdown to
Output Low (Except ISL83488) tZL(SHDN) RL = 110Ω, CL = 50pF, SW = VCC (Figure 3),
(Notes 7, 8) Full - 126 2000 ns
RECEIVER SWITCHING CHARACTERISTICS (All Versions)
Receiver Input to Output Delay tPLH, tPHL (Figure 4) Full 25 45 90 ns
Receiver Skew | tPLH - tPHL |t
SKD (Figure 4) 25 - 2 10 ns
Full - 2 12 ns
Receiver Enable to Output High
(Except ISL83488 and ISL83490) tZH RL = 1kΩ, CL = 15pF, SW = GND (Figure 5),
(Note 6) Full - 11 50 ns
Receiver Enable to Output Low
(Except ISL83488 and ISL83490) tZL RL = 1kΩ, CL = 15pF, SW = VCC (Figure 5),
(Note 6) Full - 11 50 ns
Receiver Disable from Output High
(Except ISL83488 and ISL83490) tHZ RL = 1kΩ, CL = 15pF, SW = GND (Figure 5) Full - 7 45 ns
Receiver Disable from Output Low
(Except ISL83488 and ISL83490) tLZ RL = 1kΩ, CL = 15pF, SW = VCC (Figure 5) Full - 7 45 ns
Time to Shutdown
(Except ISL83488 and ISL83490) tSHDN (Note 7) Full 80 190 300 ns
Receiver Enable from Shutdown to
Output High
(Except ISL83488 and ISL83490)
tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure 5),
(Notes 7, 9) Full - 240 600 ns
Receiver Enable from Shutdown to
Output Low
(Except ISL83488 and ISL83490)
tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 5),
(Notes 7, 9) Full - 240 600 ns
NOTES:
2. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
3. Supply current specification is valid for loaded drivers when DE = 0V.
4. Applies to peak current. See “Typical Performance Curves” for more information.
5. When testing the ISL83483, ISL83485, ISL83491, keep RE = 0 to prevent the device from entering SHDN.
6. When testing the ISL83483, ISL83485, ISL83491, the RE signal high time must be short enough (typically <100ns) to prevent the device from
entering SHDN.
7. The ISL83483, ISL83485, ISL83491 are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 80ns, the
parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 300ns, the parts are guaranteed to have entered shutdown.
See “Low-Power Shutdown Mode” section.
8. Keep RE = VCC, and set the DE signal low time >300ns to ensure that the device enters SHDN.
9. Set the RE signal high time >300ns to ensure that the device enters SHDN.
Electrical Specifications Test Conditions: VCC = 3V to 3.6V; Unless Otherwise Specified. Typicals are at VCC = 3.3V, TA = 25oC,
Note 2 (Continued)
PARAMETER SYMBOL TEST CONDITIONS TEMP
(oC) MIN TYP MAX UNITS
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
8
Test Circuits and Wavef orms
FIGURE 1A. VOD AND VOC FIGURE 1B. VOD WITH COMMON MODE LOAD
FIGURE 1. DC DRIVER TEST CIRCUITS
FIGURE 2A. DIFFERENTIAL TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2C. SINGLE ENDED TEST CIRCUIT
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
D
DE
DI
VCC
VOD
VOC
RL/2
RL/2
Z
YD
DE
DI
VCC
VOD
375Ω
375Ω
Z
Y
RL = 60ΩVCM
-7V to +12V
D
DE
DI
3V
SIGNAL
GENERATOR
CL = 15pF
RDIFF = 60Ω
Z
YCL = 15pF OUT (Y)
3V
0V
tPLH
1.5V1.5V
VOH
VOL
50% 50%
tPHL
OUT (Z)
tPHL
VOH
VOL
50% 50%
tPLH
DIFF OUT (Y - Z)
tR
+VOD
-VOD
90% 90%
tF
10% 10%
DI
tDD
50%
tDD
50%
SKEW = |tPLH (Y or Z) - tPHL (Z or Y)|
D
DE
DI
3V
SIGNAL
GENERATOR
Z
YCL = 15pF
RL = 27Ω
VOM
OUT
VOH + VOL
2≈1.5VVOM =
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
9
FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490)
FIGURE 4A. TEST CIRCUIT FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. RECEIVER PROPAGATION DELAY
FIGURE 5A. TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490)
Test Circuits and Wavef orms (Continued)
D
DE
DI Z
Y
VCC
GND
SW
PARAMETER OUTPUT RE DI SW
tHZ Y/Z X 1/0 GND
tLZ Y/Z X 0/1 VCC
tZH Y/Z 0 (Note 5) 1/0 GND
tZL Y/Z 0 (Note 5) 0/1 VCC
tZH(SHDN) Y/Z 1 (Note 8) 1/0 GND
tZL(SHDN) Y/Z 1 (Note 8) 0/1 VCC
SIGNAL
GENERATOR
110Ω
CL = 50pF
OUT (Y, Z)
3V
0V
1.5V1.5V
VOH
0V
VOH - 0.25V
tHZ
OUT (Y, Z)
VCC
VOL
VOL + 0.25V
tLZ
DE
OUTPUT HIGH
OUTPUT LOW
tZL, tZL(SHDN)
tZH, tZH(SHDN)
NOTE 7
50%
50%
NOTE 7
NOTE 7
SIGNAL
GENERATOR
RRO
RE
A
B
GND
+1.5V 15pF
RO
3V
0V
tPLH
1.5V1.5V
VCC
0V
50% 50%
tPHL
A
1kΩVCC
GND
SW
PARAMETER DE A SW
tHZ 0 +1.5V GND
tLZ 0-1.5VV
CC
tZH (Note 6) 0 +1.5V GND
tZL (Note 6) 0 -1.5V VCC
tZH(SHDN) (Note 9) 0 +1.5V GND
tZL(SHDN) (Note 9) 0 -1.5V VCC
SIGNAL
GENERATOR
RRO
RE
A
B
GND
15pF
RO
3V
0V
1.5V1.5V
VOH
0V
1.5V VOH - 0.25V
tHZ
RO
VCC
VOL
1.5V VOL + 0.25V
tLZ
RE
OUTPUT HIGH
OUTPUT LOW
tZL, tZL(SHDN)
tZH, tZH(SHDN)
NOTE 7
NOTE 7
NOTE 7
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
10
Application Information
RS-485 and RS-422 are differential (balanced) data
transmission standards for use in long haul or noisy
environments. RS-422 is a subset of RS-485, so RS-485
transceivers are also RS-422 compliant. RS-422 is a point-
to-multipoint (multidrop) standard, which allows only one
driver and up to 10 (assuming one unit load devices)
receivers on each b us . RS-485 is a true multipoint standard,
which allows up to 32 one unit load devices (any
combination of drivers and receivers) on each bus. To allow
f or multipoint operation, the RS-485 spec requires that
drivers must handle bus contention without sustaining any
damage.
Another important advantage of RS-485 is the e xtended
common mode range (CMR), which specifies that the driver
outputs and receiver inputs withstand signals that range from
+12V to -7V. RS-422 and RS-485 are intended for runs as
long as 4000’, so the wide CMR is necessary to handle
ground potential differences, as well as voltages induced in
the cable by external fields.
Receiver Featu r es
These de vices utilize a diff erential input receiv er f or maxim um
noise immunity and commo n mode rejection. Inpu t sensitivity
is ±200mV, as required by the RS422 a nd RS-485
specifications.
Receiver input impedance surpasses the RS-422 spec of
4kΩ, and meets the RS-485 “Unit Load” requirement of 12kΩ
minimum.
Receiver inputs function with common mode voltages as
great as +9V/-7V outside the power supplies (i.e., +12V and
-7V), making them ideal for long networks where induced
voltages are a realistic concern.
All the receivers include a “fail-safe if open” function th at
guarantees a high level receiver ou tput if the receiver inputs
are unconnected (floating).
Receivers easily meet the data rates supported by the
corresponding driver.
ISL83483, ISL83485, ISL83491 receiver outputs are tri-
statable via the active low RE input.
Driver Features
The RS-485, RS-422 driver is a diff erential output de vice that
delivers at least 1.5V across a 54Ω load (RS-485), and at
least 2V across a 100Ω load (RS-422) even with VCC =3V.
The drivers feature low propagation delay skew to maximize
bit width, and to minimize EMI.
Drivers of the ISL83483, ISL83485, ISL83491 are tri-statable
via the active high DE input.
ISL83483/88 driver outputs are slew rate limited to minimize
EMI, and to minimize reflections in unterminated or
improperly terminated networks. Data rate on these slew
rate limited versions is a maximum of 250kbps. Outputs of
ISL83485, ISL83490, ISL83491 drivers are not limited, so
faster output transition times allow data rates of at least
10Mbps.
Data Rate, Cables , and Te rmi n at ions
RS-485, RS-422 are intended for network lengths up to
4000’, but the maximum system data rate decreases as the
transmission length increases. De vices operating at 10Mbps
are limited to lengths of a few hundred feet, while the
250kbps versions can operate at full data rates with lengths
in e xcess of 1000’.
Twisted pai r is the cable of choice for RS-485, RS-422
networks. Twisted pair cables tend to pick up noise and other
electromagnetically induced voltages as common mode
signals, which are effectively rejected by the differential
receivers in these ICs.
Proper termination is imperative, when using the 10Mbps
devices, to minimize reflections. Short networks using the
250kbps versions need not be terminated, but, terminations
are recommended unless power dissipation is an overriding
concern.
In point-to-point, or point-to-multipoint (single driver on bus)
networks, the main cable should be terminated in its
characteristic impedance (typically 120Ω) at the end farthest
from the driver. In multi-receiver applications, stubs
connecting receivers to the main cable should be kept as
short as possible. Multipoint (multi-driver) systems require
that the main cable be terminated in its characteristic
impedance at both ends. Stubs connecting a transceiver to
the main cable should be kept as short as possible.
Built-In Driver Overload Pr otection
As stated previously, the RS-485 spec requires that drivers
survive worst case bus contentions undamaged. The
ISL834XX devices meet this requirement via driver output
short circuit current limits, and on-chip thermal shutdown
circuitry.
The driver output stages incorporate short circuit current
limiting circuitry which ensures that the output current never
exceeds the RS-485 spec, even at the common mode
voltage range extremes. Additionally, these devices utilize a
foldback circuit which reduces the short circuit current, and
thus the power dissipation, whenev er the contending v oltage
exceeds either supply.
In the event of a major short circuit condition, ISL834XX
de vices also include a thermal shutdown f eature that
disables the drivers whenever the die temperature becomes
excessive. This eliminates the power dissipation, allowing
the die to cool. The dr ivers automatically reenable after the
die temperature drops about 15 degrees. If the contention
persists, the thermal shutdown/reenable cycle repeats until
the fault is cleared. Receivers stay operational during
ther mal shutdown.
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
11
Low Power Shutdown Mode (ISL83483, ISL83485,
ISL83491 Only)
These CMOS transceivers all use a fraction of the power
required by their bipolar counterparts, but the ISL83483,
ISL83485, ISL83491 include a shutdown feature that
reduces the already low quiescent ICC to a 15nA trickle.
They enter shutdown whenever the receiver and driver are
simultaneously disabled (RE =V
CC and DE = GND) for a
period of at least 300ns. Disabling both the driver and the
receiver for less than 80ns guarantees that shutdown is not
entered.
Note that receiver and driver enable times increase when
these devices enable from shutdown. Refer to Notes 5-9, at
the end of the Electrical Specification table, for more
information.
Typical Performance Curves VCC = 3.3V, TA = 25oC, ISL83483 thru ISL83491; Unless Otherwise Specified
FIGURE 6. DRIVER OUTPUT CURRENT vs DIFFERENTIAL
OUTPUT VOLTAGE FIGURE 7. DRIVER DIFFERENTIAL OUTPUT V OLT AGE vs
TEMPERATURE
FIGURE 8. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT
VOLT AGE FIGURE 9. SUPPLY CURRENT vs TEMPERATURE
DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIVER OUTPUT CURRENT (mA)
00.511.522.533.5
0
10
20
30
40
50
60
70
80
90
100
110
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
-40 0 50 85
TEMPERATURE (oC)
DIFFERENTIAL OUTPUT VOLTAGE (V)
-25 25 75
RDIFF = 54Ω
RDIFF = 100Ω
OUTPUT VOLTAGE (V)
-7 -6 -4 -2 0 2 4 6 8 10 12
OUTPUT CURRENT (mA)
-60
-40
-20
0
20
40
60
80
100
120
140
160
-80
-100
-120
Y OR Z = HIGH
Y OR Z = LOW
-40 0 50 85
TEMPERATURE (oC)
ICC (µA)
-25 25 75
ISL83483/85, DE = VCC, RE = X
ISL83483/85, DE = RE = GND; ISL83491, DE = X, RE = GND;
ISL83488/90
600
650
700
750
800
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
12
FIGURE 1 0. DRIVE R PROPA GATION DELAY vs
TEMPERATURE (ISL83483, ISL83488) FIGURE 11. DRIVER SKEW vs TEMPERATURE
(ISL83483, ISL83488)
FIGURE 1 2. DRIVE R PROPA GATION DELAY vs
TEMPERATURE (ISL83485, ISL83490, ISL83491) FIGURE 13. DRIVER SKEW vs TEMPERATURE
(ISL83485, ISL84390, ISL83491)
FIGURE 14. DRIVER AND RECEIVER W A VEFORMS,
LOW TO HIGH (ISL83483, ISL83488) FIGURE 15. DRIVER AND RECEIVER W A VEFORMS,
HIGH TO LOW (ISL83483, ISL83488)
Typical Performance Curves VCC = 3.3V, TA = 25oC, ISL83483 thru ISL83491; Unless Otherwise Specified (Continued)
-40 0 50 85
TEMPERATURE (oC)
-25 25 75
PROPAGATION DELAY (ns)
700
800
900
1000
1100
1200
tPLHZ
tPHLY
tPLHY
tPHLZ
RDIFF = 54Ω
-40 0 50 85
TEMPERATU RE (oC)
SKEW (ns)
-25 25 75
0
50
100
150
200
250
300
|tPLHY - tPHLZ|
|tPHLY - tPLHZ|
|CROSS PT. OF Y↑ & Z↓ - CROSS PT. OF Y↓ & Z↑|
RDIFF = 54Ω
FIGURE 2A
-40 0 50 85
TEMPERATURE (oC)
-25 25 75
PROPAG ATION DELAY (ns)
8
9
10
11
12
13
14
15
16
tPHLY
tPHLZ
tPLHZ
tPHLY
tPLHY
RDIFF = 54Ω
-40 0 50 85
TEMPERATU RE (oC)
SKEW (ns)
-25 25 75
0.5
1
1.5
2
2.5
3
3.5
4
|tPLHY - tPHLZ|
|tPHLY - tPLHZ|
|CROSSING PT. OF Y↑ & Z↓ -
CROSSING PT. OF Y↓ & Z↑|
RDIFF = 54Ω
FIGURE 2A
TIME (400ns/DIV)
RECEIVER OUTPUT (V)
RDIFF = 54Ω, CL = 15pF
0
5
DRIVER OUTPUT (V)
0
5
DRIVER INPUT (V)
DI
RO
0
0.5
1
1.5
2
2.5
3
B/Z
A/Y
TIME (400ns/DIV)
RECEIVER OUTPUT (V)
RDIFF = 54Ω, CL = 15pF
0
5
DRIVER OUTPUT (V)
0
5
DRIVER INPUT (V)
DI
RO
0
0.5
1
1.5
2
2.5
3
B/Z
A/Y
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
13
Die Characteristics
SUBSTRATE PO TENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
528
PROCESS:
Si Gate CMOS
FIGURE 16. DRIVER AND RECEIVER W A VEFORMS,
LOW TO HIGH (ISL83485, ISL83490, ISL83491) FIGURE 17. DRIVER AND RECEIVER W A VEFORMS,
HIGH TO LOW (ISL83485, ISL83490, ISL83491)
Typical Performance Curves VCC = 3.3V, TA = 25oC, ISL83483 thru ISL83491; Unless Otherwise Specified (Continued)
TIME (10ns/DIV)
RECEIVER OUTPUT (V)
RDIFF = 54Ω, CL = 15pF
0
5
DRIVER OUTPUT (V)
0
5
DRIVER INPUT (V )
DI
RO
0
0.5
1
1.5
2
2.5
3
B/Z
A/Y
TIME (10ns/DIV)
RECEIVER OUTPUT (V)
RDIFF = 54Ω, CL = 15pF
0
5
DRIVER OUTPUT (V)
0
5
DRIVER INPUT (V)
DI
RO
0
0.5
1
1.5
2
2.5
3
A/Y
B/Z
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
14
Dual-In-Line Plastic Packages (PDIP)
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
eA-C-
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.355 0.400 9.01 10.16 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N8 89
Rev. 0 12/93
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
15
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpen-
dicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N14 149
Rev. 0 12/93
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
16
Small Outline Plastic Packages (SOIC)
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
α0o8o0o8o-
Rev. 0 12/93
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
17
All Intersil U.S. products are man ufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporati on and its products, see www.intersil.com
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3367 0.3444 8.55 8.75 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N14 147
α0o8o0o8o-
Rev. 0 12/93
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
