MB15E03SL
Single Serial Input PLL Frequency Synthesizer
On-chip 1.2 GHz Prescaler
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-08431 Rev. *A Revised Thursday, December 22, 2016
The Cypress MB15E03SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1.2 GHz prescaler. The 1.2 GHz
prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing operation.
The supply voltage range is between 2.4 V and 3.6 V. The MB15E03SL uses the latest BiCMOS process, as a result, the supply
current is typically 2.0 mA at 2.7 V. A refined charge pump supplies a well balanced output currents of 1.5 mA or 6 mA. The charge
pump current is selectable by serial data.
Features
■High frequency operation: 1.2 GHz max
■Low power supply voltage: VCC = 2.4 V to 3.6 V
■Ultra Low power supply current:ICC = 2.0 mA typ. (VCC = Vp = 2.7 V, Ta = +25C, in locking state)
ICC = 2.5 mA typ. (VCC = Vp = 3 V, Ta = +25C, in locking state)
■Direct power saving function:Power supply current in power saving mode
Typ. 0.1 A (VCC = Vp = 3 V, Ta = +25C), Max. 10A (VCC = Vp = 3 V)
■Dual modulus prescaler: 64/65 or 128/129
■Serial input 14-bit programmable reference divider: R = 3 to 16,383
■Serial input programmable divider consisting of:
❐Binary 7-bit swallow counter: 0 to 127
❐Binary 11-bit programmable counter: 3 to 2,047
■Selectable charge pump current
■On-chip phase control for phase comparator
■Operating temperature: Ta = –40 to +85C
Document Number: 002-08431 Rev. *A Page 2 of 27
MB15E03SL
Contents
Pin Assignments ...............................................................3
Pin Description ..................................................................4
Block Diagram ...................................................................5
Absolute Maximum Ratings .............................................6
Recommended Operating Conditions ............................6
Electrical Characteristics .................................................7
Functional Description .....................................................9
Pulse Swallow Function ...............................................9
Serial Data Input ..........................................................9
Do Output Control ......................................................12
Power Saving Mode (Intermittent Mode Control
Circuit) ........................................................................12
Serial Data Input Timing .................................................13
Phase Comparator Output Waveform ...........................14
Measurement Circuit (for Measuring Input
Sensitivity fin/OSCIN) .....................................................15
Typical Characteristics ...................................................16
fin Input Sensitivity .....................................................16
OSCIN Input Sensitivity .............................................16
Do Output Current .....................................................17
fin Input Impedance ...................................................18
OSCIN Input Impedance ...........................................18
Reference Information ....................................................19
Application Example .......................................................22
Usage Precautions ..........................................................23
Ordering Information ......................................................23
Package Dimensions ......................................................24
Document History ........................................................... 26
Sales, Solutions, and Legal Information ...................... 27
Document Number: 002-08431 Rev. *A Page 3 of 27
MB15E03SL
1. Pin Assignments
OSCIN
OSCOUT
VP
VCC
DO
GND
Xfin
fin
φR
φP
LD/fout
ZC
PS
LE
Data
Clock
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
TOP
VIEW
LD/fout
ZC
PS
LE
VP
VCC
DO
GND
Xfin fin Clock Data
OSCOUTOSCIN RP
3
2
1
4
5678
9
10
11
12
16 15 14 13
(FPT-16P-M05)
16-pin SSOP
(LCC-16P-M69)
16-pin QFN
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MB15E03SL
2. Pin Description
Pin No. Pin Name I/O Descriptions
SSOP QFN
115OSCIN I Programmable reference divider input.
Oscillator input connection to a TCXO.
216OSC
OUT O Oscillator output.
31VP— Power supply voltage input for the charge pump.
42VCC — Power supply voltage input.
53D
OO Charge pump output.
Phase of the charge pump can be selected via programming of the FC bit.
6 4 GND — Ground.
7 5 Xfin I Prescaler complementary input which should be grounded via a capacitor.
8 6 fin I Prescaler input.
Connection to an external VCO should be done via AC coupling.
9 7 Clock I Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock.
(Open is prohibited.)
10 8 Data I Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
11 9 LE I Load enable signal input. (Open is prohibited.)
When LE is set high, the data in the shift register is transferred to a latch according
to the control bit in the serial data.
12 10 PS I Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
PS = “H”; Normal mode
PS = “L”; Power saving mode
13 11 ZC I Forced high-impedance control for the charge pump (with internal pull up resistor.)
ZC = “H”; Normal Do output.
ZC = “L”; Do becomes high impedance.
14 12 LD/fout O Lock detect signal output (LD)/phase comparator monitoring output (fout).
The output signal is selected via programming of the LDS bit.
LDS = “H”; outputs fout (fr/fp monitoring output)
LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)
15 13 P O Phase comparator N-channel open drain output for an external charge pump. Phase
can be selected via programming of the FC bit.
16 14 R O Phase comparator CMOS output for an external charge pump. Phase can be
selected via programming of the FC bit.
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3. Block Diagram
Clock
Data
fin
LE
OSC
OUT
OSC
IN
Reference
oscillator
circuit
Phase
comparator
Lock
detector
LD/fr/fp
selector
Binary 14-bit
reference
counter
Binary 7-bit
swallow
counter
Binary 11-bit
programmable
counter
14-bit latch 4-bit latch
19-bit shift register
Intermittent mode
control
(power save)
1-bit
cotrol
latch
Prescaler
64 / 65,
128 / 129
7-bit latch
Charge pump
Current switch
11-bit latch
PS
D
O
V
P
R
LD/fout
P
Xfin
GND
V
CC
MD
ZC
C
N
T
SW FC CS
LDS
fr
fp
16
15
14
13
12
11
10
98
7
6
5
4
3
2
1
(15)
(16)
(1)
(2)
(3)
(4)
(5)
(6) (7)
(8)
(9)
(10)
(11)
(12)
(14)
(13)
: SSOP
( ) : QFN
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MB15E03SL
4. Absolute Maximum Ratings
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
5. Recommended Operating Conditions
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Parameter Symbol Condition Rating Unit Remark
Min. Max.
Power supply voltage VCC —–0.54.0V
VP—VCC 6.0 V
Input voltage VI—–0.5VCC +0.5 V
Output voltage VOExcept Do GND VCC V
VODo GND VPV
Storage temperature Tstg — –55 +125 C
Parameter Symbol Value Unit Remark
Min. Typ. Max.
Power supply voltage VCC 2.4 3.0 3.6 V
VPVCC —5.5V
Input voltage VIGND — VCC V
Operating temperature Ta –40 — +85 C
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6. Electrical Characteristics
(VCC = 2.4 to 3.6 V, Ta = –40 to +85C)
(Continued)
Parameter Symbol Condition Value Unit
Min. Typ. Max.
Power supply current*1ICC VCC = VP = 2.7 V
(VCC = VP = 3.0 V)
—2.0
(2.5)
—mA
Power saving current IPS ZC = “H” or open — 0.1*2 10 A
Operating frequency fin fin — 100 — 1200 MHz
OSCIN fOSC —3—40MHz
Input sensitivity fin*3 Pfin 50system
(Refer to the Measurment circuit.)
–15 — +2 dBm
OSCIN*3 VOSC —0.5—VCC Vp-p
“H” level input voltage Data,
Clock,
LE, PS,
ZC
VIH —VCC 0.7——V
“L” level input voltage VIL — ——VCC0.3
“H” level input current Data,
Clock,
LE, PS
IIH*4 — –1.0 — +1.0 A
“L” level input current IIL*4 — –1.0 — +1.0
“H” level input current OSCIN IIH —0—+100A
“L” level input current IIL*4 — –100 — 0
“H” level input current ZC IIH*4 — –1.0 — +1.0 A
“L” level input current IIL*4 Pull up input –100 — 0
“L” level output voltage PV
OL Open drain output — — 0.4 V
“H” level output voltage R,
LD/fout
VOH VCC = VP = 3 V, IOH = –1 mA VCC – 0.4 — — V
“L” level output voltage VOL VCC = VP = 3 V, IOL = 1 mA——0.4
“H” level output voltage Do VDOH VCC = VP = 3 V, IDOH = –0.5 mA VP – 0.4 — — V
“L” level output voltage VDOL VCC = VP = 3 V, IDOL = 0.5 mA — — 0.4
High impedance cutoff
current
Do IOFF VCC = VP = 3 V,
VOFF = 0.5 V to VP – 0.5 V
——2.5nA
“L” level output current PI
OL Open drain output 1.0 — — mA
“H” level output current R,
LD/fout
IOH — — — –1.0 mA
“L” level output current IOL —1.0——
“H” level output current Do IDOH*4 VCC = 3 V,
VP = 3 V,
VDO = VP/2
Ta = +25C
CS bit = “H” — –6.0 — mA
CS bit = “L” — –1.5 —
“L” level output current IDOL CS bit = “H” — 6.0 —
CS bit = “L” — 1.5 —
Charge pump current rate IDOL/IDOH IDOMT*5 VDD = VP/2 —3 —%
vs VDO IDOVD*6 0.5 V VDO VP – 0.5 V — 10 — %
vs Ta IDOTA*7 – 40C Ta +85C—10—%
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MB15E03SL
(Continued)
*1: Conditions; fin = 1200 MHz, fosc = 12 MHz, Ta = +25C, in locking state.
*2: VCC = VP = 3.0 V, fosc = 12.8 MHz, Ta = +25C, in power saving mode
*3: AC coupling. 1000 pF capacitor is connected under the condition of min. operating frequency.
*4: The symbol “–” (minus) means direction of current flow.
*5: VCC = VP = 3.0 V, Ta = +25C (|I3| – |I4|) / [(|I3| + |I4|) /2] 100(%)
*6: VCC = VP = 3.0 V, Ta = +25C [(|I2| – |I1|) /2] / [(|I1| + |I2|) /2] 100(%) (Applied to each IDOL, IDOH)
*7: VCC = VP = 3.0 V, VDO = VP/2 (|IDO(+85C) – IDO(–40C)| /2) / (|IDO(+85C) + IDO(–40C)| /2) 100(%) (Applied to each IDOL, IDOH)
I1
I1
I3I2
I2I4
IDOL
IDOH
0.5 VP/2
Charge Pump Output Voltage (V)
VP
VP − 0.5
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MB15E03SL
7. Functional Description
7.1 Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M N) + A] fOSC R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 A 127)
fOSC : Output frequency of the reference frequency oscillator
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
M : Preset divide ratio of the dual modulus prescaler (64 or 128)
7.2 Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the pro-
grammable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE pin is taken high, stored data is latched
according to the control bit data as follows:
Table 1. Control Bit
Control Bit (CNT) Destination of Serial Data
HFor the programmable reference divider
LFor the programmable divider
7.2.1 Shift Register Configuration
1 2345678910111213141516171819
CNT R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 SW FC LDS CS
Programmable Reference Counter
MSB
Data Flow
CNT : Control bit [Table 1]
R1 to R14 : Divide ratio setting bit for the programmable reference counter (3 to 16,383) [Table 2]
SW : Divide ratio setting bit for the prescaler (64/65 or 128/129) [Table 5]
FC : Phase control bit for the phase comparator [Table 8]
LDS : LD/fout signal select bit [Table 7]
CS : Charge pump current select bit [Table 6]
Note: Start data input with MSB first.
LSB
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Table 2. Binary 14-bit Programmable Reference Counter
Data Setting
Divide ratio
(R) R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1
3 00000000000011
4 00000000000100
× ××××××××××××××
16383 11111111111111
Note: Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Divide ratio
(N) N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1
3 00000000011
4 00000000100
× ×××××××××××
2047 11111111111
Note: Divide ratio less than 3 is prohibited.
Table 4. Binary 7-bit Swallow Counter Data Setting
Divide ratio
(A) A7 A6 A5 A4 A3 A2 A1
0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 1
× × × × × × × ×
127 1111111
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MB15E03SL
Table 5. Prescaler Data Setting
SW Prescaler Divide Ratio
H64/65
L128/129
Table 6. Charge Pump Current Setting
CS Current Value
H6.0 mA
L1.5 mA
Table 7. LD/fout Output Select Data Setting
LDS LD/fOUT Output Signal
Hfout signal
LLD signal
7.2.2 Relation between the FC Input and Phase Characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level (DO) and the
phase comparator output (R, P) are reversed according to the FC bit. Also, the monitor pin (fout) output is controlled by the FC bit.
The relationship between the FC bit and each of DO, R, and P is shown below.
Table 8. Table 8. FC Bit Data Setting (LDS = “H”)
FC = High FC = Low
DORPLD/fout DORPLD/fout
fr > fp H L L fout = fr L H Z* fout = fp
fr < fp L H Z* H L L
fr = fp Z* LZ* Z* LZ*
*: High impedance
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
(1)
VCO
Output
Frequency
LPF Output Voltage
(2)
■When the LPF and VCO characteristics are similar to
(1), set FC bit high.
■When the VCO characteristics are similar to (2), set FC
bit low.
PLL LPF VCO
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7.3 Do Output Control
Table 9. ZC Pin Setting
ZC pin Do output
HNormal output
LHigh impedance
7.4 Power Saving Mode (Intermittent Mode Control Circuit)
Table 10. Table 10. PS Pin Setting
PS pin Status
HNormal mode
LPower saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Char-
acteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the signal PLL, the lock detector, LD, remains high, indicating a locked condition.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Note:
■When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 s.
■PS pin must be set “L” for Power-ON.
ONOFF
VCC
Clock
Data
LE
PS
(1) (2) (3)
tV ≥ 1 μs
tPS ≥ 100 ns
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 s later after power supply remains stable (VCC 2.2 V).
(3) Release power saving mode (PS: “L” “H”) 100 ns later after setting serial data.
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8. Serial Data Input Timing
Data
Clock
LE
MSB LSB
Control bit Invalid data
2nd data1st data
t
1
t
2
t
3
t
6
t
5
t
4
t
7
∼
∼
∼
∼
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MB15E03SL
9. Phase Comparator Output Waveform
fr
fp
LD
D
O
H
L
L
H
D
O
t
WU
t
WL
Z
Z
Notes:
■Phase error detection range: –2 to +2
■Pulses on Do output signal during locked state are output to prevent dead zone.
■LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL
or less and continues to be so for three cycles or more.
tWU and tWL depend on OSCIN input frequency.
tWU > 2/fosc (s) (e. g. tWU > 156.3 ns, fosc = 12.8 MHz)
tWU < 4/fosc (s) (e. g. tWL < 312.5 ns, fosc = 12.8 MHz)
■LD becomes high during the power saving mode (PS = “L”).
[FC = “H”]
[FC = “L”]
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10. Measurement Circuit (for Measuring Input Sensitivity fin/OSCIN)
S
.G.
50
1000 pF S.G.
50
1000 pF
0.1 F
0.1 F
86431
9101112 14
75 2
13 15 16
1000 pF
VCC
fin Xfin GND DOVCC VPOSCOUT OSCIN
Clock
Controller
(setting divide ratio) Oscilloscope
Data LE PS ZC LD/fout PR
Note: SSOP-16
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MB15E03SL
11. Typical Characteristics
11.1 fin Input Sensitivity
10
0
0 500 1000 1500 2000
-10
-20
-30
-40
-50
Ta = +25 °C
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
Input sensitivity - Input frequency (Prescaler 64/65)
Input frequency fin (MHz)
Input sensitivity Pfin (dBm)
SPEC
11.2 OSCIN Input Sensitivity
VCC = 2.4 V
VCC = 3.0 V
VCC = 3.6 V
0 50 100
Ta = +25 °C
Input sensitivity - Input frequency
Input frequency fOSC (MHz)
10
0
-10
-20
-30
-40
-50
-60
Input sensitivity V
OSC
(dBm)
SPEC
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MB15E03SL
11.3 Do Output Current
10.00
IOH
IOL
2.000
/div
0
0 4.800
.6000/div
− 10.00
VDO − IDO
Charge pump output voltage VDO (V)
Charge pump output current IDO (mA)
Ta = +25 °C
VCC = 3.0 V
VP = 3.0 V
4.800
− 10.00
VDO − IDO
Charge pump output voltage VDO (V)
Charge pump output current IDO (mA)
10.00
IOH
IOL
2.000
/div
0
0.6000/div
Ta = +25 °C
VCC = 3.0 V
VP = 3.0 V
1.5 mA mode
6.0 mA mode
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MB15E03SL
11.4 fin Input Impedance
297.63 Ω
−656.53 Ω
100 MHz
24.523 Ω
−185.55 Ω
400 MHz
9.3789 Ω
−77.168 Ω
800 MHz
10.188 Ω
−33.143 Ω
1.2 GHz
1 :
2 :
3 :
4 :
4
3
2
START 100.000 000 MHz STOP 1 200.000 000 MHz
1
11.5 OSCIN Input Impedance
9.063 kΩ
−3.113 kΩ
3 MHz
3.8225 Ω
−4.6557 kΩ
10 MHz
1.5735 Ω
−3.2154 kΩ
20 MHz
405.69 Ω
−1.8251 kΩ
40 MHz
1 :
2 :
3 :
4 :
3
1
START 3.000 000 MHz STOP 40.000 000 MHz
4
3
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MB15E03SL
12. Reference Information
S.G. OSCIN
fin
VCO
DOLPF
Spectrum
Analyzer
fVCO = 810.425 MHz
KV = 17 MHz/V
fr = 25 kHz
fOSC = 14.4 MHz
exp current: 6.0 mA
4.2 kΩ
47000 pF
9.1 kΩ
4700 pF 1500 pF
VCODo
■LPF
ATTEN
CENTER SPAN 20.00 kHz810.42500 MHz
RBW 100 Hz ** SWPVBW 100 Hz 3.00 s
ΔMKR − 53.00 dB10 dB
RL 2.23 kHz− 5.0 dBm
73.0 dBc/Hz
ATTEN
CENTER SPAN 200.0 kHz810.42500 MHz
RBW 1.0 kHz SWPVBW 1.0 kHz 1.00 s
ΔMKR − 79.83 dB10 dB
RL 25.0 kHz− 5.0 dBm
79.8 dBc
**
Ta = +25C
■PLL Reference Leakage
■PLL Phase Noise
Ta = +25C
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MB15E03SL
(Continued)
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(Continued)
830.00500
MHz
2.00
KHz/div
829.99500
MHz
5.0000000 ms
830.00500
MHz
2.00
KHz/div
829.99500
MHz
5.0000000 ms
850.00500
MHz
10.00000
Hz/div
810.00000
MHz
5.0000000 ms
860.00000
MHz
10.00000
Hz/div
810.00000
MHz
5.0000000 ms
PLL Lock Up Time
810.425 MHz 826.4251 kHz
Lch Hch 1.40 ms
PLL Lock Up Time
826.425 MHz 810.4251 kHz
Hch Lch 1.52 ms
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13. Application Example
VP: 5.5 V Max
Notes:
■In case of using a crystal resonator, it is necessary to optimize matching between the crystal and
this LSI, and perform detailed system evaluation. It is recommended to consult with a supplier of
the crystal resonator. (Reference oscillator circuit provides its own bias, feedback resistor is
100 k (typ).)
■SSOP-16
10 kΩ
0.1 μF
1000 pF
Output
V
P
12 kΩ
12 kΩ
10 kΩ
LPF VCO
16 15 13 12 11 10 9
123 4 56 78
0.1 μF1000 pF
Lock detect.
MB15E03SL
From
a controller
φRφPLD/fout ZC Clock
PS LE Data
OSC
IN
OSC
OUT
V
P
V
CC
D
O
GND Xfin fin
TCXO
1000 pF
14
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14. Usage Precautions
To protect against damage by electrostatic discharge, note the following handling precautions:
■Store and transport devices in conductive containers.
■Use properly grounded workstations, tools, and equipment.
■Turn off power before inserting device into or removing device from a socket.
■Protect leads with a conductive sheet when transporting a board-mounted device.
15. Ordering Information
Part number Package Remarks
MB15E03SLPFV1 16-pin, Plastic SSOP
(FPT-16P-M05)
MB15E03SLWQN 16-pin, Plastic QFN
(LCC-16P-M69)
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MB15E03SL
16. Package Dimensions
16-pin plastic SSOP Lead pitch 0.65 mm
Package width
×
package length
4.40 × 5.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.45mm MAX
Weight 0.07g
Code
(Reference) P-SSOP16-4.4×5.0-0.65
16-pin plastic SSOP
(FPT-16P-M05)
(FPT-16P-M05)
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F16013S-c-4-8
5.00±0.10(.197±.004)
4.40±0.10 6.40±0.20
(.252±.008)(.173±.004)
.049 –.004
+.008
–0.10
+0.20
1.25 (Mounting height)
0.10(.004)
0.65(.026) 0.24±0.08
(.009±.003)
1 8
16 9
"A"
0.10±0.10 (Stand off)
0.17±0.03
(.007±.001)
M
0.13(.005)
(.004±.004)
Details of "A" part
0~8°
(.024±.006)
0.60±0.15
(.020±.008)
0.50±0.20
0.25(.010)
LEAD No.
INDEX
*1
*2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
Document Number: 002-08431 Rev. *A Page 25 of 27
MB15E03SL
16-pin plastic QFN Lead pitch 0.50 mm
Package width ×
package length 4.00 mm × 4.00 mm
Sealing method Plastic mold
Mounting height 0.80 mm MAX
Weight 0.04 g
16-pin plastic QFN
(LCC-16P-M69)
(LCC-16P-M69)
+0.03
–0.02
–.001
+.001
0.02
(.001 )
C
2010 FUJITSU SEMICONDUCTOR LIMITED HMbC16-69Sc-1-1
INDEX AREA
(.157±.004)
4.00±0.10
4.00±0.10
(.157±.004)
2.60±0.10
0.50(.020)
TYP
(.016±.002)
0.40±0.05
1PIN CORNER
(C0.35 (C.014))
0.25±0.05
(.010±.002)
(.030±.002)
0.75±0.05
(0.20(.008))
(.102±.004)
2.60±0.10
(.102±.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Document Number: 002-08431 Rev. *A Page 26 of 27
MB15E03SL
Document History
Document Title: MB15E03SL Single Serial Input PLL Frequency Synthesizer On-chip 1.2 GHz Prescaler
Document Number: 002-08431
Revision ECN Orig. of
Change
Submission
Date Description of Change
** –TAOA 05/31/2012 Initial release.
*A 5562033 TAOA 12/22/2016 Migrated Spansion datasheet “DS04–21359–6E” into Cypress Template.
Document Number: 002-08431 Rev. *A Revised December 22, 2016 Page 27 of 27
MB15E03SL
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