All trademarks mentioned in this document
are trademarks of their respective owners.
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implemen-
tation.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA
bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restric-
tion except One Year license where time of
use is limited to 12 months.
●
○
Single Design license for
VHDL, Verilog source code called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
●
○
●
○
○
●
○
○
One Year license for
Encrypted Netlist only
Unlimited Designs license for
HDL Source
Netlist
Upgrade from
HDL Source to Netlist
Single Design to Unlimited Desi gns
SYMBOL
datai(29:0) datao(29:0)
bus
rd
we
addr(1:0)
trigsel
hyprsel
rotatemode
vectormode
en
rst
clk
PINS DESCRIPTION
PIN TYPE DESCRIPTION
clk Input Global clock
rst Input Global reset
en Input Enable computing
datai[29:0] Input Data bus (input)
we Input Write data into register
rd Input Read data from register
cs Input Chip select
addr[1:0] Input Select register to read/write
rotatemode Input Rotate mode select
vectormode Input Vectoring mode select
hyprsel Input Hyperbolic system select
trigsel Input Trigonometric system select
datao[29:0] Output Data bus (output)
busy Output Busy indicator
BLOCK DIAGRAM
ROM – stores constant coefficients used
for hyperbolic and trigonometric opera-
tions.
Registers – contains all data registers
hold temporary operation results as well
as final results. Input arguments are writ-
ten to this register also.
Control Unit – maintains control opera-
tion on Registers module, Shifters module
and ROM unit, while busy is active.
ROM
Registers
Shifters
Control
unit
cl
rs
e
datai(29:0)
datao(29:0)
addr(1:0)
w
rd
bus
Interface
rotatemod
vectormod
trigsel
hyprsel
Shifters – performs shifting operations in
successful iterations. Number of shifts