K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM Document Title 256Kx36 & 256Kx32 & 512Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. 0.0 0.1 0.2 History Draft Date Remark Initial draft 1. Delete pass- through 1. Add x32 org part and industrial temperature part May. 18 . 2001 June. 26. 2001 Aug. 11. 2001 Preliminary The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM 8Mb SB/SPB Synchronous SRAM Ordering Information Org. Part Number K7A801825B-Q(H)C(I)65/75/85 Mode VDD Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) SB 3.3 6.5/7.5/8.5 ns SPB(2E1D) 3.3 167/138 MHz SPB(2E1D) 3.3 250/225/200 MHz K7A801801B-QC(I)16/14 SPB(2E2D) 3.3 167/138 MHz K7A801808B-QC(I)25/22/20 SPB(2E2D) 3.3 250/225/200 MHz K7A803225B-QC(I)65/75/85 SB 3.3 6.5/7.5/8.5 ns SPB(2E1D) 3.3 167/138 MHz K7A801800B-Q(H)C(I)16/14 512Kx18 K7A801809B-Q(H)C(I)25/22/20 K7A803200B-QC(I)16/14 256Kx32 K7A803209B-QC(I)25/22/20 SPB(2E1D) 3.3 250/225/200 MHz K7A803201B-QC(I)16/14 SPB(2E2D) 3.3 167/138 MHz K7A803208B-QC(I)25/22/20 SPB(2E2D) 3.3 250/225/200 MHz SB 3.3 6.5/7.5/8.5 ns SPB(2E1D) 3.3 167/138 MHz SPB(2E1D) 3.3 250/225/200 MHz K7A803601B-QC(I)16/14 SPB(2E2D) 3.3 167/138 MHz K7A803608B-QC(I)25/22/20 SPB(2E2D) 3.3 250/225/200 MHz K7A803625B-Q(H)C(I)65/75/85 K7A803600B-Q(H)C(I)16/14 256Kx36 K7A803609B-Q(H)C(I)25/22/20 -2- PKG Q: 100TQFP H: 119BGA Temp C: Commercial Temperature Range I: Industrial Temperature Range Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM 256Kx36 & 256Kx32 & 512Kx18-bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION * Synchronous Operation. * 2 Stage Pipelined operation with 4 Burst. * On-Chip Address Counter. * Self-Timed Write Cycle. * On-Chip Address and Control Registers. * 3.3V+0.165V/-0.165V Power Supply. * I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O * 5V Tolerant Inputs Except I/O Pins. * Byte Writable Function. * Global Write Enable Controls a full bus-width write. * Power Down State via ZZ Signal. * LBO Pin allows a choice of either a interleaved burst or a linear burst. * Three Chip Enables for simple depth expansion with No Data Contention only for TQFP ; 2cycle Enable, 1cycle Disable. * Asynchronous Output Enable Control. * ADSP, ADSC, ADV Burst Control Pins. * TTL-Level Three-State Output. * 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package) * Operating in commeical and industrial temperature range. FAST ACCESS TIMES PARAMETER Cycle Time Symbol -16 -14 Unit tCYC 6.0 7.2 ns Clock Access Time tCD 3.5 3.8 ns Output Enable Access Time tOE 3.5 3.8 ns The K7A803600B, K7A803200B and K7A801800B are 9,437,184-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 256K(512K) words of 36/32(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW , LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by G W, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS 1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system s burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7A803600B, K7A803200B and K7A801800B are fabricated using SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP and 119BGA package (100pin TQFP only for K7A803200B). Multiple power and ground pins are utilized to minimize ground bounce. LOGIC BLOCK DIAGRAM CLK LBO BURST CONTROL LOGIC CONTROL REGISTER ADV ADSC 256Kx36/32 , 512Kx18 MEMORY ARRAY A0~A1 A0~A17 or A0~A18 ADSP ADDRESS REGISTER A2~A17 or A2~A18 DATA-IN REGISTER CONTROL REGISTER CS1 CS2 CS2 GW BW WEx (x=a,b,c,d or a,b) BURST ADDRESS A0~A1 COUNTER OUTPUT REGISTER CONTROL LOGIC BUFFER OE ZZ DQa0 ~ DQd 7 or DQa0 ~ DQb7 DQPa ~ DQPd DQPa,DQPb -3- Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM A6 A7 CS 1 CS 2 WEd WEc WEb WEa CS 2 V DD V SS CLK GW BW OE ADSC ADSP ADV A8 A9 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 Pin TQFP (20mm x 14mm) 43 44 45 46 47 48 49 50 A 10 A 11 A 12 A 13 A 14 A 15 A 16 41 V DD A 17 40 V SS 42 39 N.C. N.C. 38 N.C. 35 A2 37 34 A3 A0 33 A4 36 32 A1 31 K7A803600B(256Kx36) /K7A803200B(256Kx32) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO DQPc/NC DQc 0 DQc 1 V DDQ V SSQ DQc 2 DQc 3 DQc 4 DQc 5 V SSQ V DDQ DQc 6 DQc 7 N.C. V DD N.C. V SS DQd 0 DQd 1 V DDQ V SSQ DQd 2 DQd 3 DQd 4 DQd 5 V SSQ V DDQ DQd 6 DQd 7 DQPd/NC 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb7 DQb6 V DDQ V SSQ DQb5 DQb4 DQb3 DQb2 V SSQ V DDQ DQb1 DQb0 V SS N.C. V DD ZZ DQa7 DQa6 V DDQ V SSQ DQa5 DQa4 DQa3 DQa2 V SSQ V DDQ DQa1 DQa0 DQPa/NC PIN NAME SYMBOL A 0 - A 17 PIN NAME TQFP PIN NO. SYMBOL Address Inputs 32,33,34,35,36,37,43 44,45,46,47,48,49,50 81,82,99,100 ADV Burst Address Advance 83 ADSP Address Status Processor 84 ADSC Address Status Controller 85 CLK Clock 89 CS 1 Chip Select 98 CS 2 Chip Select 97 CS 2 Chip Select 92 WE x(x=a,b,c,d) Byte Write Inputs 93,94,95,96 OE Output Enable 86 GW Global Write Enable 88 BW Byte Write Enable 87 ZZ Power Down Input 64 LBO Burst Mode Control 31 PIN NAME TQFP PIN NO. V DD V SS N.C. Power Supply(+3.3V) Ground No Connect 15,41,65,91 17,40,67,90 14,16,38,39,42,66 DQa0~a7 DQb0~b7 DQc0 ~ c7 DQd0~d7 DQPa~P d /NC V DDQ Data Inputs/Outputs 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 Output Power Supply (2.5V or 3.3V) Output Ground 4,11,20,27,54,61,70,77 V SSQ 5,10,21,26,55,60,71,76 Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. 2. The pin 42 is reserved for address bit for the 16Mb . 3. DQPa~DQPd are NC for K7A803200B -4- Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM ADS P ADV A8 A9 83 82 81 49 50 A 16 A 17 ADS C 48 OE 85 A 15 BW 86 84 GW 87 47 CLK 88 A 14 V SS 89 46 V DD 90 A 13 CS 2 91 45 WEa 92 A 12 WEb 93 44 N.C. 94 A 11 N.C. 95 43 CS 2 96 A 18 CS 1 97 42 A7 98 N.C. A6 99 100 Pin TQFP (20mm x 14mm) 31 32 33 34 35 36 37 38 39 40 41 A4 A3 A2 A1 A0 N.C. N.C. V SS V DD K7A801800B(512Kx18) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO N.C. N.C. N.C. V DDQ V SSQ N.C. N.C. DQb0 DQb1 V SSQ V DDQ DQb2 DQb3 N.C. V DD N.C. V SS DQb4 DQb5 V DDQ V SSQ DQb6 DQb7 DQPb N.C. V SSQ V DDQ N.C. N.C. N.C. 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A 10 N.C. N.C. V DDQ V SSQ N.C. DQPa DQa7 DQa6 V SSQ V DDQ DQa5 DQa4 V SS N.C. V DD ZZ DQa3 DQa2 V DDQ V SSQ DQa1 DQa0 N.C. N.C. V SSQ V DDQ N.C. N.C. N.C. PIN NAME SYMBOL PIN NAME A 0 - A 18 Address Inputs ADV ADSP ADSC CLK CS 1 CS 2 CS 2 W Ex OE GW BW ZZ LBO Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control TQFP PIN NO. SYMBOL 32,33,34,35,36,37,43 44,45,46,47,48,49,50 80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 PIN NAME TQFP PIN NO. V DD V SS N.C. Power Supply(+3.3V) Ground No Connect 15,41,65,91 17,40,67,90 1,2,3,6,7,14,16,25,28,29, 30,38,39,42,51,52,53,56, 57,66,75,78,79,95,96 DQa 0 ~ a7 DQb 0 ~ b7 DQPa, Pb V DDQ Data Inputs/Outputs 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 4,11,20,27,54,61,70,77 V SSQ Output Power Supply (2.5V or 3.3V) Output Ground 5,10,21,26,55,60,71,76 Notes : 1. A 0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. 2. The pin 42 is reserved for address bit for the 16Mb . -5- Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM 119BGA PACKAGE PIN CONFIGURATIONS (TOP VIEW) K7A803600B(256Kx36) 1 2 3 4 5 6 7 A V DDQ A A ADSP A A V DDQ B NC CS 2 A ADSC A A NC C NC A A V DD A A NC D DQc DQPc V SS NC V SS DQPb DQb E DQc DQc V SS CS1 V SS DQb DQb F V DDQ DQc V SS OE V SS DQb V DDQ G DQc DQc WEc ADV WEb DQb DQb H DQc DQc V SS GW V SS DQb DQb J V DDQ V DD NC V DD NC V DD V DDQ K DQd DQd V SS CLK V SS DQa DQa L DQd DQd WEd NC WEa DQa DQa M V DDQ DQd V SS BW V SS DQa V DDQ N DQd DQd V SS A 1* V SS DQa DQa P DQd DQPd V SS A 0* V SS DQPa DQa R NC A LBO V DD NC A NC T NC NC A A A NC ZZ U V DDQ TMS TDI TCK TDO NC V DDQ Note : * A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME SYMBOL PIN NAME A A 0,A1 Address Inputs Burst Count Address V DD V SS Power Supply(+3.3V) Ground ADV ADSP ADSC CLK CS 1 CS 2 WE x (x=a,b,c,d) Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Byte Write Inputs N.C. No Connect DQa DQb DQc DQd DQPa~Pd Data Data Data Data Data V DDQ OE GW BW ZZ LBO Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control Output Power Supply (2.5V or 3.3V) TCK TMS TDI TDO JTAG JTAG JTAG JTAG Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outpus Test Clock Test Mode Select Test Data Input Test Data Output -6- Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM 119BGA PACKAGE PIN CONFIGURATIONS (TOP VIEW) K7A801800B(512Kx18) 1 2 3 4 5 6 7 A V DDQ A A ADSP A A V DDQ B NC CS 2 A ADSC A A NC C NC A A V DD A A NC D DQb NC V SS NC V SS DQPa NC E NC DQb V SS CS1 V SS NC DQa F V DDQ NC V SS OE V SS DQa V DDQ G NC DQb WEb ADV V SS NC DQa H DQb NC V SS GW V SS DQa NC J V DDQ V DD NC V DD NC V DD V DDQ K NC DQb V SS CLK V SS NC DQa L DQb NC V SS NC WEa DQa NC M V DDQ DQb V SS BW V SS NC V DDQ N DQb NC V SS A1 * V SS DQa NC P NC DQPb V SS A0 * V SS NC DQa R NC A LBO V DD NC A NC T NC A A NC A A ZZ U V DDQ TMS TDI TCK TDO NC V DDQ Note : * A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME SYMBOL PIN NAME A A 0,A1 Address Inputs Burst Count Address V DD V SS Power Supply(+3.3V) Ground ADV ADSP ADSC CLK CS 1 CS 2 WE x (x=a,b) Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Byte Write Inputs N.C. No Connect DQa DQb DQPa~Pb Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outpus V DDQ Output Power Supply (2.5V or 3.3V) OE GW BW ZZ LBO Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control TCK TMS TDI TDO JTAG JTAG JTAG JTAG Test Test Test Test Clock Mode Select Data Input Data Output -7- Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM FUNCTION DESCRIPTION The K7A803600B, K7A803200B and K7A801800B are synchronous SRAM designed to support the burst address accessing sequence of the Power PC based microprocessor. All inputs (with the exception of OE , LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with O E. In read operation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are carried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to control signals by disabling CS 1. All byte write is done by GW(regaedless of BW and W Ex.), and each byte write is performed by the combination of B W and WEx when GW is high. Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that samples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled Low(regaedless of O E). Data is clocked into the data input register when WE x sampled Low. The address increases internally to the next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte write enable signals(WEa, WE b, WE c or WEd) sampled low. The WEa control DQa 0 ~ DQa7 and DQPa, WEb controls DQb 0 ~ DQb 7 and DQPb, W Ec controls DQc 0 ~ DQc 7 and DQPc, and WEd control DQd0 ~ DQd 7 and DQPd. Read or write cycle may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows; ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC. WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high). Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is selected. BURST SEQUENCE TABLE LBO PIN (Interleaved Burst) Case 1 HIGH A1 0 0 1 1 First Address Fourth Address Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 1 0 0 TABLE A0 1 0 1 0 (Linear Burst) LBO PIN Case 1 LOW Case 2 Case 3 Case 4 A1 A0 A1 A0 A1 A0 A1 A0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 First Address Fourth Address Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed. ASYNCHRONOUS TRUTH TABLE OPERATION ZZ OE I/O STATUS Sleep Mode H X High-Z L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Read Notes 1. X means "Don t Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE , otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time. -8- Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS 1 CS2 CS 2 ADV WRITE CLK ADDRESS ACCESSED OPERATION H X X ADSP ADSC X L X X N/A Not Selected L L X L X X X N/A Not Selected L X H L X X X N/A Not Selected L L X X L X X N/A Not Selected L X H X L X X N/A Not Selected L H L L X X X External Address Begin Burst Read Cycle L H L H L X L External Address Begin Burst Write Cycle L H L H L X H External Address Begin Burst Read Cycle X X X H H L H Next Address Continue Burst Read Cycle H X X X H L H Next Address Continue Burst Read Cycle X X X H H L L Next Address Continue Burst Write Cycle H X X X H L L Next Address Continue Burst Write Cycle X X X H H H H Current Address Suspend Burst Read Cycle H X X X H H H Current Address Suspend Burst Read Cycle X X X H H H L Current Address Suspend Burst Write Cycle H X X X H H L Current Address Suspend Burst Write Cycle NOTE : 1. X means "Dont Care". 2. The rising edge of clock is symbolized by . 3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE ). WRITE TRUTH TABLE(x36/32) GW BW WEa WEb WEc WE d OPERATION H H X X H L H H X X READ H H READ H L L H L H H H H WRITE BYTE a L H H WRITE BYTE b H L H L H H L L WRITE BYTE c and d L L L L WRITE ALL BYTEs L X X X X X WRITE ALL BYTEs Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK() . WRITE TRUTH TABLE(x18) GW BW WEa WEb OPERATION H H X X READ H L H H READ H L L H WRITE BYTE a H L H L WRITE BYTE b H L L L WRITE ALL BYTEs L X X X WRITE ALL BYTEs Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(). -9- Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM ABSOLUTE MAXIMUM RATINGS* SYMBOL RATING UNIT Voltage on V DD Supply Relative to V SS PARAMETER V DD -0.3 to 4.6 V Voltage on V DDQ Supply Relative to V SS V DDQ V DD V Voltage on Input Pin Relative to VSS V IN -0.3 to VDD+0.3 V Voltage on I/O Pin Relative to VSS V IO -0.3 to VDDQ+0.3 V Power Dissipation PD 1.6 W TSTG -65 to 150 C Storage Temperature Operating Temperature Commercial TOPR 0 to 70 C Industrial TOPR -40 to 85 C T BIAS -10 to 85 C Storage Temperature Range Under Bias *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS at 3.3V I/O(0C TA 70C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT V DD 3.135 3.3 3.465 V V DDQ 3.135 3.3 3.465 V V SS 0 0 0 V OPERATING CONDITIONS at 2.5V I/O(0C TA 70C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT V DD 3.135 3.3 3.465 V V DDQ 2.375 2.5 2.9 V V SS 0 0 0 V CAPACITANCE* (TA=25C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION MIN MAX UNIT C IN V IN=0V - 5 pF C OUT V OUT =0V - 7 pF *Note : Sampled not 100% tested. - 10 - Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM DC ELECTRICAL CHARACTERISTICS (VDD =3.3V+0.165V/-0.165V, TA =0C to +70C) PARAMETER SYMBOL TEST CONDITIONS Input Leakage Current(except IIL V DD = Max ; VIN=VSS to V DD Output Leakage Current IOL Output Disabled, VOUT=V SS to V DDQ Operating Current ICC ISB MIN MAX UNIT -2 +2 A A -2 +2 Device Selected, I OUT=0mA, ZZV IL , Cycle Time tCYC Min -16 - 350 -14 - 300 Device deselected, I OUT=0mA, ZZ V IL , -16 - 130 f=Max, All Inputs 0.2V or V DD-0.2V -14 mA 1,2 mA - 120 ISB1 Device deselected, I OUT=0mA, ZZ 0.2V, f = 0, All Inputs=fixed (VDD-0.2V or 0.2V) - 100 mA ISB2 Device deselected, I OUT=0mA, ZZ V DD-0.2V, f=Max, All Inputs V IL or V IH - 50 mA Output Low Voltage(3.3V I/O) V OL IOL =8.0mA - 0.4 V Output High Voltage(3.3V I/O) V OH IOH=-4.0mA 2.4 - V Output Low Voltage(2.5V I/O) V OL IOL =1.0mA - 0.4 V Output High Voltage(2.5V I/O) V OH IOH=-1.0mA Input Low Voltage(3.3V I/O) V IL Input High Voltage(3.3V I/O) Standby Current NOTES 2.0 - V -0.3* 0.8 V V IH 2.0 V DD+0.3** V Input Low Voltage(2.5V I/O) V IL -0.3* 0.7 V Input High Voltage(2.5V I/O) V IH 1.7 V DD+0.3** V 3 3 Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. VIH =VDDQ +0.3V. VIH VSS VS S -1.0V 20% tCYC (MIN) TEST CONDITIONS (VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70C) Parameter Value Input Pulse Level(for 3.3V I/O) 0 to 3.0V Input Pulse Level(for 2.5V I/O) 0 to 2.5V Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) 1.0V/ns Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) 1.0V/ns Input and Output Timing Reference Levels for 3.3V I/O 1.5V Input and Output Timing Reference Levels for 2.5V I/O V DDQ /2 Output Load See Fig. 1 - 11 - Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM Output Load(A) Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O RL=50 Dout Zo=50 30pF* VL=1.5V for 3.3V I/O V DDQ/2 for 2.5V I/O 319 / 1667 Dout 353 / 1538 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS (VDD =3.3V+0.165V/-0.165V, TA=0C to +70C) PARAMETER Symbol -16 MIN -14 MAX MIN MAX UNIT Cycle Time tCYC 6.0 - 7.2 - ns Clock Access Time tCD - 3.5 - 3.8 ns Output Enable to Data Valid tOE - 3.5 - 3.8 ns Clock High to Output Low-Z tLZC 0 - 0 - ns Output Hold from Clock High tOH 1.5 - 1.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 3.0 - 3.5 ns Clock High to Output High-Z tHZC 1.5 3.0 1.5 3.5 ns Clock High Pulse Width tCH 2.3 - 2.5 - ns Clock Low Pulse Width tCL 2.3 - 2.5 - ns Address Setup to Clock High tAS 1.5 - 1.5 - ns Address Status Setup to Clock High tSS 1.5 - 1.5 - ns Data Setup to Clock High tDS 1.5 - 1.5 - ns Write Setup to Clock High (GW , BW , WE X) tWS 1.5 - 1.5 - ns Address Advance Setup to Clock High tADVS 1.5 - 1.5 - ns Chip Select Setup to Clock High tCSS 1.5 - 1.5 - ns Address Hold from Clock High tAH 0.5 - 0.5 - ns Address Status Hold from Clock High tSH 0.5 - 0.5 - ns Data Hold from Clock High tDH 0.5 - 0.5 - ns Write Hold from Clock High (G W, BW, WE X ) tWH 0.5 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.5 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.5 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. - 12 - Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Teat Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected. JTAG Instruction Coding JTAG Block Diagram IR2 SRAM CORE PI PI TDI BYPASS Reg. TDO Identification Reg. Instruction Reg. TDO Output Notes 0 0 SAMPLE-Z Boundary Scan Register 1 0 0 1 IDCODE 2 0 1 0 SAMPLE-Z Boundary Scan Register 1 0 1 1 BYPASS Bypass Register 3 1 0 0 SAMPLE Boundary Scan Register 4 1 0 1 BYPASS Bypass Register 3 1 1 0 BYPASS Bypass Register 3 1 1 1 BYPASS Bypass Register 3 Identification Register NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initiated to VS S when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 4. SAMPLE instruction dose not places DQs in Hi-Z. Control Signals TMS TCK IR1 IR0 Instruction 0 TAP Controller TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test Idle 1 Select DR 0 1 1 1 Exit2 DR 1 Update DR 0 - 13 - Capture IR 0 0 Shift IR 1 1 Exit1 DR 0 Pause DR 1 Select IR 0 1 Capture DR 0 Shift DR 1 1 1 0 0 0 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM SCAN REGISTER DEFINITION Part Instruction Register Bypass Register ID Register Boundary Scan 256Kx36 3 bits 1 bits 32 bits 70 bits 512Kx18 3 bits 1 bits 32 bits 70 bits ID REGISTER DEFINITION Part Revision Number (31:28) Part Configuration (27:18) Vendor Definition (17:12) Samsung JEDEC Code (11: 1) Start Bit(0) 256Kx36 0000 00110 00100 XXXXXX 00001001110 1 512Kx18 0000 00111 00011 XXXXXX 00001001110 1 119BGA BOUNDARY SCAN EXIT ORDER(x36) 119BGA BOUNDARY SCAN EXIT ORDER(x18) 36 4B ADSC OE 4F 35 36 4B ADSC OE 4F 35 37 4E CS 1 ADV 4G 34 37 4E CS 1 ADV 4G 34 38 4H GW CLK 4K 33 38 4H GW CLK 4K 33 39 3G BWc BW 4M 32 39 3G BWb BW 4M 32 40 3C A ADSP 4A 31 40 3C A ADSP 4A 31 41 3B A BWb 5G 30 41 3B A NC 5G 30 42 3A A A 5C 29 42 3A A A 5C 29 43 2B CS2 A 5B 28 43 2B CS2 A 5B 28 44 2C A A 5A 27 44 2C A A 5A 27 45 2A A A 6B 26 45 2A A A 6B 26 46 2D DQPc A 6A 25 46 2D NC A 6A 25 47 1E DQc A 6C 24 47 1E NC A 6C 24 48 2F DQc DQPb 6D 23 48 2F NC NC 7D 23 49 1G DQc DQb 6E 22 49 1G NC NC 6E 22 50 2H DQc DQb 6G 21 50 2H NC NC 6G 21 51 1D DQc DQb 7H 20 51 1D DQb NC 7H 20 52 2E DQc DQb 7D 19 52 2E DQb DQPa 6D 19 53 2G DQc DQb 7E 18 53 2G DQb DQa 7E 18 54 1H DQc DQb 6F 17 54 1H DQb DQa 6F 17 55 2K DQd DQb 7G 16 55 2K DQb DQa 7G 16 56 1L DQd DQb 6H 15 56 1L DQb DQa 6H 15 57 2M DQd DQa 7K 14 57 2M DQb DQa 7K 14 58 1N DQd DQa 6L 13 58 1N DQb DQa 6L 13 59 1P DQd DQa 6N 12 59 2P DQPb DQa 6N 12 60 1K DQd DQa 7P 11 60 1K NC DQa 7P 11 61 2L DQd DQa 6K 10 61 2L NC NC 6K 10 62 2N DQd DQa 7L 9 62 2N NC NC 7L 9 63 2P DQPd DQa 6M 8 63 1P NC NC 6M 8 64 3R LBO DQa 7N 7 64 3R LBO NC 7N 7 65 3L BWd DQPa 6P 6 65 3L NC NC 6P 6 66 2R A ZZ 7T 5 66 2R A ZZ 7T 5 67 3T A A 6R 4 67 3T A A 6R 4 68 4N A1 BWa 5L 3 68 4N A1 BW a 5L 3 69 4P A0 A 5T 2 69 4P A0 A 5T 2 70 2T NC A 4T 1 70 2T A A 4T 1 NOTE : NC ; Don't care. - 14 - Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM JTAG DC OPERATING CONDITIONS Symbol Min Typ Max Unit Power Supply Voltage Parameter V DD 3.135 3.3 3.465 V Input High Level ( 3.3V I/O / 2.5V I/O ) VI H 2.0 / 1.7 - V DD+0.3 V Input Low Level ( 3.3V I/O / 2.5V I/O ) V IL -0.3 - 0.8 / 0.7 V Output High Voltage ( 3.3V I/O / 2.5V I/O ) VO H 2.4 / 2.0 - - V Output Low Voltage ( 3.3V I/O / 2.5V I/O ) V OL - - 0.4 / 0.4 V Note 1 NOTE : The input level of SRAM pin is to follow the SRAM DC specification. 1. In Case of I/O Pins, the Max. VIH =V DDQ+0.3V JTAG AC TEST CONDITIONS Symbol Min Unit Input High/Low Level ( 3.3V I/O / 2.5V I/O ) Parameter V IH/VIL 3.0 / 0 , 2.5 / 0 V Input Rise/Fall Time ( 3.3V I/O / 2.5V I/O ) TR/TF 1.0 / 1.0 , 1.0 /1 .0 ns V DDQ/2 V Input and Output Timing Reference Level Note JTAG AC Characteristics Symbol Min Max Unit TCK Cycle Time Parameter tCHCH 50 - ns TCK High Pulse Width tCHCL 20 - ns TCK Low Pulse Width tCLCH 20 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns SRAM Input Setup Time tSVCH 5 - ns SRAM Input Hold Time tCHSX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns Note JTAG TIMING DIAGRAM TCK tC H C H tC H C L t MVCH t CHMX t DVCH tC H D X t SVCH t CHSX tC L C H TMS TDI PI (SRAM) t CLQV TDO - 15 - Aug 2001 Rev 0.2 - 16 - Data Out OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK tCSS tAS tSS A1 tADVS tCSH tWS tAH tSH Q1-1 A2 tHZOE tSH Q 2-1 tCD tOH Q2-2 A3 Q2-3 (ADV INSERTS WAIT STATE) BURST CONTINUED WITH NEW BASE ADDRESS NO TE S : WRITE = L mea ns GW = L, or GW = H, BW = L, WE x = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L a nd CS 2 = H, or CS 1 = L, and CS 2 = L tLZOE tOE tADVH tWH tSS tCL tCYC tCH TIMING WAVEFORM OF READ CYCLE Q 2-4 Q3-1 Q3-2 Q3-3 Unde fine d Dont Care Q 3-4 tHZC K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM Aug 2001 Rev 0.2 - 17 - Data Out Data In OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK Q 0-3 tCSS tAS tSS Q0-4 A1 tHZOE tCSH tAH tSH D1-1 tCL tCYC tCH A2 D2-1 D2-2 (ADV SUSPENDS BURST) D2-2 D2-3 (ADSC EXTENDED BURST) TIMING WAVEFORM OF WRTE CYCLE D2-4 D3-1 A3 tDS tADVS tWS tSS D3-2 tDH tADVH tWH tSH D3-3 Unde fine d Dont Care D3-4 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM Aug 2001 Rev 0.2 - 18 - Data Out Data In OE ADV CS WRITE ADDRESS ADSP CLOCK tHZC tSS A1 tSH tCD tLZC tAS Q1-1 A2 tWS tCL tHZOE tDS tADVS tAH tCYC tCH D2-1 tDH tADVH tWH A3 tLZOE Q3-1 Q 3-2 tOH Q3-3 TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED , ADSC=HIGH) Undefined Dont Care Q3-4 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM Aug 2001 Rev 0.2 - 19 - Data In Data Out OE ADV CS WRITE ADDRESS ADSC CLOCK tCSS tSS A1 tCSH tSH tOE tLZOE A2 Q1-1 A3 Q 2-1 A4 Q3-1 Q 4-1 tHZOE D5-1 A5 tDS tWS D6-1 A6 tDH tWH D7-1 A7 tCL tWS tCYC tCH A8 tLZOE tWH A9 TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED , ADSP=HIGH) Q8-1 Und efin ed Don t Care Q9-1 tOH K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM Aug 2001 Rev 0.2 - 20 - ZZ Data Out Data In OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK tCSS tAS tSS A1 tCSH tAH tSH tLZOE tOE Q1-1 ZZ Setup Cycle tPDS tHZC Sleep State ZZ Recovery Cycle tPUS tCL tCYC tCH TIMING WAVEFORM OF POWER DOWN CYCLE tWS Normal Operation Mode tHZOE A2 D2-1 tWH Unde fine d Dont Care D2-2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM APPLICATION INFORMATION DEPTH EXPANSION The Samsung 256Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic. I/O [0:71] Data Address A[0:18] A[18] A[0:17] A[18] A[0:17] Address Data CLK CS 2 CS2 CS 2 256Kx36 SPB SRAM CLK Microprocessor Address ADSC CLK CLK ADSC 256Kx36 SPB SRAM WEx WEx (Bank 0) OE Cache Controller Address Data CS2 (Bank 1) OE CS1 CS 1 ADV ADSP ADV ADSP ADS INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH) Clock tSS tSH ADSP tAS ADDRESS [0:n] A1 tAH A2 tWS tWH WRITE tCSS tCSH CS1 Bank 0 is selected by CS2, and Bank 1 deselected by CS 2 An+1 tADVS Bank 0 is deselected by CS2, and Bank 1 selected by CS2 tADVH ADV OE tOE Data Out (Bank 0) tHZC tLZOE Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Data Out (Bank 1) Q2-1 *Notes : n = 14 32K depth , 16 128K depth , 18 512K depth 15 64K depth 17 256K depth Q2-2 Q2-3 Dont Care - 21 - Q2-4 Undefined Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM APPLICATION INFORMATION DEPTH EXPANSION The Samsung 512Kx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic. I/O[0:71] Data Address A[0:19] A[0:18] A[19] A[19] Address Data CLK Address Data CS2 CS2 CS2 Microprocessor CS2 CLK Address 512Kx18 SPB SRAM ADSC CLK WEx CLK 512Kx18 SPB SRAM ADSC WEx (Bank 0) OE Cache Controller A[0:18] (Bank 1) OE CS1 CS1 ADV ADSP ADV ADSP ADS INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH) Clock tSS tSH ADSP tAS ADDRESS [0:n] tAH A1 A2 tWS tWH WRITE tCSS tCSH CS 1 Bank 0 is selected by CS2, and Bank 1 deselected by CS2 A n+1 tADVS Bank 0 is deselected by CS2, and Bank 1 selected by CS2 tADVH ADV OE tOE Data Out (Bank 0) tLZOE tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Data Out (Bank 1) *Notes : n = 14 32K depth , 16 128K depth , 18 512K depth , 15 64K depth 17 256K depth 19 1M depth Q2-1 Q2-2 Undefined - 22 - Q2-3 Q2-4 Dont Care Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM PACKAGE DIMENSIONS 100-TQFP-1420A Units ; millimeters/Inches 0~8 22.00 0.30 20.00 0.20 0.127 16.00 + 0.10 - 0.05 0.30 14.00 0.20 0.10 MAX (0.83) 0.50 #1 0.65 0.10 (0.58) 0.30 0.10 0.10 MAX 1.40 0.50 0.10 - 23 - 0.10 1.60 MAX 0.05 MIN Aug 2001 Rev 0.2 K7A803600B K7A803200B K7A801800B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM 119BGA PACKAGE DIMENSIONS 14.000.10 1.27 1.27 22.000.10 Indicator of Ball(1A) Location 20.500.10 C0.70 C1.00 0.7500.15 1.50REF 0.600.10 0.600.10 12.50 0.10 Notes 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset : 0.10 Max. 3. PCB to Cavity Offset : 0.10 Max. - 24 - Aug 2001 Rev 0.2