FS6477-02 Three-PLL VCXO Programmable Clock Generator IC 1.0 * Features 2.0 3.3 volt operation (contact factory for 5 volt) a * Fully user programmable via I C -bus serial interface * Three high-resolution, low-jitter PLLs optimized for frequency synthesis * Additional multiplier PLL for generation of highfrequency VCXO function from inexpensive fundamental mode crystals 2 Description The FS6477 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. It is especially well suited to digital video/audio systems such as digital set-top boxes. Figure 1: Pin Configuration Six CMOS clock outputs SDA 1 16 * SCL Integrated VCXO circuitry for fine-tuning (typically +/100ppm) output frequencies VDD 2 15 CLK_A * S0 and S1 control inputs can modify device power-up function (see text) VSS 3 14 VDD XIN 4 13 CLK_B XOUT 5 12 CLK_C XTUNE 6 11 VSS CLK_F/S1 7 10 CLK_D CLK_E/S0 8 9 MODE * Custom default frequency patterns, pinouts, and packages are available. Contact your local AMI Sales Representative for more information. FS6477 * 16-pin (0.150") SOIC Figure 2: Block Diagram XIN VCXO + Multiplier PLL A CLK_A XOUT XTUNE PLL B CLK_B Divider Array PLL C CLK_C CLK_D CLK_E/S0 SCL SDA I2C-bus Interface FS6477 ISO9001 Device Control CLK_F/S1 MODE 2.27.02 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC Table 1: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN TYPE NAME 1 U DI O SDA Serial interface data input/output 2 P VDD Power supply (3.3V nominal) 3 P VSS Ground 4 AI XIN 5 AO XOUT DESCRIPTION Voltage-controlled crystal oscillator feedback Voltage-controlled crystal oscillator drive 6 AI XTUNE 7 DIUO CLK_F/S1 "F" clock output / S1 control input 8 DIUO CLK_E/S0 "E" clock output / S0 control input 9 DIU MODE Device MODE select (see text) 10 DO CLK_D "D" clock output 11 P VSS 12 DO CLK_C "C" clock output 13 DO CLK_B "B" clock output 14 P VDD 15 DO CLK_A 16 U DI SCL VCXO control voltage input Ground Power supply (5V to 3.3V) "A" clock output Serial interface clock input 2 2.27.02 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC 3.0 Functional Block Description 3.1 Voltage-Controlled Crystal Oscillator (VCXO) and Multiplier EXAMPLE: A crystal with the following parameters is used. With C1 = 0.02pF, C0 = 6pF, CL1 = 10pF, and CL2 = 20pF, the tuning range (peak-to-peak) is f = 3.1.1 VCXO The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6477 system components. Load capacitors are internal to the FS6477. No external components (other than the crystal itself) are required for operation of the VCXO. Continuous fine-tuning of the VCXO frequency is accomplished by varying the voltage on the XTUNE pin. 3.1.2 Multiplier A simple Phase-Locked Loop multiplies the output frequency of the VCXO by eight for use by the programmable PLLs and Post Dividers. See below for a description of PLL operation. 3.2 Figure 3: Typical VCXO Characteristic Phase Locked Loops As shown in Figure 4, each PLL consists of a Reference Divider, a Phase-Frequency Detector (PFD), a charge pump, an internal Loop Filter, a Voltage-Controlled Oscillator (VCO), and a Feedback Divider. This is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired frequency by a ratio of integers. This frequency multiplication is exact. VCXO Deviation vs. XTUNE Input (typical) 250 200 150 Deviation - ppm 0.025 x (20 - 10) x 106 = 300 ppm . 2 x (6 + 20) x (6 + 10 ) 100 50 0 0 0.5 1 1.5 2 2.5 3 -50 Figure 4: PLL Diagram -100 -150 LFTC -200 V(XTUNE) - volts Loop Filter REFDIV[7:0] CP fREF Reference Divider The oscillator operates the crystal resonator in the parallel-resonant mode. "Pulling" of the crystal oscillation frequency is accomplished by altering the effective load capacitance presented to the crystal. The actual amount that changing the load capacitance alters the oscillator frequency will depend on the characteristics of the crystal as well as the oscillator circuit itself. Specifically, the motional capacitance of the crystal (usually referred to by crystal manufacturers as C1), the static capacitance of the crystal (C0), and the load capacitance (CL) of the oscillator determine the "pulling" capability of the crystal in the oscillator circuit. A simple formula to obtain the peak-to-peak "pulling" capability of a crystal oscillator is: f ( ppm) = (NR) PhaseFrequency Detector UP Charge Pump DOWN Voltage Controlled Oscillator fVCO FBKDIV[10:0] Feedback Divider (NF) The PFD compares the two frequencies at its input and will drive the VCO to run faster (or slower) until both frequencies are equal. When this condition has been met: ae f VCO cc e NF C1 x (C L 2 - C L1) x 10 2 x (C 0 + C L 2 ) x (C 0 + C L1) 6 o ae f REF // = cc o e NR o // . o where CL1 and CL2 are the two extremes of the applied load capacitance. 3 2.27.02 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC which can be re-arranged: aeN f VCO = f REF cc F e NR The modulus of the overall combination is controlled by the appropriate register bits (see Table 7). The Post Divider performs some useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the output frequencies that are needed in many applications. Second, the extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly. It changes the overall device frequency equation to: o // . o 3.2.1 Reference Divider The Reference Divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-down frequency to the PFD. The Reference Divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h. aeN f CLK = f REF cc F e NR 3.3 FBKDIV[2:0] FBKDIV[10:3] 010 011 100 101 110 111 00000001 8 9 - - - - - - 00000010 16 17 18 - - - - - 00000011 24 25 26 27 - - - - 00000100 32 33 34 35 36 - - - 00000101 40 41 42 43 44 45 - - 00000110 48 49 50 51 52 53 54 - 00000111 56 57 58 59 60 61 62 63 Device Control Overview The FS6477 contains an internal ROM that holds four different device configurations. When the MODE pin is LOW, the bi-directional pins (CLK_E/S0 and CLK_F/S1) are made to be INPUTS and the voltage levels applied to those pins select which one of those four states is made active. When the MODE pin is taken HIGH, the levels on those pins are latched, and both bi-directional pins are made to be OUTPUTS. Any desired new configuration can be loaded into the registers via the I2C interface at any time. The configuration will not become applied to the PLLs or Post Dividers until the appropriate SWAP bits have been set to a "1". Table 2: Feedback Modulus Below 56 001 o // o Note that a nominal 50/50 duty factor is always preserved (even for selections which have an odd modulus). 3.2.2 Feedback Divider The Feedback Divider is based on a dual-modulus divider (also called dual-modulus prescaler) technique. It permits division by any integer value between 56 and 2047. Selected values below 56 are also permitted (see Table). 000 oae 1 //cc oe N P FEEDBACK DIVIDER MODULUS 3.2.3 Post Divider The Post Divider is actually constructed of a cascade of three programmable dividers, as shown in Figure 5. Figure 5: Post Divider Control ROM POSTCTL_x [3:0] fIN Post Divider 1 Post Divider 2 Post Divider 3 fOUT POST DIVIDER (NP) 4 2.27.02 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC Table 3: Programmable Register Map Note: All programmable registers are cleared (set to "0") on power-up. REGISTER FUNCTION BANK BIT7 (MSB) BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 (LSB) 0 SWAP N/A SWAP_7 SWAP_6 SWAP_5 SWAP_4 SWAP_3 SWAP_2 SWAP_1 SWAP_0 1 REFDIV_A[7:0] 2 PLLA FBKDIV_A[7:0] 0 3 PLLPD_A PLLSRC_ A 4 LFTC_A CP_A FBKDIV_A[10:8] REFDIV_B[7:0] 5 PLLB FBKDIV_B[7:0] 1 6 PLLPD_B PLLSRC_ B 7 LFTC_B CP_B FBKDIV_B[10:8] REFDIV_C[7:0] 8 PLLC FBKDIV_C[7:0] 2 9 PLLPD_C PLLSRC_ C LFTC_C CP_C FBKDIV_C[10:8] 10 POSTDIVA 3 POSTPD_ A POSTSRC_A[1:0] POSTCTL_A[3:0] 11 POSTDIVB 4 POSTPD_ B POSTSRC_B[1:0] POSTCTL_B[3:0] 12 POSTDIVC 5 POSTPD_ C POSTSRC_C[1:0] POSTCTL_C[3:0] 13 POSTDIVD 6 POSTPD_ D POSTSRC_D[1:0] POSTCTL_D[3:0] 14 7 15 OUTPUT RESERV ED RESERV ED RESERV ED RESERV ED RESERV ED RESERV ED CLKCTL _F CLKCTL _E CLKCTL _D CLKCTL _C CLKCTL _B CLKCTL _A Table 4: Device Default Frequencies FS6477-02 A frequencies assume 13.5MHz reference (10MHz < F_REF < 15MHz) S1 S0 F(CLK_A) F(CLK_B) F(CLK_C) F(CLK_D) 0 0 13.50000 13.50000 13.50000 27.00000 0 1 18.00000 18.00000 18.00000 27.00000 1 0 27.00000 27.00000 27.00000 27.00000 1 1 54.00000 54.00000 54.00000 27.00000 ISO9001 F(CLK_E) F(CLK_F) Always = F(CLK_D) Always = F(CLK_D) FS6477-02 Three-PLL VCXO Programmable Clock Generator IC Table 5: Swap Bits NAME Table 7: Post-Divider Control Bits DESCRIPTION NAME DESCRIPTION SWAP_0 Enable PLL_A Control Bits SWAP_1 Enable PLL_B Control Bits Value Divide-by SWAP_2 Enable PLL_C Control Bits [0000] 1 SWAP_3 Enable POSTDIV_A Control Bits [0001] 2 SWAP_4 Enable POSTDIV_B Control Bits [0010] 3 SWAP_5 Enable POSTDIV_C Control Bits [0011] 4 SWAP_6 Enable POSTDIV_D Control Bits [0100] 5 SWAP_7 Enable Output Control Bits [0101] 6 [0110] 8 [0111] 9 [1000] 10 [1001] 12 [1010] 15 FeedBacK DIVider x [1011] 16 FBKDIV_A[2:0] A-Counter Value [1100] 18 FBKDIV_A[10:3] M-Counter Value POSTCTL_x[3:0] Table 6: PLL Control Bits NAME REFDIV_x [7:0] FBKDIV_x [10:0] CP_x POST-divider ConTroL x DESCRIPTION REFerence DIVider x [1101] 20 Charge Pump x control [1110] 25 Bit = 0 [1111] 50 Bit = 1 POST-divider SouRCe x Loop Filter Time Constant x LFTC_x Crystal Oscillator (x = A, B, or C) Bit = 0 [00] Bit = 1 PLL_M (x = D) POSTSRC_x[3:0] PLL reference SouRCe x PLLSRC_x Bit = 0 Crystal Oscillator Bit = 1 Mulltiplier PLL (Crystal Oscillator x 8) PLL Power-Down x PLLPD_x Bit = 0 PLL Operates Bit = 1 PLL Powered-Down (Output STOPPED) [01] PLL_A [10] PLL_B [11] PLL_C POST-divider Power-Down x POSTPD_x Bit = 0 Post-Divider Operates Bit = 1 Post-Divider Powered Down (Output STOPPED) Table 8: Output Control Bits NAME DESCRIPTION ClocK ConTroL x CLKCTL_x A ISO9001 Bit = 0 Output STOPPED Bit = 1 Output RUNS FS6477-02 Three-PLL VCXO Programmable Clock Generator IC 7 2.27.02 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC 4.0 bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first sixteen bytes will overflow into the first register, then the second, and so on, in a first-in, firstoverwritten fashion. I2C-bus Control Interface This device is a read/write slave device 2 meeting all Philips I C-bus specifications except a "general call." The bus has to be controlled by a master device that generates the serial clock SCL, controls bus access, and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. 2 I C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS). 4.1 4.1.5 Acknowledge When addressed, the receiving device is required to generate an Acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the Acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. The master must signal an end of data to the slave by not generating and acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition. Bus Conditions Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition. The following bus conditions are defined 2 by the I C-bus protocol. 4.2 I2C-bus Operation All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital inter2 face. The device accepts the following I C-bus commands. 4.1.1 Not Busy Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy. 4.2.1 Slave Address After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the device is: 4.1.2 START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition. A6 A5 A4 A3 A2 A1 A0 1 0 1 1 1 0 0 4.2.2 Random Register Write Procedure Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. 4.1.3 STOP Data Transfer A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition. 4.1.4 Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit. Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data 8 2.27.02 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC is more efficient than the Random Register Read if several registers must be read. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the Register Write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all sixteen bytes of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition. If either a STOP or a repeated START condition occurs during a Register Write, the data that has been transferred is ignored. 4.2.3 Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the Register Write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not acknowledge the transfer but does generate a STOP condition. 4.2.4 Sequential Register Write Procedure Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the Random Register Write if several registers must be written. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to sixteen bytes of data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur. Registers are therefore updated at different times during a Sequential Register Write. 4.2.5 Sequential Register Read Procedure Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure 9 2.27.02 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC Figure 6: Random Register Write Procedure S DEVICE ADDRESS W A 7-bit Receive Device Address REGISTER ADDRESS A Register Address A P Data Acknowledge START Command DATA Acknowledge STOP Condition WRITE Command From bus host to device Acknowledge From device to bus host Figure 7: Random Register Read Procedure S DEVICE ADDRESS W A 7-bit Receive Device Address REGISTER ADDRESS A S DATA A P Data Acknowledge Repeat START WRITE Command From bus host to device R A 7-bit Receive Device Address Register Address Acknowledge START Command DEVICE ADDRESS Acknowledge STOP Condition READ Command NO Acknowledge From device to bus host Figure 8: Sequential Register Write Procedure S DEVICE ADDRESS W A 7-bit Receive Device Address REGISTER ADDRESS DATA Register Address Acknowledge START Command A A DATA DATA Data Data Acknowledge A Acknowledge Data Acknowledge WRITE Command From bus host to device A P Acknowledge STOP Command From device to bus host Figure 9: Sequential Register Read Procedure S DEVICE ADDRESS 7-bit Receive Device Address W A REGISTER ADDRESS Register Address Acknowledge START Command WRITE Command From bus host to device A ISO9001 A S DEVICE ADDRESS 7-bit Receive Device Address Repeat START Acknowledge From device to bus host R A DATA A DATA Data Acknowledge READ Command A P Data Acknowledge NO Acknowledge STOP Command FS6477-02 Three-PLL VCXO Programmable Clock Generator IC 5.0 Electrical Specifications Table 9: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER Supply Voltage, dc (VSS = ground) SYMBOL MIN. MAX. UNITS VDD VSS-0.5 7 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 C Ambient Temperature Range, Under Bias TA -55 125 C Junction Temperature TJ 150 C Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 260 C 2 kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 10: Operating Conditions PARAMETER A SYMBOL Supply Voltage VDD Ambient Operating Temperature Range TA ISO9001 CONDITIONS/DESCRIPTION 3.3V 10% MIN. TYP. MAX. UNITS 3 3.3 3.6 V 70 C 0 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC Table 11: DC Electrical Specifications Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Supply Current, Dynamic, Un-Loaded Outputs * IDD mA Supply Current, Dynamic, Loaded Outputs * IDD mA Supply Current, Fully Powered Down IDDL Overall All POSTPD_x and PLLPD_x = 1 mA Serial Interface I/O (SCL, SDA) High-Level Input Voltage VIH VDD*0.75 VDD+0.3 V Low-Level Input Voltage VIL VSS-0.3 VDD*0.25 V Hysteresis Voltage Vhys High-Level Input Current VDD*0.33 IIH Low-Level Input Current IIL Low-Level Output Sink Current (SDA) IOL -1 1 -1 VOL = 0.4V, VDD = 3.0V V 1 A A VDD*0.5 mA 100 K VDD*0.5 V XTUNE Input Equivalent Input Impedance RXTUNE Equivalent Input Termination Clock Outputs (CLK_x) High-Level Output Source Current IOH mA Low-Level Output Sink Current IOL mA Output Impedance A zOH zOL Short Circuit Source Current * ISCH mA Short Circuit Sink Current * ISCL mA ISO9001 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC Table 12: AC Timing Specifications Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS 15 MHz Voltage-Controlled Crystal Oscillator (VCXO) Crystal Frequency 10 Crystal Load Capacitance At center frequency 14 pF VCXO Minimum Capacitance Typical @ VXTUNE = 0V 9 pF VCXO Maximum Capacitance Typical @ VXTUNE = 3V 20 pF Phase-Locked Loops Output Frequency VCO Frequency fO 40 fVCO 135 MHz 230 MHz Clock Outputs (CLK_x) Duty Cycle (when supplied by PLL) * Ratio of pulse width (as measured from rising edge to next falling edge at VDD*0.5) to one clock period 45 50 55 % Duty Cycle (when supplied by VCXO) * Ratio of pulse width (as measured from rising edge to next falling edge at VDD*0.5) to one clock period 40 50 60 % Rise Time * tr VO = 0.3V to 3.0V; CL = 10pF ns Fall Time * tf VO = 3.0V to 0.3V; CL = 10pF ns Jitter, Long Term (y()) (when supplied by PLL) * tj(LT) ps Jitter, Long Term (y()) (when supplied by VCXO) * tj(LT) ps Jitter, Period (peak-peak) (when supplied by PLL) * tj(P) ps Jitter, Period (peak-peak) (when supplied by VCXO) * tj(P) ps 13 2.27.02 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC Table 13: Serial Interface Timing Specifications Unless otherwise stated, all power supplies = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION SCL STANDARD MODE MIN. MAX. 0 100 UNITS Clock frequency fSCL Bus free time between STOP and START tBUF 4.7 kHz s Set up time, START (repeated) tsu:STA 4.7 s Hold time, START thd:STA 4.0 s Set up time, data input tsu:DAT SDA 250 ns Hold time, data input thd:DAT SDA 0 s Output data valid from clock tAA Minimum delay to bridge undefined region of the falling edge of SCL to avoid unintended START or STOP Rise time, data and clock tR SDA, SCL Fall time, data and clock tF SDA, SCL High time, clock tHI SCL tLO SCL Low time, clock Set up time, STOP tsu:STO 3.5 s 1000 ns 300 ns 4.0 s 4.7 s 4.0 s Figure 10: Bus Timing Data ~ ~ SCL ~ ~ thd:STA tsu:STA tsu:STO SDA ~ ~ ADDRESS OR DATA VALID START DATA CAN CHANGE STOP Figure 11: Data Transfer Sequence tHI SCL tR ~ ~ tF tLO tsu:STA thd:STA tAA tAA ~ ~ SDA IN tsu:DAT tsu:STO ~ ~ thd:DAT tBUF SDA OUT 14 2.27.02 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC 6.0 Package Information Table 14: 16-pin SOIC (0.150") Package Dimensions DIMENSIONS INCHES 16 MILLIMETERS MIN. MAX. MIN. MAX. A 0.061 0.068 1.55 1.73 A1 0.004 0.0098 0.102 0.249 A2 0.055 0.061 1.40 1.55 R B 0.013 0.019 0.33 0.49 C 0.0075 0.0098 0.191 0.249 D 0.386 0.393 9.80 9.98 E 0.150 0.157 3.81 3.99 e 0.050 BSC E 1 ALL RADII: 0.005" TO 0.01" B 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 0 8 0 8 h x 45 7 typ. e 1.27 BSC H H AMERICAN MICROSYSTEMS, INC. A2 D A A1 BASE PLANE C L SEATING PLANE Table 15: 16-pin SOIC (0.150") Package Characteristics PARAMETER SYMBOL Thermal Impedance, Junction to Free-Air 16-pin 0.150" SOIC JA Lead Inductance, Self L11 CONDITIONS/DESCRIPTION TYP. UNITS Air flow = 0 m/s 95 C/W Corner lead 4.0 Center lead 3.0 nH Lead Inductance, Mutual L12 Any lead to any adjacent lead 0.4 nH Lead Capacitance, Bulk C11 Any lead to VSS 0.5 pF A ISO9001 FS6477-02 Three-PLL VCXO Programmable Clock Generator IC 7.0 Ordering Information ORDERING CODE DEVICE NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION 11825-804 FS6477-02 16-pin (0.150") SOIC (Small Outline Package) 0C to 70C (Commercial) Tape and Reel 11825-814 FS6477-02 16-pin (0.150") SOIC (Small Outline Package) 0C to 70C (Commercial) Tubes Copyright (c) 1999, 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com 16 2.27.02