2.27.02
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or ICThree-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or IC
ISO9001
ISO9001ISO9001
ISO9001
1.0 Features
• 3.3 volt operation (contact factory for 5 volt)
• Fully user program mable via I2Cä-bus serial interface
• Three high-resolution, low-jitter PLLs optimized for
frequency synthesis
• Additional multiplier PLL for generation of high-
frequency VCXO function from inexpensive funda-
mental mode cry stals
• Six CMOS clock outputs
• Integrated VCXO circuitry for fine-tuning (typically +/-
100ppm) output frequencies
• S0 and S1 control inputs can modify device power-up
function (see text)
• Custom default frequency patterns, pinouts, and
packages are available. Contact your local AMI Sales
Representative for more information.
2.0 Description
The FS6477 is a CMOS clock generator IC designed to
minimize cost and component count in a variety of elec-
tronic systems. It is especially well suited to digital
video/audio systems such as digital set-top boxes.
Figure 1: Pin Configuration
116
2
3
4
5
6
7
8
15
14
13
12
11
10
9
SDA
VDD
VSS
XIN
XOUT
XTUNE
CLK_F/S1
CLK_E/S0 MODE
CLK_D
VSS
CLK_C
CLK_B
VDD
CLK_A
SCL
FS6477
16-pin (0.150”) SOIC
Figure 2: Block Diagram
Divider
A
rra
y
Device
Control
FS6477
VCXO +
Multiplier
XOUT
XIN PLL A
PLL B
PLL C
CLK_A
CLK_B
CLK_C
CLK_D
XTUNE
CLK_E/S0
CLK_F/S1
I2C-bus
Interface
SCL
SDA
MODE
22.27.02
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL VCXO Programmable Clock Generator IC
Three-PLL VCXO Programmable Clock Generator ICThree-PLL VCXO Programmable Clock Generator IC
Three-PLL VCXO Programmable Clock Generator IC
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN TYPE NAME DESCRIPTION
1DI
UO SDA Serial interf ace data input/output
2 P VDD Power supply (3.3V nominal )
3 P VSS Ground
4 AI XIN Voltage-controlled crystal oscillator feedback
5 AO XOUT Voltage-controlled crystal oscillator drive
6 AI XTUNE VCXO control volt age input
7DI
UO CLK_F/S1 “F” clock output / S1 control input
8DI
UO C LK_E/S0 “E” clock output / S0 control input
9DI
UMODE Device MODE select (see text)
10 DO CLK_D “D” clock output
11 P VSS Ground
12 DO CLK_C “C” clock output
13 DO CLK_B “B” cl ock out put
14 P VDD Power supply (5V t o 3.3V)
15 DO CLK_A “A” cl ock out put
16 DIUSCL Serial interface clock input
32.27.02
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL V CXO Pro
g
rammable Cloc k Generator IC
Three-PLL V CXO Pro
g
rammable Cloc k Generator ICThree-PLL VCXO Pro
g
rammable Cloc k Generator IC
Three-PLL V CXO Pro
g
rammable Cloc k Generator IC
3.0 Functional Bl ock Descripti on
3.1 Voltage-Controlled Crystal
Oscillator (VCXO) and Multiplier
3.1.1 VCXO
The VCXO provides a tunable, low-jitter frequency refer-
ence for the rest of the FS6477 system components.
Load capacitors are internal to the FS6477. No external
components (other than the crystal itself) are required f or
operation of the VCXO.
Continuous fine-tuning of the VCXO frequency is accom-
plished by varying the voltage on the XTUNE pin.
Figure 3: Typical VCXO Characteristic
VCXO Devi ation vs. XTUNE I nput (t ypi cal )
-200
-150
-100
-50
0
50
100
150
200
250
00.511.522.53
V(XTUNE) - volts
Deviation - ppm
The oscillator operates the crystal resonator in the paral-
lel-resonant mode. “Pulling” of the crystal oscillation fre-
quency is accomplished by altering the effective load ca-
pacitance presented to the crystal. The actual amount
that changing the load capacitance alters the oscillator
frequenc y will d epend on the c harac teristic s of the cr ystal
as well as the oscillator circuit itself.
Specifically, the m otional capacitance of the crystal (usu-
ally referr ed to by cr ystal m anufacturer s as C1), the st atic
capacitance of the crystal (C0), and the load capacitance
(CL) of the oscillator determine the “pulling” capability of
the crystal in the oscillator circuit.
A simple formula to obtain the peak-to-peak “pulling” ca-
pability of a crystal oscillator is:
()
()()
CCCC CCC
ppmf LL
LL
1020
6
121
210
)( +×+× ×−×
=∆
where CL1 and CL2 are the two extremes of the applied
load capacitance.
EXAMPLE: A crystal with the following parameters is
used. With C 1 = 0.02 pF, C0 = 6pF , CL1 = 10pF, a nd CL2 =
20pF, the tuning range (peak-to-peak) is
()
()()
ppm
.
f300
1062062 106
10200250 =
+×+× ×−×
=∆ .
3.1.2 Multiplier
A simple Phase-Locked Loop multiplies the output fre-
quency of the VCXO b y eight f or use by the programma-
ble PLLs and Post Dividers. See below for a description
of PLL operation.
3.2 Phase Locked Loops
As shown in Figure 4, each PLL consists of a Reference
Divider, a Phase-Frequency Detector (PFD), a charge
pump, an internal Loop Filter, a Voltage-Controlled Os-
cillator (VCO), and a Feedback Divider.
This is a standard phase- and frequency-locked loop ar-
chitecture that multiplies a reference frequency to a de-
sired frequency by a ratio of integers. This frequency
multiplication is exact.
Figure 4: PLL Diagram
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider
(N
F
)
Loop
Filter
REFDIV[7:0]
FBKDIV[10:0]
LFTC
CP
f
REF
f
VCO
Voltage
Controlled
Oscillator
The PFD compares the two frequencies at its input and
will driv e the VCO to ru n faster (or slower) until both fre-
quencies are equal. When this condition has been met:
÷
÷
ø
ö
ç
ç
è
æ
=
÷
÷
ø
ö
ç
ç
è
æ
R
REF
F
VCO N
f
N
f.
42.27.02
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL VCXO Programmable Clock Generator IC
Three-PLL VCXO Programmable Clock Generator ICThree-PLL VCXO Programmable Clock Generator IC
Three-PLL VCXO Programmable Clock Generator IC
which can be re-arranged:
÷
÷
ø
ö
ç
ç
è
æ
=R
F
REFVCO N
N
ff .
3.2.1 Reference Divider
The Reference Divider is designed for low phase jitter.
The divider accepts the output of the reference oscillator
and provides a divided-down frequency to the PFD. The
Reference Divider is an 8-bit divider, and can be pro-
gramm ed for any modulus fr om 1 to 255 by progr amm ing
the equivalent binary value. A divide-by-256 can also be
achieved by programming the eight bits to 00h.
3.2.2 Feedback Divider
The Feedback Divider is based o n a dual-m odulus d ivid er
(also called dual-modulus prescaler) technique. It per-
mits division by any integer value between 56 and 2047.
Selected values below 56 are also permitted (see Table).
Table 2: Feedback Modulus Below 56
FBKDIV[2:0]
FBKDIV[10:3] 000 001 010 011 100 101 110 111
00000001 89------
00000010 161718-----
00000011 24252627----
00000100 32 33 34 35 36 - - -
00000101 40 41 42 43 44 45 - -
00000110 48 49 50 51 52 53 54 -
00000111 56 57 58 59 60 61 62 63
FEEDBACK DIVIDE R MODUL US
3.2.3 Post Divider
The Post Divider is actually constructed of a cascade of
three programmable dividers, as shown in Figure 5.
Figure 5: Post Divider
Post
Divider 1 Post
Divider 2 Post
Div ider 3
POSTCTL_x [3:0]
POST DIVIDER (N
P
)
Control RO M
f
IN
f
OUT
The modulus of the overall combination is controlled by
the appropriate register bits (see Table 7).
The Post Divider performs some usef ul functions. First, it
allows the VCO to be operated in a narrower range of
speeds compared to the output frequencies that are
needed in man y applic at io ns . S ec ond, the ex tra integer in
the denominator permits more flexibility in the program-
ming of the lo op for m any appl ications where fr equencies
must be achieved exactly. It changes the overall device
frequency equation to:
÷
÷
ø
ö
ç
ç
è
æ
÷
÷
ø
ö
ç
ç
è
æ
=PR
F
REFCLK NN
N
ff 1
Note that a n ominal 50/50 duty factor is al wa ys pr es erved
(even for selections which have an odd modulus).
3.3 Device Control Overview
The FS6477 contains an internal ROM that holds four
different device configurations. When the MODE pin is
LOW, the bi-directional pins (CLK_E/S0 and CLK_F/S1)
are made to be IN PUTS and the volt age leve ls appl ied to
those pins select which one of those four states is made
active.
When the MODE pin is taken HIGH, the levels on those
pins are latched , and both b i-directiona l pins are m ade to
be OUTPUTS.
Any desired new configuration can be loaded into the
registers via the I2C interface at any time. The configu-
ration will not become applied to the PLLs or Post Divid-
ers until the appropriate SWAP bits have been set to a
“1”.
A
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or ICThree-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or IC
ISO9001
ISO9001ISO9001
ISO9001
Table 3: Programmable Register Map
Note: All programmable registers are cleared (set to “0”) on power-up.
REGISTER FUNCTION BANK BIT7
(MSB) BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
(LSB)
0SWAP N/A SWAP_7 SWAP_6 SWAP_5 SWAP_4 SWAP_3 SWAP_2 SWAP_1 SWAP_0
1REFDIV_A[7:0]
2FBKDIV_A[7:0]
3
PLLA 0
PLLPD_A PLLSRC_
ALFTC_A CP_A FBKDIV_A[10:8]
4REFDIV_B[7:0]
5FBKDIV_B[7:0]
6
PLLB 1
PLLPD_B PLLSRC_
BLFTC_B CP_B FBKDIV_B[10:8]
7REFDIV_C[7:0]
8FBKDIV_C[7:0]
9
PLLC 2
PLLPD_C PLLSRC_
CLFTC_C CP_C FBKDIV_C[10:8]
10 POSTDIVA 3 POSTPD_
APOSTSRC_A[1:0] POSTCTL_A[3:0]
11 POSTDIVB 4 POSTPD_
BPOSTSRC_B[1:0] POSTCTL_B[3:0]
12 POSTDIVC 5 POSTPD_
CPOSTSRC_C[1:0] POSTCTL_C[3:0]
13 POSTDIVD 6 POSTPD_
DPOSTSRC_D[1:0] POSTCTL_D[3:0]
14 RESERV
ED RESERV
ED RESERV
ED RESERV
ED RESERV
ED RESERV
ED
15 OUTPUT 7CLKCTL
_F CLKCTL
_E CLKCTL
_D CLKCTL
_C CLKCTL
_B CLKCTL
_A
Table 4: Device Default Frequencies
FS6477-02 frequencies assume 13.5MHz reference (10MHz < F_REF < 15MHz)
S1 S0 F(CLK_A) F(CLK_B) F(CLK_C) F(CLK_D) F(CLK_E) F(CLK_F)
00 13.50000 13.50000 13.50000 27.00000
01 18.00000 18.00000 18.00000 27.00000
10 27.00000 27.00000 27.00000 27.00000
11 54.00000 54.00000 54.00000 27.00000
Always =
F(CLK_D) Always =
F(CLK_D)
A
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or ICThree-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or IC
ISO9001
ISO9001ISO9001
ISO9001
Table 5: Swap Bits
NAME DESCRIPTION
SWAP_0 Enable PLL_A Control Bits
SWAP_1 Enabl e PLL_ B Contro l Bits
SWAP_2 Enabl e PLL_ C Contro l Bits
SWAP_3 Enable POSTDIV_A Control Bits
SWAP_4 Enable POSTDIV_B Control Bits
SWAP_5 Enable POSTDIV_C Control Bits
SWAP_6 Enable POSTDIV_D Control Bits
SWAP_7 Enable Output Control Bits
Table 6: PLL Control Bits
NAME DESCRIPTION
REFDIV_x
[7:0] REFerence DIVider x
FeedBacK DIVider x
FBKDIV_A[2:0] A-Counter Val ue
FBKDIV_x
[10:0] FBK DIV_A[10:3] M-Counter Value
Charge Pump x control
Bit = 0
CP_x
Bit = 1
Loop Filter Time Constant x
Bit = 0
LFTC_x
Bit = 1
PLL reference SouRCe x
Bit = 0 Crystal Oscillator
PLLSRC_x
Bit = 1 Mulltiplier PLL
(Crystal Oscillator x 8)
PLL Power-Down x
Bit = 0 P LL Operat es
PLLPD_x
Bit = 1 PLL Powered-Down
(Output STOPPED)
Table 7: Post-Divider Control Bits
NAME DESCRIPTION
POST-divider ConTroL x
Value Divide-by
[0000] 1
[0001] 2
[0010] 3
[0011] 4
[0100] 5
[0101] 6
[0110] 8
[0111] 9
[1000] 10
[1001] 12
[1010] 15
[1011] 16
[1100] 18
[1101] 20
[1110] 25
POSTCTL_x[3:0]
[1111] 50
POST-divider SouRCe x
Crystal Oscillator
(x = A, B, or C)
[00] PLL_M
(x = D)
[01] PLL_A
[10] PLL_B
POSTSRC_x[3:0]
[11] PLL_C
POST- div ider Po we r- D own x
Bit = 0 Post-Divi der Operat es
POSTPD_x
Bit = 1 Post-Divider Powered
Down
(Output STOPPED)
Table 8: Output Control Bits
NAME DESCRIPTION
ClocK ConTroL x
Bit = 0 Out put STOPPED
CLKCTL_x
Bit = 1 Output RUNS
72.27.02
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL V CXO Pro
g
rammable Cloc k Generator IC
Three-PLL V CXO Pro
g
rammable Cloc k Generator ICThree-PLL VCXO Pro
g
rammable Cloc k Generator IC
Three-PLL V CXO Pro
g
rammable Cloc k Generator IC
82.27.02
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL VCXO Programmable Clock Generator IC
Three-PLL VCXO Programmable Clock Generator ICThree-PLL VCXO Programmable Clock Generator IC
Three-PLL VCXO Programmable Clock Generator IC
4.0 I2C-bus Control Interface
This device is a read/write slave device
meeting all Philips I2C-bus specifications
except a “general call.” The bus has to be
controlled by a master device that generates
the serial c lock SCL, controls bus acc ess, and generates
the START and STOP conditions while the device works
as a slave. Both master and slave can operate as a
transmitter or receiver, but the master device determines
which mode is activated. A device that sends data onto
the bus is defined as the transmitter, and a device re-
ceiving data as the receiver.
I2C-bus logic leve ls noted herein ar e based o n a percent-
age of the power supply (VDD). A logic-one corresponds
to a nominal voltage of VDD, while a logic-zero corre-
sponds to ground (VSS).
4.1 Bus Conditions
Data transfer on the bus can only be initiated when the
bus is not busy. During the data transfer, the data line
(SDA) must remain stable whenever the clock line (SCL)
is high. Changes in the data line while the clock line is
high will be interpreted by the device as a START or
STO P conditio n. T he foll owing bus cond itions are def ine d
by the I2C-bus protocol.
4.1.1 Not Busy
Both the dat a (SD A) a nd clock (SCL) lin es r em ain hi gh t o
indicate the bus is not bus y.
4.1.2 START Data Transfer
A high to lo w transition of the SDA line while the SCL in-
put is high indicates a START condit ion. A ll co mm ands to
the device must be preceded by a START condition.
4.1.3 STOP Data Transfer
A low to high transit ion of the SD A line wh ile SCL is he ld
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.
4.1.4 Data Valid
The state of the SD A l in e repr es e nts val id d ata if the SDA
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the
SDA line must be changed only during the low period of
the SCL signal. There is one clock pulse per data bit.
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions
is determined by the master device, and can continue
indefinitely. However, data that is overwritten to the de-
vice after the first sixteen bytes will overflow into the first
register, then the second, and so on, in a first-in, first-
overwritten fashion.
4.1.5 Acknowledge
W hen addressed, the rece iving dev ice is r equired to g en-
erate an Acknowledge after each byte is received. The
master device must generate an extra clock pulse to co-
incide with the Acknowledge bit. The acknowledging de-
vice must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
The mas ter mus t signal an e nd of data t o t he sl av e by not
generating and ack nowledge b it on the last byte that has
been read (clocked) out of the slave. In this case, the
slave must leave the SDA line high to enable the m aster
to generate a STOP condition.
4.2 I2C-bus Operation
All program mable register s can be accessed r andomly or
sequentially via this bi-directional two wire digital inter-
face. The device accepts the following I2C-bus com-
mands.
4.2.1 Slave Address
After generating a START condition, the bus master
broadcasts a seven-bit slave address followed by a R/W
bit.
The address of the device is:
A6 A5 A4 A3 A2 A1 A0
1011100
4.2.2 Random Register Write Procedure
Random write operations allow the master to directly
write to any register. To initiate a write procedure, the
R/W bit that is transmitted after the seven-bit device ad-
dress is a l og ic -lo w. T his i nd ic ates to the addr es s ed sl av e
device that a register address will follow after the slave
device acknowledges its device address. The register
address is written into the slave’s address pointer. Fol-
lowing an acknowledge by the slave, the master is al-
lowed to write eight bits of data into the addressed regis-
ter. A final acknowledge is returned by the device, and
the master generates a STOP condition.
92.27.02
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL V CXO Pro
g
rammable Cloc k Generator IC
Three-PLL V CXO Pro
g
rammable Cloc k Generator ICThree-PLL VCXO Pro
g
rammable Cloc k Generator IC
Three-PLL V CXO Pro
g
rammable Cloc k Generator IC
If either a STOP or a repeated START condition occurs
during a Register Write, the data that has been trans-
ferred is ignored.
4.2.3 Random Register Read Procedure
Random read operatio ns allo w the m as ter to direc tl y read
from any register. To perform a read procedure, the R/W
bit that is transmitted after the seven-bit address is a
logic-low, as in the Register Write procedure. This indi-
cates to the addressed slave device that a register ad-
dress will follow after the slave device acknowledges its
device address. The register address is then written into
the slave’s address pointer.
Following an acknowledge by the slave, the master gen-
erates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave address is
then resent, with the R/W bit set this tim e to a logic-high,
indicating to the slave that data will be read. The slave
will acknowledge the device address, and then transmits
the eight- bit word. T he master does not acknowledg e the
transfer but does generate a STOP condition.
4.2.4 Sequential Register Write Procedure
Sequential write operations allow the master to write to
each register in order. The register pointer is automati-
cally incremented after each write. This procedure is
more efficient than the Random Register W rite if several
registers must be written.
To initiate a write pr ocedure, the R/W bit that is transmit-
ted after th e seven-b it device addr ess is a l ogic-low. This
indicates to the addressed slave device that a register
address will follow after the slave device acknowledges
its device address. The register address is written into the
slave’s address pointer. Following an acknowledge by the
slave, the master is allowed to write up to sixteen bytes of
data into the addressed register before the register ad-
dress pointer overflows back to the beginning address.
An acknowledge by the device between each byte of data
must occur before the next data byte is sent.
Registers are updated every time the device sends an
acknowledge to the host. The register update does not
wait for the STOP condition to occur. Registers are
therefore updated at different times during a Sequential
Register Write.
4.2.5 Sequential Register Read Procedure
Sequent ial read operatio ns allow the m aster to r ead from
each register in order. The register pointer is automati-
call y increm ented b y one after e ach read. T his proc edure
is more efficient than the Random Register Read if sev-
eral registers must be read.
To perform a read procedure, the R/W bit that is trans-
mitted af ter the se ven-bit addr ess is a logic- low, as in the
Register W rite procedur e. This indic at es to th e a ddr ess ed
slave device that a register address will follow after the
slave device acknowledges its device address. The reg-
ister address is then written into the slave’s address
pointer.
Following an acknowledge by the slave, the master gen-
erates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave address is
then resent, with the R/W bit set this tim e to a logic-high,
indicating to the slave that data will be read. The slave
will acknowledge the device address, and then transmits
all sixt een b ytes of data star ting with the in itial address ed
register. The register address pointer will overflow if the
initial register address is larger than zero. After the last
byte of data, the master does not acknowledge the
transfer but does generate a STOP condition.
A
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or ICThree-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or IC
ISO9001
ISO9001ISO9001
ISO9001
Figure 6: Random Register Write Procedure
AA DATAW A
From bus host
to device
S REGISTER ADDRESS P
From device
to bus host
DEVICE ADDRESS
Register Address
Acknowledge STOP Condition
Data
Acknowledge
Acknowledge
START
Command WRITE Command
7-bit Receive
Device Address
Figure 7: Random Register Read Procedure
AR AAAWS REGISTER ADDRESS PS DEVICE ADDRESS
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge READ Command
Acknowledge
Data
NO Acknowledge
STOP Condition
From bus host
to device From device
to bus host
7-bit Receive
Device Address
7-bit Receive
Device Address
DEVICE ADDRESS DATA
Repeat START
Figure 8: Sequential Register Write Procedure
AAAWS P
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Data
Acknowledge
Data
STOP Command
AcknowledgeAcknowledge
From bus host
to device From device
to bus host
7-bit Receive
Device Address
DEVICE ADDRESS AA REGISTER ADDRESS DATA DATA DATA
Figure 9: Sequential Register Read Procedure
AWS
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Acknowledge
Data
STOP Command
Acknowledge READ Command
NO Acknowledge
From bus host
to device From device
to bus host
7-bit Receive
Device Address 7-bit Receive
Device Address
DEVICE ADDRESS AA REGISTER ADDRESS AR A PS DEVICE ADDRESS DATA DATA
Repeat START
A
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or ICThree-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or IC
ISO9001
ISO9001ISO9001
ISO9001
5.0 Electrical Specifications
Table 9: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER SYMBOL MIN. MAX. UNITS
Supply Voltage, dc (VSS = ground) VDD VSS-0.5 7 V
Input Voltage, dc VIVSS-0.5 VDD+0.5 V
Output Voltage, dc VOVSS-0.5 VDD+0.5 V
Input Clamp Current, dc (V I < 0 or VI > VDD)I
IK -50 50 mA
Output Clamp Current, dc (VI < 0 or VI > VDD)I
OK -50 50 mA
Storage Temperature Range (non-condensing) TS-65 150 °C
Ambient Temperature Range, Under Bias TA-55 125 °C
Junction Temperature TJ150 °C
Lead Temperature (soldering, 10s) 260 °C
Input Static Disc harge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 k V
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage res ulting in a loss of functi onality or performance may occur if this devic e is subjected to a high-energy elec-
trostatic discharge.
Table 10: Operating Conditions
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Supply Voltage VDD 3.3V ± 10% 3 3.3 3.6 V
Ambient Operating Temperature Range TA070°C
A
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or ICThree-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or IC
ISO9001
ISO9001ISO9001
ISO9001
Tabl e 11: DC Electrical Specif ications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Supply Current, Dynamic, Un-Loaded
Outputs * IDD mA
Supply Current, Dynamic, Loaded
Outputs * IDD mA
Supply Current, Fully P owered Down IDDL All POSTPD_x and PLLPD_x = 1 mA
Serial Interface I/O (SCL, SDA)
High-Level Input V olt age VIH VDD*0.75 VDD+0.3 V
Low-Level Input V oltage VIL VSS-0.3 VDD*0.25 V
Hysteresis Voltage Vhys VDD*0.33 V
High-Level Input Current IIH -1 1 µA
Low-Level Input Current IIL -1 1 µA
Low-Level Output Sink Current (SDA) IOL VOL = 0.4V, VDD = 3.0V VDD*0.5 mA
XTUNE Input
Equivalent Input Impedance RXTUNE 100 KΩ
Equivalent Input Termination VDD*0.5 V
Clock Outputs (CLK_x)
High-Level Output Sourc e Current IOH mA
Low-Level Output Sink Current IOL mA
zOH
Output Impedance zOL Ω
Short Circuit S ource Current * ISCH mA
Short Circuit S i nk Current * ISCL mA
13 2.27.02
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FS6477-02
Three-PLL V CXO Pro
g
rammable Cloc k Generator IC
Three-PLL V CXO Pro
g
rammable Cloc k Generator ICThree-PLL VCXO Pro
g
rammable Cloc k Generator IC
Three-PLL V CXO Pro
g
rammable Cloc k Generator IC
Table 12: AC Timing Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Voltage-Controlled Cr ystal Oscillator (VCXO)
Crystal Frequency 10 15 MHz
Crystal Load Capaci tance At center frequenc y 14 pF
VCXO Minimum Capacitance Typical @ VXTUNE = 0V 9 pF
VCXO Maximum Capacitance Typi cal @ VXTUNE = 3V 20 pF
Phase-Locked Loops
Output Frequency fO40 135 MHz
VCO Frequency fVCO 230 MHz
Clock Outputs (CLK_x)
Duty Cycle
(when supplied by PLL) * Ratio of pulse width (as measured from rising edge to next falling edge at
VDD*0.5) to one clock period 45 50 55 %
Duty Cycle
(when supplied by VCXO) * Ratio of pulse width (as measured from rising edge to next falling edge at
VDD*0.5) to one clock period 40 50 60 %
Rise Time * trVO = 0.3V to 3. 0V; CL = 10pF ns
Fall Time * tfVO = 3.0 V to 0.3V ; CL = 10pF ns
Jitter, Long Term (σy(τ))
(when supplied by PLL) * tj(LT) ps
Jitter, Long Term (σy(τ))
(when supplied by VCXO) * tj(LT) ps
Jitter, Period (peak-peak)
(when supplied by PLL) * tj(∆P) ps
Jitter, Period (peak-peak)
(when supplied by VCXO) * tj(∆P) ps
14 2.27.02
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FS6477-02FS6477-02
FS6477-02
Three-PLL VCXO Programmable Clock Generator IC
Three-PLL VCXO Programmable Clock Generator ICThree-PLL VCXO Programmable Clock Generator IC
Three-PLL VCXO Programmable Clock Generator IC
Table 13: Serial Interface Timing Specifications
Unless otherwise stated, all power supplies = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
STAND ARD MODE
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. MAX. UNITS
Clock frequency fSCL SCL 0 100 kHz
Bus free time between STOP and START tBUF 4.7 µs
Set up time, START (repeated) tsu:STA 4.7 µs
Hold time, START thd:STA 4.0 µs
Set up time, data input tsu:DAT SDA 250 ns
Hold time, data input thd:DAT SDA 0 µs
Output data valid from clock tAA Minimum delay to bridge undefined region of the fall-
ing edge of SCL to avoid unintended START or STOP 3.5 µs
Rise time, data and clock tRSDA, SCL 1000 ns
Fall time, data and clock tFSDA, SCL 300 ns
High time, clock tHI SCL 4.0 µs
Low time, clock tLO SCL 4.7 µs
Set up time, STOP tsu:STO 4.0 µs
Figure 10: Bus Timing Data
SCL
SDA
~
~~
~~
~
STOP
t
su:STO
t
hd:STA
START
t
su:STA
ADDRESS OR
DATA VALID DATA CAN
CHANGE
Figure 11: Data Transfer Sequence
SCL
SDA
IN
t
hd:DAT
~
~
t
hd:STA
t
su:STA
t
su:STO
t
LO
t
HI
SDA
OUT
t
su:DAT
~
~~
~
t
BUF
t
R
t
F
t
AA
t
AA
A
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or ICThree-PLL VCXO Programmable Clock Generat or IC
Three-PLL VCXO Programmable Clock Generat or IC
ISO9001
ISO9001ISO9001
ISO9001
6.0 Package Information
Table 14: 16-pin SOIC (0.150") Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A 0.061 0.068 1.55 1.73
A1 0.004 0.0098 0.102 0.249
A2 0.055 0.061 1.40 1.55
B 0.013 0.019 0.33 0.49
C 0.0075 0.0098 0.191 0.249
D 0.386 0.393 9.80 9.98
E 0.150 0.157 3.81 3.99
e 0.050 BSC 1.27 BSC
H 0.230 0.244 5.84 6.20
h 0.010 0.016 0.25 0.41
L 0.016 0.035 0.41 0.89
Θ0°8°0°8°
Be
DA
1
SEATING PLANE
HE
16
1ALL RADII:
0.005" TO 0.01"
BASE PLANE
A
2
C
L
θ
7° typ.h x 45°
A
AMERICAN MICROSYSTEMS, INC.
R
Table 15: 16-pin SOIC (0.150") Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air
16-pin 0.150” SOIC ΘJA Air flow = 0 m/s 95 °C/W
Corner lead 4.0
Lead Inductanc e, Self L11 Center lead 3.0 nH
Lead Inductanc e, Mutual L12 Any lead to any adjacent l ead 0.4 nH
Lead Capacitance, Bulk C11 Any lead to VSS 0.5 pF
16 2.27.02
FS6477-02
FS6477-02FS6477-02
FS6477-02
Three-PLL VCXO Programmable Clock Generator IC
Three-PLL VCXO Programmable Clock Generator ICThree-PLL VCXO Programmable Clock Generator IC
Three-PLL VCXO Programmable Clock Generator IC
7.0 Ordering Information
ORDERING CODE DEVICE NUMBER PACKAGE TYPE OPERATING
TEM PERATURE R ANGE SHIPPING
CONFIGURATION
11825-804 FS6477-02 16-pin (0.150”) S OIC
(Small Outl i ne Package) 0°C to 70°C (Commercial) Tape and Reel
11825-814 FS6477-02 16-pin (0.150”) S OIC
(Small Outl i ne Package) 0°C to 70°C (Commercial) Tubes
Copyright © 1999, 2000 American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI
makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom
of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-
serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are
intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-
ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom-
mended without additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Address: http://www.amis.com E-mail: tgp@amis.com
