LMR10510 www.ti.com SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 LMR10510 SIMPLE SWITCHER(R) 5.5Vin, 1A Step-Down Voltage Regulator in SOT-23 and WSON Check for Samples: LMR10510 FEATURES DESCRIPTION * * * * The LMR10510 regulator is a monolithic, high frequency, PWM step-down DC/DC converter in a 5 pin SOT-23 and a 6 Pin WSON package. It provides all the active functions to provide local DC/DC conversion with fast transient response and accurate regulation in the smallest possible PCB area. With a minimum of external components, the LMR10510 is easy to use. The ability to drive 1.0A loads with an internal 130 m PMOS switch results in the best power density available. The world-class control circuitry allows on-times as low as 30ns, thus supporting exceptionally high frequency conversion over the entire 3V to 5.5V input operating range down to the minimum output voltage of 0.6V. The LMR10510 is a constant frequency PWM buck regulator IC that delivers a 1.0A load current. The regulator has a preset switching frequency of 1.6MHz or 3.0MHz. This high frequency allows the LMR10510 to operate with small surface mount capacitors and inductors, resulting in a DC/DC converter that requires a minimum amount of board space. The LMR10510 is internally compensated, so it is simple to use and requires few external components. Even though the operating frequency is high, efficiencies up to 93% are easy to achieve. External shutdown is included, featuring an ultra-low stand-by current of 30 nA. The LMR10510 utilizes current-mode control and internal compensation to provide high-performance regulation over a wide range of operating conditions. Additional features include internal soft-start circuitry to reduce inrush current, pulse-by-pulse current limit, thermal shutdown, and output over-voltage protection. 1 23 * * * * * * * Input Voltage Range of 3V to 5.5V Output Voltage Range of 0.6V to 4.5V Output Current up to 1A 1.6MHz (LMR10510X) and 3 MHz (LMR10510Y) Switching Frequencies Low Shutdown Iq, 30 nA Typical Internal Soft-Start Internally Compensated Current-Mode PWM Operation Thermal Shutdown SOT-23 (2.92 x 2.84 x 1 mm) and WSON (3 x 3 x 0.8 mm) Packaging Fully Enabled for WEBENCH(R) Power Designer APPLICATIONS * * * * * * Point-of-Load Conversions from 3.3V, and 5V Rails Space Constrained Applications Battery Powered Equipment Industrial Distributed Power Applications Power Meters Portable Hand-Held Instruments PERFORMANCE BENEFITS * * Extremely easy to use Tiny overall solution reduces system cost 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2013, Texas Instruments Incorporated LMR10510 SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 www.ti.com System Performance Efficiency vs Load Current - "Y" VIN = 5V 100 100 90 90 EFFICIENCY (%) EFFICIENCY (%) Efficiency vs Load Current - "X" VIN = 5V 80 70 60 50 80 70 60 50 1.8Vout 3.3Vout 40 1.8Vout 3.3Vout 40 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) Typical Application FB EN LMR10510 R3 GND L1 VIN VOUT SW VIN R1 C1 D1 C2 C3 R2 Connection Diagrams FB 1 GND 2 SW 3 EN 6 EN DAP 3 FB 2 GND 5 VINA 4 VIND VIN Figure 1. 6-Pin WSON See Package Number NGG0006A 2 4 5 1 SW Figure 2. 5-Pin SOT-23 See Package Number DBV (R-PDSO-G5) Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 LMR10510 www.ti.com SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 PIN DESCRIPTIONS 5-Pin SOT-23 Pin Name Function 1 SW 2 GND Switch node. Connect to the inductor and catch diode. 3 FB Feedback pin. Connect to external resistor divider to set output voltage. 4 EN Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN + 0.3V. 5 VIN Input supply voltage. Signal and power ground pin. Place the bottom resistor of the feedback network as close as possible to this pin. PIN DESCRIPTIONS 6-Pin WSON Pin Name 1 FB 2 GND Function Feedback pin. Connect to external resistor divider to set output voltage. Signal and power ground pin. Place the bottom resistor of the feedback network as close as possible to this pin. 3 SW 4 VIND Switch node. Connect to the inductor and catch diode. Power Input supply. 5 VINA Control circuitry supply voltage. Connect VINA to VIND on PC board. 6 EN DAP Die Attach Pad Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than VINA + 0.3V. Connect to system ground for low thermal impedance, but it cannot be used as a primary GND connection. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN -0.5V to 7V FB Voltage -0.5V to 3V EN Voltage -0.5V to 7V SW Voltage -0.5V to 7V ESD Susceptibility 2kV Junction Temperature (3) 150C -65C to +150C Storage Temperature For soldering specifications: http://www.ti.com/lit/SNOA549C (1) (2) (3) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for which the device is intended to be functional, but does not ensure specfic performance limits. For specific specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device. Operating Ratings VIN 3V to 5.5V -40C to +125C Junction Temperature Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 3 LMR10510 SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 www.ti.com Electrical Characteristics (1) (2) VIN = 5V unless otherwise indicated under the Conditions column. Limits in standard type are for TJ = 25C only; limits in boldface type apply over the junction temperature (TJ) range of -40C to +125C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Symbol VFB VFB/VIN IB UVLO Parameter Conditions Feedback Voltage Feedback Voltage Line Regulation Min Typ Max 0.588 0.600 0.612 VIN = 3V to 5V 0.02 Feedback Input Bias Current Undervoltage Lockout VIN Rising VIN Falling 1.85 UVLO Hysteresis FSW Switching Frequency DMAX Maximum Duty Cycle DMIN Minimum Duty Cycle RDS(ON) ICL VEN_TH (2) (3) 4 Switch Current Limit 100 nA 2.73 2.90 V 2.3 0.43 1.2 1.6 1.95 LMR10510-Y 2.25 3.0 3.75 LMR10510-X 86 94 LMR10510-Y 82 90 LMR10510-X 5 LMR10510-Y 7 WSON Package 150 SOT-23 Package 130 1.2 Switch Leakage Enable Pin Current Quiescent Current (switching) MHz % % 195 1.75 m A 0.4 Enable Threshold Voltage IEN V LMR10510-X VIN = 3.3V V %/V 0.1 Shutdown Threshold Voltage ISW IQ (1) Switch On Resistance Units 1.8 100 V nA Sink/Source 100 LMR10510X VFB = 0.55 3.3 5 mA 6.5 mA LMR10510Y VFB = 0.55 4.3 Quiescent Current (shutdown) All Options VEN = 0V 30 JA Junction to Ambient 0 LFPM Air Flow (3) WSON Package 80 SOT-23 Package 118 JC Junction to Case WSON Package 18 SOT-23 Package 80 TSD Thermal Shutdown Temperature 165 nA nA C/W C/W C Min and Max limits are 100% production tested at 25C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate TI's Average Outgoing Quality Level (AOQL). Typical numbers are at 25C and represent the most likely parametric norm. Applies for packages soldered directly onto a 3" x 3" PC board with 2oz. copper on 4 layers in still air. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 LMR10510 www.ti.com SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 Typical Performance Characteristics Unless stated otherwise, all curves taken at VIN = 5.0V with configuration in typical application circuit shown in Figure 22. TJ = 25C, unless otherwise specified. vs Load "Y" Vin = 5V, Vo = 3.3V & 1.8V 100 100 90 90 EFFICIENCY (%) EFFICIENCY (%) vs Load "X" Vin = 5V, Vo = 1.8V & 3.3V 80 70 60 50 40 80 70 60 50 1.8Vout 3.3Vout 40 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 1.8Vout 3.3Vout 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) Figure 3. Figure 4. vs Load "X and Y" Vin = 3.3V, Vo = 1.8V Load Regulation Vin = 3.3V, Vo = 1.8V (All Options) 100 EFFICIENCY (%) 90 80 70 60 50 40 LMR10510Y LMR10510X 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) Figure 5. Figure 6. Load Regulation Vin = 5V, Vo = 1.8V (All Options) Load Regulation Vin = 5V, Vo = 3.3V (All Options) Figure 7. Figure 8. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 5 LMR10510 SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless stated otherwise, all curves taken at VIN = 5.0V with configuration in typical application circuit shown in Figure 22. TJ = 25C, unless otherwise specified. Oscillator Frequency vs Temperature - "X" Oscillator Frequency vs Temperature - "Y" 3.45 OSCILLATOR FREQUENCY (MHz) OSCILLATOR FREQUENCY (MHz) 1.81 1.76 1.71 1.66 1.61 1.56 1.51 1.46 1.41 1.36 -45 -40 -10 20 50 3.35 3.25 3.15 3.05 2.95 2.85 2.75 2.65 2.55 -45 -40 80 110 125 130 TEMPERATURE (C) -10 20 50 80 110 125 130 TEMPERATURE (C) Figure 9. Figure 10. Current Limit vs Temperature Vin = 3.3V RDSON vs Temperature (WSON Package) 2000 1950 CURRENT LIMIT (mA) 1900 1850 1800 1750 1700 1650 1600 1550 1500 -45 -40 -10 20 50 80 110 125 130 TEMPERATURE (oC) Figure 11. Figure 12. RDSON vs Temperature (SOT-23 Package) LMR10510X IQ (Quiescent Current) 3.6 3.5 IQ (mA) 3.4 3.3 3.2 3.1 3.0 -45 -40 -10 20 50 80 110 125 130 TEMPERATURE (C) Figure 13. 6 Figure 14. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 LMR10510 www.ti.com SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless stated otherwise, all curves taken at VIN = 5.0V with configuration in typical application circuit shown in Figure 22. TJ = 25C, unless otherwise specified. Line Regulation Vo = 1.8V, Io = 500mA LMR10510Y IQ (Quiescent Current) 4.6 4.5 IQ (mA) 4.4 4.3 4.2 4.1 4.0 -45 -40 -10 20 50 80 110 125 130 TEMPERATURE (C) Figure 15. Figure 16. VFB vs Temperature Gain vs Frequency (Vin = 5V, Vo = 1.2V @ 1A) FEEBACK VOLTAGE (V) 0.610 0.605 0.600 0.595 0.590 -45 -40 -10 20 50 80 110 125 130 TEMPERATURE (C) Figure 17. Figure 18. Phase Plot vs Frequency (Vin = 5V, Vo = 1.2V @ 1A) Figure 19. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 7 LMR10510 SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 www.ti.com Simplified Block Diagram EN VIN + ENABLE and UVLO ThermalSHDN I SENSE - + - I LIMIT - 1 .15 x VREF + OVPSHDN Ramp Artificial Control Logic cv I SENSE R R Q + FB S 1.6 MHz PFET - + DRIVER Internal - Comp SW VREF = 0.6V SOFT - START Internal - LDO GND Figure 20. APPLICATIONS INFORMATION THEORY OF OPERATION The following operating description of the LMR10510 will refer to the Simplified Block Diagram (Figure 20) and to the waveforms in Figure 21. The LMR10510 supplies a regulated output voltage by switching the internal PMOS control switch at constant frequency and variable duty cycle. A switching cycle begins at the falling edge of the reset pulse generated by the internal oscillator. When this pulse goes low, the output control logic turns on the internal PMOS control switch. During this on-time, the SW pin voltage (VSW) swings up to approximately VIN, and the inductor current (IL) increases with a linear slope. IL is measured by the current sense amplifier, which generates an output proportional to the switch current. The sense signal is summed with the regulator's corrective ramp and compared to the error amplifier's output, which is proportional to the difference between the feedback voltage and VREF. When the PWM comparator output goes high, the output switch turns off until the next switching cycle begins. During the switch off-time, inductor current discharges through the Schottky catch diode, which forces the SW pin to swing below ground by the forward voltage (VD) of the Schottky catch diode. The regulator loop adjusts the duty cycle (D) to maintain a constant output voltage. 8 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 LMR10510 www.ti.com SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 VSW D = TON/TSW VIN SW Voltage TOFF TON 0 VD IL t TSW IPK Inductor Current t 0 Figure 21. Typical Waveforms SOFT-START This function forces VOUT to increase at a controlled rate during start up. During soft-start, the error amplifier's reference voltage ramps from 0V to its nominal value of 0.6V in approximately 600 s. This forces the regulator output to ramp up in a controlled fashion, which helps reduce inrush current. OUTPUT OVERVOLTAGE PROTECTION The over-voltage comparator compares the FB pin voltage to a voltage that is 15% higher than the internal reference VREF. Once the FB pin voltage goes 15% above the internal reference, the internal PMOS control switch is turned off, which allows the output voltage to decrease toward regulation. UNDERVOLTAGE LOCKOUT Under-voltage lockout (UVLO) prevents the LMR10510 from operating until the input voltage exceeds 2.73V (typ). The UVLO threshold has approximately 430 mV of hysteresis, so the part will operate until VIN drops below 2.3V (typ). Hysteresis prevents the part from turning off during power up if VIN is non-monotonic. CURRENT LIMIT The LMR10510 uses cycle-by-cycle current limiting to protect the output switch. During each switching cycle, a current limit comparator detects if the output switch current exceeds 1.75A (typ), and turns off the switch until the next switching cycle begins. THERMAL SHUTDOWN Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature exceeds 165C. After thermal shutdown occurs, the output switch doesn't turn on until the junction temperature drops to approximately 150C. EN 3.3 PH (; YHUVLRQ) U1 R3 6 VIN 4, 5 2 EN SW 1.0 PH VINA/VIND GND VOUT L1 3 FB 1 1.8V R1 20k C3 22 PF C2 C1 2.2 PF R2 10k D1 2.2 PF GND C4 22 PF Chf 22 nF (opt.) GND Figure 22. Typical Application Schematic Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 9 LMR10510 SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 www.ti.com Design Guide INDUCTOR SELECTION The Duty Cycle (D) can be approximated quickly using the ratio of output voltage (VO) to input voltage (VIN): D= VOUT VIN The catch diode (D1) forward voltage drop and the voltage drop across the internal PMOS must be included to calculate a more accurate duty cycle. Calculate D by using the following formula: D= VOUT + VD VIN + VD - VSW VSW can be approximated by: VSW = IOUT x RDSON The diode forward drop (VD) can range from 0.3V to 0.7V depending on the quality of the diode. The lower the VD, the higher the operating efficiency of the converter. The inductor value determines the output ripple current. Lower inductor values decrease the size of the inductor, but increase the output ripple current. An increase in the inductor value will decrease the output ripple current. One must ensure that the minimum current limit (1.2A) is not exceeded, so the peak current in the inductor must be calculated. The peak current (ILPK) in the inductor is calculated by: ILPK = IOUT + iL 'i L I OUT VIN - VOUT VOUT L L DTS TS t Figure 23. Inductor Current VIN - VOUT L = 2'iL DTS In general, iL = 0.1 x (IOUT) 0.2 x (IOUT) If iL = 20% of 1A, the peak current in the inductor will be 1.2A. The minimum specified current limit over all operating conditions is 1.2A. One can either reduce iL, or make the engineering judgment that zero margin will be safe enough. The typical current limit is 1.75A. The LMR10510 operates at frequencies allowing the use of ceramic output capacitors without compromising transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple. See the OUTPUT CAPACITOR section for more details on calculating output voltage ripple. Now that the ripple current is determined, the inductance is calculated by: L= DTS x (VIN - VOUT) 2'iL where TS = * 10 1 fS Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 LMR10510 www.ti.com SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 When selecting an inductor, make sure that it is capable of supporting the peak output current without saturating. Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating correctly. Because of the speed of the internal current limit, the peak current of the inductor need only be specified for the required maximum output current. For example, if the designed maximum output current is 1.0A and the peak current is 1.25A, then the inductor should be specified with a saturation current limit of > 1.25A. There is no need to specify the saturation or peak current of the inductor at the 1.75A typical switch current limit. The difference in inductor size is a factor of 5. Because of the operating frequency of the LMR10510, ferrite based inductors are preferred to minimize core losses. This presents little restriction since the variety of ferritebased inductors is huge. Lastly, inductors with lower series resistance (RDCR) will provide better operating efficiency. For recommended inductors see Example Circuits:LMR10510X Design Example 1 LMR10510X Design Example 2 LMR10510Y Design Example 3 LMR10510Y Design Example 4. INPUT CAPACITOR An input capacitor is necessary to ensure that VIN does not drop excessively during switching transients. The primary specifications of the input capacitor are capacitance, voltage, RMS current rating, and ESL (Equivalent Series Inductance). The recommended input capacitance is 22 F.The input voltage rating is specifically stated by the capacitor manufacturer. Make sure to check any recommended deratings and also verify if there is any significant change in capacitance at the operating input voltage and the operating temperature. The input capacitor maximum RMS input current rating (IRMS-IN) must be greater than: IRMS_IN D IOUT2 (1-D) + 'i2 3 Neglecting inductor ripple simplifies the above equation to: IRMS_IN = IOUT x D(1 - D) It can be shown from the above equation that maximum RMS capacitor current occurs when D = 0.5. Always calculate the RMS at the point where the duty cycle D is closest to 0.5. The ESL of an input capacitor is usually determined by the effective cross sectional area of the current path. A large leaded capacitor will have high ESL and a 0805 ceramic chip capacitor will have very low ESL. At the operating frequencies of the LMR10510, leaded capacitors may have an ESL so large that the resulting impedance (2fL) will be higher than that required to provide stable operation. As a result, surface mount capacitors are strongly recommended. Sanyo POSCAP, Tantalum or Niobium, Panasonic SP, and multilayer ceramic capacitors (MLCC) are all good choices for both input and output capacitors and have very low ESL. For MLCCs it is recommended to use X7R or X5R type capacitors due to their tolerance and temperature characteristics. Consult capacitor manufacturer datasheets to see how rated capacitance varies over operating conditions. OUTPUT CAPACITOR The output capacitor is selected based upon the desired output ripple and transient response. The initial current of a load transient is provided mainly by the output capacitor. The output ripple of the converter is: 'VOUT = 'IL RESR + 1 8 x FSW x COUT When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the output ripple will be approximately sinusoidal and 90 phase shifted from the switching action. Given the availability and quality of MLCCs and the expected output voltage of designs using the LMR10510, there is really no need to review any other capacitor technologies. Another benefit of ceramic capacitors is their ability to bypass high frequency noise. A certain amount of switching edge noise will couple through parasitic capacitances in the inductor to the output. A ceramic capacitor will bypass this noise while a tantalum will not. Since the output capacitor is one of the two external components that control the stability of the regulator control loop, most applications will require a minimum of 22 F of output capacitance. Capacitance often, but not always, can be increased significantly with little detriment to the regulator stability. Like the input capacitor, recommended multilayer ceramic capacitors are X7R or X5R types. CATCH DIODE The catch diode (D1) conducts during the switch off-time. A Schottky diode is recommended for its fast switching times and low forward voltage drop. The catch diode should be chosen so that its current rating is greater than: Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 11 LMR10510 SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 www.ti.com ID1 = IOUT x (1-D) The reverse breakdown rating of the diode must be at least the maximum input voltage plus appropriate margin. To improve efficiency, choose a Schottky diode with a low forward voltage drop. OUTPUT VOLTAGE The output voltage is set using the following equation where R2 is connected between the FB pin and GND, and R1 is connected between VO and the FB pin. A good value for R2 is 10k. When designing a unity gain converter (Vo = 0.6V), R1 should be between 0 and 100, and R2 should be equal or greater than 10k. R1 = VOUT VREF - 1 x R2 VREF = 0.60V PCB LAYOUT CONSIDERATIONS When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The most important consideration is the close coupling of the GND connections of the input capacitor and the catch diode D1. These ground ends should be close to one another and be connected to the GND plane with at least two through-holes. Place these components as close to the IC as possible. Next in importance is the location of the GND connection of the output capacitor, which should be near the GND connections of CIN and D1. There should be a continuous ground plane on the bottom layer of a two-layer board except under the switching node island. The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with the GND of R1 placed as close as possible to the GND of the IC. The VOUT trace to R2 should be routed away from the inductor and any other traces that are switching. High AC currents flow through the VIN, SW and VOUT traces, so they should be as short and wide as possible. However, making the traces wide increases radiated noise, so the designer must make this trade-off. Radiated noise can be decreased by choosing a shielded inductor. The remaining components should also be placed as close as possible to the IC. Please see Application Note AN-1229 for further considerations and the LMR10510 demo board as an example of a good layout. Calculating Efficiency, and Junction Temperature The complete LMR10510 DC/DC converter efficiency can be calculated in the following manner. K= POUT PIN Or K= POUT POUT + PLOSS Calculations for determining the most significant power losses are shown below. Other losses totaling less than 2% are not discussed. Power loss (PLOSS) is the sum of two basic types of losses in the converter: switching and conduction. Conduction losses usually dominate at higher output loads, whereas switching losses remain relatively fixed and dominate at lower output loads. The first step in determining the losses is to calculate the duty cycle (D): D= VOUT + VD VIN + VD - VSW VSW is the voltage drop across the internal PFET when it is on, and is equal to: VSW = IOUT x RDSON VD is the forward voltage drop across the Schottky catch diode. It can be obtained from the diode manufactures Electrical Characteristics section. If the voltage drop across the inductor (VDCR) is accounted for, the equation becomes: 12 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 LMR10510 www.ti.com D= SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 VOUT + VD + VDCR VIN + VD + VDCR - VSW The conduction losses in the free-wheeling Schottky diode are calculated as follows: PDIODE = VD x IOUT x (1-D) Often this is the single most significant power loss in the circuit. Care should be taken to choose a Schottky diode that has a low forward voltage drop. Another significant external power loss is the conduction loss in the output inductor. The equation can be simplified to: PIND = IOUT2 x RDCR The LMR10510 conduction loss is mainly associated with the internal PFET: PCOND = (IOUT2 x D) 1 + 'iL 1 x 3 IOUT 2 RDSON If the inductor ripple current is fairly small, the conduction losses can be simplified to: PCOND = IOUT2 x RDSON x D Switching losses are also associated with the internal PFET. They occur during the switch on and off transition periods, where voltages and currents overlap resulting in power loss. The simplest means to determine this loss is to empirically measuring the rise and fall times (10% to 90%) of the switch at the switch node. Switching Power Loss is calculated as follows: PSWR = 1/2(VIN x IOUT x FSW x TRISE) PSWF = 1/2(VIN x IOUT x FSW x TFALL) PSW = PSWR + PSWF Another loss is the power required for operation of the internal circuitry: PQ = IQ x VIN IQ is the quiescent operating current, and is typically around 3.3mA for the 1.6MHz frequency option. Typical Application power losses are: Table 1. Power Loss Tabulation VIN 5.0V VOUT 3.3V IOUT 1.0A VD 0.45V FSW 1.6MHz POUT 3.3W PDIODE 150mW IQ 3.3mA PQ 17mW TRISE 4nS PSWR 16mW TFALL 4nS PSWF 16mW RDS(ON) 150m PCOND 100mW INDDCR 70m PIND 70mW D 0.667 PLOSS 369mW 88% PINTERNAL 149mW PCOND + PSW + PDIODE + PIND + PQ = PLOSS PCOND + PSWF + PSWR + PQ = PINTERNAL PINTERNAL = 149mW Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 13 LMR10510 SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 www.ti.com Thermal Definitions TJ = Chip junction temperature TA = Ambient temperature RJC = Thermal resistance from chip junction to device case RJA = Thermal resistance from chip junction to ambient air Heat in the LMR10510 due to internal power dissipation is removed through conduction and/or convection. Conduction: Heat transfer occurs through cross sectional areas of material. Depending on the material, the transfer of heat can be considered to have poor to good thermal conductivity properties (insulator vs. conductor). Heat Transfer goes as: Silicon package lead frame PCB Convection: Heat transfer is by means of airflow. This could be from a fan or natural convection. Natural convection occurs when air currents rise from the hot device to cooler air. Thermal impedance is defined as: RT = 'T Power Thermal impedance from the silicon junction to the ambient air is defined as: RTJA = TJ - TA Power The PCB size, weight of copper used to route traces and ground plane, and number of layers within the PCB can greatly effect RJA. The type and number of thermal vias can also make a large difference in the thermal impedance. Thermal vias are necessary in most applications. They conduct heat from the surface of the PCB to the ground plane. Four to six thermal vias should be placed under the exposed pad to the ground plane if the WSON package is used. Thermal impedance also depends on the thermal properties of the application operating conditions (Vin, Vo, Io etc), and the surrounding circuitry. Silicon Junction Temperature Determination Method 1: To accurately measure the silicon temperature for a given application, two methods can be used. The first method requires the user to know the thermal impedance of the silicon junction to case temperature. RJC is approximately 18C/Watt for the 6-pin WSON package with the exposed pad. Knowing the internal dissipation from the efficiency calculation given previously, and the case temperature, which can be empirically measured on the bench we have: RTJC = TJ - TC Power where TC is the temperature of the exposed pad and can be measured on the bottom side of the PCB. Therefore: Tj = (RJC x PLOSS) + TC From the previous example: Tj = (RJC x PINTERNAL) + TC Tj = 18C/W x 0.149W + TC The second method can give a very accurate silicon junction temperature. 14 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 LMR10510 www.ti.com SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 The first step is to determine RJA of the application. The LMR10510 has over-temperature protection circuitry. When the silicon temperature reaches 165C, the device stops switching. The protection circuitry has a hysteresis of about 15C. Once the silicon temperature has decreased to approximately 150C, the device will start to switch again. Knowing this, the RJA for any application can be characterized during the early stages of the design one may calculate the RJA by placing the PCB circuit into a thermal chamber. Raise the ambient temperature in the given working application until the circuit enters thermal shutdown. If the SW-pin is monitored, it will be obvious when the internal PFET stops switching, indicating a junction temperature of 165C. Knowing the internal power dissipation from the above methods, the junction temperature, and the ambient temperature RJA can be determined. RTJA = 165 - Ta PINTERNAL Once this is determined, the maximum ambient temperature allowed for a desired junction temperature can be found. An example of calculating RJA for an application using the LMR10510 is shown below. A sample PCB is placed in an oven with no forced airflow. The ambient temperature was raised to 147C, and at that temperature, the device went into thermal shutdown. From the previous example: PINTERNAL = 149 mW RTJA = 165C - 147C 149 mW = 121C/W Since the junction temperature must be kept below 125C, then the maximum ambient temperature can be calculated as: Tj - (RJA x PLOSS) = TA 125C - (121C/W x 149 mW) = 107C WSON Package Figure 24. Internal WSON Connection For certain high power applications, the PCB land may be modified to a "dog bone" shape (see Figure 25). By increasing the size of ground plane, and adding thermal vias, the RJA for the application can be reduced. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 15 LMR10510 SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 www.ti.com FB 1 GND 2 6 EN GND 5 VINA PLANE SW 3 4 VIND Figure 25. 6-Lead WSON PCB Dog Bone Layout LMR10510X Design Example 1 FB EN R3 VIN = 5V C1 LMR10510 100k GND L1 VIN SW 3.3 PH 1.5A 22 PF 10V D1 1.5A 20V VO = 1.2V @ 1.0A R1 15k R2 15k C2 22 PF 6.3V Figure 26. LMR10510X (1.6MHz): Vin = 5V, Vo = 1.2V @ 1.0A LMR10510X Design Example 2 FB EN R3 VIN = 5V LMR10510 100k VIN GND L1 SW 2.2 PH 1.8A C1 22 PF 10V D1 1.5A 20V VO = 3.3V @ 1.0A R1 45.3k R2 100k C2 22 PF 6.3V Figure 27. LMR10510X (1.6MHz): Vin = 5V, Vo = 3.3V @ 1.0A 16 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 LMR10510 www.ti.com SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 LMR10510Y Design Example 3 FB EN R3 VIN = 5V LMR10510 100k GND L1 VIN SW 1.6 PH 2.0A C1 22 PF 10V D1 1.5A 20V VO = 3.3V @ 1.0A R1 45.3k R2 100k C2 22 PF 6.3V Figure 28. LMR10510Y (3MHz): Vin = 5V, Vo = 3.3V @ 1.0A LMR10510Y Design Example 4 FB EN R3 VIN = 5V C1 LMR10510 100k VIN 22 PF 10V GND L1 SW 1.6 PH 2.0A D1 1.5A 20V VO = 1.2V @ 1.0A R1 10k R2 10k C2 22 PF 6.3V Figure 29. LMR10510Y (3MHz): Vin = 5V, Vo = 1.2V @ 1.0A Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 17 LMR10510 SNVS727B - OCTOBER 2011 - REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision A (April 2013) to Revision B * 18 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 17 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: LMR10510 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LMR10510XMF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SH7B LMR10510XMFE/NOPB ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SH7B LMR10510XMFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SH7B LMR10510YMF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SH9B LMR10510YMFE/NOPB ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SH9B LMR10510YMFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SH9B LMR10510YSD/NOPB ACTIVE WSON NGG 6 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L268B LMR10510YSDE/NOPB ACTIVE WSON NGG 6 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L268B LMR10510YSDX/NOPB ACTIVE WSON NGG 6 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L268B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LMR10510XMF/NOPB SOT-23 DBV 5 1000 178.0 8.4 LMR10510XMFE/NOPB SOT-23 DBV 5 250 178.0 LMR10510XMFX/NOPB SOT-23 DBV 5 3000 178.0 LMR10510YMF/NOPB SOT-23 DBV 5 1000 LMR10510YMFE/NOPB SOT-23 DBV 5 LMR10510YMFX/NOPB SOT-23 DBV LMR10510YSD/NOPB WSON NGG LMR10510YSDE/NOPB WSON LMR10510YSDX/NOPB WSON 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 NGG 6 250 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 NGG 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMR10510XMF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMR10510XMFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0 LMR10510XMFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMR10510YMF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMR10510YMFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0 LMR10510YMFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMR10510YSD/NOPB WSON NGG 6 1000 210.0 185.0 35.0 LMR10510YSDE/NOPB WSON NGG 6 250 210.0 185.0 35.0 LMR10510YSDX/NOPB WSON NGG 6 4500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com MECHANICAL DATA NGG0006A SDE06A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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