LTC3807
1
3807fa
For more information www.linear.com/LTC3807
IOUT (A)
FIGURE 13 CIRCUIT
Burst Mode OPERATION
0
EFFICIENCY (%)
POWER LOSS (W)
70
100
10.10.010.0010.0001 10
3807 TA01b
50
40
30
20 0.01
0.1
1
10
0.001
10
60
80
90
VIN = 24V
VOUT = 12V
POWER LOSS
EFFICIENCY
TYPICAL APPLICATION
FEATURES DESCRIPTION
Low IQ, Synchronous
Step-Down Controller with 24V
Output Voltage Capability
The LTC
®
3807 is a high performance step-down switching
regulator DC/DC controller that drives an all N-channel
synchronous power MOSFET stage. A constant fre-
quency current mode architecture allows a phase-lockable
frequency of up to 750kHz.
The 50μA no-load quiescent current extends operating run
time in battery-powered systems. OPTI-LOOP
®
compensa-
tion allows the transient response to be optimized over
a wide range of output capacitance and ESR values. The
LTC3807 features a precision 0.8V reference and power
good output indicator. A wide 4V to 38V input supply range
encompasses a wide range of intermediate bus voltages
and battery chemistries. The output voltage of the LTC3807
can be programmed between 0.8V to 24V.
The TRACK/SS pin ramps the output voltages during
start-up. Current foldback limits MOSFET heat dissipation
during short-circuit conditions. The PLLIN/MODE pin se-
lects among Burst Mode operation, pulse-skipping mode,
or continuous conduction mode at light loads.
Efficiency and Power Loss vs
Output Current
APPLICATIONS
n Wide VIN Range: 4V to 38V (40V Abs Max)
n Low Operating IQ: 50μA
n Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 24V
n RSENSE or DCR Current Sensing
n Phase-Lockable Frequency (75kHz to 750kHz)
n Programmable Fixed Frequency (50kHz to 900kHz)
n Selectable Continuous, Pulse-Skipping or Low Ripple
Burst Mode
®
Operation at Light Load
n Selectable Current Limit
n Very Low Dropout Operation: 99% Duty Cycle
n Adjustable Output Voltage Soft-Start or Tracking
n Power Good Output Voltage Monitor
n Output Overvoltage Protection
n Low Shutdown IQ: 14μA
n Internal LDO Powers Gate Drive from VIN or EXTVCC
n No Current Foldback During Start-Up
n Small 20-Pin 3mm × 4mm QFN and TSSOP Packages
n Automotive Always-On Systems
n Battery Powered Digital Devices
n Distributed DC Power Systems
L, LT, LTC, LTM, OPTI-LOOP, Burst Mode, Linear Technology and the Linear logo are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Patents, including 5481178, 5705919, 6611131, 6498466, 6580258,
7230497.
0.1µF
22µF
V
IN
12.5V TO 38V
60.4k
15.4k
4.7nF
100k
6.98k
3807 TA01a
2.2µF
47pF
0.1µF
FREQ
ITH
SGND
EXTVCC
VOUT
LTC3807
VIN INTVCC
10µH 4mΩ
INTVCC
BOOST
SW
BG
PGND
SENSE–
SENSE+
TG
100k
150µF
V
OUT
12V
10A
TRACK/SS
VFB
PGOOD
High Efficiency 12V/10A Step-Down Converter
LTC3807
2
3807fa
For more information www.linear.com/LTC3807
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (VIN) ......................... –0.3V to 40V
Topside Driver Voltage (BOOST) ................ –0.3V to 46V
Switch Voltage (SW) ..................................... –5V to 40V
(BOOST-SW) ................................................ –0.3V to 6V
RUN ............................................................. –0.3V to 8V
Maximum Current Sourced into Pin from
Source > 8V ......................................................100μA
SENSE+, SENSE– Voltages ......................... –0.3V to 28V
PLLIN/MODE, INTVCC Voltages ................... –0.3V to 6V
ILIM, FREQ Voltages ..............................–0.3V to INTVCC
EXTVCC ...................................................... –0.3V to 14V
(Note 1)
20 19 18 17
7 8
TOP VIEW
21
SGND
UDC PACKAGE
20-LEAD (3mm
×
4mm) PLASTIC QFN
9 10
6
5
4
3
2
1
11
12
13
14
15
16
PLLIN/MODE
SGND
SGND
RUN
SENSE–
SENSE+
PGND
EXTVCC
INTVCC
BG
BOOST
SW
FREQ
TRACK/SS
ILIM
VIN
VFB
ITH
PGOOD
TG
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
TRACK/SS
FREQ
PLLIN/MODE
SGND
SGND
RUN
SENSE–
SENSE+
VFB
ITH
ILIM
VIN
PGND
EXTVCC
INTVCC
BG
BOOST
SW
TG
PGOOD
21
SGND
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3807EUDC#PBF LTC3807EUDC#TRPBF LGSG 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
LTC3807IUDC#PBF LTC3807IUDC#TRPBF LGSG 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
LTC3807HUDC#PBF LTC3807HUDC#TRPBF LGSG 20-Lead (3mm × 4mm) Plastic QFN –40°C to 150°C
LTC3807MPUDC#PBF LTC3807MPUDC#TRPBF LGSG 20-Lead (3mm × 4mm) Plastic QFN –55°C to 150°C
LTC3807EFE#PBF LTC3807EFE#TRPBF LTC3807FE 20-Lead Plastic TSSOP –40°C to 125°C
LTC3807IFE#PBF LTC3807IFE#TRPBF LTC3807FE 20-Lead Plastic TSSOP –40°C to 125°C
ITH, VFB Voltages ......................................... –0.3V to 6V
PGOOD Voltage ............................................ –0.3V to 6V
TRACK/SS Voltage ....................................... –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 3)
LTC3807E, LTC3807I ......................... –40°C to 125°C
LTC3807H .......................................... –40°C to 150°C
LTC3807MP ....................................... –55°C to 150°C
Maximum Junction Temperature (Notes 2, 3)
LTC3807E, LTC3807I ........................................ 125°C
LTC3807H, LTC3807MP ................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
LTC3807
3
3807fa
For more information www.linear.com/LTC3807
The l denotes the specifications which apply over the specified
operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, EXTVCC = 0V unless
otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Supply Operating Voltage Range 4 38 V
VOUT Regulated Output Voltage Range 0.8 24 V
VFB Regulated Feedback Voltage (Note 4); ITH Voltage = 1.2V
–40°C to 85°C
LTC3807E, LTC3807I
LTC3807H, LTC3807MP
l
l
0.792
0.788
0.786
0.800
0.800
0.800
0.808
0.812
0.812
V
V
V
IFB Feedback Current (Note 4) ±5 ±50 nA
Reference Voltage Line Regulation (Note 4); VIN = 4.5V to 38V 0.002 0.02 %/V
Output Voltage Load Regulation (Note 4)
Measured in Servo Loop;
∆ITH Voltage = 1.2V to 0.7V
l0.01 0.1 %
(Note 4)
Measured in Servo Loop;
∆ITH Voltage = 1.2V to 2V
l–0.01 –0.1 %
gmTransconductance Amplifier gm(Note 4); ITH = 1.2V; Sink/Source 5µA 2 mmho
IQInput DC Supply Current (Note 5)
Pulse Skip or Forced Continuous Mode VFB = 0.83V (No Load) 2 mA
Sleep Mode VFB = 0.83V (No Load) 50 75 µA
Shutdown RUN = 0V 14 25 µA
UVLO Undervoltage Lockout INTVCC Ramping Up
INTVCC Ramping Down
l
l
3.6 3.92
3.80 4.2
4.0 V
V
Feedback Overvoltage Protection Measured at VFB Relative to Regulated VFB 7 10 13 %
SENSE+ Pin Current ±1 µA
SENSE– Pins Current VSENSE– < INTVCC – 0.5V
VSENSE– > INTVCC + 0.5V
700 ±2 µA
µA
Maximum Duty Factor In Dropout 98 99 %
Soft-Start Charge Current VTRACK = 0V 7 10 14 µA
VRUN On RUN Pin On Threshold VRUN Rising l1.15 1.21 1.27 V
VRUN Hyst RUN Pin Hysteresis 50 mV
VSENSE(MAX) Maximum Current Sense Threshold VFB = 0.7V, VSENSE– = 3.3V, ILIM = 0
VFB = 0.7V, VSENSE– = 3.3V, ILIM = INTVCC
VFB = 0.7V, VSENSE– = 3.3V, ILIM = FLOAT
l
l
l
22
43
64
30
50
75
36
57
85
mV
mV
mV
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3807HFE#PBF LTC3807HFE#TRPBF LTC3807FE 20-Lead Plastic TSSOP –40°C to 150°C
LTC3807MPFE#PBF LTC3807MPFE#TRPBF LTC3807FE 20-Lead Plastic TSSOP –55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC3807
4
3807fa
For more information www.linear.com/LTC3807
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified
operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, EXTVCC = 0V unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Driver
TG Pull-Up On-Resistance
TG Pull-Down On-Resistance 2.5
1.5 Ω
Ω
BG Pull-Up On-Resistance
BG Pull-Down On-Resistance 2.4
1.1 Ω
Ω
TG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
16
ns
ns
BG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
13
ns
ns
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time CLOAD = 3300pF 30 ns
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time CLOAD = 3300pF 30 ns
tON(MIN) Minimum On-Time (Note 7) 95 ns
INTVCC Linear Regulator
Internal VCC Voltage 6V < VIN < 38V, VEXTVCC = 0V 4.85 5.1 5.35 V
INTVCC Load Regulation ICC = 0mA to 50mA, VEXTVCC = 0V 0.7 1.1 %
Internal VCC Voltage 6V < VEXTVCC < 13V 4.85 5.1 5.35 V
INTVCC Load Regulation ICC = 0mA to 50mA,
VEXTVCC = 8.5V 0.6 1.1 %
EXTVCC Switchover Voltage ICC = 0mA to 50mA,
EXTVCC Ramping Positive 4.5 4.7 4.9 V
EXTVCC Hysteresis 250 mV
Oscillator and Phase-Locked Loop
Programmable Frequency RFREQ = 25k;
PLLIN/MODE = DC Voltage 105 kHz
Programmable Frequency RFREQ = 65k;
PLLIN/MODE = DC Voltage 375 440 505 kHz
Programmable Frequency RFREQ =105k;
PLLIN/MODE = DC Voltage 835 kHz
Low Fixed Frequency VFREQ = 0V;
PLLIN/MODE = DC Voltage 320 350 380 kHz
High Fixed Frequency VFREQ = INTVCC;
PLLIN/MODE = DC Voltage 485 535 585 kHz
Synchronizable Frequency PLLIN/MODE = External Clock l75 750 kHz
PGOOD Output
PGOOD Voltage Low IPGOOD = 2mA 0.2 0.4 V
LTC3807
5
3807fa
For more information www.linear.com/LTC3807
The l denotes the specifications which apply over the specified
operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, EXTVCC = 0V unless
otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT CURRENT (A)
FIGURE 12 CIRCUIT
0
EFFICIENCY (%)
POWER LOSS (mW)
70
100
10.10.010.0010.0001 10
3807 G01
50
40
30
20 1
10
100
1000
10000
0.1
10
60
80
90
VIN = 12V
VOUT = 3.3V BURST EFFICIENCY
FCM LOSS
PULSE-SKIPPING
LOSS
BURST LOSS
FCM EFFICIENCY
PULSE-SKIPPING
EFFICIENCY
OUTPUT CURRENT (A)
0
EFFICIENCY (%)
70
100
10.10.010.0010.0001 10
3807 G02
50
40
30
20
10
60
80
90 VOUT = 8.5V
VOUT = 3.3V
VIN = 12V
Burst Mode OPERATION
FIGURES 12, 14 CIRCUITS
INPUT VOLTAGE (V)
80
EFFICIENCY (%)
94
100
20 30 35 40151050 25
3807 G03
90
88
86
84
82
92
96
98
VOUT = 3.3V
VOUT = 8.5V
ILOAD = 2A
FIGURES 12, 14 CIRCUITS
Efficiency and Power Loss vs
Output Current Efficiency vs Output Current Efficiency vs Input Voltage
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3807 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3807E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3807I is guaranteed
over the –40°C to 125°C operating junction temperature range, the
LTC3807H is guaranteed over the –40°C to 150°C operating junction
temperature range and the LTC3807MP is tested and guaranteed over
the –55°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes; operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors.
Note 3: The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according to
the formula:
TJ = TA + (PD • θJA), where θJA is 43°C/W for the QFN or 38°C/W for the
TSSOP.
Note 4: The LTC3807 is tested in a feedback loop that servos VITH to a
specified voltage and measures the resultant VFB. The specification at
85°C is not tested in production and is assured by design, characterization
and correlation to production testing at other temperatures (125°C for
the LTC3807E/LTC3807I, 150°C for the LTC3807H/LTC3807MP). For the
LTC3807MP, the specification at –40°C is not tested in production and is
assured by design, characterization and correlation to production testing
at –55°C.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥ 40% of IMAX (See Minimum On-Time
Considerations in the Applications Information section).
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PGOOD Leakage Current VPGOOD = 5V ±1 µA
PGOOD Trip Level VFB with Respect to Set Regulated Voltage
VFB Ramping Negative –13 –10 –7 %
Hysteresis 2.5 %
VFB Ramping Positive 7 10 13 %
Hysteresis 2.5 %
Delay for Reporting a Fault 25 µs
LTC3807
6
3807fa
For more information www.linear.com/LTC3807
TYPICAL PERFORMANCE CHARACTERISTICS
IOUT (A)
0
EFFICIENCY (%)
70
100
10.10.010.0010.0001
10
3807 G28
50
40
30
20
10
60
80
90 Burst Mode OPERATION
PULSE SKIP
Mode
FC Mode
VIN = 24V
VOUT = 12V
FIGURE 13 CIRCUIT
Efficiency vs Output Current
Load Step
Forced Continuous Mode Start-Up
VIN = 12V
VOUT = 3.3V
ILOAD = 200µA
5µs/DIV 3807 G07
FORCED
CONTINUOUS
MODE
PULSE-SKIPPING
MODE
Burst Mode
OPERATION
1A/DIV
Inductor Current at Light Load Soft Start-Up Tracking Start-Up
FIGURES 12, 14 CIRCUITS
2ms/DIV 3807 G08
VOUT = 3.3V
2V/DIV
VOUT = 8.5V
2V/DIV
2ms/DIV 3807 G09
VOUT 2V/DIV
FIGURE 12, 14 CIRCUITS
TRACKING RESISTORS ADDED
TO FIGURE 12 CIRCUIT
MASTER
2V/DIV
Load Step
Burst Mode Operation
Load Step
Forced Continuous Mode
Load Step
Pulse-Skipping Mode
LOAD STEP = 100mA TO 3A
VIN = 12V
VOUT = 3.3V
FIGURE 12 CIRCUIT
50µs/DIV 3807 G04
VOUT
100mV/DIV
AC-
COUPLED
IL
2A/DIV
LOAD STEP = 100mA TO 3A
VIN = 12V
VOUT = 3.3V
FIGURE 12 CIRCUIT
50µs/DIV 3807 G05
VOUT
100mV/DIV
AC-
COUPLED
IL
2A/DIV
LOAD STEP = 300mA TO 7A
VIN = 24V
VOUT = 12V
FIGURE 13 CIRCUIT
100µs/DIV 3807 G29
VOUT
500mV/DIV
AC-
COUPLED
IL
5A/DIV
VIN = 24V
VOUT = 12V
FIGURE 13 CIRCUIT
2ms/DIV
3807 G30
VOUT
5V/DIV
RUN
5V/DIV
PGOOD
5V/DIV
LOAD STEP = 100mA TO 3A
VIN = 12V
VOUT = 3.3V
FIGURE 12 CIRCUIT
50µs/DIV 3807 G06
VOUT
100mV/DIV
AC-
COUPLED
IL
2A/DIV
LTC3807
7
3807fa
For more information www.linear.com/LTC3807
TYPICAL PERFORMANCE CHARACTERISTICS
VITH (V)
0
CURRENT SENSE THESHOLD (mV)
40
60
80
0.6 1.0
3807 G13
20
0
0.2 0.4 0.8 1.2 1.4
–20
–40
Burst Mode
OPERATION
PULSE-SKIPPING MODE
5% DUTY CYCLE
FORCED CONTINUOUS MODE
ILIM = FLOAT
ILIM = INTVCC
ILIM = GND
VSENSE COMMON MODE VOLTAGE (V)
0
SENSE– CURRENT (µA)
20
3807 G14
400
300
10 155 25
800
700
600
500
200
100
0
–100
DUTY CYCLE (%)
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
50
40
60
70
80
3807 G15
30
20 20 40 50 100
80
60
10 30 90
70
ILIM = FLOAT
ILIM = INTVCC
ILIM = GND
FEEDBACK VOLTAGE (MV)
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
40
60
800
3807 G16
20
0200 400 500
80
30
50
10
70
600
100 300 700
ILIM = FLOAT
ILIM = INTVCC
ILIM = GND
TEMPERATURE (°C)
–75
QUIESCENT CURRENT (µA)
75
50250
3807 G17
60
50
–50 –25 75
45
30
40
35
80
70
65
55
100 125 150
VIN = 12V
Burst Mode OPERATION
Maximum Current Sense Voltage
vs ITH Voltage SENSE– Pin Input Bias Current
Maximum Current Sense
Threshold vs Duty Cycle
Foldback Current Limit Quiescent Current vs Temperature INTVCC vs INTVCC Load Current
TEMPERATURE (°C)
–75
REGULATED FEEDBACK VOLTAGE (mV)
806
0 25 50
3807 G21
800
796
–50 –25 75
794
792
808
804
802
798
100 125 150
TRACK/SS Pull-Up Current
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
Regulated Feedback Voltage
vs Temperature
INTVCC LOAD CURRENT (mA)
0
INTVCC VOLTAGE (V)
5.25
40
3807 G18
4.50
20 60
4.00
5.50
5.00
4.75
4.25
80 100
EXTVCC = 5V
EXTVCC = 8.5V
EXTVCC = 0V
VIN = 12V
TEMPERATURE (°C)
–75
TRACK/SS CURRENT (µA)
11.5
5025
3807 G19
10.0
–25 0–50 75
12.0
11.0
10.5
9.5
9.0
8.5
8.0 125100 150
TEMPERATURE (°C)
–75
RUN PIN VOLTAGE (V)
500 25
3807 G20
1.20
–25–50 75
1.30
1.25
1.15
1.10 125100 150
RUN RISING
RUN FALLING
LTC3807
8
3807fa
For more information www.linear.com/LTC3807
TEMPERATURE (°C)
–75
INTVCC VOLTAGE (V)
3.7
3.8
3.9
4.1
–25 75 100
3807 G25
3.6
4.2
4.0
–50 0 25 50 125 150
FALLING
RISING
INPUT VOLTAGE (V)
344
OSCILLATOR FREQUENCY (kHz)
348
350
356
20 30 35 4015105 25
3807 G26
346
352
354
FREQ = GND
TEMPERATURE (°C)
8
SHUTDOWN CURRENT (µA)
12
14
22
20
25 50 75 100 125 150–25–75 –50 0
3807 G27
10
16
18
VIN = 12V
Undervoltage Lockout Threshold
vs Temperature
Oscillator Frequency vs Input
Voltage Shutdown Current vs Temperature
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT VOLTAGE (V)
0
SHUTDOWN CURRENT (µA)
10
15
30
25
20 30 35 4015105 25
3807 G23
5
20
TEMPERATURE (°C)
–75
FREQUENCY (kHz)
500
550
600
0 25 50 100
3807 G24
450
400
–50 –25 75 125 150
350
300
FREQ = GND
FREQ = INTVCC
SENSE– Pin Input Bias Current
vs Temperature
Shutdown Current vs Input
Voltage
Oscillator Frequency
vs Temperature
TEMPERATURE (°C)
–75
SENSE– CURRENT (µA)
50250
3807 G22
400
300
–25–50 75
800
700
600
500
200
100
0
–100 125100 150
VOUT > INTVCC + 0.5V
VOUT < INTVCC – 0.5V
INPUT VOLTAGE (V)
0
SUPPLY CURRENT (µA)
200
300
20 30 35 4015105 25
3807 G10
150
100
50
250
NO LOAD
300µA LOAD
FIGURE 12 CIRCUIT
TEMPERATURE (°C)
–75
4.0
EXTVCC AND INTVCC VOLTAGE (V)
4.2
4.6
4.8
5.0
6.0
5.4
–25 25 50 75 100
3807 G11
4.4
5.6
5.8
5.2
–50 0125 150
INTVCC
EXTVCC RISING
EXTVCC FALLING
Total Input Supply Current vs
Input Voltage
EXTVCC Switchover and INTVCC
Voltages vs Temperature INTVCC vs INTVCC Load Current
INTVCC LOAD CURRENT (mA)
3.5
INTVCC (V)
4.1
4.3
4.7
4.5
4.9
5.5
20 30 10040 50 60 70 9080100
3807 G12
3.7
3.9
5.3
5.1
VIN = 5.5V
VIN = 5V
LTC3807
9
3807fa
For more information www.linear.com/LTC3807
PIN FUNCTIONS
PLLIN/MODE (Pin 1/Pin 3): External Synchronization
Input to Phase Detector and Forced Continuous Mode
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG signal to be
synchronized with the rising edge of the external clock,
and the regulator operates in forced continuous mode.
When not synchronizing to an external clock, this input
determines how the LTC3807 operates at light loads. Pull-
ing this pin to ground selects Burst Mode operation. An
internal 100k resistor to ground also invokes Burst Mode
operation when the pin is floated. Tying this pin to INTVCC
forces continuous inductor current operation. Tying this
pin to a voltage greater than 1.2V and less than INTVCC
–1.3V selects pulse-skipping operation.
SGND (Pins 2, 3, Exposed Pad Pin 21/Pins 4, 5,
Exposed Pad Pin 21): Small-signal ground, must be routed
separately from high current grounds to the common (–)
terminals of the CIN capacitor. Pins 2, 3/4, 5, must both be
electrically connected to small signal ground for proper
operation. The exposed pad must be soldered to PCB
ground for rated thermal performance.
RUN (Pin 4/Pin 6): Run Control Input. Forcing this pin
below 1.16V shuts down the controller. Forcing this pin
below 0.7V shuts down the entire LTC3807, reducing
quiescent current to approximately 14µA.
SENSE– (Pin 5/Pin 7): The (–) Input to the Differential
Current Comparator. When greater than INTVCC – 0.5V, the
SENSE– pin supplies power to the current comparator.
SENSE+ (Pin 6/Pin 8): The (+) input to the differential
current comparator is normally connected to DCR sensing
network or current sensing resistor. The ITH pin voltage and
controlled offsets between the SENSE– and SENSE+ pins in
conjunction with RSENSE set the current trip threshold.
VFB (Pin 7/Pin 9): Receives the remotely sensed feed-
back voltage from an external resistive divider across
the output.
ITH (Pin 8/Pin 10): Error Amplifier Outputs and Switching
Regulator Compensation Point. The current comparator
trip point increases with this control voltage.
PGOOD (Pin 9/Pin 11): Open-Drain Logic Output. PGOOD
is pulled to ground when the voltage on the VFB pin is not
within 10% of its set point.
TG (Pin 10/Pin 12): High Current Gate Drives for Top
N-channel MOSFET. This is the output of floating driver
with a voltage swing equal to INTVCC superimposed on
the switch node voltage SW.
SW (Pin 11/ Pin 13): Switch Node Connection to Induc-
tor.
BOOST (Pin 12/Pin 14): Bootstrapped Supply to the Top-
side Floating Driver. A capacitor is connected between the
BOOST and SW pin and a Schottky diode is tied between
the BOOST and INTVCC pins. Voltage swing at the BOOST
pin is from INTVCC to (VIN + INTVCC).
BG (Pin 13/Pin 15): High Current Gate Drive for Bottom
(Synchronous) N-channel MOSFET. Voltage swing at this
pin is from ground to INTVCC.
INTVCC (Pin 14/Pin 16): Output of the Internal Linear
Low Dropout Regulator. The driver and control circuits
are powered from this voltage source. Must be decoupled
to PGND with a minimum of 2.2µF ceramic or other low
ESR capacitor. Do not use the INTVCC pin for any other
purpose.
(QFN/TSSOP)
LTC3807
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For more information www.linear.com/LTC3807
PIN FUNCTIONS
EXTVCC (Pin 15/Pin 17): External Power Input to an
Internal LDO Connected to INTVCC. This LDO supplies
INTVCC power, bypassing the internal LDO powered from
VIN whenever EXTVCC is higher than 4.7V. See EXTVCC
Connection in the Applications Information section. Do
not float or exceed 14V on this pin. Connect to ground
(SGND or PGND) if not used.
PGND (Pin 16/Pin 18): Driver Power Ground. Connects to
the source of bottom (synchronous) N-channel MOSFET
and the (–) terminal of CIN.
VIN (Pin 17/Pin 19): Main Supply Pin. A bypass capacitor
should be tied between this pin and the SGND pins.
ILIM (Pin 18/Pin 20): Current Comparator Sense Voltage
Range Inputs. Tying this pin to SGND, FLOAT or INTVCC
sets the maximum current sense threshold to one of three
different levels for the comparator.
TRACK/SS (Pin 19/Pin 1): External Tracking and Soft-Start
Input. The LTC3807 regulates the VFB voltage to the smaller
of 0.8V or the voltage on the TRACK/SS pin. An internal
10μA pull-up current source is connected to this pin. A
capacitor to ground at this pin sets the ramp time to final
regulated output voltage. Alternatively, a resistor divider
on another voltage supply connected to this pin allows the
LTC3807 output to track another supply during start-up.
FREQ (Pin 20/Pin 2): The frequency control pin for the
internal VCO. Connecting the pin to GND forces the VCO
to a fixed low frequency of 350kHz. Connecting the pin
to INTVCC forces the VCO to a fixed high frequency of
535kHz. Other frequencies between 50kHz and 900kHz
can be programmed by using a resistor between FREQ
and GND. An internal 20µA pull-up current develops the
voltage to be used by the VCO to control the frequency.
LTC3807
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For more information www.linear.com/LTC3807
FUNCTIONAL DIAGRAM
SW
TOP
BOOST
TG CB
CIN
D
DB
PGND
BOT BG
INTVCC
INTVCC
VIN
C
OUT
V
OUT
3807 FD
RSENSE
DROP
OUT
DET BOT
TOP ON
S
R
Q
Q
SHDN
SLEEP
0.425V
ICMP
2.7V
0.65V
IR
2mV
SLOPE COMP
SENSE+
SENSE–
PGOOD
VFB
0.88V
0.72V
L
+
–
+
–
FREQ
+
–
+
–
+
–
–
+
+
+
–
+
–
SWITCH
LOGIC
VFB
RA
CC
RC
CC2
RB
0.80V
TRACK/SS
0.88V
7µA
11V
RUN
ITH
TRACK/SS
+
–
CSS
10µA
SHDN
CURRENT
LIMIT
FOLDBACK
SHDN
RST
2(VFB)
PLLIN/MODE
20µA
VCO
LDO
EN
INTVCC
5.1V
SYNC
DET
100k
CLK2
CLK1
ILIM
VIN
EXTVCC
LDO
PFD
EN
4.7V
5.1V
+
–
SGND
EA
OV
LTC3807
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For more information www.linear.com/LTC3807
OPERATION
Main Control Loop
The LTC3807 uses a constant frequency, current mode
step-down architecture. During normal operation, the
external top MOSFET is turned on when the clock for
that channel sets the RS latch, and is turned off when the
main current comparator, ICMP, resets the RS latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifier, EA. The error amplifier
compares the output voltage feedback signal at the VFB
pin (which is generated with an external resistor divider
connected across the output voltage, VOUT, to ground)
to the internal 0.800V reference voltage. When the load
current increases, it causes a slight decrease in VFB rela-
tive to the reference, which causes the EA to increase the
ITH voltage until the average inductor current matches
the new load current.
After the top MOSFET is turned off each cycle, the bottom
MOSFET is turned on until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is tied to a voltage less than 4.7V,
the VIN LDO (low dropout linear regulator) supplies 5.1V
from VIN to INTVCC. If EXTVCC is taken above 4.7V, the VIN
LDO is turned off and an EXTVCC LDO is turned on. Once
enabled, the EXTVCC LDO supplies 5.1V from EXTVCC to
INTVCC. Using the EXTVCC pin allows the INTVCC power
to be derived from a high efficiency external source such
as the LTC3807 switching regulator output.
The top MOSFET driver is biased from the floating bootstrap
capacitor, CB, which normally recharges during each cycle
through an external diode when the top MOSFET turns
off. If the input voltage, VIN, decreases to a voltage close
to VOUT, the loop may enter dropout and attempt to turn
on the top MOSFET continuously. The dropout detector
detects this and forces the top MOSFET off for about one
twelfth of the clock period every tenth cycle to allow CB
to recharge.
Shutdown and Start-Up (RUN, TRACK/SS Pins)
The LTC3807 can be shut down using the RUN pin. Pulling
this pin below 1.16V shuts down the main control loop.
Pulling the RUN pin below 0.7V disables the controller and
most internal circuits, including the INTVCC LDOs. In this
state, the LTC3807 draws only 14μA of quiescent current.
Releasing the RUN pin allows a small internal current to
pull up the pin to enable the controller. The RUN pin has
a 7μA pull-up which is designed to be large enough so
that the RUN pin can be safely floated (to always enable
the controller) without worry of condensation or other
small board leakage pulling the pin down. This is ideal
for always-on applications where the controller is enabled
continuously and never shut down.
The RUN pin may be externally pulled up or driven directly
by logic. When driving the RUN pin with a low impedance
source, do not exceed the absolute maximum rating of
8V. The RUN pin has an internal 11V voltage clamp that
allows the RUN pin to be connected through a resistor to a
higher voltage (for example, VIN), so long as the maximum
current into the RUN pin does not exceed 100μA.
The RUN pin can also be implemented as a UVLO by
connecting it to the output of an external resistor divider
network off VIN (see Applications Information section).
The start-up of the controller’s output voltage VOUT is
controlled by the voltage on the TRACK/SS pin. When the
voltage on the TRACK/SS pin is less than the 0.8V internal
reference, the LTC3807 regulates the VFB voltage to the
TRACK/SS pin voltage instead of the 0.8V reference. This
allows the TRACK/SS pin to be used to program a soft-start
by connecting an external capacitor from the TRACK/SS
pin to SGND. An internal 10μA pull-up current charges
this capacitor creating a voltage ramp on the TRACK/SS
pin. As the TRACK/SS voltage rises linearly from 0V to
0.8V (and beyond up to about 5V), the output voltage VOUT
rises smoothly from zero to its final value. Alternatively
the TRACK/SS pin can be used to cause the start-up of
VOUT to track that of another supply. Typically, this requires
connecting to the TRACK/SS pin an external resistor
divider from the other supply to ground (see Applications
Information section).
LTC3807
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For more information www.linear.com/LTC3807
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode)
(PLLIN/MODE Pin)
The LTC3807 can be enabled to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping mode,
or forced continuous conduction mode at low load cur-
rents. To select Burst Mode operation, tie the PLLIN/MODE
pin to SGND. To select forced continuous operation, tie
the PLLIN/MODE pin to INTVCC. To select pulse-skipping
mode, tie the PLLIN/MODE pin to a DC voltage greater
than 1.2V and less than INTVCC – 1.3V.
When the controller is enabled for Burst Mode opera-
tion, the minimum peak current in the inductor is set to
approximately 25% of the maximum sense voltage even
though the voltage on the ITH pin indicates a lower value.
If the average inductor current is higher than the load cur-
rent, the error amplifier, EA, will decrease the voltage on
the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.450V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3807 draws to
only 50μA. In sleep mode, the load current is supplied by
the output capacitor. As the output voltage decreases, the
EA’s output begins to rise. When the output voltage drops
enough, the ITH pin is reconnected to the output of the
EA, the sleep signal goes low, and the controller resumes
normal operation by turning on the top external MOSFET
on the next cycle of the internal oscillator.
When the controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator, IR, turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus, the
controller operates in discontinuous operation.
In forced continuous operation or clocked by an external
clock source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop section), the inductor
current is allowed to reverse at light loads or under large
transient conditions. The peak inductor current is deter-
OPERATION
mined by the voltage on the ITH pin, just as in normal
operation. In this mode, the efficiency at light loads is
lower than in Burst Mode operation. However, continu-
ous operation has the advantage of lower output voltage
ripple and less interference to audio circuitry. In forced
continuous mode, the output ripple is independent of
load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3807 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator, ICMP, may remain tripped for several
cycles and force the external top MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
Frequency Selection and Phase-Locked Loop (FREQ
and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3807 can be selected
using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied
to INTVCC or programmed through an external resistor.
Tying FREQ to SGND selects 350kHz while tying FREQ to
INTVCC selects 535kHz. Placing a resistor between FREQ
and SGND allows the frequency to be programmed between
50kHz and 900kHz, as shown in Figure 9.
A phase-locked loop (PLL) is available on the LTC3807
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3807
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For more information www.linear.com/LTC3807
LTC3807’s phase detector adjusts the voltage (through an
internal lowpass filter) of the VCO input to align the turn-on
of the controller’s external top MOSFET to the rising edge
of the synchronizing signal.
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the phase-locked loop is from
approximately 55kHz to 900kHz, with a guarantee to be
between 75kHz and 750kHz. In other words, the LTC3807’s
PLL is guaranteed to lock to an external clock source whose
frequency is between 75kHz and 750kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling). It is recommended
that the external clock source swing from ground (0V) to
at least 2.5V.
Output Overvoltage Protection
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that may
overvoltage the output. When the VFB pin rises by more
than 10% above its regulation point of 0.800V, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good Pin
The PGOOD pin is connected to an open drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the VFB pin voltage is not within ±10%
of the 0.8V reference voltage. The PGOOD pin is also pulled
low when the RUN pin is low (shut down). When the VFB
pin voltage is within the ±10% requirement, the MOSFET
is turned off and the pin is allowed to be pulled up by an
external resistor to a source no greater than 6V.
Foldback Current
When the output voltage falls to less than 70% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the VFB voltage is keeping up with the
TRACK/SS voltage).
OPERATION
LTC3807
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For more information www.linear.com/LTC3807
The Typical Application on the first page is a basic LTC3807
application circuit. LTC3807 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value. Next, the
power MOSFETs and Schottky diodes are selected. Finally,
input and output capacitors are selected.
Current Limit Programming
The ILIM pin is a tri-level logic input which sets the maximum
current limit of the controller. When ILIM is grounded, the
maximum current limit threshold voltage of the current
comparator is programmed to be 30mV. When ILIM is
floated, the maximum current limit threshold is 75mV.
When ILIM is tied to INTVCC, the maximum current limit
threshold is set to 50mV.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the cur-
rent comparators. The common mode voltage range on
these pins is 0V to 28V (abs max), enabling the LTC3807
to regulate output voltages up to a nominal 24V (allowing
margin for tolerances and transients).
The SENSE+ pin is high impedance over the full common
mode range, drawing at most ±1μA. This high impedance
allows the current comparators to be used in inductor
DCR sensing.
The impedance of the SENSE– pin changes depending on
the common mode voltage. When SENSE– is less than
INTVCC – 0.5V, a small current of less than 1μA flows out
of the pin. When SENSE– is above INTVCC + 0.5V, a higher
current (~700μA) flows into the pin. Between INTVCC – 0.5V
and INTVCC + 0.5V, the current transitions from the smaller
current to the higher current.
APPLICATIONS INFORMATION
Filter components mutual to the sense lines should be
placed close to the LTC3807, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If inductor DCR
sensing is used (Figure 2b), resistor R1 should be placed
close to the switching node, to prevent noise from coupling
into sensitive small-signal nodes.
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
COUT
TO SENSE FILTER,
NEXT TO THE CONTROLLER
INDUCTOR OR RSENSE
3807 F01
VIN VIN
RSENSE
INTVCC
BOOST
TG
SW
BG
PLACE CAPACITOR NEAR
SENSE PINS
SENSE+
SENSE–
SGND
LTC3807
VOUT
3807 F02a
*R1 AND C1 ARE OPTIONAL
C1*
R1*
VIN VIN
INTVCC
BOOST
TG
SW
BG
*PLACE C1 NEAR
SENSE PINS
INDUCTOR
DCRL
SENSE+
SENSE–
SGND
LTC3807
VOUT
3807 F02b
R1
R2C1*
(R1||R2) • C1 = L
DCR RSENSE(EQ) = DCR R2
R1 + R2
Figure 2. Current Sensing Methods
(2b) Using the Inductor DCR to Sense Current
(2a) Using a Resistor to Sense Current
LTC3807
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For more information www.linear.com/LTC3807
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current.
The current comparator has a maximum threshold
VSENSE(MAX) determined by the ILIM setting. The current
comparator threshold voltage sets the peak of the induc-
tor current, yielding a maximum average output current,
IMAX, equal to the peak value less half the peak-to-peak
ripple current, ∆IL. To calculate the sense resistor value,
use the equation:
RSENSE =
V
SENSE(MAX)
IMAX +DIL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the Maximum Current Sense Threshold
(VSENSE(MAX)) in the Electrical Characteristics table (30mV,
50mV or 75mV, depending on the state of the ILIM pin).
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due
to the internal compensation required to meet stability
criterion for buck regulators operating at greater than
50% duty factor. A curve is provided in the Typical Perfor-
mance Characteristics section to estimate this reduction
in peak inductor current depending upon the operating
duty factor.
Inductor DCR Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC3807 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC resistance of the copper wire, which can be
less than 1mΩ for today’s low value, high current inductors.
In a high current application requiring such an inductor,
power loss through a sense resistor would cost several
points of efficiency compared to inductor DCR sensing.
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult the
manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor
value is:
RSENSE(EQUIV) =
V
SENSE(MAX)
IMAX +DIL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the Maximum Current Sense Threshold
(VSENSE(MAX)) in the Electrical Characteristics table (30mV,
50mV or 75mV, depending on the state of the ILIM pin).
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value (RD), use the divider ratio:
RD=
R
SENSE(EQUIV)
DCRMAX atTL(MAX)
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1 || R2 to around 2k, reducing error that might
have been caused by the SENSE+ pin’s ±1μA current.
APPLICATIONS INFORMATION
LTC3807
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The equivalent resistance R1 || R2 is scaled to the tem-
perature inductance and maximum DCR:
R1||R2=
L
DCR at 20°C
( )
•C1
The sense resistor values are:
R1=
R1||R2
R
D
; R2=
R1•R
D
1–R
D
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
PLOSS R1=VIN(MAX) – VOUT
( )
•VOUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET switching and gate charge losses. In addition to
this basic trade-off, the effect of inductor value on ripple
current and low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current, ∆IL, decreases with higher
inductance or higher frequency and increases with higher
VIN:
DIL=1
f
( )
L
( )
VOUT 1– VOUT
VIN
Accepting larger values of ∆IL allows the use of low in-
ductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ∆IL = 0.3(IMAX). The maximum ∆IL occurs
at the maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates hard, which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
APPLICATIONS INFORMATION
LTC3807
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Power MOSFET and Schottky Diode (Optional)
Selection
Two external power MOSFETs must be selected for the
LTC3807 controller: one N-channel MOSFET for the top
(main) switch, and one N-channel MOSFET for the bottom
(synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC
voltage. This voltage is typically 5.1V during start-up
(see EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
Pay close attention to the BVDSS specification for the
MOSFETs as well.
Selection criteria for the power MOSFETs include the on-
resistance, RDS(ON), Miller capacitance, CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle=
V
OUT
VIN
Synchronous Switch Duty Cycle=VIN −VOUT
V
IN
The MOSFET power dissipations at maximum output
current are given by:
PMAIN =
V
OUT
VIN
IMAX
( )
21+δ
( )
RDS(ON) +
VIN
( )
2IMAX
2
RDR
( )
CMILLER
( )
•
1
VINTVCC – VTHMIN
+1
VTHMIN
f
( )
PSYNC =VIN – VOUT
V
IN
IMAX
( )
21+δ
( )
RDS(ON)
APPLICATIONS INFORMATION
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1+ δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
A Schottky diode can be inserted in parallel with the bot-
tom MOSFET to conduct during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on,
storing charge during the dead-time and requiring a
reverse recovery period that could cost as much as 3%
in efficiency at high VIN. A 1A to 3A Schottky is generally
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
CIN and COUT Selection
The selection of CIN is usually based off the worst-case RMS
input current. The highest (VOUT)(IOUT) product needs to
be used in the formula shown in Equation 1 to determine
the maximum RMS capacitor current requirement.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
LTC3807
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APPLICATIONS INFORMATION
maximum RMS current must be used. The maximum RMS
capacitor current is given by:
CIN Required IRMS ≈
I
MAX
V
IN
VOUT
( )
VIN – VOUT
( )
1/2
(1)
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3807, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
A small (0.1μF to 1μF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3807, is also
suggested. A small (≤10Ω) resistor placed between CIN
(C1) and the VIN pin provides further isolation.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
DVOUT ≈ DILESR+1
8• f•COUT
where f is the operating frequency, COUT is the output
capacitance and ∆IL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ∆IL increases with input voltage.
Setting Output Voltage
The LTC3807 output voltage is set by an external feedback
resistor divider carefully placed across the output, as shown
in Figure 3. The regulated output voltage is determined by:
VOUT =0.8V 1+RB
RA
To improve the frequency response, a feedforward ca-
pacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
RUN Pin
The LTC3807 is enabled using the RUN pin. It has a rising
threshold of 1.21V with 50mV of hysteresis. Pulling the
RUN pin below 1.16V shuts down the main control loop.
Pulling it below 0.7V disables the controller and most
internal circuits, including the INTVCC LDOs. In this state,
the LTC3807 draws only 14μA of quiescent current.
Releasing the RUN pin allows a 7μA internal current to
pull up the pin to enable the controller. The RUN pin may
be externally pulled up or driven directly by logic. When
driving the RUN pin with a low impedance source, do not
exceed the absolute maximum rating of 8V. The RUN pin
has an internal 11V voltage clamp that allows the RUN pin
to be connected through a resistor to a higher voltage (for
example, VIN), so long as the maximum current into the
RUN pin does not exceed 100μA.
The RUN pin can be implemented as a UVLO by connecting
it to the output of an external resistor divider network off
VIN, as shown in Figure 4.
LTC3807
VFB
VOUT
RBCFF
RA
3807 F03
Figure 3. Setting Output Voltage
LTC3807
RUN
VIN
RB
RA
3807 F04
Figure 4. Using the RUN Pin as a UVLO
LTC3807
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The rising and falling UVLO thresholds are calculated using
the RUN pin thresholds:
VUVLO(RISING) =1.21V 1+
R
B
R
A
–7µA •RB
VUVLO(FALLING) =1.16V 1+
R
B
R
A
–7µA •RB
The resistor values should be carefully chosen such that
the absolute maximum ratings of the RUN pin do not get
violated over the entire VIN voltage range.
Tracking and Soft-Start (TRACK/SS Pin)
The start-up of VOUT is controlled by the voltage on the
TRACK/SS pin. When the voltage on the TRACK/SS pin is
less than the internal 0.8V reference, the LTC3807 regulates
the VFB pin voltage to the voltage on the TRACK/SS pin
instead of 0.8V. The TRACK/SS pin can be used to program
an external soft-start function or to allow VOUT to track
another supply during start-up.
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 5.
An internal 10μA current source charges the capacitor,
providing a linear ramping voltage at the TRACK/SS pin.
The LTC3807 will regulate the VFB pin (and hence VOUT)
according to the voltage on the TRACK/SS pin, allowing
VOUT to rise smoothly from 0V to its final regulated value.
The total soft-start time will be approximately:
tSS =CSS •
0.8V
10µA
APPLICATIONS INFORMATION
pin of the slave supply (VOUT), as shown in Figure 7.
During start-up VOUT will track VX according to the ratio
set by the resistor divider:
V
X
VOUT
=
R
A
RTRACKA
•
R
TRACKA
+R
TRACKB
RA+RB
For coincident tracking (VOUT = VX during start-up):
RA = RTRACKA
RB = RTRACKB
Figure 5. Using the TRACK/SS Pin to Program Soft-Start
LTC3807
TRACK/SS
CSS
SGND
3807 F05
Alternatively, the TRACK/SS pin can be used to track
another supply during start-up, as shown qualitatively in
Figures 6a and 6b. To do this, a resistor divider should be
connected from the master supply (VX) to the TRACK/SS
TIME
VX(MASTER)
VOUT(SLAVE)
OUTPUT VOLTAGE
3807 F06a
TIME 3807 F06b
VX(MASTER)
VOUT(SLAVE)
OUTPUT VOLTAGE
(6a) Coincident Tracking
(6b) Ratiometric Tracking
Figure 6. Two Different Modes of Output Voltage Tracking
LTC3807
VOUT
Vx
VFB
TRACK/SS
3807 F07
RB
RA
RTRACKA
RTRACKB
Figure 7. Using the TRACK/SS Pin for Tracking
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INTVCC Regulators
The LTC3807 features two separate internal P-channel low
dropout linear regulators (LDO) that supply power at the
INTVCC pin from either the VIN supply pin or the EXTVCC
pin depending on the connection of the EXTVCC pin. INTVCC
powers the gate drivers and much of the LTC3807’s internal
circuitry. The VIN LDO and the EXTVCC LDO regulate INTVCC
to 5.1V. Each of these can supply a peak current of at least
50mA and must be bypassed to ground with a minimum
of 2.2μF ceramic capacitor. No matter what type of bulk
capacitor is used, an additional 1μF ceramic capacitor
placed directly adjacent to the INTVCC and PGND pins is
highly recommended. Good bypassing is needed to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between the channels.
High input voltage applications in which large MOSFETs are
being driven at high frequencies may cause the maximum
junction temperature rating for the LTC3807 to be exceeded.
The INTVCC current, which is dominated by the gate charge
current, may be supplied by either the VIN LDO or the
EXTVCC LDO. When the voltage on the EXTVCC pin is less
than 4.7V, the VIN LDO is enabled. Power dissipation for the
IC in this case is highest and is equal to VIN • IINTVCC. The
gate charge current is dependent on operating frequency
as discussed in the Efficiency Considerations section.
The junction temperature can be estimated by using the
equations given in Note 3 of the Electrical Characteristics.
For example, the LTC3807 INTVCC current is limited to less
than 32mA from a 40V supply when not using the EXTVCC
supply at a 70°C ambient temperature:
TJ = 70°C + (32mA)(40V)(43°C/W for QFN) = 125°C
To prevent the maximum junction temperature from be-
ing exceeded, the input supply current must be checked
while operating in forced continuous mode (PLLIN/MODE
= INTVCC) at maximum VIN.
When the voltage applied to EXTVCC rises above 4.7V, the
VIN LDO is turned off and the EXTVCC LDO is enabled. The
EXTVCC LDO remains on as long as the voltage applied to
EXTVCC remains above 4.5V. The EXTVCC LDO attempts
to regulate the INTVCC voltage to 5.1V, so while EXTVCC
is less than 5.1V, the LDO is in dropout and the INTVCC
voltage is approximately equal to EXTVCC. When EXTVCC
is greater than 5.1V, up to an absolute maximum of 14V,
INTVCC is regulated to 5.1V.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from the LTC3807’s switch-
ing regulator output (4.7V ≤ VOUT ≤ 14V) during normal
operation and from the VIN LDO when the output is out
of regulation (e.g., start-up, short-circuit). If more current
is required through the EXTVCC LDO than is specified, an
external Schottky diode can be added between the EXTVCC
and INTVCC pins. In this case, do not apply more than 6V
to the EXTVCC pin and make sure that EXTVCC ≤ VIN.
Significant efficiency and thermal gains can be realized
by powering INTVCC from the output, since the VIN cur-
rent resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
For 5V to 14V regulator outputs, this means connecting
the EXTVCC pin directly to VOUT. Tying the EXTVCC pin to
an 8.5V supply reduces the junction temperature in the
previous example from 125°C to:
TJ = 70°C + (32mA)(8.5V)(43°C/W) = 82°C
However, for 3.3V and other low voltage outputs, addi-
tional circuitry is required to derive INTVCC power from
the output.
The following list summarizes the four possible connec-
tions for EXTVCC:
1. EXTVCC Grounded. This will cause INTVCC to be powered
from the internal 5.1V regulator resulting in an efficiency
penalty of up to 10% at high input voltages.
2. EXTVCC Connected Directly to VOUT. This is the normal
connection for a 5V to 14V regulator and provides the
highest efficiency.
3. EXTVCC Connected to an External Supply. If an external
supply is available in the 5V to 14V range, it may be
used to power EXTVCC providing it is compatible with
the MOSFET gate drive requirements. Ensure that
EXTVCC < VIN.
APPLICATIONS INFORMATION
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4. EXTVCC Connected to an Output-Derived Boost Network.
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with the capacitive charge
pump shown in Figure 8. Ensure that EXTVCC < VIN.
APPLICATIONS INFORMATION
Topside MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor, CB, connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFET. Capacitor CB in the Functional Diagram is charged
though external diode DB from INTVCC when the SW pin
is low. When the topside MOSFET is to be turned on, the
driver places the CB voltage across the gate-source of
the MOSFET. This enhances the top MOSFET switch and
turns it on. The switch node voltage, SW, rises to VIN and
the BOOST pin follows. With the topside MOSFET on, the
boost voltage is above the input supply: VBOOST = VIN +
VINTVCC. The value of the boost capacitor, CB, needs to be
100 times that of the total input capacitance of the top-
side MOSFET(s). The reverse breakdown of the external
Schottky diode must be greater than VIN(MAX).
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the efficiency has
improved. If there is no change in input current, then there
is no change in efficiency.
EXTVCC
VIN
TG
SW
BG
PGND
LTC3807 RSENSE VOUT
NDS7002
COUT
3807 F08
MBOT
MTOP
CIN
L
BAT85 BAT85
BAT85
Figure 8. Capacitive Charge Pump for EXTVCC
Fault Conditions: Current Limit and Current Foldback
The LTC3807 includes current foldback to help limit
load current when the output is shorted to ground. If
the output voltage falls below 70% of its nominal output
level, then the maximum sense voltage is progressively
lowered from 100% to 45% of its maximum selected
value. Under short-circuit conditions with very low duty
cycles, the LTC3807 will begin cycle skipping in order to
limit the short-circuit current. In this situation the bottom
MOSFET will be dissipating most of the power but less
than in normal operation. The short-circuit ripple current
is determined by the minimum on-time, tON(MIN), of the
LTC3807 (≈95ns), the input voltage and inductor value:
DIL(SC) =tON(MIN) VIN
L
The resulting average short-circuit current is:
ISC =45%•ILIM(MAX) –
1
2
DIL(SC)
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes huge
currents to flow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the control-
ler is operating.
A comparator monitors the output for overvoltage condi-
tions. The comparator detects faults greater than 10%
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously
for as long as the overvoltage condition persists; if VOUT
returns to a safe level, normal operation automatically
resumes.
A shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
LTC3807
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Phase-Locked Loop and Frequency Synchronization
The LTC3807 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET to be locked to the rising edge
of an external clock signal applied to the PLLIN/MODE pin.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the VCO input. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
Note that the LTC3807 can only be synchronized to an
external clock whose frequency is within range of the
LTC3807’s internal VCO, which is nominally 55kHz to
900kHz.
This is guaranteed to be between 75kHz and 750kHz. Typi-
cally, the external clock (on the PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.1V.
Rapid phase locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
APPLICATIONS INFORMATION
the frequency slightly to achieve phase lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2
FREQ PIN PLLIN/MODE PIN FREQUENCY
0V DC Voltage 350kHz
INTVCC DC Voltage 535kHz
Resistor DC Voltage 50kHz to 900kHz
Any of the Above External Clock Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3807 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
FREQ PIN RESISTOR (kΩ)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
3807 F09
400
200
500
700
900
300
100
065 75 85 95 105 115 125
Figure 9. Relationship Between Oscillator Frequency and
Resistor Value at the FREQ Pin
LTC3807
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charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
V
OUT
VIN f
( )
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3807 is approximately
95ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3807 circuits: 1) IC VIN current, 2) IN-
TVCC regulator current, 3) I2R losses, 4) topside MOSFET
transition losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. VIN current typically results
in a small (<0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
APPLICATIONS INFORMATION
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
Supplying INTVCC from an output-derived source power
through EXTVCC will scale the VIN current required
for the driver and control circuits by a factor of (Duty
Cycle)/(Efficiency). For example, in a 20V to 5V applica-
tion, 10mA of INTVCC current results in approximately
2.5mA of VIN current. This reduces the midcurrent loss
from 10% or more (if the driver was powered directly
from VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor and input and output capacitor ESR. In continuous
mode the average output current flows through L and
RSENSE, but is chopped between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs have
approximately the same RDS(ON), then the resistance
of one MOSFET can simply be summed with the resis-
tances of L, RSENSE and ESR to obtain I2R losses. For
example, if each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE
= 10mΩ and RESR = 40mΩ (sum of both input and
output capacitance losses), then the total resistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
Efficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) • VIN2 • IO(MAX) • CRSS • f
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APPLICATIONS INFORMATION
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5%
to 10% efficiency degradation in portable systems. It
is very important to include these system level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and very low ESR at
the switching frequency. A 25W supply will typically
require a minimum of 20μF to 40μF of capacitance
having a maximum of 20mΩ to 50mΩ of ESR. Other
losses including body diode conduction losses during
dead-time and inductor core losses generally account
for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recov-
ery time VOUT can be monitored for excessive overshoot
or ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior, but it also
provides a DC coupled and AC filtered closed-loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin. The
ITH external components shown in Figure 12 circuit will
provide an adequate starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Placing a power MOSFET directly across the output
capacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better to
look at the ITH pin signal which is in the feedback loop and
is the filtered and compensated control loop response.
The gain of the loop will be increased by increasing RC
and the bandwidth of the loop will be increased by de-
creasing CC. If RC is increased by the same factor that
CC is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example, assume VIN = 12V (nominal),
VIN = 22V (max), VOUT = 3.3V, IMAX = 5A, VSENSE(MAX)
= 75mV and f = 350kHz. The inductance value
is chosen first based on a 30% ripple current
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APPLICATIONS INFORMATION
assumption. The highest value of ripple current occurs
at the maximum input voltage. Tie the FREQ pin to GND,
generating 350kHz operation. The minimum inductance
for 30% ripple current is:
DIL=VOUT
f
( )
L
( )
1– VOUT
VIN(NOM)
A 4.7μH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 95ns is not violated. The minimum on-time occurs at
maximum VIN:
tON(MIN) =
V
OUT
VIN(MAX) f
( )
=
3.3V
22V 350kHz
( )
=429ns
The equivalent RSENSE resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (64mV):
RSENSE ≤
64mV
5.73A
≈0.01Ω
Choosing 1% resistors: RA = 25k and RB = 78.7k yields
an output voltage of 3.32V.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF. At
maximum input voltage with T(estimated) = 50°C:
PMAIN =
3.3V
22V 5A
( )
21+0.005
( )
50°C–25°C
( )
0.035Ω
( )
+22V
( )
25A
22.5Ω
( )
215pF
( )
•
1
5V – 2.3V +1
2.3V
350kHz
( )
=331mW
A short-circuit to ground will result in a folded back cur-
rent of:
ISC =34mV
0.01Ω–1
2
95ns 22V
( )
4.7µH
=3.18A
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
PSYNC =3.18A
( )
21.125
( )
0.022Ω
( )
=250mW
which is less than under full-load conditions. CIN is chosen
for an RMS current rating of at least 3A at temperature.
COUT is chosen with an ESR of 0.02Ω for low output ripple.
The output ripple in continuous mode will be highest at
the maximum input voltage. The output voltage ripple due
to ESR is approximately:
VORIPPLE = RESR(DIL) = 0.02Ω(1.45A) = 29mVP-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC.
Check the following in your layout:
1. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) ter-
minals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
2. Does the LTC3807 VFB pin’s resistive divider connect to
the (+) terminal of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
LTC3807
27
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For more information www.linear.com/LTC3807
APPLICATIONS INFORMATION
3. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
4. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1μF ceramic capacitor placed
immediately next to the INTVCC and PGND pins can help
improve noise performance substantially.
5. Keep the SW, TG, and BOOST nodes away from sensi-
tive small-signal nodes. All of these nodes have very
large and fast moving signals and therefore should be
kept on the output side of the LTC3807 and occupy
minimum PC trace area.
6. Use a modified star ground technique: a low impedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the INTVCC decoupling
capacitor, the bottom of the voltage feedback resistive
divider and the SGND pin of the IC.
PC Board Layout Debugging
It is helpful to use a DC-50MHz current probe to monitor
the current in the inductor while testing the circuit. Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
output voltage as well. Check for proper performance over
the operating voltage and current range expected in the
application. The frequency of operation should be main-
tained over the input voltage range down to dropout and
until the output load drops below the low current opera-
tion threshold—typically 25% of the maximum designed
current level in Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
LTC3807
28
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For more information www.linear.com/LTC3807
APPLICATIONS INFORMATION
VIN
CIN
COUT
VPULL-UP
ROUT
CINTVCC
M1
PGOOD
1µF
CERAMIC
L1 VOUT
3807 F10
RSENSE
SENSE–
SENSE+
VFB
ITH
EXTVCC
INTVCC
BG
BOOST
SW
TG
PGOOD
LTC3807
TRACK/SS
FREQ
PLLIN/MODE
SGND
SGND
RUN
*R1, C1 AND D2 ARE OPTIONAL
R1*
C1* M2 D2*
D1
+
+
ILIM
VIN
PGND
GND
RL1
D1
L1
SW RSENSE VOUT
COUT
VIN
CIN
RIN
BOLD LINES INDICATE HIGH SWITCHING
CURRENT. KEEP LINES TO A MINIMUM LENGTH.
3807 F11
Figure 10. Recommended Printed Circuit Layout Diagram
Figure 11. Branch Current Waveforms
LTC3807
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For more information www.linear.com/LTC3807
Figure 12. High Efficiency 3.3V Step-Down Converter
0.1µF
CIN
22µF
VIN
4V TO 38V
INTVCC
41.2k
10k
2200pF
100k
100k
31.6k
3807 F12
2.2µF
D1
100pF
0.1µF
FREQ
ITH
SGND
SGND
LTC3807
VIN
PGOOD
RUN
ILIM
EXTVCC
PLLIN/MODE
INTVCC
PGND
L1
4.7µH RSENSE
8mΩ
BOOST
SW
BG
SENSE+
SENSE–
VFB
TG MTOP
MBOT
1nF
COUT
150µF
VOUT
3.3V
5A
TRACK/SS
MTOP, MBOT: Si7850DP
L1 COILCRAFT SER1360-472KL
COUT: SANYO 6TPE150M
D1: DFLS1100
10µF
+
APPLICATIONS INFORMATION
LTC3807
30
3807fa
For more information www.linear.com/LTC3807
Figure 13. High Efficiency 12V Step-Down Converter
0.1µF
CIN
22µF
VIN
12.5V TO 38V
VOUT
INTVCC
15.4k
4.7nF
100k
1M
MTOP, MBOT: RJK0452
L1 WÜRTH 7443320470
COUT: SANYO 16SVP150M
D1: DFLS1100
71.5k
3807 F13
2.2µF
D1
47pF
0.1µF
FREQ
ITH
SGND
SGND
LTC3807
VIN
PGOOD
RUN
ILIM
EXTVCC
PLLIN/MODE
60.4k
INTVCC
PGND
L1
4.7µH RSENSE
5mΩ
BOOST
SW
BG
SENSE+
SENSE–
VFB
TG MTOP
MBOT
1nF
VOUT
12V
10A
TRACK/SS
COUT
180µF
10µF
+
APPLICATIONS INFORMATION
LTC3807
31
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For more information www.linear.com/LTC3807
PACKAGE DESCRIPTION
3.00 ±0.10 1.50 REF
4.00 ±0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
19 20
1
2
BOTTOM VIEW—EXPOSED PAD
2.50 REF
0.75 ±0.05
R = 0.115
TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UDC20) QFN 1106 REV Ø
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
2.50 REF
3.10 ±0.05
4.50 ±0.05
1.50 REF
2.10 ±0.05
3.50 ±0.05
PACKAGE OUTLINE
R = 0.05 TYP
1.65 ±0.10
2.65 ±0.10
1.65 ±0.05
2.65 ±0.05
0.50 BSC
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
Please refer to http://www.linear.com/product/LTC3807#packaging for the most recent package drawings.
LTC3807
32
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For more information www.linear.com/LTC3807
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3807#packaging for the most recent package drawings.
FE20 (CB) TSSOP REV K 0913
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10
DETAIL A
DETAIL A IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
111214 13
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60
±0.10
1.05 ±0.10
3.86
(.152)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation CB
DETAIL A
0.60
(.024)
REF
0.28
(.011)
REF
LTC3807
33
3807fa
For more information www.linear.com/LTC3807
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 10/15 Corrected polarity inputs to EA Amplifier
Modified Transition Loss Equation
Changed PSYNC Equation
11
24
26
LTC3807
34
3807fa
For more information www.linear.com/LTC3807
LINEAR TECHNOLOGY CORPORATION 2014
LT 1015 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3807
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC3857/LTC3857-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down
DC/DC Controllers with 99% Duty Cycle Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 24V, IQ = 50µA
LTC3858/LTC3858-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down
DC/DC Controllers with 99% Duty Cycle Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 24V, IQ = 170µA, Short-Circuit Latchoff
LTC3868/LTC3868-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down
DC/DC Controller with 99% Duty Cycle Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 24V,
0.8V ≤ VOUT ≤ 14V, IQ = 170µA, Short-Circuit Latchoff
LTC3834/LTC3834-1 Low IQ, Single Output Synchronous Step-Down DC/DC
Controller with 99% Duty Cycle Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V ≤ VIN ≤ 36V,
0.8V ≤ VOUT ≤ 10V, IQ = 30µA
LTC3859AL Low IQ, Triple Output Buck/Buck/Boost Synchronous
DC/DC Controller All Outputs Remain in Regulation Through Cold Crank, 2.5V ≤ VIN
≤ 38V, VOUT(BUCKS) Up to 24V, VOUT(BOOST) Up to 60V, IQ = 28µA
LTC3867 Synchronous Step-Down DC/DC Controller with
Nonlinear Control and Remote Sense Fast Transient Response, tON(MIN) = 65ns, 4V ≤ VIN ≤ 38V,
0.6V ≤ VOUT ≤ 14V, 4mm × 4mm QFN-24
LTC3864 Low IQ, High Voltage Step-Down DC/DC Controller
with 100% Duty Cycle Fixed Frequency 50kHz to 850kHz, 3.5V≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ VIN,
IQ = 40µA, MSOP-12E, 3mm × 4mm DFN-12
LTC3891 60V, Low IQ, Synchronous Step-Down DC/DC
Controller PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V,
IQ = 50µA
LTC3890/LTC3890-1/
LTC3890-2/LTC3890-3 60V, Low IQ, Dual Output 2-Phase Synchronous Step-
Down DC/DC Controller Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V,
0.8V ≤ VOUT ≤ 24V, IQ = 50µA
0.1µF
CIN
22µF
VIN
9V TO 38V
VOUT
INTVCC
34.8k
470pF
100k
100k
MTOP, MBOT: Si7850DP
L1 COILCRAFT SER1360-802KL
COUT: SANYO 10TPE330M
D1: DFLS1100
10.5k
3807 F14
2.2µF
D1
0.1µF
FREQ
ITH
SGND
SGND
LTC3807
VIN
PGOOD
RUN
ILIM
EXTVCC
PLLIN/MODE
INTVCC
PGND
L1
8µH RSENSE
10mΩ
BOOST
SW
BG
SENSE+
SENSE–
VFB
TG MTOP
MBOT
1nF
VOUT
8.5V
3A
TRACK/SS
350kHz
COUT
330µF
10µF
+
Figure 14. High Efficiency 8.5V Step-Down Converter
