DS1312
Nonvolatile Controller with Lithium
Battery Monitor
DS1312
022598 1/10
FEATURES
•Converts CMOS SRAM into nonvolatile memory
•Unconditionally write–protects SRAM when VCC is
out of tolerance
•Automatically switches to battery backup supply
when VCC power failure occurs
•Monitors voltage of a lithium cell and provides
advanced warning of impending battery failure
•Signals low–battery condition on active low Battery
W arning output signal
•Optional –5% or –10% power fail detection
•Space–saving 8–pin DIP and SOIC packages
•Optional 16–pin SOIC and 20–pin TSSOP versions
reset processor when power failure occurs and hold
processor in reset during system power–up
•Industrial temperature range of –40°C to +85°C
DESCRIPTION
The DS1312 Nonvolatile Controller with Battery Monitor
is a CMOS circuit which solves the application problem
of converting CMOS RAM into nonvolatile memory.
Incoming power is monitored for an out–of–tolerance
condition. When such a condition is detected, chip
enable is inhibited to accomplish write protection and
the battery is switched on to supply the RAM with unin-
terrupted power. Special circuitry uses a low–leakage
CMOS process which affords precise voltage detection
at extremely low battery consumption.
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
VCCI
RST
NC
BW
CEO
NC
CEI
NC
VCCO
NC
VBAT
NC
TOL
NC
GND
DS1312S 16–PIN SOIC
(300 MIL)
NC
VCCI
RST
NC
NC
BW
NC
CEO
NC
CEI
NC
VCCO
NC
VBAT
NC
NC
TOL
NC
NC
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DS1312E 20–PIN TSSOP
DS1312 8–PIN DIP
VCCI
BW
CEO
CEI
VCCO
VBAT
TOL
GND
1
2
3
4
8
7
6
5
(300 MIL)
1
2
3
4
8
7
6
5
VCCI
BW
CEO
CEI
VCCO
VBAT
TOL
GND
DS1312S–2 8–PIN SOIC
(150 MIL)
PIN DESCRIPTION
VCCI – +5V Power Supply Input
VCCO – SRAM Power Supply Output
VBAT – Backup Battery Input
CEI – Chip Enable Input
CEO – Chip Enable Output
TOL – VCC Tolerance Select
BW – Battery Warning Output (Open Drain)
RST – Reset Output (Open Drain)
GND – Ground
NC – No Connection
DS1312
022598 2/10
In addition to battery–backup support, the DS1312 per-
forms the important function of monitoring the remaining
capacity of the lithium battery and providing a warning
before the battery reaches end–of–life. Because the
open–circuit voltage of a lithium backup battery remains
relatively constant over the majority of its life, accurate
battery monitoring requires loaded–battery voltage
measurement. The DS1312 performs such measure-
ment by periodically comparing the voltage of the bat-
tery as it supports an internal resistive load with a care-
fully selected reference voltage. If the battery voltage
falls below the reference voltage under such conditions,
the battery will soon reach end–of–life. As a result, the
Battery Warning pin is activated to signal the need for
battery replacement.
MEMORY BACKUP
The DS1312 performs all the circuit functions required
to provide battery–backup for an SRAM. First, the
device provides a switch to direct power from the bat-
tery or the system power supply (VCCI). Whenever VCCI
is less than the switch point VSW and VCCI is less than
the battery voltage VBAT, the battery is switched in to
provide backup power to the SRAM. This switch has
voltage drop of less than 0.2 volts.
Second, the DS1312 handles power failure detection
and SRAM write–protection. VCCI is constantly moni-
tored, and when the supply goes out of tolerance, a pre-
cision comparator detects power failure and inhibits
chip enable output (CEO) in order to write–protect the
SRAM. This is accomplished by holding CEO to within
0.2 volts of VCCO when VCCI is out of tolerance. If CEI is
(active) low at the time that power failure is detected, the
CEO signal is kept low until CEI is brought high again.
Once CEI is brought high, CEO is taken high and held
high until after VCCI has returned to its nominal voltage
level. If CEI is not brought high by 1.5 µs after power fail-
ure is detected, CEO is forced high at that time. This
specific scheme for delaying write protection for up to
1.5 µs guarantees that any memory access in progress
when power failure occurs will complete properly.
Power failure detection occurs in the range of 4.75 to 4.5
volts (5% tolerance) when the TOL pin is wired to GND
or in the range of 4.5 to 4.25 volts (10% tolerance) when
TOL is connected to VCCO.
BATTERY VOLTAGE MONITORING
The DS1312 automatically performs periodic battery
voltage monitoring at a factory–programmed time inter-
val of 24 hours. Such monitoring begins within tREC
after VCCI rises above VCCTP, and is suspended when
power failure occurs.
After each 24 hour period (tBTCN) has elapsed, the
DS1312 connects VBAT to an internal 1.2 MΩ test resis-
tor (RINT) for one second (tBTPW). During this one
second, if VBAT falls below the factory–programmed
battery voltage trip point (VBTP), the battery warning
output BW is asserted. While BW is active battery test-
ing will be performed with period tBTCW to detect battery
removal and replacement. Once asserted, BW remains
active until the battery is physically removed and
replaced by a fresh cell. The battery is still retested after
each VCC power–up, however, even if BW was active on
power–down. If the battery is found to be higher than
VBTP during such testing, BW is deasserted and regular
24–hour testing resumes. BW has an open–drain out-
put driver.
Battery replacement following BW activation is normally
done with VCCI nominal so that SRAM data is not lost.
During battery replacement, the minimum time duration
between old battery detachment and new battery
attachment (tBDBA) must be met or BW will not deacti-
vate following attachment of the new battery. Should
BW not deactivate for this reason, the new battery can
be detached for tBDBA and then re–attached to clear
BW.
NOTE: The DS1312 cannot constantly monitor an
attached battery because such monitoring would drasti-
cally reduce the life of the battery. As a result, the
DS1312 only tests the battery for one second out of
every 24 hours and does not monitor the battery in any
way between tests. If a good battery (one that has not
been previously flagged with BW) is removed between
battery tests, the DS1312 may not immediately sense
the removal and may not activate BW until the next
scheduled battery test. If a battery is then reattached to
the DS1312, the battery may not be tested until the next
scheduled test.
NOTE: Battery monitoring is only an useful technique
when testing can be done regularly over the entire life of
a lithium battery. Because the DS1312 only performs
battery monitoring when VCC is nominal, systems
which are powered–down for excessively long periods
can completely drain their lithium cells without receiving
any advanced warning. T o prevent such an occurrence,
systems using the DS1312 battery monitoring feature
should be powered–up periodically (at least once every
few months) in order to perform battery testing. Further-
DS1312
022598 3/10
more, anytime BW is activated on the first battery test
after a power–up, data integrity should be checked via
checksum or other technique.
POWER MONITORING
DS1312S and DS1312E varieties have an additional
reset pin. These varieties detect out–of–tolerance
power supply conditions and warn a processor–based
system of impending power failure. When VCCI falls
below the trip point level defined by the TOL pin
(VCCTP), the VCCI comparator activates the reset signal
RST. Reset occurs in the range of 4.75 to 4.5 volts (5%
tolerance) when the T OL pin is connected to GND or in
the range of 4.5 to 4.25 volts (10% tolerance) when TOL
is connected to VCCO.
RST also serves as a power–on reset during power–up.
After VCCI exceeds VCCTP, RST will be held active for
200 ms nominal (tRPU). This reset period is suf ficiently
long to prevent system operation during power–on tran-
sients and to allow tREC to expire. RST has an open–
drain output driver.
FRESHNESS SEAL MODE
When the battery is first attached to the DS1312 without
VCC power applied, the device does not immediately
provide battery–backup power on VCCO. Only after
VCCI exceeds VCCTP and later falls below both VSW and
VBAT will the DS1312 leave Freshness Seal Mode and
provide battery–backup power. This mode allows a bat-
tery to be attached during manufacturing but not used
until after the system has been activated for the first
time. As a result, no battery energy is drained during
storage and shipping.
FUNCTIONAL BLOCK DIAGRAM Figure 1
BW
DELAY TIMING
CIRCUITRY
RST
CEI CEO
TOL
1.2 MΩ
+
–
VCCTP REF
VCCI
+
–
VSW REF
+
–
+
–
BATTERY WARNING
CONTROL CIRCUITRY
+
–
CURRENT–LIMITING
RESISTOR
REDUNDANT LOGIC
VBTP REF
VBAT
REDUNDANT
SERIES FET
VCCO
BATTERY CHARGING/SHORTING
PROTECTION CIRCUITRY
(U.L. RECONGNIZED)
DS1312
022598 4/10
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground –0.5V to +7.0V
Operating Temperature –40°C to +85°C
Storage Temperature –55°C to +125°C
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (–40°C to +85°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage TOL=GND VCCI 4.75 5.0 5.5 V 1
Supply Voltage TOL=VCCO VCCI 4.5 5.0 5.5 V 1
Battery Supply Voltage VBAT 2.0 6.0 V 1
Logic 1 Input VIH 2.0 VCCI+0.3 V 1, 12
Logic 0 Input VIL –0.3 +0.8 V 1, 12
DC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCCI >VCCTP)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Operating Current (TTL inputs) ICC1 200 400 µA 2
Operating Current (CMOS inputs) ICC2 50 100 µA2, 5
RAM Supply Current
(VCCO ≥VCCI –0.2V) ICCO1 140 mA 3
RAM Supply Current
(VCCO ≥VCCI –0.3V) ICCO1 200 mA 4
VCC Trip Point (TOL=GND) VCCTP 4.50 4.62 4.75 V 1
VCC Trip Point (TOL=VCCO) VCCTP 4.25 4.37 4.50 V 1
VBAT Trip Point VBTP 2.5 2.6 2.7 V 1
VCC/VBAT Switch Point VSW 2.6 2.7 2.8 V 1
Output Current @ 2.4V IOH –1 mA 7, 10
Output Current @ 0.4V IOL 4mA 7, 10
Input Leakage IIL –1.0 +1.0 µA
Output Leakage ILO –1.0 +1.0 µA
Battery Monitoring Test Load RINT 0.8 1.2 1.5 MΩ
DS1312
022598 5/10
DC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCCI < VBAT; VCCI < VSW)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Battery Current IBAT 100 nA 2
Battery Backup Current ICCO2 500 µA 6
Supply Voltage VCCO VBAT–0.2 V 1
CEO Output VOHL VBAT–0.2 V 1, 8
CAPACITANCE (tA=25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance (CEI, TOL) CIN 7pF
Output Capacitance
(CEO, BW, RST) COUT 7 pF
AC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCCI > VCCTP)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CEI to CEO Propagation Delay tPD 510 ns
CE Pulse Width tCE 1.5 µs11
VCC Valid to End of Write
Protection tREC 12 125 ms 9
VCC Valid to CEI Inactive tPU 2ms
VCC Valid to RST Inactive tRPU 150 200 350 ms 10
VCC Valid to BW Valid t BPU 1 s 10
AC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCCI < VCCTP)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Slew Rate tF150 µs
VCC Fail Detect to RST Active tRPD 515 µs 10
VCC Slew Rate tR150 µs
AC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCCI > VCCTP)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Battery Test to BW Active tBW 1 s 10
Battery Test Cycle–Normal tBTCN 24 hr
Battery Test Cycle–Warning tBTCW 5 s
Battery Test Pulse Width tBTPW 1 s
Battery Detach to Battery Attach tBDBA 7 s
Battery Attach to BW Inactive tBABW 1 s 10
DS1312
022598 6/10
TIMING DIAGRAM: POWER UP
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
CEI
VSW
tPD
DON’T CARE
VCCTP
VBAT – 0.2
CEO
VCCI
tREC
tPD
tRPU
RST
tBPU
BW SLEWS UP
WITH VCC
SLEWS UP
WITH VCC
VBAT
VCCO
tR
VSW
VIH
VIL
tPU
NOTE:
If VBAT < VSW, VCCO will begin to slew with VCCI when VCCI = VBAT.
DS1312
022598 7/10
TIMING DIAGRAM: POWER DOWN
ÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
CEI
tF
DON’T CARE
VBAT – 0.2
VSW
tPD
tPD
CEO
VCCI
tCE
tCE
VCCTP
RST
BW
SLEWS DOWN
WITH VCC
SLEWS DOWN
WITH VCC
VBAT
VCCO
tRPD
VSW
VIL
NOTE:
If VBAT < VSW, VCCO will slew down with VCCI until VCCI = VBAT.
DS1312
022598 8/10
TIMING DIAGRAM: BATTERY WARNING DETECTION
BATTERY
tBPU
VBTP
VCCTP
VBAT
TEST
ACTIVE
BW
tBTCN tBTCW
tBW
tBTPW
VCC
VIL
NOTE:
tBW is measured from the expiration of the internal timer to the activation of the battery warning output BW.
TIMING DIAGRAM: BATTERY REPLACEMENT
BATTERY
VBTP
VBAT
VCC
TEST
ACTIVE
BW
tBDBA
tBABW
FLOATING
BATTERY
DETACH BATTERY
ATTACH
VIH
DS1312
022598 9/10
NOTES:
1. All voltages referenced to ground.
2. Measured with outputs open circuited.
3. ICCO1 is the maximum average load which the DS1312 can supply to attached memories at VCCO > VCCI–0.2V.
4. ICCO1 is the maximum average load which the DS1312 can supply to attached memories at VCCO > VCCI–0.3V.
5. All inputs within 0.3V of ground or VCCI.
6. ICCO2 is the maximum average load current which the DS1312 can supply to the memories in the battery backup
mode.
7. Measured with a load as shown in Figure 1.
8. Chip Enable Output CEO can only sustain leakage current in the battery–backup mode.
9. CEO will be held high for a time equal to tREC after VCCI crosses VCCTP on power–up.
10.BW and RST are open drain outputs and, as such, cannot source current. External pull–up resistors should be
connected to these pins for proper operation. Both BW and RST can sink 10 mA.
11. tCE maximum must be met to ensure data integrity on power–down.
12.In battery–backup mode, inputs must never be below ground or above VCCO.
13.The DS1312 is recognized by Underwriters Laboratory (U.L.) under file E99151.
DC TEST CONDITIONS
Outputs Open
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: See below
Input Pulse Levels: 0 – 3.0V
T iming Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall T imes: 5 ns
OUTPUT LOAD Figure 1
+5 VOLTS
D.U.T.
1.1KΩ
680KΩ
30 pF*
* INCLUDING SCOPE AND JIG CAPACITANCE
DS1312
022598 10/10
DATA SHEET REVISION SUMMARY
The following represent the key differences between 12/16/96 and 06/12/97 version of the DS1312 data sheet.
Please review this summary carefully.
1. Changed VBAT max to 6V
2. Changed tBABW from 75 to 1s max
3. Changed block diagram to show UL compliance
The following represent the key differences between 06/12/97 and 08/29/97 version of the DS1312 data sheet.
Please review this summary carefully.
1. Changed AC test conditions
The following represent the key differences between 08/29/97 and 12/16/97 version of the DS1312 data sheet.
Please review this summary carefully.
1. Specified Input Capacitance as being only for CEI, TOL and output capacitance as being only for CEO, BW
and RST. This is not a change but rather a clarification.
2. Add note 13 describing UL recognition.
