© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 8
1Publication Order Number:
MC34025/D
MC34025, MC33025
High Speed Double-Ended
PWM Controller
The MC34025 series are high speed, fixed frequency, double−ended
pulse width modulator controllers optimized for high frequency
operation. They are specifically designed for Off−Line and
DC−to−DC converter applications offering the designer a cost
effective solution with minimal external components. These
integrated circuits feature an oscillator, a temperature compensated
reference, a wide bandwidth error amplifier, a high speed current
sensing comparator, steering flip−flop, and dual high current totem
pole outputs ideally suited for driving power MOSFETs.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, and a latch for single pulse metering.
The flexibility of this series allows it to be easily configured for
either current mode or voltage mode control.
Features
•50 ns Propagation Delay to Outputs
•Dual High Current Totem Pole Outputs
•Wide Bandwidth Error Amplifier
•Fully−Latched Logic with Double Pulse Suppression
•Latching PWM for Cycle−By−Cycle Current Limiting
•Soft−Start Control with Latched Overcurrent Reset
•Input Undervoltage Lockout with Hysteresis
•Low Startup Current (500 mA Typ)
•Internally Trimmed Reference with Undervoltage Lockout
•45% Maximum Duty Cycle (Externally Adjustable)
•Precision Trimmed Oscillator
•Voltage or Current Mode Operation to 1.0 MHz
•Functionally Similar to the UC3825
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Figure 1. Simplified Application
Error
Amp
Oscillator
4
16
Vref
Clock
5
6
RT
CT
3
7
Ramp
Error Amp
Output
2
Inverting
Input 1
8
Soft-Start Soft-Start
Latching
PWM and
Steering
Flip Flop
Ground
10
9Current
Limit/
Shutdown
Output B
14
VC
13
VCC
15
UVLO
5.1V
Reference
11
Noninverting
Input Power
Ground
12
Output A
This device contains 227 active transistors.
PDIP−16
P SUFFIX
CASE 648
1
16
SO−16WB
DW SUFFIX
CASE 751G
1
16
MARKING
DIAGRAMS
PIN CONNECTIONS
1
16
MC3x025P
AWLYYWWG
11
5
2
1
Error Amp
Noninverting Input
Current Limit/
Shutdown
Ground
Output A
Power Ground
VC
Output B
VCC
Vref
9
10
12
13
14
15
16
8
7
6
4
3
(Top View)
Soft-Start
Ramp
CT
RT
Clock
Error Amp Output
Error Amp
Inverting Input
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*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
16
1
MC3x025DW
AWLYYWWG
x = 3 or 4
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
ORDERING INFORMATION
MC34025, MC33025
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2
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC 30 V
Output Driver Supply Voltage VC25 V
Output Current, Source or Sink (Note 1)
DC
Pulsed (0.5 ms)
IO0.5
2.0
A
Current Sense, Soft−Start, Ramp, and Error Amp Inputs Vin −0.3 to +7.0 V
Error Amp Output and Soft−Start Sink Current IO10 mA
Clock and RT Output Current ICO 5.0 mA
Power Dissipation and Thermal Characteristics
SO−16 Package (Case 751G)
Maximum Power Dissipation @ TA = + 25°C
Thermal Resistance, Junction−to−Air
DIP Package (Case 648)
Maximum Power Dissipation @ TA = + 25°C
Thermal Resistance, Junction−to−Air
PD
RqJA
PD
RqJA
862
145
1.25
100
mW
°C/W
W
°C/W
Operating Junction Temperature TJ+150 °C
Operating Ambient Temperature (Note 2)
MC34025
MC33025
TA0 to +70
−40 to +105
°C
Storage Temperature Range Tstg −55 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kW, CT = 1.0 nF, for typical values TA = + 25°C, for min/max values TA
is the operating ambient temperature range that applies [Note 2], unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = + 25°C) Vref 5.05 5.1 5.15 V
Line Regulation (VCC = 10 V to 30 V) Regline −2.0 15 mV
Load Regulation (IO = 1.0 mA to 10 mA) Regload −2.0 15 mV
Temperature Stability TS−0.2 −mV/°C
Total Output Variation over Line, Load, and Temperature Vref 4.95 −5.25 V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = + 25°C) Vn−50 −mV
Long Term Stability (TA = +125°C for 1000 Hours) S−5.0 −mV
Output Short Circuit Current ISC −30 −65 −100 mA
OSCILLATOR SECTION
Frequency
TJ = + 25°C
Line (VCC = 10 V to 30 V) and Temperature (TA = Tlow to Thigh)
fosc 380
370
400
400
420
430
kHz
Frequency Change with Voltage (VCC = 10 V to 30 V) Dfosc/DV−0.2 1.0 %
Frequency Change with Temperature (TA = Tlow to Thigh)Dfosc/DT−2.0 −%
Sawtooth Peak Voltage VP2.6 2.8 3.0 V
Sawtooth Valley Voltage VV0.7 1.0 1.25 V
Clock Output Voltage
High State
Low State
VOH
VOL
3.9
−
4.5
2.3
−
2.9
V
1. Maximum package power dissipation limits must be observed.
2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for MC34025 Thigh = +70°C for MC34025
Tlow = −40°C for MC33025 Thigh = +105°C for MC33025
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ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kW, CT = 1.0 nF, for typical values TA = + 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 4], unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
ERROR AMPLIFIER SECTION
Input Offset Voltage VIO − − 15 mV
Input Bias Current IIB −0.6 3.0 mA
Input Offset Current IIO −0.1 1.0 mA
Open−Loop Voltage Gain (VO = 1.0 V to 4.0 V) AVOL 60 95 −dB
Gain Bandwidth Product (TJ = + 25°C) GBW 4.0 8.3 −MHz
Common Mode Rejection Ratio (VCM = 1.5 V to 5.5 V) CMRR 75 95 −dB
Power Supply Rejection Ratio (VCC = 10 V to 30 V) PSRR 85 110 −dB
Output Current, Source (VO = 4.0 V)
Sink (VO = 1.0 V)
ISource
ISink
0.5
1.0
3.0
3.6
−
−
mA
Output Voltage Swing, High State (IO = −0.5 mA)
Low State (IO = 1.0 mA)
VOH
VOL
4.5
0
4.75
0.4
5.0
1.0
V
Slew Rate SR 6.0 12 −V/ms
PWM COMPARATOR SECTION
Ramp Input Bias Current IIB − −0.5 −5.0 mA
Duty Cycle of Each Output, Maximum
Minimum
DC(max)
DC(min)
40
−
45
−
−
0
%
Zero Duty Cycle Threshold Voltage Pin 3(4) (Pin 7(9) = 0 V) Vth 1.1 1.25 1.4 V
Propagation Delay (Ramp Input to Output, TJ = + 25°C) tPLH(in/out) −60 100 ns
SOFT−START SECTION
Charge Current (VSoft−Start = 0.5 V) Ichg 3.0 9.0 20 mA
Discharge Current (VSoft−Start = 1.5 V) Idischg 1.0 4.0 −mA
CURRENT SENSE SECTION
Input Bias Current (Pin 9(12) = 0 V to 4.0 V) IIB − − 15 mA
Current Limit Comparator Threshold
Shutdown Comparator Threshold
Vth
Vth
0.9
1.25
1.0
1.40
1.10
1.55
V
Propagation Delay (Current Limit/Shutdown to Output, TJ = + 25°C) tPLH(in/out) −50 80 ns
OUTPUT SECTION
Output Voltage
Low State (ISink = 20 mA)
(ISink = 200 mA)
High State (ISource = 20 mA)
(ISource = 200 mA)
VOL
VOH
−
−
13
12
0.25
1.2
13.5
13
0.4
2.2
−
−
V
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 0.5 mA) VOL(UVLO) −0.25 1.0 V
Output Leakage Current (VC = 20 V) IL−100 500 mA
Output Voltage Rise Time (CL = 1.0 nF, TJ = + 25°C) tr−30 60 ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = + 25°C) tf−30 60 ns
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (VCC Increasing) Vth(on) 8.8 9.2 9.6 V
UVLO Hysteresis Voltage (VCC Decreasing After Turn−On) VH0.4 0.8 1.2 V
TOTAL DEVICE
Power Supply Current
Startup (VCC = 8.0 V)
Operating
ICC
−
−
0.5
25
1.2
35
mA
3. Maximum package power dissipation limits must be observed.
4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for MC34025 Thigh = +70°C for MC34025
Tlow = −40°C for MC33025 Thigh = +105°C for MC33025
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Gain
Phase
1
CT=
1. 100 nF
2. 47 nF
3. 22 nF
4. 10 nF
5. 4.7 nF
6. 2.2 nF
7. 1.0 nF
8. 470 pF
9. 220 pF
2
3
4
5
6
7
8
9
-55 -25 0 25 75 100 125
AVOL, OPEN LOOP VOLTAGE GAIN (dB)
, OSCILLATOR FREQUENCY (kHz)fosc
Figure 2. Timing Resistor versus
Oscillator Frequency
, TIMING RESISTOR ( )
100 1000 104105106107
fosc, OSCILLATOR FREQUENCY (Hz)
Figure 3. Oscillator Frequency versus Temperature
TA, AMBIENT TEMPERATURE (°C)
Figure 4. Error Amp Open Loop Gain and
Phase versus Frequency
10 100 1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)
Figure 5. PWM Comparator Zero Duty Cycle
Threshold Voltage versus Temperature
-55 -25 0 25 50 75 100
TA, AMBIENT TEMPERATURE (°C)
Figure 6. Error Amp Small Signal
Transient Response
Figure 7. Error Amp Large Signal
Transient Response
RTΩ
125
0
45
90
135
, EXCESS PHASE (°C)
θ
Vth, ZERO DUTY CYCLE (V)
0.1 ms/DIV 0.1 ms/DIV
VCC = 15 V
RT = 3.6 k
CT = 1.0 nF
RT = 1.2 k
CT = 1.0 nF
RT = 36 k
CT = 1.0 nF
50
50 kHz
400 kHz
1.0 MHz
VCC = 15 V
Pin 7(9) = 0 V
VCC = 15 V
TA = + 25°C
1.3
1.28
1.26
1.24
1.22
1.2
100 k
10 k
1.0 k
470
1200
1000
800
600
400
200
120
100
80
60
40
20
0
0
-20
2.55 V
2.5 V
2.45 V
3.0 V
2.5 V
2.0 V
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(CL), CURRENT LIMIT THRESHOLD CHANGE (mV)Vth
, SHUTDOWN THRESHOLD VOLTAGE (V)Vth
VCC = 15 V
010 20 30 40 50
TA, AMBIENT TEMPERATURE (°C)
, REFERENCE SHORT CIRCUIT CURRENT (mA)
Figure 8. Reference Voltage Change
versus Source Current
, REFERENCE VOLTAGE CHANGE (mV)
ISource, SOURCE CURRENT (mA)
Figure 9. Reference Short Circuit Current
versus Temperature
-55
TA, AMBIENT TEMPERATURE (°C)
- 25 0 25 50 75 100 125
Figure 10. Reference Line Regulation Figure 11. Reference Load Regulation
Figure 12. Current Limit Comparator Threshold
Change versus Temperature
TA, AMBIENT TEMPERATURE (°C)
Figure 13. Shutdown Comparator Threshold
Voltage versus Temperature
-55 -25 25 50 75 100 12
5
- 50 - 25 0 25 50 75 125
Vref
ISC
100 0
TA = + 25°C
TA = - 55°C
Vref LINE REGULATION 10 V - 24 V
2.0 ms/DIV
2.0 mV/DIV
Vref LINE REGULATION 1.0 mA - 10 mA
2.0 ms/DIV
2.0 mV/DIV
TA = +125°C
Δ
VCC = 15 V
VCC = 15 V
1.42
4.0
2.0
- 4.0
- 8.0
-10
-12
0
-5.0
-10
-15
-20
-25
-30
66
65.6
65.2
64.8
64.4
64
1.50
1.46
1.38
1.34
1.30
0
- 2.0
- 6.0
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Source Saturation
(Load to Ground)
VCC = 15 V
80 ms Pulsed Load
120 Hz Rate
TA = + 25°C
VCC
Ground Sink Saturation
(Load to VCC)
VCC Decreasing
VCC Increasing
VCC = 15 V
TA, AMBIENT TEMPERATURE (°C)
, OUTPUT SATURATION VOLTAGE (V)
Figure 14. Soft−Start Charge Current
versus Temperature
A)
-55 -25 0 25 50 75 100 125
IO, OUTPUT LOAD CURRENT (A)
Figure 15. Output Saturation Voltage
versus Load Current
0 0.2 0.4 0.6 0.8 1.0
Figure 16. Drive Output Rise and Fall Time Figure 17. Drive Output Rise and Fall Time
VCC, SUPPLY VOLTAGE (V)
0 4.0 8.0 12 16 20
, SUPPLY CURRENT (mA)
μIchg, SOFT‐START CHARGE CURRENT (
Vsat
ICC
Figure 18. Supply Voltage versus Supply Current
OUTPUT RISE & FALL TIME 1.0 nF LOAD
50 ns/DIV
OUTPUT RISE & FALL TIME 10.0 nF LOAD
50 ns/DIV
RT = 3.65 kW
CT = 1.0 nF
0
2.0
1.0
10
9.5
9.0
8.5
8.0
7.5
7.0
-1.0
-2.0
0
30
25
20
15
10
5.0
0
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7
Vref
VCC
UVLO
Reference
Regulator
4.2 V
Figure 19. Representative Block Diagram
Q
S
R
Q
Q
T
Steering
Flip Flop
Output A
1.0 V
0.5 V
16
4
5
6
7
3
2
1
8
CSS
10
9
11
12
14
13
15
PWM Latch
Soft-Start Latch
Vin
9.0 mA
Error
Amp
PWM
Comparator
Vref
UVLO
9.2 V
Oscillator
1.4 V
Current
Limit
Q
S
R
VCC
Clock
RT
CT
Noninverting Input
Inverting Input
Error Amp Output
Ramp
Soft-Start
Ground
Current Limit/
Shutdown
Power Ground
Output B
VC
VCC
+
1.25 V
Shutdown
Figure 20. Current Limit Operating Waveforms
Output B
Output A
PWM
Comparator
Ramp
Clock
CT
Soft-Start
Error Amp Output
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8
OPERATING DESCRIPTION
The MC33025 and MC34025 series are high speed, fixed
frequency, double−ended pulse width modulator controllers
optimized for high frequency operation. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost effective
solution with minimal external components. A
representative block diagram is shown in Figure 19.
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. The RT pin
is set to a temperature compensated 3.0 V. By selecting the
value of RT, the charge current is set through a current mirror
for the timing capacitor CT. This charge current runs
continuously through CT. The discharge current ratio is to be
10 times the charge current, which yields the maximum duty
cycle of 90%. CT is charged to 2.8 V and discharged to 1.0
V. During the discharge of CT, the oscillator generates an
internal blanking pulse that resets the PWM Latch, inhibits
the outputs, and toggles the steering flip−flop. The threshold
voltages on the oscillator comparator is trimmed to
guarantee an oscillator accuracy of 5.0% at 25°C.
Additional dead time can be added by externally
increasing the charge current to CT as shown in Figure 24.
This changes the charge to discharge ratio of CT which is set
internally to Icharge/10 Icharge. The new charge to discharge
ratio will be:
% Deadtime +Iadditional)Icharge
10 (Icharge)
A bidirectional clock pin is provided for synchronization
or for master/slave operation. As a master, the clock pin
provides a positive output pulse during the discharge of CT.
As a slave, the clock pin is an input that resets the PWM latch
and blanks the drive output, but does not discharge CT.
Therefore, the oscillator is not synchronized by driving the
clock pin alone. Figures 30 and 31 provide suggested
synchronization.
Error Amplifier
A fully compensated Error Amplifier is provided. It
features a typical DC voltage gain of 95 dB and a gain
bandwidth product of 8.3 MHz with 75 degrees of phase
margin (Figure 4). Typical application circuits will have the
noninverting input tied to the reference. The inverting input
will typically be connected to a feedback voltage generated
from the output of the switching power supply. Both inputs
have a Common Mode Voltage (VCM) input range of 1.5 V
to 5.5 V. The Error Amplifier Output is provided for external
loop compensation.
Soft−Start Latch
Soft−Start is accomplished in conjunction with an
external capacitor. The soft start capacitor is charged by an
internal 9.0 mA current source. This capacitor clamps the
output of the error amplifier to less than its normal output
voltage, thus limiting the duty cycle.
The time it takes for a capacitor to reach full charge is
given by:
t[(4.5 •105)C
Soft-Start
A Soft−Start latch is incorporated to prevent erratic
operation of this circuitry. Two conditions can cause the
Soft−Start circuit to latch so that the Soft−Start capacitor
stays discharged. The first condition is activation of an
undervoltage lockout of either VCC or Vref. The second
condition is when current sense input exceeds 1.4 V. Since
this latch is “set dominant”, it cannot be reset until either of
these signals is removed, and the voltage at CSoft−Start is less
than 0.5 V.
PWM Comparator and Latch
A PWM circuit typically compares an error voltage with
a ramp signal. The outcome of this comparison determines
the state of the output. In voltage mode operation the ramp
signal is the voltage ramp of the timing capacitor. In current
mode operation the ramp signal is the voltage ramp induced
in a current sensing element. The ramp input of the PWM
comparator is pinned out so that the user can decide which
mode of operation best suits the application requirements.
The ramp input has a 1.25 V offset such that whenever the
voltage at this pin exceeds the Error Amplifier Output
voltage minus 1.25 V, the PWM comparator will cause the
PWM latch to set, disabling the outputs. Once the PWM
latch is set, only a blanking pulse by the oscillator can reset
it, thus initiating the next cycle.
A toggle flip flop connected to the output of the PWM
latch controls which output is active. The flip flop is pulsed
by an OR gate that gets its inputs from the oscillator clock
and the output of the PWM latch. A pulse from either one
will cause the flip flop to enable the other output.
Current Limiting and Shutdown
A pin is provided to perform current limiting and
shutdown operations. Two comparators are connected to the
input of this pin. When the voltage at this pin exceeds 1.0 V,
one of the comparators is activated. The output of this
comparator sets the PWM latch, which disables the output.
In this way cycle−by−cycle current limiting is
accomplished. If a current limit resistor is used in series with
the power devices, the value of the resistor is found by:
RSense +
1.0 V
Ipk (switch)
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9
If the voltage at this pin exceeds 1.4 V, the second
comparator is activated. This comparator sets a latch which,
in turn, causes the Soft−Start capacitor to be discharged. In
this way a “hiccup” mode of recovery is possible in the case
of output short circuits. If a current limit resistor is used in
series with the output devices, the peak current at which the
controller will enter a “hiccup” mode is given by:
Ishutdown +
1.4 V
RSense
Undervoltage Lockout
There are two undervoltage lockout circuits within the IC.
The first senses VCC and the second Vref. During power−up,
VCC must exceed 9.2 V and Vref must exceed 4.2 V before
the outputs can be enabled and the Soft−Start latch released.
If VCC falls below 8.4 V or Vref falls below 3.6 V, the outputs
are disabled and the Soft−Start latch is activated. When the
UVLO is active, the part is in a low current standby mode
allowing the IC to have an off−line bootstrap startup circuit.
Typical startup current is 500 mA.
Output
The MC34025 has two high current totem pole outputs
specifically designed for direct drive of power MOSFETs.
They are capable of up to ±2.0 A peak drive current with a
typical rise and fall time of 30 ns driving a 1.0 nF load.
Separate pins for VC and Power Ground are provided.
With proper implementation, a significant reduction of
switching transient noise imposed on the control circuitry is
possible. The separate VC supply input also allows the
designer added flexibility in tailoring the drive voltage
independent of VCC.
Reference
A 5.1 V bandgap reference is pinned out and is trimmed
to an initial accuracy of ±1.0% at 25°C. This reference has
short circuit protection and can source in excess of 10 mA
for powering additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. With high
frequency, high power, switching power supplies it is
imperative to have separate current loops for the signal paths
and for the power paths. The printed circuit layout should
contain a ground plane with low current signal and high
current switch and output grounds returning on separate
paths back to the input filter capacitor. All bypass capacitors
and snubbers should be connected as close as possible to the
specific part in question. The PC board lead lengths must be
less than 0.5 inches for effective bypassing or snubbing.
Instabilities
In current mode control, an instability can be encountered
at any given duty cycle. The instability is caused by the
current feedback loop. It has been shown that the instability
is caused by a double pole at half the switching frequency.
If an external ramp (Se) is added to the on−time ramp (Sn)
of the current−sense waveform, stability can be achieved
(see Figure 21).
One must be careful not to add too much ramp
compensation. If too much is added, the system will start to
perform like a voltage mode regulator. All benefits of
current mode control will be lost. Figures 29A and 29B show
examples of two different ways in which external ramp
compensation can be implemented.
1.25 V
+
+
Ramp Input
Current Signal
Sn
Ramp Compensation
Se
Figure 21. Ramp Compensation
A simple equation can be used to calculate the amount of
external ramp necessary to add that will achieve stability in
the current loop. For the following equations, the calculated
values for the application circuit in Figure 37 are also shown.
Se+
VO
LǒNS
NPǓ(RS)Ai
where: = DC output voltage
= number of power transformer primary
=or secondary turns
= gain of the current sense network
=(see Figures 26, 27 and 28)
= output inductor
= current sense resistance
VO
NP
, NS
Ai
L
RS
+0.115 Vńμs
For the application circuit: Se+
5
1.8 μǒ4
16Ǔ(0.3)(0.55)
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PIN FUNCTION DESCRIPTION
Pin No.
Function Description
DIP/SOIC
1Error Amp Inverting
Input
This pin is usually used for feedback from the output of the power supply.
2Error Amp
Noninverting Input
This pin is used to provide a reference in which an error signal can be produced on the output of the
error amp. Usually this is connected to Vref, however an external reference can also be used.
3Error Amp Output This pin is provided for compensating the error amp for poles and zeros encountered in the power
supply system, mostly the output LC filter.
4 Clock This is a bidirectional pin used for synchronization.
5 RTThe value of RT sets the charge current through timing Capacitor, CT
.
6 CTIn conjunction with RT
, the timing Capacitor sets the switching frequency. Because this part is a
push−pull output, each output runs at one−half the frequency set at this pin.
7Ramp Input For voltage mode operation this pin is connected to CT
. For current mode operation this pin is
connected through a filter to the current sensing element.
8 Soft−Start A capacitor at this pin sets the Soft−Start time.
9Current
Limit/Shutdown
This pin has two functions. First, it provides cycle−by−cycle current limiting. Second, if the current is
excessive, this pin will reinitiate a Soft−Start cycle.
10 Ground This pin is the ground for the control circuitry.
11 Output A This is a high current totem pole output.
12 Power Ground This is a separate power ground return that is connected back to the power source. It is used to
reduce the effects of switching transient noise on the control circuitry.
13 VCThis is a separate power source connection for the outputs that is connected back to the power
source input. With a separate power source connection, it can reduce the effects of switching
transient noise on the control circuitry.
14 Output B This is a high current totem pole output.
15 VCC This pin is the positive supply of the control IC.
16 Vref This is a 5.1 V reference. It is usually connected to the noninverting input of the error amplifier.
Output Voltage
Feedback Input 2
1
3
7
6
5
4
1.25 V
Oscillator
Vref
CT
Figure 22. Voltage Mode Operation
In voltage mode operation, the control range on the output of
the Error Amplifier from 0% to 90% duty cycle is from 2.25 V
to 4.05 V.
Output Voltage
Feedback Input 2
1
3
7
6
5
4
1.25 V
Oscillator
Vref
CT
From Current
Sense Element
Figure 23. Current Mode Operation
In current mode control, an RC filter should be placed at the
ramp input to filter the leading edge spike caused by turn−on of
a power MOSFET.
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CT
Vref
RDT
RT
4
Oscillator
Figure 24. Dead Time Addition
5
6
Additional dead time can be added by the addition of a dead
time resistor from Vref to CT
. See text on oscillator section for
more information.
5.0 V
0 V
CT
RT
Oscillator
Figure 25. External Clock Synchronization
4
5
6
The sync pulse fed into the clock pin must be at least 3.9 V. RT
and CT need to be set 10% slower than the sync frequency. This
circuit is also used in voltage mode operation for master/slave
operation. The clock signal would be coming from the master
which is set at the desired operating frequency, while the slave
is set 10% slower.
Figure 26. Resistive Current Sensing
ISense
9
The addition of an RC filter will eliminate instability caused by the
leading edge spike on the current waveform. This sense signal
can also be used at the ramp input pin for current mode control.
For ramp compensation it is necessary to know the gain of the
current feedback loop. If a transformer is used, the gain can be
calculated by:
Ai+RSense
turns ratio
Figure 27. Primary Side Current Sensing
RwISense
9
Figure 28. Primary or Secondary Side
Current Sensing
0
ISense
Rw
9
Ai+
Rw
turns ratio
The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also
be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback
loop. The gain can be calculated by:
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3
7
6
5
4
Figure 29A. Slope Compensation (Noise Sensitive)
Oscillator
CTC1
R1
R2
Current Sense
Information
1.25 V
This method of slope compensation is easy to implement, however, it is noise sensitive. Capacitor C1 provides AC coupling. The oscillator
signal is added to the current signal by a voltage divider consisting of resistors R1 and R2.
7
3
7
3
Figure 29B. Slope Compensation (Noise Immune)
Rw
Output RM
CM
Rf
Cf
1.25 V
Ramp
Input
Current Sense
Transformer
Current Sense
Resistor RfCf
CM
1.25 V
RM
Ramp
Input
Output
Figure 29. Keeps Fig numbering sequence correct
When only one output is used, this method of slope compensation can be used and it is relatively noise immune. Resistor RM and
capacitor CM provide the added slope necessary. By choosing RM and CM with a larger time constant than the switching frequency, you
can assume that its charge is linear. First choose CM, then RM can be adjusted to achieve the required slope. The diode provides a reset
pulse at the ramp input at the end of every cycle. The charge current IM can be calculated by IM = CMSe. Then RM can be calculated by
RM = VCC/IM.
Figure 30. Current Mode Master/Slave Operation Over Short Distances
Vref
6
5
4
Oscillator
CT
RT
6
5
4
Oscillator
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Figure 31. Synchronization Over Long Distances
MC34071 1.0 k
3320
Provides Current
Sense Amplification &
Eliminates Leading
Edge Spike
Provides Leading
Edge Blanking
MMBT3904
1.0 k
From Curr
Sense
From Curr
Sense
100 k
562
680 pF
680 pF
562
Output B
Output A
79
10
8
12
14
11
4
16
13
15
6
5
1
3
2
100
MMBT3904
MMBD914
470 pF
22 k
21
470 pF
30 k
+15 V
1.0 k
2200
430
MMBT3906
4700
20
4.7 k
4.7 k
10 k
10 k
+15 V
4
16
13
15
2
79
10
8
14
11
6
5
1
3
Output A
Output B
3.0 k
MC34025 MC34025
FBFB
Synchronizes Both Converters
to the Same Operating Frequency
Synchronizes Both
Converters
to the Same Phase
12
MC34025, MC33025
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14
Vref
R2
R1
CSS
1
2
8
+
Figure 32. Buffered Maximum Clamp Level
In voltage mode operation, the maximum duty cycle can be
clamped. By the addition of a PNP transistor to buffer the clamp
voltage, the Soft−Start current is not affected by R1.
The new equation for Soft−Start is t[
Vclamp )0.6
9.0 μAǒCSSǓ
In current mode operation, this circuit will limit the maximum
voltage allowed at the ramp input to end a cycle.
Q
Q
T
Vin
To Current
Sense Input RS
12
11
14
15
VC
Base Charge
Removal
0
-
+
IB
Figure 33. Bipolar Transistor Drive
The totem pole output can furnish negative base current for
enhanced transistor turn−off, with the addition of the capacitor in
series with the base.
Q
Q
T
12
11
14
15
VC
Isolation
Boundary
Figure 34. Isolated MOSFET Drive
12
11
14
15
Q
Q
TVC
VC
Figure 35. Direct Transformer Drive
The totem pole output can easily drive pulse transformers. A Schottky diode is recommended when driving inductive loads at high
frequencies. The diode can reduce the driver’s power dissipation due to excessive ringing, by preventing the output pin from being driven
below ground.
Q
Q
T
Vin
To Current
Sense Input
RS
12
11
14
15
VC
Figure 36. MOSFET Parasitic Oscillations
A series gate resistor may be needed to damp high frequency
parasitic oscillation caused by a MOSFET’s input capacitance
and any series wiring inductance in the gate−source circuit. The
series resistor will also decrease the MOSFET’s switching speed.
A Schottky diode can reduce the driver’s power dissipation due to
excessive ringing, by preventing the output pin from being driven
below ground. The Schottky diode also prevents substrate
injection when the output pin is driven below ground.
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Primary: 16 turns center tapped #48 AWG (1300 strands litz wire)
Secondary: 4 turns center tapped 0.003” (2 layers) copper foil
Bootstrap: 1 turn added to each secondary output #36 AWG
Core: Philips 3F3, part #4312 020 4124
Bobbin: Philips part #4322 021 3525
Coilcraft P3269−A
2 turns #48 AWG (1300 strands litz wire)
Core: Philips 3F3, part #EP10−3F3
Bobbin: Philips part #EP10PCB1−8
L = 1.8 H
Coilcraft P3270−A
Power FET: AAVID Heatsink #533902B02554 with clip
All power devices are insulated with Berquist Sil−Pad 1500
5 (1.5 ) resistors in parallel
T1
L1
1
2
Heatsinks −
Output Rectifiers: AAVID Heatsink #533402B02552 with clip
Insulators −
−
−
−
−
Test Condition Result
Line Regulation
Load Regulation
Output Ripple
Efficiency
V = 40 V to 56 V, I = 15 A
in O
V = 48 V, I = 8.0 V to 15 A
in O
V = 48 V, I = 15 A
in O
V = 48 V, I = 15 A
in O
μ
Ω
μ
14 mV = 0.275%
54 mV = 1.0%
50 mVp−p
71.2%
±
±
7 turns #18 AWG, 1/2” diameter air core
Coilcraft P3271−A
L2−
2 (1.0 F) cearmic capacitors in parallel
3−μ
10 (1.0 F) ceramic capacitors in parallel
Vin
100
47 k
47
4.7
1N5819
1500 pF
22
5.0 V
T1
22 1500 pF
1N5819
L2
15
13
14
11
12
9
16
4
5
6
7
3
2
1
8
2.0 k
1000 pF
1.2 k
1.0
0.01
22 k
0.015 Fμ
47 k
0.01
Error
Amp
1.25 V
Oscillator
4.0 V
9.0 Aμ
R
S
Q
10
Shutdown 1.4 V
Current
Limit
9.2 V
100
47
1N5819
4.7
4.7
1N5819
10
10
100
220 pF
R
S
Q
0.5 V
Reference
Regulator
1.0 V
PWM Latch
MBR2535CTL
Ω0.3
L1
2.0 Fμ
10 Fμ
IRF640
50
1600 pF
1.8 Hμ900 nH
36 V to 56 V
VO
3
2
1
Q
Q
T
Figure 37. Application Circuit
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16
4.0″
6.5″
(Top View)
Figure 38. PC Board With Components
100 pF
1+
10
+
1000 pF
0.01
0.01
2200 pF
1N5819
1N5819
1N5819
1N5819
MBR
2535CTI
1500 pF
MBR
2535CTI
1500 pF
1
1
4.7 Hμ
100 pF
MC34025, MC33025
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17
(Top View)
Figure 39. PC Board Without Components
4.0″
6.5″
(Bottom View)
MC34025, MC33025
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18
ORDERING INFORMATION
Device Package Shipping†
MC33025DWG SOIC−16WB
(Pb−Free)
47 Units / Rail
MC33025DWR2G SOIC−16WB
(Pb−Free)
1000 Units / Tape & Reel
MC33025PG PDIP−16
(Pb−Free)
25 Units / Rail
MC34025DWG SOIC−16WB
(Pb−Free)
47 Units / Rail
MC34025DWR2G SOIC−16WB
(Pb−Free)
1000 Units / Tape & Reel
MC34025PG PDIP−16
(Pb−Free)
25 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
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PACKAGE DIMENSIONS
SOIC−16WB
DW SUFFIX
CASE 751G−03
ISSUE C
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45_
M
B
M
0.25
H8X
E
B
A
e
T
A1
A
L
C
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
__
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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MC34025/D
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