Advisory July 2002 TSI-8 Time-Slot Interchanger Introduction TXD Precharge Resistors This document describes technical issues that are known to exist with the device and/or the documentation of the device. TXD[23:00] are not properly equipped with precharge resistors. Issues External precharge resistors for TXD[23:00] must be provided if hot insertion is required by the application. TXD Buffer Strength The TXD[31:00] output buffers are capable of excessive output drive, resulting in excessive overshoot and undershoot. Workaround Series source and termination resistors may be required for TXD[31:00] to achieve acceptable signal integrity. Corrective Action This will be corrected in a future respin. Workaround Corrective Action This will be corrected in a future respin. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. Copyright (c) 2002 Agere Systems Inc. All Rights Reserved July 2002 AY02-027SWCH (Must accompany DS02-121SWCH, DS02-122SWCH, and DS02-123SWCH) Advance Information May 2002 TSI-8 Time-Slot Interchanger Product Description Introduction Features This document is a high-level description for the TSI-8 time-slot interchanger device. The features and functions of the device are listed and explained at a level intended to meet the needs of the system design and component selection processes. Any standards governing the operation of the device are referenced, and the level of compliance is stated as appropriate. Broad definitions of its intended applications are given. 8,192 input channels x 8,192 output channels nonblocking DS0 time-slot interchange fabric. 32 full-duplex, serial time-division multiplexer (TDM) concentration highway interfaces. Compatible with GCI, SLD interfaces, and H.110. Data rate selection of 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s per highway. Bit and byte offset to 1/4 bit resolution per highway. Frame integrity mode to ensure intact transfer of wideband data (N x DS0, ISDN H-channels). Low-latency mode for minimum delay on voice channels. 16-bit synchronous microprocessor interface for access to connection data and device registers. 16 programmable time-slot translation tables allow for real-time digital transform of TDM data. These are selected per connection to provide fixed gain/ loss, A-law to -law conversion, etc. Related Documents More information on the TSI-8 is contained in the following documents: The hardware design guide contains all information relevant to the use of the device in a board design. Pin descriptions, dc electrical characteristics, timing diagrams, ac timing parameters, packaging, and operating conditions are included. The register description defines the address map for the TSI-8, and describes the purpose and operation of each register bit, its dependencies and initial state. The systems design guide describes how to design software and hardware to support the device in various applications. The initialization procedure as well as some fundamental test setups for loopbacks and pattern generation are also described. IEEE(R) 1149.1 boundary-scan test port (JTAG). Pattern generation and checking for on-line system testing (pseudorandom bit sequence (PRBS), quasirandom signal sequence (QRSS), or userdefined byte). Low-power 1.5 V core power supply with 3.3 V digital I/O compatibility. 240-pin ball grid array (PBGA) package, 19 mm square with 1.0 mm ball pitch. -40 C to +85 C industrial temperature range. TSI-8 Time-Slot Interchanger Product Description Advance Information May 2002 Applications Description The TSI-8 is suited to a wide variety of small-tomedium sized DS0 TDM switch applications. It has sufficient capacity to support up to an OC-12 link containing 64 kbits/s channels; it can provide useful grooming, first-stage switching, loopback, and test access on high-density transmission port cards (e.g., OC-12, OC-3, and DS3). For lower-density systems, with several T1 ports for example, it can support all the DS0 switching needs for the entire system. Typical applications include: The TSI-8 time-slot interchanger (TSI) is a time/space switch with DS0 granularity. The fabric is a nonblocking structure with 8,192 input channels that may be interchanged to any of 8,192 output channels. The input and output channels are arranged on timedivision multiplexed serial highways. The timing and structure of these highways complies with Agere Systems Inc. concentration highway interface (CHI) standard. Each CHI is independently programmed, and the output CHIs support multidriver busing. The CHIs have a programmable data rate (up to 16.384 Mbits/s) and frame offset. Transmit and receive configurations are also independently programmable. The TSI-8 is configured via a 16-bit synchronous microprocessor interface, which is used to control the connection data and to access the device's registers. Central office TDM switch. Integrated access devices. Next-generation digital loop carriers. Digital cross connects. Remote access concentrators. Remote access servers. Voice/IP gateways. Multiservice access platforms. Wireless base stations. Terminal multiplexer. The TSI-8 supports a number of additional time-slot test and code substitution functions in addition to its primary switching role. These options are programmed in a similar fashion to normal connections, by setting special bits in the connection control store. A frame integrity mode ensures constant delay for bonded DS0 channels in applications that switch wideband data (i.e., N x DS0 or ISDN H-channels). Low latency mode ensures minimal delay for voice circuits. Figure 1 represents a high-level block diagram of the TSI-8. 2 Agere Systems Inc. TSI-8 Time-Slot Interchanger Product Description Advance Information May 2002 Description (continued) Block Diagram TEST PATTERN GENERATOR TEST PATTERN MONITOR TRANSLATION TABLE LOOKUP TEST ACCESS PORT SWITCH FABRIC 32 RECEIVE CHI TRANSMIT CHI DATA STORE WRITE ADDRESS COUNTER CONNECTION STORE READ ADDRESS COUNTER 32 MICROPROCESSOR INTERFACE CLOCK GENERATOR Figure 1. TSI-8 Block Diagram Agere Systems Inc. 3 TSI-8 Time-Slot Interchanger Product Description Advance Information May 2002 Switch Fabric Expansion The switch fabric performs the nonblocking switching function. It can switch any of the 8,192 possible incoming time slots to any of the 8,192 possible outgoing time slots. It uses the classic configuration of two memories, one containing the traffic data and the second containing the switching configuration. The switch fabric performs this switching function without regard to the physical link from which the time slot was taken; hence, the TSI-8 TSI is a time-space switch. Time slots are rearranged in order within a frame (time) and among physical ports (space). To interconnect more DS0 traffic than the 8,192 input and 8,192 output time slots, which a single TSI-8 allows, a geometric expansion of TSIs will be needed. The best alternative would be to use the TSI-16 or STSI-144 device, which allows a linear growth in 16k increments by adding a single device at each growth stage up to a maximum of 144k time slots with as few as nine devices. See the TSI-16 and/or STSI-144 documentation for more details. Time-slot data from the input TDM highways is converted to a common-rate parallel format by the CHI blocks. These data are written into the data store sequentially. The write address for the address for the data store is generated from the system clock (CHICLK) and frame synchronization (FSYNC) pulse; the clock is multiplied up to 164 MHz by a PLL in the clock generator block so that all 8,192 input time slots can be written into the data store during a 125 s frame. The entire switching operation from the input to output CHIs is synchronous to the CHICLK and frame locked to FSYNC. Connections are established by programming the connection store. Each time slot on the output highways has an associated address in the connection store; each of those locations may be programmed with the input highway and time slot to which a connection is required. The connection store is also used to program all other per-time-slot options, such as frame integrity, translation table look-up, and test pattern insertion. The switch fabric has the ability to select one of the following two latency modes for each connection: Frame integrity. Frame integrity mode ensures proper operation with wideband data by getting all of the time slots in an output frame from the same input frame. Low latency. Low latency mode minimizes delay for voice applications. The time-slot interchanger core is a memory-based implementation consisting of a data store and a connection store. The data store provides temporary storage for each of the 8,192 input TDM time slots. Received serial data is converted to parallel format, stored sequentially in the data store, and read to output time slots under control of data in the connection store. The connection store contains setup information for each of the 8,192 output time slots. 4 Microprocessor Interface The TSI-8 has a versatile 16-bit microprocessor interface that provides access to its registers and connection store. It is designed to connect directly to the address and data buses of a synchronous generalpurpose microprocessor and is compatible with Motorola (R), Intel (R), and other nonmultiplexed bus structures. The required microprocessor signals are as follows: 16-bit data bus (DATA[15:00]). 16-bit address bus (ADDR[15:00]). Four control lines (chip select (CS), address strobe (AS), read/write (R/W), and data transfer acknowledge (DT)). A processor clock (MPUCLK). Interrupt output (INT). The connection store and device configuration registers are directly addressed. The TSI-8 generates interrupts on certain error conditions--illegal address, CHI timings errors, for example. These may all be masked individually. Concentration Highway Interface (CHI) The TSI-8 transmits and receives time-slot data via 32 transmit CHIs and 32 receive CHIs, which are single-ended serial TDM links. A programmable clock signal and a global frame synchronization pulse signal provide the required timing references to the CHI interface. The TSI-8 supports CHIs with unaligned framing; that is, each CHI's offset from the frame synchronization signal is independently programmable. Although the frame offsets can be different, they must be locked to a common frame reference. The transmit CHIs may be placed into the high-impedance (Hi-Z) state to allow busing of multiple drivers. Each CHI may be independently configured for direct connection to a variety of serial TDM interfaces operating at a Agere Systems Inc. TSI-8 Time-Slot Interchanger Product Description Advance Information May 2002 CHI Frame Offset Selection Concentration Highway Interface (CHI) (continued) variety of data rates, including GCI, SLD, and H.110. Each CHI supports data rates of 2.048 Mbits/s (32 time slots), 4.096 Mbits/s, 8.192 Mbits/s, and 16.384 Mbits/s (256 time slots). The receive CHI block reformats the serial CHI input data into a parallel format so that it can be written as 8-bit words into the data store. A 164 MHz clock is used for those transfers. This clock is derived using an internal phase-locked loop. The transmit CHIs are similar in number, format, and flexibility to the receive CHIs. A parallel-serial conversion process is performed, and the time-slot data are slowed down from the 164 MHz internal clock rate to the required CHI output rate (2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s). The output CHI block also makes any time slot or bit offset adjustments that have been programmed. The receive CHIs are single-ended serial TDM interfaces. The transmit CHIs can be configured as bidirectional. In this case, the CHI receive (Rx) input is disabled and the input CHI data comes from the bidirectional TXD signal. The transmit drivers can be set to a high-impedance state, and the device output pin can be driven with input CHI data. This output enable can be configured independently for each time slot to support multiplexed TDM bus architectures such as H.110. Thirty-two hot-swapable bidirectional TDM ports can be configured for compatibility with H.110. TSI-8 supports unaligned (but synchronous) TDM data streams. Each input CHI and each output CHI has a programmable offset (see Table 1) ranging from 0 to virtually a full frame. The TDM streams can be timed to align with the connecting device rather than having to be absolutely aligned with the TSI-8 frame synchronization input. Test Pattern Generator and Monitor The test pattern generator (TPG) and test pattern monitor (TPM) are a set of selectable test logic for support of transmission facility testing and maintenance. This block can supply and check any one of the test patterns defined in ITU-T O.150, O.151, or O.152, as well as user-defined patterns. Any combination of DS0s can be concatenated as a single broadband stream to test high-speed facilities. Additionally, the TPG/TPM provides the ability to perform diagnostic tests at both the system and device levels of operation. System-level troubleshooting is facilitated with full narrowband/wideband test pattern generation and detection. Extensive device-level testing can quickly be performed with specialized test pattern generation and monitoring functions targeted at the CHI interface as well as the switch fabric itself. An effective self-test can be performed by configuring a test path and using the TPG/TPM and the internal loopback capabilities of the CHIs. Test pattern generation and monitoring options are configured using the connection store. Only one type of test pattern can be transmitted at once, but it may be concatenated on any number of channels. The test pattern monitor may only check a single pattern on one time slot or wideband channel. Table 1. Fractional Bit Offset Resolution CHI Data Rate CHICLK 2.048 Mbits/s 8.192 MHz 1/4 bit (122.1 ns) 1/4 bit (122.1 ns) 2.048 Mbits/s 16.384 MHz 1/4 bit (122.1 ns) 1/4 bit (122.1 ns) 4.096 Mbits/s 8.192 MHz 1/4 bit (61.0 ns) 1/4 bit (61.0 ns) 4.096 Mbits/s 16.384 MHz 1/4 bit (61.0 ns) 1/4 bit (61.0 ns) 8.192 Mbits/s 8.192 MHz 1/4 bit (30.5 ns) 1/2 bit (61.0 ns) 8.192 Mbits/s 16.384 MHz 1/4 bit (30.5 ns) 1/4 bit (30.5 ns) 16.384 Mbits/s 16.384 MHz 1/4 bit (15.25 ns) 1/2 bit (30.5 ns) Agere Systems Inc. Receive Offset Resolution Transmit Offset Resolution 5 TSI-8 Time-Slot Interchanger Product Description Advance Information May 2002 Translation Table Look-Up Logic Clocks The translation table look-up (TTL) logic is a set of 16 look-up tables that can optionally be inserted in the TDM path at the output of the switch fabric. This allows the end user to perform real-time digital transforms on the outgoing TDM data. These look-up tables are user programmable and are useful for various TDM related transform functions such as -law to A-law conversion, gain adjustment, or message conversion for static (i.e., robbed bit) signaling schemes. The various transforms can be selected on a per-time-slot basis by programming the connection store. The TSI-8 has two clock domains: one used for TDM data and the second used for the microprocessor interface. Delay Through the TSI-8 The second timing domain is used for the microprocessor interface. The MPUCLK input should be supplied along with the microprocessor data, address, and control signals. Typically, this is available as an output on most microprocessors, and is often referred to as the peripheral clock. For each connection written to the connection store, the switch fabric is set to operate in low latency mode or frame integrity mode. Low latency mode operates with minimum delay of a DS0 byte from an input to output time slot and is typically selected for voice applications. Frame integrity mode ensures intact switching of wideband data so that all the bonded time slots in one 125 s input frame are switched to the same 125 s output frame. Assuming the most favorable conditions, the minimum switch time (first bit in to first bit out) is two time-slot periods. The longest delay in low latency mode is about one frame plus three time slots. The longest delay in frame integrity mode is about three frames plus three time slots. 6 The input and output CHIs are in the TDM timing domain. The CHICLK input, which may be 16.384 MHz or 8.192 MHz, is the reference source for the TDM timing. Internally, this clock is multiplied up to 164 MHz for internal data transfer. An on-chip PLL is used for this purpose. An 8 kHz frame synchronization pulse is also required that must be synchronous with CHICLK. This is used as a reference for all the time-slot locations in the transmit and receive CHIs. Reset The TSI-8 has a hardware reset input that is used to initialize various internal logic functions. This may be used during initialization and for device and board-level testing. A similar reset is available as a register bit to allow hardware reset under software control. Note: Neither of these resets affects the contents of the data store, or more importantly, the connection store. However, the reset does put the device into a benign state (outputs high impedance or inactive). Agere Systems Inc. TSI-8 Time-Slot Interchanger Product Description Advance Information May 2002 Ordering Information Device Part Number Ball Count Package Comcode TSI-8 TTSI008321BL-1 240 PBGAM1 109101907 Agere Systems Inc. 7 IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of Intel Corporation. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. Copyright (c) 2002 Agere Systems Inc. All Rights Reserved May 2002 DS02-121SWCH