Data Sheet
V1.2 2016-08
Microcontrollers
XMC™1400 AA-Step
Microcontroller Series
for Industrial Applications
XMC™1000 Family
ARM® Cortex®-M0
32-bit processor core
Edition 2016-08
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
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Data Sheet
V1.2 2016-08
Microcontrollers
XMC™1400 AA-Step
Microcontroller Series
for Industrial Applications
XMC™1000 Family
ARM® Cortex®-M0
32-bit processor core
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet V1.2, 2016-08
Trademarks
C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered®, Cortex®, Thumb® and AMBA® are registered trademarks of
ARM, Limited.
CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are
trademarks of ARM, Limited.
XMC1400 Data Sheet
Revision History: V1.2 2016-08
Previous Versions:
V1.1 2016-06
V1.0 2016-02
V0.3 2015-10
Page Subjects
many Added XMC™ trademark
10, 12, 14 Added XMC1402-T 038X0200, XMC1402-Q040X0200 and
XMC1402-Q048X0200 marking variants
V1.1 2016-06
many Added TSSOP-38-9 package
10, 12, 14 Added XMC1402-T038 marking variants in TSSOP-38
10, 12, 14 Added XMC1403-Q040 marking variants
V1.0 2016-02
9The device provides four USIC channels.
10 XMC1401 devices available for max. ambient temperature of 85°C.
32 Reformatted pinout table.
57 Updated footnote to the definition of the start-up times of OSC_XTAL and
RTC_XTAL oscillators.
72 Added ΔfLT parameter to on-chip oscillators DCO1 and DCO2.
84 Update d pa cka ge outline dr aw i ngs.
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve th e quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Table of Contents
Data Sheet 5 V1.2, 2016-08
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Pin Configuration and Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.1 Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2.2 Port Pin for Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.3 Port I/O Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.4 Hardware Controlled I/O Function Description . . . . . . . . . . . . . . . . . . . 31
3 Electrical Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.1.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.1.4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.1 Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.2 Analog to Digital Converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2.3 Out of Range Comparator (ORC) Characteristics . . . . . . . . . . . . . . . . . 53
3.2.4 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2.5 Temperature Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.2.6 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2.7 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.2.8 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3.2 Power-Up and Supply Threshold Characteristics . . . . . . . . . . . . . . . . . 70
3.3.3 On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.3.4 Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . . 73
3.3.5 SPD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.3.6 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.3.6.1 Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 75
3.3.6.2 Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.3.6.3 Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 80
4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table of Contents
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Table of Contents
Data Sheet 6 V1.2, 2016-08
4.1.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5 Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
About this Document
Data Sheet 7 V1.2, 2016-08
About this Document
This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of the XMC1400 series devices.
The document describes the characteristics of a superset of the XMC1400 series
devices. For simplicity, the various device types are referred to by the collective term
XMC1400 throughout this document.
XMC™1000 Family User Documentation
The set of user documentation includes:
•Reference Manu al
– decribes the functionality of the superset of devices.
•Data Sheets
– list the complete ordering designations, available features and electrical
characteristics of derivative devices.
•Errata Sheets
– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about your device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc1000 to get access to the latest versions
of those documents.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Summary of Features
Data Sheet 8 V1.2, 2016-08
1 Summary of Features
The XMC1400 devices are members of the XMC™1000 Family of microcontrollers based
on the ARM Cortex-M0 processor core. The XMC1400 series addresses the real-time
control needs of motor control and digital power conversion. It also features peripherals
for LED Lighting applications and Human-Machine Interface (HMI).
Figure 1 Block Diagram
CCU80
CCU81
POSIF0
POSIF1
AHB-Lite Bus
MATH
WDT
SCU
APB Bus
PRNG
LEDTS0
LEDTS1
LEDTS2
BCCU0
FLASH
1
SRAM
ROM
DTS
Analog
System
ANACTRL
2 x DCO
EVR
AHB to APB
Bridge
PAU
ACMP &
ORC
PORTS RTC
ERU0
USIC1
USIC0 VADC
CCU40
CCU41MultiCAN+
ERU1
Debug
System
SWD
CPU
ARM
®
Cortex
®
–
M0
NVIC SPD
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 9 V1.2, 2016-08
Features
CPU subsystem
• 32-bit ARM Cortex-M0 CPU Core
– 0.84 DMIPS/MHz (Dhrystone 2.1) at
48 MHz
• Nested Vectored Interrupt Controller
• 64 interrupt nodes
• MATH coprocessor
– 24-bit trigonometric calculation
(CORDIC)
– 32-bit divide operation
• 2x4 channels ERU for event
interconnections
On-Chip Memories
•8Kbyte ROM
• 16 Kbyte SRAM (with parity)
• up to 200 Kbyte Flash (with ECC)
Supply, Reset and Clock
• 1.8 V to 5.5 V supply with power on reset
and brownout detector
• On-chip clock monitor
• External crystal oscillator support (32 kHz
and 4 to 20 MHz)
• Internal slow and fast oscillators without
the need of PLL
System Control
• Window watchdog
• Real time clock module
• Pseudo random number generator
Communication Peripherals
• Four USIC channels, usable as
– UART (up to 12 Mb/s)
– single-SPI (up to 12 Mb/s)
– double-SPI (up to 2 ×12 Mb/s)
– quad-SPI (up to 4 ×12 Mb/s)
– IIC (up to 400 kb/s)
– IIS (up to 12 Mb/s)
– LIN interfaces (20kb/s)
• LEDTS in Human-Machine interface
– up to 24 touch pads
– drive up to 144 LEDs
• MultiCAN+, Full-CAN/Basic-CAN with 2
nodes, 32 message objects (up to
1 MBaud)
Analog Frontend Peripherals
• A/D Converters (up to 12 analog inputs)
– 2 sample and hold stages
– fast 12-bit ADC (up to 1.1 MS/s),
adjustable gain
– 0 V to 5.5 V input range
• Up to 8 channels out of range
comparators
• Up to 4 fast analog comparators
• Temperature Sensor
Industrial Control Peripherals
• 2x4 16-bit 96 MHz CCU4 timers for signal
monitoring and PWM
• 2x4 16-bit 96 MHz CCU8 timers for
complex PWM, complementary high/low
side switches and multi phase control
• 2x POSIF for hall and quadrature
encoders, motor positioning
• 9 channel BCCU (brightness and color
control) for LED lighting applications
Up to 56 Input/Output Ports
• 1.8 V to 5.5 V capable
• up to 8 high current pads (50 mA sink)
On-Chip Debug Support
• 4 breakpoints, 2 watchpoints
• ARM serial wire debug, single-pin debug
interfaces
Programming Support
• Single-pin bootloader
• Secure bootstrap loader SBSL (optional)
Packages
• TSSOP-38 (9.7 ×6.4 mm2)
• VQFN-40/48/64 (5×5/7×7/8×8mm
2)
•LQFP-64 (12 ×12 mm2)
Tools
• Free DAVE™ toolchain with low
level drivers and apps
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 10 V1.2, 2016-08
1.1 Device Overview
The following table lists the available features per device type for the XMC1400 series.
Table 1 Features of XMC1400 Device Types1)
Features
XMC1401-Q048
XMC1401-F064
XMC1402-T038
XMC1402-Q040
XMC1402-Q048
XMC1402-Q064
XMC1402-F064
XMC1403-Q040
XMC1403-Q048
XMC1403-Q064
XMC1404-Q048
XMC1404-Q064
XMC1404-F064
CPU frequency 48 MHz
Operating
temperature
(ambient)
-40 to
85 °C -40 to 105 °C
Operating
voltage 1.8 V to 5.5 V
Flash options
(Kbytes) 64,
128 64,
128 32,
64,
128
200
32,
64,
128
200
32,
64,
128
200
64,
128
200
64,
128
200
64,
128
200
64,
128
200
64,
128
200
64,
128
200
64,
128
200
64,
128
200
SRAM (Kbytes) 16 16 16 16 16 16 16 16 16 16 16 16 16
MATH --11111---111
Industrial Control
CCU4 2222222222222
CCU8 - - 2 2 222- - - 222
POSIF --11222---222
BCCU --11111---111
Communication
USIC
(modules /
channels)
2/
22/
22/
22/
22/
22/
22/
22/
22/
22/
22/
22/
22/
2
LEDTS 33--------333
MultiCAN+
(nodes /
MOs)
-------2/
32 2/
32 2/
32 2/
32 2/
32 2/
32
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 11 V1.2, 2016-08
1.2 Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC1<DDD>-<Z><PPP><T><FFFF>” identifies:
• <DDD> the derivatives function set
• <Z> the package variant
– T: TSSOP
–Q: VQFN
–F: LQFP
• <PPP> package pin count
• <T> the temperature range:
– F: -40°C to 85°C
– X: -40°C to 105°C
• <FFFF> the Fla sh memory size in Kbytes.
For ordering codes for the XMC1400 plea se contact your sales representative or local
distributor.
This document describes several derivatives of the XMC1400 series, some descriptions
may not apply to a specific product. Please see Table 2.
For simplicity the term XMC1400 is used for all derivatives throughout this document.
Analog
ADC
(kernels /
analog
inputs)
2/
12 2/
12 2/
12 2/
12 2/
12 2/
12 2/
12 2/
12 2/
12 2/
12 2/
12 2/
12 2/
12
ACMP --33444---444
GPIOs 34 48 26 27 34 48 48 27 34 48 34 48 48
GPIs 8888888888888
Packages
VQFN-48
LQFP-64
TSSOP-38
VQFN-40
VQFN-48
VQFN-64
LQFP-64
VQFN-40
VQFN-48
VQFN-64
VQFN-48
VQFN-64
LQFP-64
1) Features that are not included in this table are available in all the derivatives
Table 1 Features of XMC1400 Device Types1) (cont’d)
Features
XMC1401-Q048
XMC1401-F064
XMC1402-T038
XMC1402-Q040
XMC1402-Q048
XMC1402-Q064
XMC1402-F064
XMC1403-Q040
XMC1403-Q048
XMC1403-Q064
XMC1404-Q048
XMC1404-Q064
XMC1404-F064
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 12 V1.2, 2016-08
1.3 Device Types
These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 2 Synopsis of XMC1400 Device Types
Derivative Package Flash Kbytes
XMC1401-Q048F0064 PG-VQFN-48 64
XMC1401-Q048F0128 PG-VQFN-48 128
XMC1401-F064F0064 PG-LQFP-64 64
XMC1401-F064F0128 PG-LQFP-64 128
XMC1402-T038X0032 PG-TSSOP-38 32
XMC1402-T038X0064 PG-TSSOP-38 64
XMC1402-T038X0128 PG-TSSOP-38 128
XMC1402-T038X0128 PG-TSSOP-38 200
XMC1402-Q040X0032 PG-VQFN-40 32
XMC1402-Q040X0064 PG-VQFN-40 64
XMC1402-Q040X0128 PG-VQFN-40 128
XMC1402-Q040X0200 PG-VQFN-40 200
XMC1402-Q048X0032 PG-VQFN-48 32
XMC1402-Q048X0064 PG-VQFN-48 64
XMC1402-Q048X0128 PG-VQFN-48 128
XMC1402-Q048X0128 PG-VQFN-48 200
XMC1402-Q064X0064 PG-VQFN-64 64
XMC1402-Q064X0128 PG-VQFN-64 128
XMC1402-Q064X0200 PG-VQFN-64 200
XMC1402-F064X0064 PG-LQFP-64 64
XMC1402-F064X0128 PG-LQFP-64 128
XMC1402-F064X0200 PG-LQFP-64 200
XMC1403-Q040X0064 PG-VQFN-40 64
XMC1403-Q040X0128 PG-VQFN-40 128
XMC1403-Q040X0200 PG-VQFN-40 200
XMC1403-Q048X0064 PG-VQFN-48 64
XMC1403-Q048X0128 PG-VQFN-48 128
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 13 V1.2, 2016-08
XMC1403-Q048X0200 PG-VQFN-48 200
XMC1403-Q064X0064 PG-VQFN-64 64
XMC1403-Q064X0128 PG-VQFN-64 128
XMC1403-Q064X0200 PG-VQFN-64 200
XMC1404-Q048X0064 PG-VQFN-48 64
XMC1404-Q048X0128 PG-VQFN-48 128
XMC1404-Q048X0200 PG-VQFN-48 200
XMC1404-Q064X0064 PG-VQFN-64 64
XMC1404-Q064X0128 PG-VQFN-64 128
XMC1404-Q064X0200 PG-VQFN-64 200
XMC1404-F064X0064 PG-LQFP-64 64
XMC1404-F064X0128 PG-LQFP-64 128
XMC1404-F064X0200 PG-LQFP-64 200
Table 2 Synopsis of XMC1400 Device Types (cont’d)
Derivative Package Flash Kbytes
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 14 V1.2, 2016-08
1.4 Chip Identification Number
The Chip Identification Number allows software to i dentify the ma rking. It is an 8 words
value with the most significant 7 words stored in Flash configur ation sector 0 (CS0) at
address location : 1000 0F00H (MSB) - 1000 0F1BH (LSB). The least significant word and
most significant word of the Chip Identification Number are the value of registers
DBGROMID and IDCHIP, respectively.
Table 3 XMC1400 Chip Identification Number
Derivative Value Marking
XMC1401-Q048F0064 00014082 07CF00FF 1E0 71FF7 20006000
00000D00 00001000 00011000 10204083H
AA
XMC1401-Q048F0128 00014082 07CF00FF 1E0 71FF7 20006000
00000D00 00001000 00021000 10204083H
AA
XMC1401-F064F0064 000140A2 07CF00FF 1E071FF7 20006000
00000D00 00001000 00011000 10204083H
AA
XMC1401-F064F0128 000140A2 07CF00FF 1E071FF7 20006000
00000D00 00001000 00021000 10204083H
AA
XMC1402-T038X0032 00014013 07F F00FF 1E071FF7 000F900 F
00000D00 00001000 00009000 10204083H
AA
XMC1402-T038X0064 00014013 07F F00FF 1E071FF7 000F900 F
00000D00 00001000 00011000 10204083H
AA
XMC1402-T038X0128 00014013 07F F00FF 1E071FF7 000F900 F
00000D00 00001000 00021000 10204083H
AA
XMC1402-T038X0200 00014013 07F F00FF 1E071FF7 000F900 F
00000D00 00001000 00033000 10204083H
AA
XMC1402-Q040X0032 00014043 07FF00FF 1E071FF7 000F900F
00000D00 00001000 00009000 10204083H
AA
XMC1402-Q040X0064 00014043 07FF00FF 1E071FF7 000F900F
00000D00 00001000 00011000 10204083H
AA
XMC1402-Q040X0128 00014043 07FF00FF 1E071FF7 000F900F
00000D00 00001000 00021000 10204083H
AA
XMC1402-Q040X0200 00014043 07FF00FF 1E071FF7 000F900F
00000D00 00001000 00033000 10204083H
AA
XMC1402-Q048X0032 00014083 07FF00FF 1E071FF7 100F900F
00000D00 00001000 00009000 10204083H
AA
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 15 V1.2, 2016-08
XMC1402-Q048X0064 00014083 07FF00FF 1E071FF7 100F900F
00000D00 00001000 00011000 10204083H
AA
XMC1402-Q048X0128 00014083 07FF00FF 1E071FF7 100F900F
00000D00 00001000 00021000 10204083H
AA
XMC1402-Q048X0200 00014083 07FF00FF 1E071FF7 100F900F
00000D00 00001000 00033000 10204083H
AA
XMC1402-Q064X0064 00014093 07FF00FF 1E071FF7 100F900F
00000D00 00001000 00011000 10204083H
AA
XMC1402-Q064X0128 00014093 07FF00FF 1E071FF7 100F900F
00000D00 00001000 00021000 10204083H
AA
XMC1402-Q064X0200 00014093 07FF00FF 1E071FF7 100F900F
00000D00 00001000 00033000 10204083H
AA
XMC1402-F064X0064 000140A3 07FF00FF 1E071FF7 100F900F
00000D00 00001000 00011000 10204083H
AA
XMC1402-F064X0128 000140A3 07FF00FF 1E071FF7 100F900F
00000D00 00001000 00021000 10204083H
AA
XMC1402-F064X0200 000140A3 07FF00FF 1E071FF7 100F900F
00000D00 00001000 00033000 10204083H
AA
XMC1403-Q040X0064 00014043 07CF00FF 1E071FF7 00B00000
00000D00 00001000 00011000 10204083H
AA
XMC1403-Q040X0128 00014043 07CF00FF 1E071FF7 00B00000
00000D00 00001000 00021000 10204083H
AA
XMC1403-Q040X0200 00014043 07CF00FF 1E071FF7 00B00000
00000D00 00001000 00033000 10204083H
AA
XMC1403-Q048X0064 00014083 07CF00FF 1E071FF7 00B00000
00000D00 00001000 00011000 10204083H
AA
XMC1403-Q048X0128 00014083 07CF00FF 1E071FF7 00B00000
00000D00 00001000 00021000 10204083H
AA
XMC1403-Q048X0200 00014083 07CF00FF 1E071FF7 00B00000
00000D00 00001000 00033000 10204083H
AA
XMC1403-Q064X0064 00014093 07CF00FF 1E071FF7 00B00000
00000D00 00001000 00011000 10204083H
AA
XMC1403-Q064X0128 00014093 07CF00FF 1E071FF7 00B00000
00000D00 00001000 00021000 10204083H
AA
Table 3 XMC1400 Chip Identification Number (cont’d)
Derivative Value Marking
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 16 V1.2, 2016-08
XMC1403-Q064X0200 00014093 07CF00FF 1E071FF7 00B00000
00000D00 00001000 00033000 10204083H
AA
XMC1404-Q048X0064 00014083 07FF00FF 1E071FF7 30BFF00F
00000D00 00001000 00011000 10204083H
AA
XMC1404-Q048X0128 00014083 07FF00FF 1E071FF7 30BFF00F
00000D00 00001000 00021000 10204083H
AA
XMC1404-Q048X0200 00014083 07FF00FF 1E071FF7 30BFF00F
00000D00 00001000 00033000 10204083H
AA
XMC1404-Q064X0064 00014093 07FF00FF 1E071FF7 30BFF00F
00000D00 00001000 00011000 10204083H
AA
XMC1404-Q064X0128 00014093 07FF00FF 1E071FF7 30BFF00F
00000D00 00001000 00021000 10204083H
AA
XMC1404-Q064X0200 00014093 07FF00FF 1E071FF7 30BFF00F
00000D00 00001000 00033000 10204083H
AA
XMC1404-F064X0064 000140A3 07FF00FF 1E071FF7 30BFF00F
00000D00 00001000 00011000 10204083H
AA
XMC1404-F064X0128 000140A3 07FF00FF 1E071FF7 30BFF00F
00000D00 00001000 00021000 10204083H
AA
XMC1404-F064X0200 000140A3 07FF00FF 1E071FF7 30BFF00F
00000D00 00001000 00033000 10204083H
AA
Table 3 XMC1400 Chip Identification Number (cont’d)
Derivative Value Marking
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 17 V1.2, 2016-08
2 General Device Information
This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1 Logic Symbols
Figure 2 XMC1400 Logic Symbol for TSSOP-38-9
XMC1400
TSSOP-38
Port 0
12 bit
V
DDP
(2) V
SSP
(2)
Port 0 / XTAL
4 bit
P ort 1 / Hi gh-current
6bit
P ort 2 / A nal og i nput
4 bit
P ort 2 / A nal og i nput
8 bit
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 18 V1.2, 2016-08
Figure 3 XMC1400 Logic Symbol for PG-VQFN-40-17
XMC1400
VQFN-40
V
DD
(1)
V
SS
(1)
Port 0
12 bit
V
DDP
(2)
V
SSP
(1)
Port 0 / XTAL
4 bit
P ort 1 / Hi gh-current
7 bit
P ort 2 / A nal og i nput
4 bit
P ort 2 / A nal og i nput
8 bit
Exp. Die Pad
(
V
SSP
)
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 19 V1.2, 2016-08
Figure 4 XMC1400 Logic Symbol for PG-VQFN-48-73
XMC1400
VQFN-48
VDD
(1)
VSS
(1)
Port 0
12 bi t
VDDP
(3)
VSSP
(1)
P ort 2 / A nal og input
6 bi t
P ort 2 / A nal og input
8 bi t
Port 3
1 bi t
Port 4
4 bi t
Port 0 / XTA L
4 bi t
Exp. Die Pad
(
VSSP
)
P ort 1 / Hi gh-c urrent
7 bit
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 20 V1.2, 2016-08
Figure 5 XMC1400 Logic Symbol for PG-LQFP-64-26 / PG-VQFN-64-6
XMC1400
VQFN -64 / LQFP-64
V
DD
(1)
V
SS
(1)
V
DDP
(4)
V
SSP
(2)
P ort 1 / Hi gh -current
8 bi t
Port 1
1 bi t
Port 0
12 bit
Port 0 / XTAL
4 bit
Exp . Die Pa d
(
V
SSP
)
1)
1) VQFN64 only
Port 2 / Analog input
6 bit
Port 2 / Analog input
8 bit
Port 3
5 bit
Port 4
12 bit
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 21 V1.2, 2016-08
2.2 Pin Configuration and Definition
The following figures summarize all pins, showing their locations on the different
packages.
Figure 6 XMC1400 PG-TSSOP-38-9 Pin Configuration (top view)
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 22 V1.2, 2016-08
Figure 7 XMC1400 PG-VQFN-40-17 Pin Configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
13
14
15
24
23
22
21
20
19
18
17
16
36
35
34
33
32
31
30
29
28
27
26
25
37
38
39
40
P0.13
P0.12
A nalog inpu t / P2.0
V
DDP
V
SSP
P0.1
P0.2
P0.0
12
A nalog inpu t / P2.1
Analog input / P2.2
Analog input / P2.3
A nal og in put / P2.4
A nal og in put / P2.5
Analog input / P2.6
A nal og in put / P2 .7
A nal og in put / P2 .8
A nal og in put / P2 .9
Analog input / P2.10
Analog input / P2.11
P 1 . 2 / Hig h-current
P0.6
P0.7
P0.5
P0.3
P0.4
P0.15
P0.14
P0.8 / RTC_XTAL1
P0.9 / RTC_XTAL2
P0.10 / XTAL1
P0.11 / XTAL 2
V
DDP
V
SS
V
DD
P1 .0 / H i g h -c u r rent
P1 .1 / H i g h -c u r rent
P 1 . 3 / Hig h-current
P 1 . 4 / Hig h-current
P 1 . 5 / Hig h-current
P 1 . 6 / Hig h-current
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 23 V1.2, 2016-08
Figure 8 XMC1400 PG-VQFN-48-73 Pin Configuration (top view)
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
45
46
47
48
P0.13
P0.12
P4.6
VDDP
VSSP
P4.7
A nal og i np ut / P2.0
A nal og i nput / P2 . 1
A nal og i np ut / P2.2
A nal og i np ut / P2.3
Analog i nput / P2 .4
Analog input / P2.5
A nal og i np ut / P2.6
A nal og i np ut / P2.7
P0.15
P0.14
11
12
A nal og i np ut / P2.8
A nal og i np ut / P2.9
13
15
16
17
20
19
18
14
22
21
24
23
A nal og i nput / P2.12
Ana l og i npu t / P2.13
28
27
26
25
32
31
30
29
34
33
36
35 P0.6
P0.7
P3.0
P0.1
P0.2
P0.0
P0.5
P0.3
P0.4
VDDP
38
37
P4.4
P4.5
P0.8 / RTC_XTAL1
P0.9 / RTC_XTAL2
P0 . 10 / XT AL 1
P0 . 11 / XT AL 2
VDDP
VSS
VDD
P 1.0 / Hi gh-curre nt
P 1.1 / Hi gh-curre nt
P1 .2 / H ig h -c u rr e nt
P1 .3 / H ig h -c u rr e nt
P1 .4 / H ig h -c u rr e nt
P1 .5 / H ig h -c u rr e nt
P1 .6 / H ig h -c u rr e nt
An al og i n put / P2.10
Ana l og input / P2 .11
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 24 V1.2, 2016-08
Figure 9 XMC1400 PG-LQFP-64-26 / PG-VQFN-64-6 Pin Configuration (top
view)
1
2
3
4
5
6
7
8
9
10
60
59
58
57
56
55
61
62
63
64
P0.13
P0.12
P4.6
P4.7
P0.15
P0.14
11
12
54
53
P4.0
P4.1
13
14
15
16
17
19
20
21
24
23
22
18
26
25
28
27
36
35
34
33
40
39
38
37
42
41
44
43 P0.2
P0.3
P3.0
P3.2
P3.3
P3.1
P0.1
P3.4
P0.0
VDDP
30
29
32
31
46
45 P0.4
P0.5
48
47 P0.6
P0.7
50
49
52
51 P 0. 8 / RTC_XTA L1
VSSP
VDDP
P4.8
P4.9
P4.10
P4.11
Analog input / P2.8
P1.8
P1.7 / High-current
VSSP
VDDP
P4.2
P4.3
P4.4
P4.5
P0.9 / RTC _XTAL2
P0.10 / XT AL1
P0.11 / XT AL2
VDDP
VSS
VDD
P1.0 / High-current
P1.1 / High-current
P1.2 / Hig h-current
P1.3 / Hig h-current
P1.4 / Hig h-current
P1.5 / Hig h-current
P1.6 / Hig h-current
A nalog i nput / P2. 0
Anal og input / P 2. 1
A nalog i nput / P2 .2
Analog input / P2.3
A nalog i nput / P2. 4
A nalog i nput / P2. 5
Analog input / P2.6
Analog input / P2.7
An a log in pu t / P2 .9
Analog input / P2.10
Ana log i nput / P2 .11
Analog input / P2.12
Analog input / P2.13
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 25 V1.2, 2016-08
2.2.1 Package Pin Summary
The following general building block is used to describe each pin:
The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),
followed by the supply pins.
The following columns, title d with the supported package variants, lists the pa ckage pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type:
• STD_INOUT (standard bi-directional pads)
• STD_INOUT/AN (standard bi-directional pads with analog input)
• STD_INOUT/clock (standard bi-directional pads with oscillator function)
• High Current (high current bi-directional pads)
• STD_IN/AN (standard input pads with analog input)
• Power (power supply)
Details about the pad properties are defined in the Electrical Parameter chapter.
Table 4 Package Pin Mapping Description
Function Package A Package B ... Pad Type
Px.y N N Pad Class
Table 5 Package Pin Mapping
Function LQFP
64,
VQFN
64
VQFN
48 VQFN
40 TSSOP
38 Pad Type Notes
P0.0 41 29 23 17 STD_INOUT
P0.1 42 30 24 18 STD_INOUT
P0.2 43 31 25 19 STD_INOUT
P0.3 44 32 26 20 STD_INOUT
P0.4 45 33 27 21 STD_INOUT
P0.5 46 34 28 22 STD_INOUT
P0.6 47 35 29 23 STD_INOUT
P0.7 48 36 30 24 STD_INOUT
P0.8/
RTC_
XTAL1
51 39 33 27 STD_INOUT
/clock_IN
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 26 V1.2, 2016-08
P0.9/
RTC_
XTAL2
52 40 34 28 STD_INOUT
/clock_O
P0.10/
XTAL1 53 41 35 29 STD_INOUT
/clock_IN
P0.11/
XTAL2 54 42 36 30 STD_INOUT
/clock_O
P0.1255433731STD_INOUT
P0.1356443832STD_INOUT
P0.1457453933STD_INOUT
P0.1558464034STD_INOUT
P1.0 34 26 22 16 High Current
P1.1 33 25 21 15 High Current
P1.2 32 24 20 14 High Current
P1.3 31 23 19 13 High Current
P1.4 30 22 18 12 High Current
P1.5 29 21 17 11 High Current
P1.6 28 20 16 - High Current
P1.7 27 - - - High Current
P1.8 26 - - - STD_INOUT
P2.0 9 3 1 35 STD_INOUT
/AN
P2.1 10 4 2 36 STD_INOUT
/AN
P2.2 11 5 3 37 STD_IN/AN
P2.3 12 6 4 38 STD_IN/AN
P2.4 13 7 5 1 STD_IN/AN
P2.5 14 8 6 2 STD_IN/AN
P2.6 15 9 7 3 STD_IN/AN
P2.7 16 10 8 4 STD_IN/AN
Table 5 Package Pin Mapping (cont’d)
Function LQFP
64,
VQFN
64
VQFN
48 VQFN
40 TSSOP
38 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 27 V1.2, 2016-08
P2.8 17 11 9 5 STD_IN/AN
P2.9 18 12 10 6 STD_IN/AN
P2.10 19 13 11 7 STD_INOUT
/AN
P2.11 20 14 12 8 STD_INOUT
/AN
P2.12 21 15 - - STD_INOUT
/AN
P2.13 22 16 - - STD_INOUT
/AN
P3.0 36 28 - - STD_INOUT
P3.1 37 - - - STD_INOUT
P3.2 38 - - - STD_INOUT
P3.3 39 - - - STD_INOUT
P3.4 40 - - - STD_INOUT
P4.0 59 - - - STD_INOUT
P4.1 60 - - - STD_INOUT
P4.2 61 - - - STD_INOUT
P4.3 62 - - - STD_INOUT
P4.4 63 47 - - STD_INOUT
P4.5 64 48 - - STD_INOUT
P4.6 3 1 - - STD_INOUT
P4.7 4 2 - - STD_INOUT
P4.8 5 - - - STD_INOUT
P4.9 6 - - - STD_INOUT
P4.10 7 - - - STD_INOUT
P4.11 8 - - - STD_INOUT
VSS 23 17 13 9 Power Supply GND, ADC
reference GND
Table 5 Package Pin Mapping (cont’d)
Function LQFP
64,
VQFN
64
VQFN
48 VQFN
40 TSSOP
38 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 28 V1.2, 2016-08
VDD 24 18 14 10 Power Supply VDD, ADC
reference voltage/
ORC reference
voltage
VDDP 25 19 15 10 Power When VDD is
supplied, VDDP
has to be supplied
with the same
voltage.
VDDP 2 - - - Power I/O port supply
VDDP 35 27 - - Power I/O port supply
VDDP 50 38 32 26 Power I/O port supply
VSSP 1 - - - Power I/O port ground
VSSP 49 37 31 25 Power I/O port ground
VSSP Exp.
Pad
(in
VQFN
64 only)
Exp.
Pad Exp.
Pad - Power Exposed Die Pad
The exposed die
pad is connected
internally to VSSP.
For proper
operation, it is
mandatory to
connect the
exposed pad to
the board ground.
For thermal
aspects, please
refer to the
Package and
Reliability chapter.
Table 5 Package Pin Mapping (cont’d)
Function LQFP
64,
VQFN
64
VQFN
48 VQFN
40 TSSOP
38 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 29 V1.2, 2016-08
2.2.2 Port Pin for Boot Modes
Port functions can be overruled by the boot mode selected. The type of boot mode is
selected via BMI. Table 6 shows the port pins used for the various boot modes.
Table 6 Port Pin for Boot Modes
Pin Boot Boot Description
P0.13 CS(O) SSC BSL mode
P0.14 SWDIO_0 Debug mode (SWD)
SPD_0 Debug mode (SPD)
RX/TX ASC BSL half-duplex mode
RX ASC BSL full-duplex mode
RX CAN BSL mode
SCLK(O) SSC BSL mode
P0.15 SWDCLK_0 Debug mode (SWD)
TX ASC BSL full-duplex mode
TX CAN BSL mode
DATA(I/O) SSC BSL mode
P1.2 SWDCLK_1 Debug mode (SWD)
TX ASC BSL full-duplex mode
TX CAN BSL mode
P1.3 SWDIO_1 Debug mode (SWD)
SPD_1 Debug mode (SPD)
RX/TX ASC BSL half-duplex mode
RX ASC BSL full-duplex mode
RX CAN BSL mode
P4.6 HWCON0 Boot Pins
(Boot from pins mode must be selected)
P4.7 HWCON1
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 30 V1.2, 2016-08
2.2.3 Port I/O Function Description
The following general building block is used to describe the I/O functions of each PORT
pin:
Figure 10 Simplified Port Structure
Pn.y is the port pin name , d efinin g the con t rol and data bi ts/registers associ ated with i t.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to nine alternate output functions (ALT1 to ALT9) can be mapped to a single port pin,
selected by Pn_IOCR.PC. The output value is directly drive n by the respective module,
with the pin characteristics controlled by the port registers (within the limits of the
connected pad).
The port pin input can be connected to mult iple peripherals. Most peripherals have an
input multiplexer to select between different possi b l e in put sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
Please refer to the Port I/O Functions table for the complete Port I/O function mapping.
Table 7 Port I/O Functi on Description
Function Outputs Inputs
ALT1 ALTn Input Input
P0.0 MODA.OUT MODC.INA
Pn.y MODA.OUT MODA.INA MODC.INB
XMC1000
Pn.y
V
DDP
GND
Pn.y
ALT1
...
ALTn
HWO0
HWO1
SW
Control Logi c
Input 0
Input n
...
PAD
HWI0
HWI1
MODB.OUT
MODB
MODA
MODA.INA
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
General Device Information
Data Sheet 31 V1.2, 2016-08
2.2.4 Hardware Controlled I/O Function Description
The following general building block is used to describe the hardware I/O and pull control
functions of each PORT pin:
By Pn_HWSEL, it is possible to select between different hardware “masters”
(HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s).
Hardware control overrules settings in the respective port pin registers. Additional
hardware signals HW0_PD/HW1_PD and HW0_PU/HW1_PU controlled by the
peripherals can be used to control the pull devices of the pin.
Please refer to the Hardware Controlled I/O Functions table for the complete hardware
I/O and pull control function mapping.
Table 8 Hardware Controlled I/O Function Description
Function Outputs Inputs Pu ll Control
HWO0 HWI0 HW0_PD HW0_PU
P0.0 MODB.OUT MODB.INA
Pn.y MODC.OUT MODC.OUT
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 32 V1.2, 2016-08
Port I/O Function Table
Table 9 Port I/O Functions
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 Input Input Input Input Input Input Input Input Input Input Input Input
P0.0 ERU0.P
DOUT0 LEDTS0
.LINE7 ERU0.G
OUT0 CCU40.
OUT0 CCU80.
OUT00 USIC0_
CH0.SE
LO0
USIC0_
CH1.SE
LO0
CCU81.
OUT00 USIC1_
CH1.DO
UT0
BCCU0.
TRAPIN
B
CCU40.I
N0AC USIC1_
CH1.DX
0A
USIC0_
CH0.D
X2A
USIC0_
CH1.DX
2A
P0.1 ERU0.P
DOUT1 LEDTS0
.LINE6 ERU0.G
OUT1 CCU40.
OUT1 CCU80.
OUT01 BCCU0.
OUT8 SCU.VD
ROP USIC1_
CH1.SC
LKOUT
USIC1_
CH1.DO
UT0
CCU40.I
N1AC USIC1_
CH1.DX
0B
USIC1_
CH1.D
X1A
P0.2 ERU0.P
DOUT2 LEDTS0
.LINE5 ERU0.G
OUT2 CCU40.
OUT2 CCU80.
OUT02 VADC0.
EMUX02 CCU80.
OUT10 USIC1_
CH0.SC
LKOUT
USIC1_
CH0.DO
UT0
CCU40.I
N2AC USIC1_
CH0.DX
0A
USIC1_
CH0.D
X1A
P0.3 ERU0.P
DOUT3 LEDTS0
.LINE4 ERU0.G
OUT3CCU40.
OUT3 CCU80.
OUT03 VADC0.
EMUX01 CCU80.
OUT11 USIC1_
CH1.SC
LKOUT
USIC1_
CH0.DO
UT0
CCU40.I
N3AC USIC1_
CH0.DX
0B
P0.4 BCCU0.
OUT0 LEDTS0
.LINE3 LEDTS0
.COL3 CCU40.
OUT1 CCU80.
OUT13 VADC0.
EMUX00 WWDT.
SERVIC
E_OUT
USIC1_
CH1.SE
LO0
CAN.N0
_TXD CCU41.I
N0AB CCU80.I
N0AB CAN.N0
_RXDA
P0.5 BCCU0.
OUT1 LEDTS0
.LINE2 LEDTS0
.COL2 CCU40.
OUT0 CCU80.
OUT12 ACMP2.
OUT CCU80.
OUT01 VADC0.
EMUX10 CAN.N0
_TXD CCU41.I
N1AB CCU80.I
N1AB CAN.N0
_RXDB
P0.6 BCCU0.
OUT2 LEDTS0
.LINE1 LEDTS0
.COL1 CCU40.
OUT0 CCU80.
OUT11 USIC0_
CH1.MC
LKOUT
USIC0_
CH1.DO
UT0
VADC0.
EMUX11 CCU41.
OUT0 CCU40.I
N0AB CCU41.I
N2AB USIC0_
CH1.DX
0C
P0.7 BCCU0.
OUT3LEDTS0
.LINE0 LEDTS0
.COL0 CCU40.
OUT1 CCU80.
OUT10 USIC0_
CH0.SC
LKOUT
USIC0_
CH1.DO
UT0
VADC0.
EMUX12 CCU41.
OUT1 CCU40.I
N1AB CCU41.I
N3AB USIC0_
CH0.D
X1C
USIC0_
CH1.DX
0D
USIC0_
CH1.DX
1C
P0.8/
RTC_XTAL1 BCCU0.
OUT4 LEDTS1
.LINE0 LEDTS0
.COLA CCU40.
OUT2 CCU80.
OUT20 USIC0_
CH0.SC
LKOUT
USIC0_
CH1.SC
LKOUT
CCU81.
OUT20 CCU41.
OUT2 CCU40.I
N2AB USIC0_
CH0.D
X1B
USIC0_
CH1.DX
1B
P0.9/
RTC_XTAL2 BCCU0.
OUT5 LEDTS1
.LINE1 LEDTS0
.COL6 CCU40.
OUT3 CCU80.
OUT21 USIC0_
CH0.SE
LO0
USIC0_
CH1.SE
LO0
CCU81.
OUT21 CCU41.
OUT3 CCU40.I
N3AB USIC0_
CH0.D
X2B
USIC0_
CH1.DX
2B
P0.10/
XTAL1 BCCU0.
OUT6 LEDTS1
.LINE2 LEDTS0
.COL5 ACMP0.
OUT CCU80.
OUT22 USIC0_
CH0.SE
LO1
USIC0_
CH1.SE
LO1
CCU81.
OUT22 CCU80.I
N2AB CCU81.I
N2AB USIC0_
CH0.D
X2C
USIC0_
CH1.DX
2C
P0.11/
XTAL2 BCCU0.
OUT7 LEDTS1
.LINE3 LEDTS0
.COL4 USIC0_
CH0.MC
LKOUT
CCU80.
OUT23 USIC0_
CH0.SE
LO2
USIC0_
CH1.SE
LO2
CCU81.
OUT23 USIC0_
CH0.D
X2D
USIC0_
CH1.DX
2D
P0.12 BCCU0.
OUT6 LEDTS1
.LINE4 LEDTS0
.COL3 LEDTS1
.COL3 CCU80.
OUT33 USIC0_
CH0.SE
LO3
CCU80.
OUT20 CAN.N1
_TXD BCCU0.
TRAPIN
A
CCU40.I
N0AA CCU40.I
N1AA CCU40.I
N2AA CCU81.I
N0AU CCU40.I
N3AA CCU80.I
N0AA USIC0_
CH0.D
X2E
CCU80.I
N1AA CCU80.I
N2AA CAN.N1
_RXDA CCU80.I
N3AA
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 33 V1.2, 2016-08
P0.13 WWDT.
SERVIC
E_OUT
LEDTS1
.LINE5 LEDTS0
.COL2 LEDTS1
.COL2 CCU80.
OUT32 USIC0_
CH0.SE
LO4
CCU80.
OUT21 CAN.N1
_TXD CCU80.I
N3AB CCU81.I
N1AU POSIF0.
IN0B USIC0_
CH0.D
X2F
CAN.N1
_RXDB
P0.14 BCCU0.
OUT7 LEDTS1
.LINE6 LEDTS0
.COL1 LEDTS1
.COL1 CCU80.
OUT31 USIC0_
CH0.DO
UT0
USIC0_
CH0.SC
LKOUT
CAN.N0
_TXD CCU81.I
N2AU POSIF0.
IN1B USIC0_
CH0.DX
0A
USIC0_
CH0.D
X1A
USIC1_
CH1.DX
5B
CAN.N0
_RXDC
P0.15 BCCU0.
OUT8 LEDTS1
.LINE7 LEDTS0
.COL0 LEDTS1
.COL0 CCU80.
OUT30 USIC0_
CH0.DO
UT0
USIC0_
CH1.MC
LKOUT
CAN.N0
_TXD CCU81.I
N3AU POSIF0.
IN2B USIC0_
CH0.DX
0B
USIC1_
CH1.DX
3B
USIC1_
CH1.DX
4B
CAN.N0
_RXDD
P1.0 BCCU0.
OUT0 CCU40.
OUT0 LEDTS0
.COL0 LEDTS1
.COLA CCU80.
OUT00 ACMP1.
OUT USIC0_
CH0.DO
UT0
CCU81.
OUT00 CAN.N0
_TXD POSIF0.
IN2A USIC0_
CH0.DX
0C
CAN.N0
_RXDG
P1.1 ERU1.P
DOUT1 CCU40.
OUT1 LEDTS0
.COL1 LEDTS1
.COL0 CCU80.
OUT01 USIC0_
CH0.DO
UT0
USIC0_
CH1.SE
LO0
CCU81.
OUT01 CAN.N0
_TXD POSIF0.
IN1A USIC0_
CH0.DX
0D
USIC0_
CH0.D
X1D
USIC0_
CH1.DX
2E
CAN.N0
_RXDH
P1.2 ERU1.P
DOUT2 CCU40.
OUT2 LEDTS0
.COL2 LEDTS1
.COL1 CCU80.
OUT10 ACMP2.
OUT USIC0_
CH1.DO
UT0
CCU81.
OUT10 CAN.N1
_TXD POSIF0.
IN0A USIC0_
CH1.DX
0B
CAN.N1
_RXDG
P1.3 ERU1.P
DOUT3 CCU40.
OUT3 LEDTS0
.COL3 LEDTS1
.COL2 CCU80.
OUT11 USIC0_
CH1.SC
LKOUT
USIC0_
CH1.DO
UT0
CCU81.
OUT11 CAN.N1
_TXD USIC0_
CH1.DX
0A
USIC0_
CH1.DX
1A
CAN.N1
_RXDH
P1.4 ERU1.P
DOUT0 USIC0_
CH1.SC
LKOUT
LEDTS0
.COL4 LEDTS1
.COL3 CCU80.
OUT20 USIC0_
CH0.SE
LO0
USIC0_
CH1.SE
LO1
CCU81.
OUT20 CCU41.
OUT0 USIC0_
CH0.DX
5E
USIC0_
CH1.DX
5E
P1.5 ERU1.P
DOUT1 USIC0_
CH0.DO
UT0
LEDTS0
.COLA BCCU0.
OUT1 CCU80.
OUT21 USIC0_
CH0.SE
LO1
USIC0_
CH1.SE
LO2
CCU81.
OUT21 CCU41.
OUT1 USIC0_
CH1.DX
5F
P1.6 ERU1.P
DOUT2 USIC0_
CH1.DO
UT0
LEDTS0
.COL5 USIC0_
CH0.SC
LKOUT
BCCU0.
OUT2 USIC0_
CH0.SE
LO2
USIC0_
CH1.SE
LO3
CCU81.
OUT30 CCU41.
OUT2 POSIF1.
IN2A USIC0_
CH0.DX
5F
P1.7 BCCU0.
OUT8 CCU40.
OUT3 LEDTS0
.COL6 LEDTS1
.COL4 ACMP3.
OUT ERU1.P
DOUT3 CCU81.
OUT31 CCU41.
OUT3 POSIF1.
IN1A USIC1_
CH0.DX
5B
USIC1_
CH1.DX
2C
P1.8 BCCU0.
OUT0 CCU40.
OUT0 USIC1_
CH1.SC
LKOUT
VADC0.
EMUX02 ACMP1.
OUT ERU1.P
DOUT0 CCU81.
OUT32 POSIF1.
IN0A USIC1_
CH0.DX
3B
USIC1_
CH0.D
X4B
USIC1_
CH1.DX
1C
P2.0 ERU0.P
DOUT3 CCU40.
OUT0 ERU0.G
OUT3 LEDTS1
.COL5 CCU80.
OUT20 USIC0_
CH0.DO
UT0
USIC0_
CH0.SC
LKOUT
CCU81.
OUT20 CAN.N0
_TXD VADC0.
G0CH5 USIC0_
CH0.DX
0E
USIC0_
CH0.D
X1E
USIC0_
CH1.DX
2F
CAN.N0
_RXDE ERU0.0
B0
P2.1 ERU0.P
DOUT2 CCU40.
OUT1 ERU0.G
OUT2 LEDTS1
.COL6 CCU80.
OUT21 USIC0_
CH0.DO
UT0
USIC0_
CH1.SC
LKOUT
CCU81.
OUT21 CAN.N0
_TXD ACMP2.I
NP VADC0.
G0CH6 USIC0_
CH0.DX
0F
USIC0_
CH1.DX
3A
USIC0_
CH1.DX
4A
CAN.N0
_RXDF ERU0.1
B0
Table 9 Port I/O Functions (cont’d)
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 Input Input Input Input Input Input Input Input Input Input Input Input
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 34 V1.2, 2016-08
P2.2 ACMP2.I
NN VADC0.
G0CH7 ORC0.AI
NUSIC1_
CH0.DX
5E
USIC0_
CH0.DX
3A
USIC0_
CH0.D
X4A
USIC0_
CH1.DX
5A
ERU0.0
B1
P2.3 VADC0.
G1CH5 ORC1.AI
NUSIC1_
CH0.DX
3E
USIC1_
CH0.DX
4E
USIC1_
CH1.DX
5C
USIC0_
CH0.D
X5B
USIC0_
CH1.DX
3C
USIC0_
CH1.DX
4C
ERU0.1
B1
P2.4 VADC0.
G1CH6 ORC2.AI
NUSIC1_
CH1.DX
3C
USIC1_
CH1.DX
4C
USIC0_
CH0.DX
3B
USIC0_
CH0.D
X4B
USIC1_
CH0.DX
5F
USIC0_
CH1.DX
5B
ERU0.0
A1
P2.5 VADC0.
G1CH7 ORC3.AI
NUSIC1_
CH1.DX
5D
USIC0_
CH0.DX
5D
USIC0_
CH1.DX
3E
USIC0_
CH1.DX
4E
ERU0.1
A1
P2.6 ACMP1.I
NN VADC0.
G0CH0 ORC4.AI
NUSIC1_
CH1.DX
3E
USIC1_
CH1.DX
4E
USIC0_
CH0.DX
3E
USIC0_
CH0.D
X4E
USIC0_
CH1.DX
5D
ERU0.2
A1
P2.7 ACMP1.I
NP VADC0.
G1CH1 ORC5.AI
NUSIC1_
CH1.DX
5E
USIC0_
CH0.DX
5C
USIC0_
CH1.DX
3D
USIC0_
CH1.DX
4D
ERU0.3
A1
P2.8 ACMP0.I
NN VADC0.
G0CH1 VADC0.
G1CH0 ORC6.AI
NUSIC0_
CH0.DX
3D
USIC0_
CH0.D
X4D
USIC0_
CH1.DX
5C
ERU0.3
B1
P2.9 ACMP0.I
NP VADC0.
G0CH2 VADC0.
G1CH4 ORC7.AI
NUSIC0_
CH0.DX
5A
USIC0_
CH1.DX
3B
USIC0_
CH1.DX
4B
ERU0.3
B0
P2.10 ERU0.P
DOUT1 CCU40.
OUT2 ERU0.G
OUT1 LEDTS1
.COL4 CCU80.
OUT30 ACMP0.
OUT USIC0_
CH1.DO
UT0
CAN.N1
_TXD VADC0.
G0CH3 VADC0.
G1CH2 USIC0_
CH0.DX
3C
USIC0_
CH0.D
X4C
USIC0_
CH1.DX
0F
CAN.N1
_RXDE ERU0.2
B0
P2.11 ERU0.P
DOUT0 CCU40.
OUT3 ERU0.G
OUT0 LEDTS1
.COL3 CCU80.
OUT31 USIC0_
CH1.SC
LKOUT
USIC0_
CH1.DO
UT0
CAN.N1
_TXD ACMP.R
EF VADC0.
G0CH4 VADC0.
G1CH3 USIC0_
CH1.DX
0E
USIC0_
CH1.DX
1E
CAN.N1
_RXDF ERU0.2
B1
P2.12 BCCU0.
OUT3 VADC0.
EMUX00 USIC1_
CH0.SC
LKOUT
USIC1_
CH1.SC
LKOUT
ACMP2.
OUT USIC1_
CH1.DO
UT0
LEDTS2
.COL6 ACMP3.I
NN USIC1_
CH0.DX
3A
USIC1_
CH0.D
X4A
USIC1_
CH1.DX
0C
USIC1_
CH1.DX
1B
ERU1.3
A2
P2.13 BCCU0.
OUT4 CCU40.
OUT3 USIC1_
CH0.MC
LKOUT
CCU81.
OUT31 VADC0.
EMUX01 USIC1_
CH1.DO
UT0
CCU81.
OUT33 CCU41.
OUT3 ACMP3.I
NP USIC1_
CH0.DX
5A
USIC1_
CH1.DX
0D
ERU1.3
A3
P3.0 BCCU0.
OUT0 USIC1_
CH1.DO
UT0
USIC1_
CH1.SC
LKOUT
LEDTS2
.COLA CCU80.
OUT21 ACMP1.
OUT USIC1_
CH0.SE
LO1
CCU81.
OUT21 CCU41.
OUT0 BCCU0.
TRAPIN
C
CCU41.I
N0AA CCU41.I
N1AA CCU41.I
N2AA CCU41.I
N3AA CCU81.I
N0AA CCU81.I
N1AA CCU81.
IN2AA USIC1_
CH1.DX
0E
USIC1_
CH1.DX
1D
CCU81.I
N3AA ERU1.0
A1
P3.1 BCCU0.
OUT1 USIC1_
CH1.DO
UT0
LEDTS2
.COL0 CCU80.
OUT20 ACMP3.
OUT USIC1_
CH0.SE
LO0
CCU81.
OUT20 CCU41.
OUT1 USIC1_
CH0.D
X2F
USIC1_
CH1.DX
0F
ERU1.1
A1
Table 9 Port I/O Functions (cont’d)
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 Input Input Input Input Input Input Input Input Input Input Input Input
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 35 V1.2, 2016-08
P3.2 BCCU0.
OUT2 USIC1_
CH1.SC
LKOUT
LEDTS2
.COL1 CCU80.
OUT11 ACMP2.
OUT USIC1_
CH0.SC
LKOUT
CCU81.
OUT11 CCU41.
OUT2 USIC1_
CH0.DX
3C
USIC1_
CH0.D
X4C
USIC1_
CH1.DX
3D
USIC1_
CH1.DX
4D
ERU1.2
A1
P3.3 BCCU0.
OUT5 USIC1_
CH0.DO
UT0
LEDTS2
.COL2 CCU80.
OUT10 ACMP0.
OUT USIC1_
CH1.SE
LO0
CCU81.
OUT10 CCU41.
OUT3 USIC1_
CH0.DX
0E
USIC1_
CH1.DX
2A
ERU1.1
A3
P3.4 BCCU0.
OUT6 USIC1_
CH0.DO
UT0
USIC1_
CH0.SC
LKOUT
LEDTS2
.COL3 CCU80.
OUT01 USIC1_
CH1.MC
LKOUT
USIC1_
CH1.SE
LO1
CCU81.
OUT01 USIC1_
CH0.DX
0F
USIC1_
CH0.D
X1E
USIC1_
CH1.DX
2B
ERU1.2
A3
P4.0 BCCU0.
OUT0 ERU1.P
DOUT0 LEDTS2
.COL5 ERU1.G
OUT0 CCU40.
OUT0 ACMP1.
OUT USIC1_
CH1.SE
LO1
CCU81.
OUT10 CCU41.
OUT0 CCU40.I
N0BA CCU41.I
N0AC CCU80.I
N0AU USIC1_
CH0.DX
3D
USIC1_
CH0.D
X4D
P4.1 BCCU0.
OUT8 ERU1.P
DOUT1 LEDTS2
.COL4 ERU1.G
OUT1 CCU40.
OUT1 ACMP3.
OUT USIC1_
CH1.SE
LO2
CCU81.
OUT11 CCU41.
OUT1 CCU40.I
N1BA CCU41.I
N1AC CCU80.I
N1AU POSIF1.
IN0B USIC1_
CH0.DX
5C
P4.2 BCCU0.
OUT4 ERU1.P
DOUT2 CCU81.
OUT20 ERU1.G
OUT2 CCU40.
OUT2 ACMP2.
OUT USIC1_
CH1.SE
LO3
CCU81.
OUT12 CCU41.
OUT2 CCU40.I
N2BA CCU41.I
N2AC CCU80.I
N2AU CCU81.I
N1AB POSIF1.
IN1B USIC1_
CH0.DX
5D
P4.3 BCCU0.
OUT5 ERU1.P
DOUT3 CCU81.
OUT21 ERU1.G
OUT3 CCU40.
OUT3 ACMP0.
OUT USIC1_
CH0.SC
LKOUT
CCU81.
OUT13 CCU41.
OUT3 CCU40.I
N3BA CCU41.I
N3AC CCU80.I
N3AU POSIF1.
IN2B USIC1_
CH0.D
X1B
P4.4 BCCU0.
OUT0LEDTS2
.LINE0 LEDTS1
.COLA CCU80.
OUT00 USIC1_
CH0.DO
UT0
CCU81.
OUT00 CCU41.
OUT0 CCU41.I
N0AV USIC1_
CH0.DX
0C
USIC1_
CH1.DX
5F
ERU1.0
A2
P4.5 BCCU0.
OUT8 LEDTS2
.LINE1 LEDTS1
.COL6 CCU80.
OUT01 USIC1_
CH0.DO
UT0
USIC1_
CH0.SC
LKOUT
CCU81.
OUT01 CCU41.
OUT1 CCU41.I
N1AV USIC1_
CH0.DX
0D
USIC1_
CH0.D
X1C
ERU1.1
A2
P4.6 BCCU0.
OUT2 LEDTS2
.LINE2 CCU81.
OUT10 LEDTS1
.COL5 CCU80.
OUT10 USIC1_
CH0.SC
LKOUT
CCU81.
OUT02 CCU41.
OUT2 CCU41.I
N2AV CCU81.I
N0AB USIC1_
CH0.D
X1D
ERU1.2
A2
P4.7 BCCU0.
OUT5 LEDTS2
.LINE3 CCU81.
OUT11 LEDTS1
.COL4 CCU80.
OUT11 USIC1_
CH0.SE
LO0
CCU81.
OUT03 CCU41.
OUT3 CCU41.I
N3AV USIC1_
CH0.D
X2A
ERU1.0
A3
P4.8 BCCU0.
OUT7 LEDTS2
.LINE4 LEDTS2
.COL3 LEDTS1
.COL3 CCU80.
OUT30 CCU40.
OUT0 USIC1_
CH0.SE
LO1
CCU81.
OUT30 CAN.N1
_TXD CCU40.I
N0AV CCU41.I
N0BA USIC1_
CH0.D
X2B
CAN.N1
_RXDC
P4.9 BCCU0.
OUT3 LEDTS2
.LINE5 LEDTS2
.COL2 LEDTS1
.COL2 CCU80.
OUT31 CCU40.
OUT1 USIC1_
CH0.SE
LO2
CCU81.
OUT31 CAN.N1
_TXD CCU40.I
N1AV CCU41.I
N1BA USIC1_
CH0.D
X2C
CAN.N1
_RXDD
Table 9 Port I/O Functions (cont’d)
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 Input Input Input Input Input Input Input Input Input Input Input Input
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 36 V1.2, 2016-08
P4.10 LEDTS2
.LINE6 LEDTS2
.COL1 LEDTS1
.COL1 CCU80.
OUT00 CCU40.
OUT2 USIC1_
CH0.SE
LO3
CCU81.
OUT32 CCU81.
OUT00 BCCU0.
TRAPIN
D
CCU40.I
N2AV CCU41.I
N2BA CCU81.I
N3AB USIC1_
CH0.D
X2D
USIC1_
CH1.DX
5A
P4.11 LEDTS2
.LINE7 LEDTS2
.COL0 LEDTS1
.COL0 CCU80.
OUT01 CCU40.
OUT3 USIC1_
CH0.SE
LO4
CCU81.
OUT33 CCU81.
OUT01 CCU40.I
N3AV CCU41.I
N3BA USIC1_
CH0.D
X2E
USIC1_
CH1.DX
3A
USIC1_
CH1.DX
4A
Table 9 Port I/O Functions (cont’d)
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 Input Input Input Input Input Input Input Input Input Input Input Input
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 37 V1.2, 2016-08
Table 10 Hardware I/O Controlled Functions
Function Outputs Outputs Inputs Inputs Pull Control Pull Control Pull Control P ull Control
HWO0 HWO1 HWI0 HWI1 HW0_PD HW0_PU HW1_PD HW1_PU
P0.0 LEDTS0.
EXTENDED7 LEDTS0.TSIN7 LEDTS0.TSIN7 Reserved for LEDTS
Scheme A:
pull-down disabled
always
Reserved for LEDTS
Scheme A:
pull-down enabled
always
Reserved for LEDTS Scheme B:
pull-up enabled and pull-down disabled, and
vice versa
P0.1 LEDTS0.
EXTENDED6 LEDTS0.TSIN6 LEDTS0.TSIN6
P0.2 LEDTS0.
EXTENDED5 LEDTS0.TSIN5 LEDTS0.TSIN5
P0.3 LEDTS0.
EXTENDED4 LEDTS0.TSIN4 LEDTS0.TSIN4
P0.4 LEDTS0.
EXTENDED3 LEDTS0.TSIN3 LEDTS0.TSIN3
P0.5 LEDTS0.
EXTENDED2 LEDTS0.TSIN2 LEDTS0.TSIN2
P0.6 LEDTS0.
EXTENDED1 LEDTS0.TSIN1 LEDTS0.TSIN1
P0.7 LEDTS0.
EXTENDED0 LEDTS0.TSIN0 LEDTS0.TSIN0
P0.8 LEDTS1.
EXTENDED0 LEDTS1.TSIN0 LEDTS1.TSIN0
P0.9 LEDTS1.
EXTENDED1 LEDTS1.TSIN1 LEDTS1.TSIN1
P0.10 LEDTS1.
EXTENDED2 LEDTS1.TSIN2 LEDTS1.TSIN2
P0.11 LEDTS1.
EXTENDED3 LEDTS1.TSIN3 LEDTS1.TSIN3
P0.12 LEDTS1.
EXTENDED4 LEDTS1.TSIN4 LEDTS1.TSIN4
P0.13 LEDTS1.
EXTENDED5 LEDTS1.TSIN5 LEDTS1.TSIN5
P0.14 LEDTS1.
EXTENDED6 LEDTS1.TSIN6 LEDTS1.TSIN6
P0.15 LEDTS1.
EXTENDED7 LEDTS1.TSIN7 LEDTS1.TSIN7
P1.0 USIC0_CH0.DOUT0 USIC0_CH0.HWIN0 BCCU0.OUT2 BCCU0.OUT2
P1.1 USIC0_CH0.DOUT1 USIC0_CH0.HWIN1 BCCU0.OUT3 BCCU0.OUT3
P1.2 USIC0_CH0.DOUT2 USIC0_CH0.HWIN2 BCCU0.OUT4 BCCU0.OUT4
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 38 V1.2, 2016-08
P1.3 USIC0_CH0.DOUT3 USIC0_CH0.HWIN3 BCCU0.OUT5 BCCU0.OUT5
P1.4 BCCU0.OUT6 BCCU0.OUT6
P1.5 BCCU0.OUT7 BCCU0.OUT7
P1.6 BCCU0.OUT8 BCCU0.OUT8
P1.7
P1.8
P2.0 BCCU0.OUT1 BCCU0.OUT1
P2.1 BCCU0.OUT6 BCCU0.OUT6
P2.2 BCCU0.OUT0 BCCU0.OUT0 CCU40.OUT3 CCU40.OUT3
P2.3 ACMP2.OUT ACMP2.OUT
P2.4 BCCU0.OUT8 BCCU0.OUT8
P2.5 ACMP1.OUT ACMP1.OUT
P2.6 BCCU0.OUT2 BCCU0.OUT2 CCU40.OUT3 CCU40.OUT3
P2.7 BCCU0.OUT8 BCCU0.OUT8 CCU40.OUT3 CCU40.OUT3
P2.8 BCCU0.OUT1 BCCU0.OUT1 CCU40.OUT2 CCU40.OUT2
P2.9 BCCU0.OUT7 BCCU0.OUT7 CCU40.OUT2 CCU40.OUT2
P2.10 BCCU0.OUT4 BCCU0.OUT4
P2.11 BCCU0.OUT5 BCCU0.OUT5
P2.12 BCCU0.OUT3 BCCU0.OUT3 CCU41.OUT0 CCU41.OUT0
P2.13 BCCU0.OUT4 BCCU0.OUT4 CCU41.OUT2 CCU41.OUT2
P3.0
P3.1 USIC1_CH0.DOUT3 USIC1_CH0.HWIN3
P3.2 USIC1_CH0.DOUT2 USIC1_CH0.HWIN2
P3.3 USIC1_CH0.DOUT1 USIC1_CH0.HWIN1
P3.4 USIC1_CH0.DOUT0 USIC1_CH0.HWIN0
P4.0
P4.1
P4.2
P4.3
Table 10 Hardware I/O Controlled Functions
Function Outputs Outputs Inputs Inputs Pull Control Pull Control Pull Control P ull Control
HWO0 HWO1 HWI0 HWI1 HW0_PD HW0_PU HW1_PD HW1_PU
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Data Sheet 39 V1.2, 2016-08
P4.4 LEDTS2.
EXTENDED0 LEDTS2.TSIN0 LEDTS2.TSIN0 Reserved for LEDTS
Scheme A:
pull-down disabled
always
Reserved for LEDTS
Scheme A:
pull-down enabled
always
Reserved for LEDTS Scheme B:
pull-up enabled and pull-down disabled, and
vice versa
P4.5 LEDTS2.
EXTENDED1 LEDTS2.TSIN1 LEDTS2.TSIN1
P4.6 LEDTS2.
EXTENDED2 LEDTS2.TSIN2 LEDTS2.TSIN2
P4.7 LEDTS2.
EXTENDED3 LEDTS2.TSIN3 LEDTS2.TSIN3
P4.8 LEDTS2.
EXTENDED4 LEDTS2.TSIN4 LEDTS2.TSIN4
P4.9 LEDTS2.
EXTENDED5 LEDTS2.TSIN5 LEDTS2.TSIN5
P4.10 LEDTS2.
EXTENDED6 LEDTS2.TSIN6 LEDTS2.TSIN6
P4.11 LEDTS2.
EXTENDED7 LEDTS2.TSIN7 LEDTS2.TSIN7
Table 10 Hardware I/O Controlled Functions
Function Outputs Outputs Inputs Inputs Pull Control Pull Control Pull Control P ull Control
HWO0 HWO1 HWI0 HWI1 HW0_PD HW0_PU HW1_PD HW1_PU
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 40 V1.2, 2016-08
3 Electrical Parameter
This section provides the electrical parameter which are implementation-specific for the
XMC1400.
3.1 General Parameters
3.1.1 Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XMC1400
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
•CC
Such parameters indicate Controller Characteristics, wh ich ar e distinctive feature of
the XMC1400 and must be regarded for a system design.
•SR
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC1400 is designed in.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 41 V1.2, 2016-08
3.1.2 Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 11 Absolute Maximum Rating Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Junction temperature TJ SR -40 – 115 °C–
Storage temperature TST SR -40 – 125 °C–
Voltage on power supply
pin with respect to VSSP
VDDP SR -0.3 – 6 V –
Voltage on any pin with
respect to VSSP
VIN SR -0.5 – VDDP +
0.5 or
max. 6
V whichever is
lower
Voltage on any analog
input pin with respect to
VSSP
VAIN SR -0.5 – VDDP +
0.5 or
max. 6
V whichever is
lower
Input current on any pin
during overload condition IIN SR -10 – 10 mA –
Absolute sum of all input
currents during overload
condition
Σ|IIN| SR -50 – 50 mA –
Analog comparator input
voltage VCM SR -0.3 – VDDP +
0.3 V
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 42 V1.2, 2016-08
3.1.3 Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 12 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
• full operation life-time is not exceeded
•Operating Co nditions are met for
– pad supply levels (VDDP)
– temperature
If a pin current is outside of the Operating Conditions but within the overload
conditions, then the parameters of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations li ke short to battery.
Figure 11 shows th e path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
Table 12 Overload Parameter s
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input current on any port pin
during overload condition IOV SR -5 – 5 mA
Absolute sum of all input
circuit currents during
overload condition
IOVS SR – – 25 mA
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 43 V1.2, 2016-08
Figure 11 Input Ove rload Current via ESD structures
Table 13 and Table 14 list input voltages that can be reached under overload conditions.
Note that the absolute maximum input voltages as de fined in the Absolute Maximum
Ratings must not be exceeded during overload.
Table 13 PN-Junction Characteri sitics for positive Overload
Pad Type IOV =5mA, TJ=-40°C IOV =5mA, TJ= 115 °C
Standard,
High-current,
AN/DIG_IN
VIN =VDDP +0.5V VIN =VDDP +0.5V
Table 14 PN-Junction Characteri sitics for negative Overload
Pad Type IOV =5mA, TJ=-40°C IOV =5mA, TJ= 115 °C
Standard,
High-current,
AN/DIG_IN
VIN =VSS -0.5V VIN =VSS -0.5V
Pn.y IOVx
GND
ESD Pad
GND
VDDP
VDDP
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 44 V1.2, 2016-08
3.1.4 Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC1400. All parameters specified in the following tables
refer to these operating conditions, unless noted otherw ise.
Table 15 Operating Conditions Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Ambient Temperature TA SR -40 −8 5 °C Temp. Range F
-40 −105 °C Temp. Range X
Digital supply voltage1)
1) See also the Supply Monitoring thresholds, Chapter 3.3.2.
VDDP SR 1.8 −5.5 V
Short circuit current of
digital outputs ISC SR -5 −5mA
Absolute sum of short
circuit currents of the
device
ΣISC_D SR −−25 mA
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 45 V1.2, 2016-08
3.2 DC Parameters
3.2.1 Input/Output Characteristics
Table 16 provides the characteristics of the input/output pins of the XMC1400.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Unless otherwise stated, input DC and AC characteristics, including peripheral
timings, assume that the input pads operate with the standard hysteresis.
Table 16 Input/Output Ch aracteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit Test Conditions
Min. Max.
Output low voltage on
port pins
(with standard pads)
VOLP CC – 1.0 V IOL = 11 mA (5 V)
IOL = 7 mA (3.3 V)
–0.4V
IOL = 5 mA (5 V)
IOL = 3.5 mA (3.3 V)
Output low voltage on
high current pads VOLP1 CC – 1.0 V IOL = 50 mA (5 V)
IOL = 25 mA (3.3 V)
–0.32V
IOL = 10 mA (5 V)
–0.4V
IOL = 5 mA (3.3 V)
Output high voltage on
port pins
(with standard pads)
VOHP CC VDDP -
1.0 –VIOH = -10 mA (5 V)
IOH = -7 mA (3.3 V)
VDDP -
0.4 –VIOH =-4.5mA (5V)
IOH =-2.5mA (3.3V)
Output high voltage on
high current pads VOHP1 CC VDDP -
0.32 –VIOH = -6 mA (5 V)
VDDP -
1.0 –VIOH = -8 mA (3.3 V)
VDDP -
0.4 –VIOH = -4 mA (3.3 V)
Input low voltage on port
pins
(Standard Hysteresis)
VILPS SR – 0.19 ×
VDDP
V CMOS Mode
(5 V, 3.3 V & 2.2 V)
Input high voltage on
port pins
(Standard Hysteresis)
VIHPS SR 0.7 ×
VDDP
–VCMOS Mode
(5 V, 3.3 V & 2.2 V)
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 46 V1.2, 2016-08
Input low voltage on port
pins
(Large Hysteresis)
VILPL SR – 0.08 ×
VDDP
V CMOS Mode
(5 V, 3.3 V & 2.2 V)
Input high voltage on
port pins
(Large Hysteresis)
VIHPL SR 0.85 ×
VDDP
–VCMOS Mode
(5 V, 3.3 V & 2.2 V)
Rise/fall time on High
Current Pad1) tHCPR,
tHCPF
CC – 9 ns 50 pF @ 5 V2)
– 12 ns 50 pF @ 3.3 V3)
– 25 ns 50 pF @ 1.8 V4)
Rise/fall time on
Standard Pad1) tR, tFCC – 12 ns 50 pF @ 5 V5)
– 15 ns 50 pF @ 3.3 V6).
– 31 ns 50 pF @ 1.8 V7).
Input Hysteresis on port
pin except P2.3 - P2.98) HYS CC 0.08 ×
VDDP
– V CMOS Mode (5 V),
Standard Hysteresis
0.03 ×
VDDP
– V CMOS Mode (3.3 V),
Standard Hysteresis
0.02 ×
VDDP
– V CMOS Mode (2.2 V),
Standard Hysteresis
0.5 ×
VDDP
0.75 ×
VDDP
V CMOS Mode(5 V),
Large Hysteresis
0.4 ×
VDDP
0.75 ×
VDDP
V CMOS Mode(3.3 V),
Large Hysteresis
0.2 ×
VDDP
0.65 ×
VDDP
V CMOS Mode(2.2 V),
Large Hysteresis
Table 16 Input/Output Ch aracteristics (Operating Conditions apply) (cont’d)
Parameter Symbol Limit Values Unit Test Conditions
Min. Max.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 47 V1.2, 2016-08
Input Hysteresis on port
pin P2.3 - P2.98) HYS_
P2 CC 0.08 ×
VDDP
– V CMOS Mode (5 V),
Standard Hysteresis
0.03 ×
VDDP
– V CMOS Mode (3.3 V),
Standard Hysteresis
0.02 ×
VDDP
– V CMOS Mode (2.2 V),
Standard Hysteresis
0.35 ×
VDDP
0.75 ×
VDDP
V CMOS Mode(5 V),
Large Hysteresis
0.25 ×
VDDP
0.75 ×
VDDP
V CMOS Mode(3.3 V),
Large Hysteresis
0.15 ×
VDDP
0.65 ×
VDDP
V CMOS Mode(2.2 V),
Large Hysteresis
Pin capacitance (digital
inputs/outputs) CIO CC – 10 pF
Pull-up current on port
pins IPUP CC – -80 μAVIH,min (5 V)
-95 – μAVIL,max (5 V)
–-50μAVIH,min (3.3 V)
-65 – μAVIL,max (3.3 V)
Pull-down current on
port pins IPDP CC – 40 μAVIL,max (5 V)
95 – μAVIH,min (5 V)
–30μAVIL,max (3.3 V)
60 – μAVIH,min (3.3 V)
Input leakage current
except P0.119) IOZP CC -1 1 μA0 < VIN < VDDP,
TA≤105 °C
Input leakage current for
P0.119) IOZP1 CC -10 1 μA0 < VIN < VDDP,
TA≤105 °C
Voltage on any pin
during VDDP power off VPO SR – 0.3 V 10)
Maximum current per
pin (excluding P1, VDDP
and VSS)
IMP SR -10 11 mA –
Maximum current per
high currrent pins IMP1A SR -10 50 mA –
Table 16 Input/Output Ch aracteristics (Operating Conditions apply) (cont’d)
Parameter Symbol Limit Values Unit Test Conditions
Min. Max.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 48 V1.2, 2016-08
Maximum current into
VDDP (VQFN64,
LQFP64)
IMVDD1 SR – 520 mA
Maximum current into
VDDP (VQFN48) IMVDD2 SR – 390 mA
Maximum current into
VDDP (VQFN40) IMVDD3 SR – 260 mA
Maximum current out of
VSS (VQFN64, LQFP64) IMVSS1 SR – 390 mA
Maximum current out of
VSS (VQFN48) IMVSS2 SR – 260 mA
Maximum current out of
VSS (VQFN40) IMVSS3 SR – 260 mA
1) Rise/Fall time parameters are taken with 10% - 90% of supply.
2) Additional rise/fall time valid for CL=50pF-C
L= 100 pF @ 0.150 ns/pF at 5 V supply voltage.
3) Additional rise/fall time valid for CL=50pF-C
L= 100 pF @ 0.205 ns/pF at 3.3 V supply voltage.
4) Additional rise/fall time valid for CL=50pF-C
L= 100 pF @ 0.445 ns/pF at 1.8 V supply voltage.
5) Additional rise/fall time valid for CL=50pF-C
L= 100 pF @ 0.225 ns/pF at 5 V supply voltage.
6) Additional rise/fall time valid for CL=50pF-C
L= 100 pF @ 0.288 ns/pF at 3.3 V supply voltage.
7) Additional rise/fall time valid for CL=50pF-C
L= 100 pF @ 0.588 ns/pF at 1.8 V supply voltage.
8) Hysteresis is implemented to avoid meta st able stat es and switching due to int ernal grou nd bounce . It cannot
be guaranteed that it suppresses switch ing due to external system noise.
9) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
10)However, for applications with strict low power-down current requirements, it is mandatory that no active
voltage source is supplied at any GPIO pin when VDDP is powered off.
Table 16 Input/Output Ch aracteristics (Operating Conditions apply) (cont’d)
Parameter Symbol Limit Values Unit Test Conditions
Min. Max.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 49 V1.2, 2016-08
3.2.2 Analog to Digital Converters (ADC)
Table 17 shows the Analog to Digital Converter (ADC) characteristics.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 17 ADC Characteristics (Operating Conditions apply)1)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Supply voltage range
(internal reference) VDD_int
SR 2.0 – 3.0 V SHSCFG.AREF = 11B;
CALCTR.CALGNST C =
0CH for fSH = 32 MHz,
12H for fSH = 48 MHz
3.0 – 5.5 V SHSCFG.AREF = 10B
Supply voltage range
(external reference) VDD_ext
SR 3.0 – 5.5 V SHSCFG.AREF = 00B
Analog input voltage
range VAIN SR VSSP
- 0.05 –VDDP
+ 0.05 V
Auxiliary analog
reference ground2) VREFGND
SR VSSP
- 0.05 –1.0VG0CH0
VSSP
- 0.05 –0.2VG1CH0
Internal reference
voltage (full scale
value)
VREFINT
CC 5V
Switched
capacitance of an
analog input
CAINS
CC – 1 .2 2 pF GNCTRxz.GAINy = 00B
(unity gain)
– 1 .2 2 pF GNCTRxz.GAINy = 01B
(gain g1)
– 4 .5 6 pF GNCTRxz.GAINy = 10B
(gain g2)
– 4 .5 6 pF GNCTRxz.GAINy = 11B
(gain g3)
Total capaci tance of
an analog input CAINT
CC – – 10 pF
Total capaci tance of
the reference input CAREFT
CC – – 10 pF
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 50 V1.2, 2016-08
Gain settings GIN CC 1 – GNCTRxz.GAINy = 00B
(unity gain)
3 – GNCTRxz.GAINy = 01B
(gain g1)
6 – GNCTRxz.GAINy = 10B
(gain g2)
12 – GNCTRxz.GAINy = 11B
(gain g3)
Sample Time tsample
CC 5––1 /
fADC
VDD = 5.0 V,
fADCI = 48 MHz
3––1 /
fADC
VDD = 5.0 V,
fADCI = 32 MHz
3––1 /
fADC
VDD = 3.3 V,
fADCI = 32 MHz
30 – – 1 /
fADC
VDD = 2.0 V,
fADCI = 32 MHz
Conversion time
in fast compare
mode
tCF CC 9 1 /
fADC
3)
Conversion time
in 12-bit mode tC12 CC 20 1 /
fADC
3)
Maximum sample
rate in 12-bit mode4) fC12 CC – – fADC /
42.5 –1 sample
pending
––
fADC /
62.5 –2 samples
pending
Conversion time
in 10-bit mode tC10 CC 18 1 /
fADC
3)
Maximum sample
rate in 10-bit mode4) fC10 CC – – fADC /
40.5 –1 sample
pending
––fADC /
58.5 –2 samples
pending
Conversion time
in 8-bit mode tC8 CC 16 1 /
fADC
3)
Table 17 ADC Characteristics (Operating Conditions apply)1) (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 51 V1.2, 2016-08
Maximum sample
rate in 8-bit mode4) fC8 CC – – fADC /
38.5 –1 sample
pending
––
fADC /
54.5 –2 samples
pending
RMS noise5) ENRMS
CC –1.5–LSB
12 DC input,
SHSCFG.AREF = 00B,
GNCTRxz.GAINy = 00B
(unity gain),
VDD = 5.0 V,
VAIN = 2.5 V,
25°C
DNL error EADNL
CC – ±2.0 – LSB
12
INL error EAINL
CC – ±4.0 – LSB
12
Gain error with
external reference EAGAIN
CC – ±0.5 – % SHSCFG.AREF = 00B
(calibrated)
Gain error with
internal reference6) EAGAIN
CC – ±3.6 – % SHSCFG.AREF = 1XB
(calibrated),
-40°C - 110°C
– ±2.0 – % SHSCFG.AREF = 1XB
(calibrated),
0°C - 85°C
Offset error EAOFF
CC – ±8.0 – mV Calibrated,
VDD = 5.0 V
1) The parameters are defined for ADC clock frequencies fSH = 32 MHz for the full supply range, and fSH = 48
MHz at VDD_int , VDD_ext = 5 V. Usage of any other frequencies may affect the ADC performance.
2) The alternate reference gr ound connect ion is sepa rate for each co nverter. This mode, therefor e, provides t he
lowest noise impact.
3) No pending samples assumed, excluding sampling time and calibration.
4) Includes synchronization and calibration (average of gain and offset calibration).
5) This parameter can also be defined as an SNR value: SNR[dB] = 20 × log(AMAXeff / NRMS).
With AMAXeff = 2N / 2, SNR[dB] = 20 × log ( 2048 / NRMS) [N = 12].
NRMS = 1.5 LSB12, therefore, equals SNR = 20 × log (2048 / 1.5) = 62.7 dB.
6) Includes error from the reference voltage.
Table 17 ADC Characteristics (Operating Conditions apply)1) (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 52 V1.2, 2016-08
Figure 12 ADC Voltage Supply
MC_VADC_AREFPATHS
AREF
:
V
AGND
SAR
Converter
V
CAL
VSS
VDD Internal
Reference
REFSEL
0 1
00 1X
V
DD
CH7
.
.
CH0
V
DDint
/
V
DDext
V
AIN
V
REFGND
V
REFINT
CHNR
V
AREF
V
REF
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 53 V1.2, 2016-08
3.2.3 Out of Range Comparator (ORC) Characteristics
The Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above
VDDP on selected input pins (ORCx.AIN) and generates a service request trigger
(ORCx.OUT).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 13 ORCx.OUT Trigger Generation
Table 18 Out of Range Comparator (ORC) Characteristics (Operating
Conditions appl y; VDDP = 3.0 V - 5.5 V; CL = 0.25pF)
Parameter Symbol Values Unit Not e / Test Condition
Min. Typ. Max.
DC Switching Level VODC CC −− 180 mV VAIN ≥ VDDP + VODC
Hysteresis VOHYS CC 15 −54 mV
Always detected
Overvoltage Pulse tOPDD CC 103 −−ns VAIN ≥ VDDP + 150 mV
88 −−ns VAIN ≥ VDDP + 350 mV
Never detected
Overvoltage Pulse tOPDN CC −− 21 ns VAIN ≥ VDDP + 150 mV
−− 11 ns VAIN ≥ VDDP + 350 mV
Detection Delay tODD CC 39 −132 ns VAIN ≥ VDDP + 150 mV
31 −121 ns VAIN ≥ VDDP + 350 mV
Release Delay tORD CC 44 −240 ns VAIN ≤ VDDP; VDDP = 5 V
57 −340 ns VAIN ≤ VDDP; VDDP = 3.3 V
Enable Delay tOED CC −− 300 ns ORCCTRL.ENORCx = 1
V
SS
V
DDP
t
ORD
V
ODC
V
OHYS
t
ODD
ORCx.OUT
ORCx.AIN
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 54 V1.2, 2016-08
Figure 14 ORC Detection Ranges
VAIN (V)
VSSA
VDDP + 350 mV
t
VDDP + 150 mV
Overvoltage
may be
detected
(long enough,
level uncertain )
Never
detected
Overvoltage
Pulse
(Too shor t)
T < tOPDN tOPDN < T < tOPDD
Overvoltage
may be
detected
T > tOPDD
Always detected
Overvoltage Pulse
T < t OPDN
Never
detected
Overvoltage
Pulse
(Too s hor t)
tOPDN < T < tOPDD T > t OPDD
Always detected
Overvoltage Pulse
VDDP + 60 mV
Overvoltage
may be
detected
T > tOPDD
Never
detected
Overvoltage
Pulse
(Too low )
VDDP
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 55 V1.2, 2016-08
3.2.4 Analog Comparator Characteristics
Table 19 below show s the Analog Compa r ator characteristics.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 19 Analog Comparator Characteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit Notes/
Test Conditions
Min. Typ. Max.
Input Voltage VCMP SR -0.05 – VDDP +
0.05 V
Input Offset VCMPOFF CC – +/-3 – mV High power mode
Δ VCMP < 200 mV
Propagation
Delay1)
1) Total Analog Comparator Delay is the sum of Propagation Delay and Filter Delay.
tPDELAY CC – 25 – ns High power mode,
Δ VCMP = 100 mV
– 80 – n s High power mo de,
Δ VCMP = 25 mV
– 250 – ns L ow power mode,
Δ VCMP = 100 mV
– 700 – ns L ow power mode,
Δ VCMP = 25 mV
Current
Consumption IACMP CC – 100 – μA First active ACMP in
high power mode,
ΔVCMP > 30 mV
–66– μA Each additional ACMP
in high power mode,
ΔVCMP > 30 mV
–10– μA First active ACMP in
low power mode
–6– μA Each additional ACMP
in low power mode
Input Hysteresis VHYS CC – +/-15 – mV
Filter Delay1) tFDELAY CC – 5 – ns
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 56 V1.2, 2016-08
3.2.5 Temperature Sensor Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 20 Temperature Sensor Characteristics
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Measurement time tM CC −− 10 ms
Temperature sensor range TSR SR -40 −115 °C
Sensor Accuracy1)
1) The temperature sensor accuracy is independent of the supply voltage.
TTSAL
CC -6 – 6 °C TJ > 20°C
-10 – 10 °C 0°C ≤ TJ ≤ 20°C
−-/+8 – °C TJ < 0°C
Start-up time tTSST SR −− 15 μs
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 57 V1.2, 2016-08
3.2.6 Oscillator Pins
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The oscillator pins can be operated with an external crystal/resonator (see Figure 15) or
in direct input mode (see Figure 16).
Figure 15 Oscillator in Crystal Mode
XTAL1
XTAL2
f
OSC
Damping resistor
may be needed for
some crystals
V
PPX
V
PPX_min
≤V
PPX
≤V
PPX_max
t
V
V
PPX_min
t
OSCS
GND
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 58 V1.2, 2016-08
Figure 16 Oscillator in Direct Input Mode
V
VIHBX_max
VSS
t
Input High Voltage
Input Low Voltage
Input High Voltage
XTAL1
XTAL2
not connected
External Clock
Source
Direct Input Mode
VIHBX_min
VILBX_max
VILBX_min
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 59 V1.2, 2016-08
Table 21 OSC_XTAL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input frequency fOSC SR 4 −48 MHz Direct Input Mode
4−20 MHz External Crystal
Mode
Oscillator start-up
time1)2)
1) tOSCS is defined from the moment the oscillator is enabled wih SCU_ANAOSCHPCTRL.MODE until the
oscillations reach an amplitude at XTAL1 of 0.9 * VPPX.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
tOSCS
CC −−10 ms
Input voltage at XTAL1 VIX SR -0.3 −1.5 V External Crystal
Mode
-0.3 −5.5 V Direc t Input Mode
Input amplitude (peak-
to-peak) at XTAL12)3)
3) If the shaper unit is enabled and not bypassed.
VPPX SR 0.6 −1.7 V External Crystal
Mode
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 60 V1.2, 2016-08
Table 22 RTC_XTAL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input frequency fOSC SR −32.768 −kHz
Oscillator start-up
time1)2)
1) tOSCS is defined from the moment the oscillator is enabled by the user with SCU_ANAOSCLPCTRL.MODE
until the oscillations reach an amplitude at RTC_XTAL1 of 0.9 * VPPX.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
tOSCS
CC −−5s
Input voltage at
RTC_XTAL1 VIX SR -0.3 −1.5 V
Input amplitude (peak-
to-peak) at
RTC_XTAL12)3)
3) If the shaper unit is enabled and not bypassed.
VPPX SR 0.2 −1.2 V
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 61 V1.2, 2016-08
3.2.7 Power Supply Current
The total power supply current defined below consists of a leakage and a switching
component.
Application relevant values are typically lowe r than those given in the followi ng tables,
and depend on the custo mer's system operat ing condi tions (e.g . thermal connecti on or
used application configurations).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 23 Power Supply parameter table; VDDP = 5V
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ.1) Max.
Active mode current
Peripherals enabled
fMCLK / fPCLK in MH z 2)
IDDPAE CC −14.1 20 mA 48 / 96
−9.8 −mA 24 / 48
−7.8 −mA 16 / 32
−6.4 −mA 8 / 16
−4.4 −mA 1 / 1
Active mode current
Peripherals disabled
fMCLK / fPCLK in MH z 3)
IDDPAD
CC −6.2 mA 48 / 96
−4.6 −mA 24 / 48
−3.6 −mA 16 / 32
−3.1 −mA 8 / 16
−1.8 −mA 1 / 1
Active mode current
Code execution from
RAM
Flash is powered down
fMCLK / fPCLK in MH z
IDDPAR
CC −9.6 −mA 48 / 96
Sleep mode current
Peripherals clock enabled
fMCLK / fPCLK in MH z 4)
IDDPSE CC −11.0 −mA 48 / 96
−7.6 −mA 24 / 48
−6.4 −mA 16 / 32
−5.3 −mA 8 / 16
−4.2 −mA 1 / 1
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 62 V1.2, 2016-08
Sleep mode current
Peripherals clock
disabled
Flash active
fMCLK / fPCLK in MH z 5)
IDDPSD
CC −2.8 −mA 48 / 96
−2.2 −mA 24 / 48
−2.0 −mA 16 / 32
−1.9 −mA 8 / 16
−1.7 −mA 1 / 1
Sleep mode current
Peripherals clock
disabled
Flash powered down
fMCLK / fPCLK in MH z 6)
IDDPSR
CC −2.2 −mA 48 / 96
−1.7 −mA 24 / 48
−1.4 −mA 16 / 32
−1.2 −mA 8 / 16
−1.1 −mA 1 / 1
Deep Sleep mode
current7) IDDPDS
CC −0.27 −mA
Wake-up time from Sleep
to Active mode8) tSSA CC −6−cycl
es
Wake-up time from Deep
Sleep to Active mode9) tDSA CC −290 −μsec
1) The typical values are measured at TA=+25°C and VDDP =5V.
2) CPU and all peripherals clock enabled, Flash is in active mode.
3) CPU enabled, all peripherals clock disabled, Flash is in active mode.
4) CPU in sleep, all peripherals clock enabled and Flash is in active mode.
5) CPU in sleep, Flash is in active mode.
6) CPU in sleep, Flash is powered down and code executed from RAM after wake-up.
7) CPU in sleep, peripherals clock d isabled, Flash is powered down and code executed from RAM aft er wake-up.
8) CPU in sleep, Flash is in active mode during sleep mode.
9) CPU in sleep, Flash is in powered down mode during deep sleep mode.
Table 23 Power Supply parameter table; VDDP = 5V
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ.1) Max.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 63 V1.2, 2016-08
Figure 17 shows typical graphs for active mode supply current for V DDP = 5 V, VDDP =
3.3 V, VDDP = 1.8 V across different clock frequencies.
Figure 17 Active mode, a) peripherals clocks enabled, b) peripherals clocks
disabled: Supply current IDDPA over supply voltage VDDP for different
clock frequencies
Condition:
1. TA = +25° C
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
1/1 8/16 16/32 24/48 48/96
I(mA)
MCLK/PCLK(MHz)
IDDPAE5V/3.3V
IDDPAE1.8V
IDDPAD 5V /3.3V/1.8V
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 64 V1.2, 2016-08
Figure 18 shows typical graphs for sleep mode current for VDDP = 5 V, VDDP = 3.3 V,
VDDP = 1.8 V across differen t clock frequencies.
Figure 18 Sleep mode, peripherals clocks disabled, Flash powered down:
Supply current IDDPSD over supply voltage VDDP for different clock
frequencies
Condition:
1. TA = +25° C
0.0
0.5
1.0
1.5
2.0
2.5
1/1 8/16 16/32 24/48 32/64
I(mA)
MCLK/PCLK(MHz)
IDDPSR5V/3.3V/1.8V
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 65 V1.2, 2016-08
Table 24 provides the active current consumption of some modules operating at 5 V
power supply at 25
°
C. The typical values shown are used as a reference guide on the
current consumption when these modules are enabled.
Table 24 Ty pical Active Current parameter table
Active Current
Consumption Symbol Limit
Values Unit Test Condition
Typ.
Baseload current ICPUDDC 4.14 mA Modules including Core, SCU,
PORT, memories, ANATOP1)
1) Baseload current is mea sured with de vice running in user mode, MCLK=PCLK=4 8 MHz, with an en dless loop
in the flash memory. The clock to the modules stated in CGATSTAT0 are gated.
VADC and SHS IADCDDC 3.73 mA Set CGATCLR0.VADC to 12)
2) Active current is measured with: module enab led, MCLK=48 MHz, running in auto-scan conversion mode
USICx IUSIC0DDC 1.35 mA Set CGATCLR0.USIC0 to 13)
3) Active current is measured with: module enabled, each of the 2 USIC channels sending alternate messages
at 57.6 kbaud every 200 ms
CCU4x ICCU40DDC 0.99 mA Set CGATCLR0.CCU40 to 14)
4) Active current is measured with: module enabled, MCLK=P CLK=48 MHz, 1 CCU4 slice for PWM switchi ng at
20kHz with duty cycle varying at 10%-90%, 1 CCU4 slice in capture mode for reading period and duty cycle
CCU8x ICCU80DDC 1.00 mA Set CGATCLR0.CCU80 to 15)
5) Active current is measured with: module enabled, MCLK=PCLK=48 MHz, 3 CCU8 slices with PWM frequency
at 20kHz and a period match interrupt used to toggle duty cycle between 10% and 90%
POSIFx IPIF0DDC 1.05 mA Set CGATCLR0.POSIF0 to 16)
6) Active current is measured with: module enabled, MCLK=48 MHz, PCLK=96 MHz, hall sensor mode
LEDTSx ILTSxDDC 1.14 mA Set CGATCLR0.LEDTSx to 17)
7) Active current is measured with: module enabled, MCLK=48 MHz, 1 LED column, 6 LED/TS lines, Pad
Scheme A with large pad hysteresis config, time slice duration = 1.048 ms
BCCU0 IBCCU0DDC 0.29 mA Set CGATCLR0.BCCU0 to 18)
8) Active current is measured with: module enabled, MCLK=48 MHz, PCLK=96MHz, FCLK=0.8 MHz, Normal
mode (BCCU clock = FCLK/4), 4 BCCU Channels with packers enabled and 1 Dimming Engine, change color
or dim every 1s
MATH IMATHDDC 0.50 mA Set CGATCLR0.MATH to 19)
9) Active current is measured with: module enabled, MCLK=48 MHz, PCLK=96 MHz, tangent calculation in wh ile
loop; CORDIC circular rotation, no keep, autostart; 32-by-32 bit signed DIV, autostart, DVS right shift by 11
WDT IWDTDDC 0.03 mA Set CGATCLR0.WDT to 110)
RTC IRTCDDC 0.01 mA Set CGATCLR0.RTC to 111)
MultiCAN IMCANDDC 1.38 mA Set CGATCLR0.MCAN0 to 112)
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 66 V1.2, 2016-08
10)Active current is measured with: module enabled, MCLK=48 MHz, time-out mode; WLB = 0, WUB =
0x00008000; WDT serviced every 1 s
11)Active current is measured with: module enabled, MCLK=48 MHz, Periodic interrupt enabled
12)Active current is measured with: module enabled, MCLK=48 MHz, running at 20 MHz baudrate generator, 1
node activated, 1 transmit and 1 receive object active.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 67 V1.2, 2016-08
3.2.8 Flash Memory Parameters
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 25 Flas h Memory Para meters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Erase time per
page / sector tERASE CC 6.8 7.1 7.6 ms
Program time per
block tPSER CC 102 152 204 μs
Wake-Up time tWU CC −32.2 −μs
Read time per word ta CC −50 −ns
Data Retention Time tRET CC 10 −− years Max. 100 erase /
program cycles
Flash Wait States 1)
1) Flash wait states are automatically inserted by the Flash module during memory read when needed. Typical
values are calculated from the execution of the Dhrystone benchmark program.
NWSFLASH CC 0 0 0 fMCLK = 8 MHz
011 fMCLK = 16 MHz
122 fMCLK = 32 MHz
223 fMCLK = 48 MHz
Erase Cycles NECYC CC −−5*104cycles Sum of page and
sector erase cycles
Total Erase Cycles NTECYC CC −−2*106cycles
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 68 V1.2, 2016-08
Figure 19 Logical Structure of the Flash
word 0 word 1 word 2 word 3
sector 1
sector N_ LOG_SEC-1
page 0
page 1
page 15
page 14
page 13
1 sector
= 16 Pa ges = 4 K B
sector 0
data block 0 data block 1 data block 14 data block 15
1 page = 16 datablock s= 256 By tes
1 block = 4 words = 16 B ytes
data block 2
NVM N_LO G_SEC1) * 4 KB
1) T he number of sectors, N_LO G_SEC, depends on t he Flash m em or y s ize of the pr oduct derivative.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 69 V1.2, 2016-08
3.3 AC Parameters
3.3.1 Testing Waveforms
Figure 20 Rise/Fall Time Parameters
Figure 21 Testing Waveform, Output Delay
Figure 22 Testing Waveform, Output High Impedance
10%
90%
V
SS
V
DDP
t
R
t
F
10%
90%
V
DDP
/ 2 V
DDP
/ 2
V
DDP
V
SS
Test Points
VLOAD + 0.1 V Timing
Reference
Points
VLOAD -0.1V
VOH -0.1V
VOL + 0.1V
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 70 V1.2, 2016-08
3.3.2 Power-Up and Supply Threshold Characteristics
Table 26 provides the characteristics of the supply threshold in XMC1400.
The guard band between the lowest valid operating voltage and the brownout reset
threshold provides a margin for noise immunity and hysteresis. The electrical
parameters may be violated while VDDP is outside its operating range.
The brownout detection triggers a reset within the defined range. The prewarning
detection can be used to trigger an early warning and issue corrective and/or fail-safe
actions in case of a critical supply voltage drop.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 26 Power-Up and Supply Thresho ld Paramete rs (Operating Cond itions
apply)
Parameter Symbol Values Un it Note /
Test Condition
Min. Typ. Max.
VDDP ramp-up time tRAMPUP SR VDDP/
SVDDPrise
−107μs
VDDP slew rate SVDDPOP SR 0 −0.1 V/μs Slope during
normal operation
SVDDP10 SR 0 −10 V/μs Slope during fast
transient within +/-
10% of VDDP
SVDDPrise SR 0 −10 V/μs Slope during
power-on or
restart after
brownout event
SVDDPfall1) SR 0 −0.25 V/μs Slope during
supply falling out
of the +/-10%
limits2)
VDDP prewarning
voltage VDDPPW CC 2.1 2.25 2.4 V ANAVDEL.VDEL_
SELECT = 00B
2.85 3 3.15 V ANAVDEL.VDEL_
SELECT = 01B
4.2 4.4 4.6 V ANAVDEL.VDEL_
SELECT = 10B
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 71 V1.2, 2016-08
Figure 23 Supply Threshold Parameters
VDDP brownout reset
voltage VDDPBO CC 1.55 1.62 1.75 V calibrated, before
user code starts
running
VDDP voltage to
ensure defined pad
states
VDDPPA CC −1.0 −V
Start-up time from
power-on reset tSSW SR −260 – μs Time to the first
user code
instruction3)
BMI program time tBMI SR −8.25 – ms Time taken from a
user-triggered
system reset after
BMI installation is
is requested
1) A capacitor of at least 100 nF has to be added between VDDP and VSSP to fulfill the requirement as stated for
this parameter.
2) Valid for a 100 nF buffer capacitor connected to supply pin where cu rrent from capacitor is forwarded only to
the chip. A larger capacitor value has to be chosen if the power source sink a current.
3) This values does not include the ramp-up time. Duri ng startup firmware execution, MCLK is running at 48 MHz
and the clocks to peripheral as specified in register CGATSTAT0 are gated.
Table 26 Power-Up and Supply Thresho ld Paramete rs (Operating Cond itions
apply) (cont’d)
Parameter Symbol Values Un it Note /
Test Condition
Min. Typ. Max.
VDDP
}
5.0V
V
DDPPW
V
DDPBO
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 72 V1.2, 2016-08
3.3.3 On-Chip Oscillator Characteristics
Table 27 provides the characteristics of the 96 MHz digital controlled oscillator DCO1.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 28 provides th e characteristics of the 32 kHz digital controlled oscillator DCO2.
Table 27 96 MHz DCO1 Characteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit Test Conditions
Min. Typ
.Max.
Nominal frequency fNOM CC – 96 – MHz under nominal
conditions1) after trimming
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA=+25 °C.
Accuracy with
adjustment based on
XTAL as reference
ΔfLTX CC -0.3 – 0.3 % with respect to fNOM(typ),
over temperature
(-40 °C to 105 °C)
Accuracy ΔfLT CC -1.7 – 3.4 % with respect to fNOM(typ),
over temperature
(0 °C to 85 °C)
-3.9 – 4.0 % with respect to fNOM(typ),
over temperature
(-40 °C to 105 °C)
Table 28 32 kHz DCO2 Characteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit Test Conditions
Min. Typ. Max.
Nominal frequency fNOM CC – 32.75 – kHz under nominal
conditions1) after trimming
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA=+25 °C.
Accuracy ΔfLT CC -1.7 – 3.4 % with respect to fNOM(typ),
over temper ature
(0 °C to 85 °C)
-3.9 – 4.0 % with respect to fNOM(typ),
over temper ature
(-40 °C to 105 °C)1)
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 73 V1.2, 2016-08
3.3.4 Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 24 SWD Timing
Table 29 SWD Interface Timing Param eters(Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SWDCLK high time t1 SR 50 – 500000 ns –
SWDCLK low time t2 SR 50 – 500000 ns –
SWDIO input setup
to SWDCLK rising edge t3 SR 10 – – ns –
SWDIO input hold
after SWDCLK rising edge t4 SR 10 – – ns –
SWDIO output valid time
after SWDCLK rising edge t5 CC – – 68 ns CL=50pF
––62nsC
L=30pF
SWDIO output hold time
from SWDCLK rising edge t6 CC 4 – – ns
SWDCLK
SWDIO
(Output)
t
1
t
2
t
6
t
5
SWDIO
(Input)
t
3
t
4
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 74 V1.2, 2016-08
3.3.5 SPD Timing Requirements
The optimum SPD decision time between 0B and 1B is 0.75 µs. With this value the
system has maximum robustness against frequency deviations of the sampling clock on
tool and on device side. However it is not always possible to exactly match this value
with the given constraints fo r the sample clock. For instance for a o versampling rate of
4, the sample clock will be 8 MHz and in this case the closest possible effective decision
time is 5.5 clock cycles (0.69 µs).
For a balanced distribution of the timing robustness of SPD between tool and device, the
timing requirements for the tool are:
• Frequency deviation of the sample clock is +/- 5%
• Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal
sample frequency)
Table 30 Optimum Number of Sample Clocks for SPD
Sample
Freq. Sampling
Factor Sample
Clocks 0B
Sample
Clocks 1B
Effective
Decision
Time1)
1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0B sample clocks)
Remark
8 MHz 4 1 to 5 6 to 12 0.69 µs The other closest option
(0.81 µs) for the effective
decision time is less robust.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 75 V1.2, 2016-08
3.3.6 Peripheral Timings
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.3.6.1 Synchronous Serial Interface (USIC SSC) Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: Operating Conditions apply.
Table 31 USIC SSC Master Mode Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SCLKOUT master clock
period tCLK CC 4/MCLK −− ns
Slave select output SELO
active to first SCLKOUT
transmit edg e
t1 CC tCLK/2 - 28 −− ns
Slave select output SELO
inactive afte r last
SCLKOUT receive edge
t2 CC 0 −− ns
Data output DOUT[3:0]
valid time t3 CC -28 −28 ns
Receive data input
DX0/DX[5:3] setup time to
SCLKOUT receive edge
t4 SR 75 −− ns
Data input DX0/DX[5:3]
hold time from SCLKOUT
receive edg e
t5 SR 0 −− ns
Table 32 USIC SSC Slave Mode Timing
Parameter Symbol Values Unit Note /
Test Conditio
n
Min. Typ. Max.
DX1 slave clock period tCLK SR 4/MCLK −− ns
Select input DX2 setup to
first clock input DX1 transmit
edge1)
t10 SR 16 −− ns
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 76 V1.2, 2016-08
Select input DX2 hold after
last clock input DX1 receive
edge1)
t11
SR 17 −− ns
Receive data input
DX0/DX[5:3] setup time to
shift clock receive edge1)
t12
SR 21 −− ns
Data input DX0/DX[5:3] hold
time from clock input DX1
receive edg e1)
t13
SR 15 −− ns
Data output DOUT[3:0] valid
time t14
CC -−71 ns
1) These input timings are valid for asynchronous inpu t signal handling of slave select input, shif t clock input, and
receive data input (bits DXnCR.DSEN = 0).
Table 32 USIC SSC Slave Mode Timing
Parameter Symbol Values Unit Note /
Test Conditio
n
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 77 V1.2, 2016-08
Figure 25 USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
t
2
t
1
USIC_SSC_TMGX.VSD
Clock O utput
SCLKOUT
Data Output
DOUT[3:0]
t
3
t
3
t
5
Data
valid
t
4
First Transmit
Edge
Data Input
DX0/DX[5:3]
Select Output
SELOx
Active
Master Mode Ti m ing
S l ave Mode Tim i ng
t
11
t
10
Clock I nput
DX1
Data Output
DOUT[3:0]
t
14
t
14
Data
valid
Data Input
DX0/DX[5:3]
Select Input
DX2
Active
t
13
t
12
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, rec e ive data at recei ve data inpu t is latched.
Receive
Edge Last Receive
Edge
InactiveInactive
Trans mit
Edge
InactiveInactive
Firs t Transm it
Edge Receive
Edge Transm it
Edge Last Receive
Edge
t
5
Data
valid
t
4
Data
valid
t
12
t
13
Drawn for BRGH.SCLKCFG = 00B. Also valid fo r for SCLK CFG = 01 B with i n verted SCLKOUT signal.
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 78 V1.2, 2016-08
3.3.6.2 Inter-IC (IIC) Interface Timing
The following parameters are applicable for a USIC channel operated in IIC mode.
Note: Operating Conditions apply.
Table 33 USIC IIC Standard Mode Timing1)
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-d rain mode. The high level o n these lines must be held b y an external pull-up de vice,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Fall time of both SDA and
SCL t1
CC/SR --300ns
Rise time of both SDA and
SCL t2
CC/SR - - 1000 ns
Data hold time t3
CC/SR 0- - µs
Data set-up time t4
CC/SR 250 - - ns
LOW period of SCL clock t5
CC/SR 4.7 - - µs
HIGH period of SCL clock t6
CC/SR 4.0 - - µs
Hold time for (repeated)
START condition t7
CC/SR 4.0 - - µs
Set-up time for repeated
START condition t8
CC/SR 4.7 - - µs
Set-up time for STOP
condition t9
CC/SR 4.0 - - µs
Bus free time between a
STOP and START
condition
t10
CC/SR 4.7 - - µs
Capacitive load for each
bus line Cb SR - - 400 pF
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 79 V1.2, 2016-08
Table 34 USIC IIC Fast Mode Timing1)
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-d rain mode. The high level o n these lines must be held b y an external pull-up de vice,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Fall time of both SDA and
SCL t1
CC/SR 20 +
0.1*Cb
2)
2) Cb refers to the total capacitance of one bus line in pF.
-300ns
Rise time of both SDA and
SCL t2
CC/SR 20 +
0.1*Cb
-300ns
Data hold time t3
CC/SR 0- - µs
Data set-up time t4
CC/SR 100 - - ns
LOW period of SCL clock t5
CC/SR 1.3 - - µs
HIGH period of SCL clock t6
CC/SR 0.6 - - µs
Hold time for (repeated)
START condition t7
CC/SR 0.6 - - µs
Set-up time for repeated
START condition t8
CC/SR 0.6 - - µs
Set-up time for STOP
condition t9
CC/SR 0.6 - - µs
Bus free time between a
STOP and START
condition
t10
CC/SR 1.3 - - µs
Capacitive load for each
bus line Cb SR - - 400 pF
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 80 V1.2, 2016-08
Figure 26 USIC IIC Timing
3.3.6.3 Inter-IC Sound (IIS) Interface Timing
The following parameters are applicable for a USIC channel operated in IIS mode.
Note: Operating Conditions apply.
Table 35 USIC IIS Master Transmitter Tim i ng
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Clock period t1 CC 4/fMCLK --ns
Clock HIGH t2 CC 0.35 x
t1min
--ns
Clock Low t3 CC 0.35 x
t1min
--ns
Hold time t4 CC 0 - - ns
Clock rise time t5 CC - - 0.15 x
t1min
ns
SCL
SDA
SCL
SDA
t
1
t
2
t
1
t
2
t
10
t
9
t
7
t
8
t
7
t
3
t
4
t
5
t
6
PSSr
S
70%
30%
9
th
clock
9
th
clock
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Electrical Parameter
Data Sheet 81 V1.2, 2016-08
Figure 27 USIC IIS Mast er Tr ansmitter Timi ng
Figure 28 USIC IIS Slave Receiver Timing
Table 36 USIC IIS Slave Receiver Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Clock period t6 SR 4/fMCLK --ns
Clock HIGH t7 SR 0.35 x
t6min
--ns
Clock Low t8 SR 0.35 x
t6min
--ns
Set-up time t9 SR 0.3 x
t6min
--ns
Hold time t10 SR 15 - - ns
SCK
WA/
DOUT
t
1
t
5
t
3
t
2
t
4
SCK
WA/
DIN
t
6
t
10
t
8
t
7
t
9
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Package and Reliability
Data Sheet 82 V1.2, 2016-08
4 Package and Reliability
The XMC1400 is a member of the XMC™1000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the exposed die pad may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
4.1 Package Parameters
Table 37 provides th e thermal characteristics of the packages used in XMC1400.
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSSP, independent of EMC and thermal requirements.
4.1.1 Thermal Considerations
When operating the XMC1400 in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting the rma l
damage.
The maximum heat that can be dissipated depend s on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 115 °C.
Table 37 Thermal Characteristics of the Packages
Parameter Symbol Limit Values Unit Package Types
Min. Max.
Exposed Die Pad
Dimensions Ex × Ey
CC -3.7×3.7 mm PG-VQFN-40-17
-4.2×4.2 mm PG-VQFN-48-73
-4.6×4.6 mm PG-VQFN-64-6
Thermal resistance
Junction-Ambient RΘJA CC - 86.0 K/W PG-TSSOP-38-91)
- 45.3 K/W PG-VQFN-40-171)
1) Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered .
- 44.9 K/W PG-VQFN-48-731)
- 66.7 K/W PG-LQFP-64-261)
- 44.7 K/W PG-VQFN-64-61)
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Package and Reliability
Data Sheet 83 V1.2, 2016-08
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
• Reduce VDDP, if possible in the system
• Reduce the system frequency
• Reduce the number of output pins
• Reduce the load on active output drivers
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Package and Reliability
Data Sheet 84 V1.2, 2016-08
4.2 Package Outlines
Figure 29 PG-TSSOP-38-9
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Package and Reliability
Data Sheet 85 V1.2, 2016-08
Figure 30 PG-VQFN-40-17
Figure 31 PG-VQFN-48-73
0.05 MAX.
STANDOFF
40x
COPLANARITY
0.9 MAX.
(0.2)
SEATING PLANE
C
0.08 C
0.1 C
9 x 0.4 = 3.6
0.4
0.4
±0.05
40x B
M
AC
0.05
0.07
M
C
±0.05
0.2
B
M
AC0.05
B
M
AC0.05
10 1
21 30
11
20
40
31
±0.1
3.6
Index Marking
±0.1
3.6
B
Index Marking
A
5
5
0.1 AC2x
0.1 B C 2x
PG-VQFN-40-13, -14, -17-PO V05
PG-VQFN-48-35, -73-PO V04
Index Marking
0.9 MAX.
0.1 C
48x0.05 C
COPLANARITY
(0.203)
SEATING PLANE
C0.05 MAX.
STAND OFF
11 x 0.5 = 5.5
0.5
0.4
±0.05
±0.1
4.1 0.1 B
M
AC
0.1 B
M
AC
±0.1
4.1
0.1
48x B
M
AC
0.05
M
C
+0.05
-0.07
0.25
7A
0.1 A
2x
B
7
0.1 B
2x
Index Marking
112
13 48
24 37
25 36
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Package and Reliability
Data Sheet 86 V1.2, 2016-08
Figure 32 PG-LQFP-64-26
D
12
H
0.2 A-B D 4x
A-B0.2 64x
64xC
DC
B
12
1
64
Index Marking
0.5
±0.05
0.22 0.08
M
A-B D
C0.08
±0.05
0.1
±0.05
1.4
1.6 MAX.
±0.15
0.6
H
A
-0.06
+0.05
0.15
64x C
10
1)
2)
10 1)
PG-LQFP-64-10, -21, -26-PO V03
15 x 0.5 = 7.5
COPLANARITY
SEATING PLANE
STAND OFF
0°...7°
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Does not include dambar protrusion of 0.08 max. per side
Subject to Agreement on the Use of Product Information
XMC™1400 AA-Step
XMC™1000 Family
Quality Declaration
Data Sheet 87 V1.2, 2016-08
Figure 33 PG-VQFN-64-6
All dimensions in mm.
5 Quality Declaration
Table 38 shows the characteristics of the quality parameters in the XMC1400.
Table 38 Quality Parameters
Parameter Symbol Limit Values Unit Notes
Min. Max.
ESD susceptibility
according to Human Body
Model (HBM)
VHBM
SR - 2000 V Conforming to
EIA/JESD22-
A114-B
ESD susceptibility
according to Charged
Device Model (CDM) pins
VCDM
SR - 500 V Conforming to
JESD22-C101-C
Moisture sensitivity level MSL
CC -3-JEDEC
J-STD-020D
Soldering te mp erature TSDR
SR - 260 °C Profile accordi ng
to JEDEC
J-STD-020D
PG-VQFN-64-6-PO V04
±0.1
4.5 0.1 B
M
AC
8A
0.1 A C 2x
B
8
0.1 BC2x
Index Marking
0.9 MAX.
0.1 C
(0.2)
64x0.08 C
COPLANARITY
SEATING PLANE
C0.05 MAX.
STAND OFF
Index Marking
0.4
±0.05
0.07
64x B
M
AC
0.05
M
C
±0.05
0.2
15 x 0.4 = 6
0.4
0.1 B
M
AC
±0.1
4.5
17
116
64
32 49
33 48
Subject to Agreement on the Use of Product Information
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