XMC TM 1400 AA-Step Microcontroller Series for Industrial Applications XMCTM1000 Family ARM(R) Cortex(R)-M0 32-bit processor core Data Sheet V1.2 2016-08 Microcontrollers Edition 2016-08 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2016 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. XMC TM 1400 AA-Step Microcontroller Series for Industrial Applications XMCTM1000 Family ARM(R) Cortex(R)-M0 32-bit processor core Data Sheet V1.2 2016-08 Microcontrollers XMCTM1400 AA-Step XMCTM1000 Family XMC1400 Data Sheet Revision History: V1.2 2016-08 Previous Versions: V1.1 2016-06 V1.0 2016-02 V0.3 2015-10 Page Subjects many Added XMCTM trademark 10, 12, 14 Added XMC1402-T038X0200, XMC1402-Q040X0200 and XMC1402-Q048X0200 marking variants V1.1 2016-06 many Added TSSOP-38-9 package 10, 12, 14 Added XMC1402-T038 marking variants in TSSOP-38 10, 12, 14 Added XMC1403-Q040 marking variants V1.0 2016-02 9 The device provides four USIC channels. 10 XMC1401 devices available for max. ambient temperature of 85C. 32 Reformatted pinout table. 57 Updated footnote to the definition of the start-up times of OSC_XTAL and RTC_XTAL oscillators. 72 Added fLT parameter to on-chip oscillators DCO1 and DCO2. 84 Updated package outline drawings. Trademarks C166TM, TriCoreTM, XMCTM and DAVETM are trademarks of Infineon Technologies AG. ARM(R), ARM Powered(R), Cortex(R), Thumb(R) and AMBA(R) are registered trademarks of ARM, Limited. CoreSightTM, ETMTM, Embedded Trace MacrocellTM and Embedded Trace BufferTM are trademarks of ARM, Limited. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Table of Contents Table of Contents 1 1.1 1.2 1.3 1.4 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Pin for Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port I/O Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Controlled I/O Function Description . . . . . . . . . . . . . . . . . . . 17 17 21 25 29 30 31 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.6.1 3.3.6.2 3.3.6.3 Electrical Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog to Digital Converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Out of Range Comparator (ORC) Characteristics . . . . . . . . . . . . . . . . . Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up and Supply Threshold Characteristics . . . . . . . . . . . . . . . . . On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . . SPD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 41 42 44 45 45 49 53 55 56 57 61 67 69 69 70 72 73 74 75 75 78 80 4 4.1 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Data Sheet 5 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Table of Contents 4.1.1 4.2 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5 Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Data Sheet 6 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family About this Document About this Document This Data Sheet is addressed to embedded hardware and software developers. It provides the reader with detailed descriptions about the ordering designations, available features, electrical and physical characteristics of the XMC1400 series devices. The document describes the characteristics of a superset of the XMC1400 series devices. For simplicity, the various device types are referred to by the collective term XMC1400 throughout this document. XMCTM1000 Family User Documentation The set of user documentation includes: * * * Reference Manual - decribes the functionality of the superset of devices. Data Sheets - list the complete ordering designations, available features and electrical characteristics of derivative devices. Errata Sheets - list deviations from the specifications given in the related Reference Manual or Data Sheets. Errata Sheets are provided for the superset of devices. Attention: Please consult all parts of the documentation set to attain consolidated knowledge about your device. Application related guidance is provided by Users Guides and Application Notes. Please refer to http://www.infineon.com/xmc1000 to get access to the latest versions of those documents. Data Sheet 7 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Summary of Features 1 Summary of Features The XMC1400 devices are members of the XMCTM1000 Family of microcontrollers based on the ARM Cortex-M0 processor core. The XMC1400 series addresses the real-time control needs of motor control and digital power conversion. It also features peripherals for LED Lighting applications and Human-Machine Interface (HMI). CPU (R) ARM Cortex(R) - M0 NVIC Analog System EVR 2 x DCO SWD Debug System SPD PRNG APB Bus DTS ANACTRL AHB to APB Bridge PAU AHB-Lite Bus FLASH MATH USIC0 VADC SRAM1 WDT USIC1 CCU40 ROM SCU MultiCAN+ CCU41 PORTS RTC BCCU0 CCU80 ACMP & ORC ERU0 LEDTS0 CCU81 ERU1 LEDTS1 POSIF0 LEDTS2 POSIF1 Figure 1 Data Sheet Block Diagram 8 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Features CPU subsystem * 32-bit ARM Cortex-M0 CPU Core - 0.84 DMIPS/MHz (Dhrystone 2.1) at 48 MHz * Nested Vectored Interrupt Controller * 64 interrupt nodes * MATH coprocessor - 24-bit trigonometric calculation (CORDIC) - 32-bit divide operation * 2x4 channels ERU for event interconnections On-Chip Memories * 8 Kbyte ROM * 16 Kbyte SRAM (with parity) * up to 200 Kbyte Flash (with ECC) Supply, Reset and Clock * 1.8 V to 5.5 V supply with power on reset and brownout detector * On-chip clock monitor * External crystal oscillator support (32 kHz and 4 to 20 MHz) * Internal slow and fast oscillators without the need of PLL System Control * Window watchdog * Real time clock module * Pseudo random number generator Communication Peripherals * Four USIC channels, usable as - UART (up to 12 Mb/s) - single-SPI (up to 12 Mb/s) - double-SPI (up to 2 x 12 Mb/s) - quad-SPI (up to 4 x 12 Mb/s) - IIC (up to 400 kb/s) - IIS (up to 12 Mb/s) - LIN interfaces (20kb/s) * LEDTS in Human-Machine interface - up to 24 touch pads - drive up to 144 LEDs * MultiCAN+, Full-CAN/Basic-CAN with 2 nodes, 32 message objects (up to 1 MBaud) Data Sheet Analog Frontend Peripherals * A/D Converters (up to 12 analog inputs) - 2 sample and hold stages - fast 12-bit ADC (up to 1.1 MS/s), adjustable gain - 0 V to 5.5 V input range * Up to 8 channels out of range comparators * Up to 4 fast analog comparators * Temperature Sensor Industrial Control Peripherals * 2x4 16-bit 96 MHz CCU4 timers for signal monitoring and PWM * 2x4 16-bit 96 MHz CCU8 timers for complex PWM, complementary high/low side switches and multi phase control * 2x POSIF for hall and quadrature encoders, motor positioning * 9 channel BCCU (brightness and color control) for LED lighting applications Up to 56 Input/Output Ports * 1.8 V to 5.5 V capable * up to 8 high current pads (50 mA sink) On-Chip Debug Support * 4 breakpoints, 2 watchpoints * ARM serial wire debug, single-pin debug interfaces Programming Support * Single-pin bootloader * Secure bootstrap loader SBSL (optional) Packages * TSSOP-38 (9.7 x 6.4 mm2) * VQFN-40/48/64 (5x5/7x7/8x8 mm2) * LQFP-64 (12 x 12 mm2) Tools * 9 Free DAVETM toolchain with low level drivers and apps V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family 1.1 Device Overview The following table lists the available features per device type for the XMC1400 series. XMC1404-F064 XMC1404-Q064 XMC1404-Q048 XMC1403-Q064 XMC1403-Q048 XMC1403-Q040 XMC1402-F064 XMC1402-Q064 XMC1402-Q048 XMC1402-Q040 XMC1402-T038 XMC1401-F064 Features Features of XMC1400 Device Types1) XMC1401-Q048 Table 1 CPU frequency 48 MHz Operating temperature (ambient) -40 to 85 C -40 to 105 C Operating voltage 1.8 V to 5.5 V Flash options (Kbytes) 64, 64, 32, 128 128 64, 128 200 32, 64, 128 200 32, 64, 64, 64, 64, 64, 64, 64, 64, 64, 128 128 128 128 128 128 128 128 128 200 200 200 200 200 200 200 200 200 16 16 16 16 16 16 16 16 16 16 16 16 MATH - - 1 1 1 1 1 - - - 1 1 1 Communication Industrial Control SRAM (Kbytes) 16 CCU4 2 2 2 2 2 2 2 2 2 2 2 2 2 CCU8 - - 2 2 2 2 2 - - - 2 2 2 POSIF - - 1 1 2 2 2 - - - 2 2 2 BCCU - - 1 1 1 1 1 - - - 1 1 1 USIC 2/ (modules / 2 channels) 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 LEDTS 3 3 - - - - - - - - 3 3 3 MultiCAN+ (nodes / MOs) - - - - - - 2/ 32 2/ 32 2/ 32 2/ 32 2/ 32 2/ 32 Data Sheet 10 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Features of XMC1400 Device Types1) (cont'd) XMC1401-F064 XMC1402-T038 XMC1402-Q040 XMC1402-Q048 XMC1402-Q064 XMC1402-F064 XMC1403-Q040 XMC1403-Q048 XMC1403-Q064 XMC1404-Q048 XMC1404-Q064 XMC1404-F064 2/ 12 2/ 12 2/ 12 2/ 12 2/ 12 2/ 12 2/ 12 2/ 12 2/ 12 2/ 12 2/ 12 2/ 12 2/ 12 ACMP - - 3 3 4 4 4 - - - 4 4 4 GPIOs 34 48 26 27 34 48 48 27 34 48 34 48 48 GPIs 8 8 8 8 8 8 8 8 8 8 8 8 8 LQFP-64 TSSOP-38 VQFN-40 VQFN-48 LQFP-64 VQFN-40 VQFN-48 VQFN-64 VQFN-48 VQFN-64 LQFP-64 Analog Features Packages VQFN-64 XMC1401-Q048 ADC (kernels / analog inputs) VQFN-48 Table 1 1) Features that are not included in this table are available in all the derivatives 1.2 Ordering Information The ordering code for an Infineon microcontroller provides an exact reference to a specific product. The code "XMC1<DDD>-<Z><PPP><T><FFFF>" identifies: * * * * * <DDD> the derivatives function set <Z> the package variant - T: TSSOP - Q: VQFN - F: LQFP <PPP> package pin count <T> the temperature range: - F: -40C to 85C - X: -40C to 105C <FFFF> the Flash memory size in Kbytes. For ordering codes for the XMC1400 please contact your sales representative or local distributor. This document describes several derivatives of the XMC1400 series, some descriptions may not apply to a specific product. Please see Table 2. For simplicity the term XMC1400 is used for all derivatives throughout this document. Data Sheet 11 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family 1.3 Device Types These device types are available and can be ordered through Infineon's direct and/or distribution channels. Table 2 Synopsis of XMC1400 Device Types Derivative Package Flash Kbytes XMC1401-Q048F0064 PG-VQFN-48 64 XMC1401-Q048F0128 PG-VQFN-48 128 XMC1401-F064F0064 PG-LQFP-64 64 XMC1401-F064F0128 PG-LQFP-64 128 XMC1402-T038X0032 PG-TSSOP-38 32 XMC1402-T038X0064 PG-TSSOP-38 64 XMC1402-T038X0128 PG-TSSOP-38 128 XMC1402-T038X0128 PG-TSSOP-38 200 XMC1402-Q040X0032 PG-VQFN-40 32 XMC1402-Q040X0064 PG-VQFN-40 64 XMC1402-Q040X0128 PG-VQFN-40 128 XMC1402-Q040X0200 PG-VQFN-40 200 XMC1402-Q048X0032 PG-VQFN-48 32 XMC1402-Q048X0064 PG-VQFN-48 64 XMC1402-Q048X0128 PG-VQFN-48 128 XMC1402-Q048X0128 PG-VQFN-48 200 XMC1402-Q064X0064 PG-VQFN-64 64 XMC1402-Q064X0128 PG-VQFN-64 128 XMC1402-Q064X0200 PG-VQFN-64 200 XMC1402-F064X0064 PG-LQFP-64 64 XMC1402-F064X0128 PG-LQFP-64 128 XMC1402-F064X0200 PG-LQFP-64 200 XMC1403-Q040X0064 PG-VQFN-40 64 XMC1403-Q040X0128 PG-VQFN-40 128 XMC1403-Q040X0200 PG-VQFN-40 200 XMC1403-Q048X0064 PG-VQFN-48 64 XMC1403-Q048X0128 PG-VQFN-48 128 Data Sheet 12 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Table 2 Synopsis of XMC1400 Device Types (cont'd) Derivative Package Flash Kbytes XMC1403-Q048X0200 PG-VQFN-48 200 XMC1403-Q064X0064 PG-VQFN-64 64 XMC1403-Q064X0128 PG-VQFN-64 128 XMC1403-Q064X0200 PG-VQFN-64 200 XMC1404-Q048X0064 PG-VQFN-48 64 XMC1404-Q048X0128 PG-VQFN-48 128 XMC1404-Q048X0200 PG-VQFN-48 200 XMC1404-Q064X0064 PG-VQFN-64 64 XMC1404-Q064X0128 PG-VQFN-64 128 XMC1404-Q064X0200 PG-VQFN-64 200 XMC1404-F064X0064 PG-LQFP-64 64 XMC1404-F064X0128 PG-LQFP-64 128 XMC1404-F064X0200 PG-LQFP-64 200 Data Sheet 13 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family 1.4 Chip Identification Number The Chip Identification Number allows software to identify the marking. It is an 8 words value with the most significant 7 words stored in Flash configuration sector 0 (CS0) at address location : 1000 0F00H (MSB) - 1000 0F1BH (LSB). The least significant word and most significant word of the Chip Identification Number are the value of registers DBGROMID and IDCHIP, respectively. Table 3 XMC1400 Chip Identification Number Derivative Value Marking XMC1401-Q048F0064 00014082 07CF00FF 1E071FF7 20006000 00000D00 00001000 00011000 10204083H AA XMC1401-Q048F0128 00014082 07CF00FF 1E071FF7 20006000 00000D00 00001000 00021000 10204083H AA XMC1401-F064F0064 000140A2 07CF00FF 1E071FF7 20006000 00000D00 00001000 00011000 10204083H AA XMC1401-F064F0128 000140A2 07CF00FF 1E071FF7 20006000 00000D00 00001000 00021000 10204083H AA XMC1402-T038X0032 00014013 07FF00FF 1E071FF7 000F900F 00000D00 00001000 00009000 10204083H AA XMC1402-T038X0064 00014013 07FF00FF 1E071FF7 000F900F 00000D00 00001000 00011000 10204083H AA XMC1402-T038X0128 00014013 07FF00FF 1E071FF7 000F900F 00000D00 00001000 00021000 10204083H AA XMC1402-T038X0200 00014013 07FF00FF 1E071FF7 000F900F 00000D00 00001000 00033000 10204083H AA XMC1402-Q040X0032 00014043 07FF00FF 1E071FF7 000F900F 00000D00 00001000 00009000 10204083H AA XMC1402-Q040X0064 00014043 07FF00FF 1E071FF7 000F900F 00000D00 00001000 00011000 10204083H AA XMC1402-Q040X0128 00014043 07FF00FF 1E071FF7 000F900F 00000D00 00001000 00021000 10204083H AA XMC1402-Q040X0200 00014043 07FF00FF 1E071FF7 000F900F 00000D00 00001000 00033000 10204083H AA XMC1402-Q048X0032 00014083 07FF00FF 1E071FF7 100F900F 00000D00 00001000 00009000 10204083H AA Data Sheet 14 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Table 3 XMC1400 Chip Identification Number (cont'd) Derivative Value Marking XMC1402-Q048X0064 00014083 07FF00FF 1E071FF7 100F900F 00000D00 00001000 00011000 10204083H AA XMC1402-Q048X0128 00014083 07FF00FF 1E071FF7 100F900F 00000D00 00001000 00021000 10204083H AA XMC1402-Q048X0200 00014083 07FF00FF 1E071FF7 100F900F 00000D00 00001000 00033000 10204083H AA XMC1402-Q064X0064 00014093 07FF00FF 1E071FF7 100F900F 00000D00 00001000 00011000 10204083H AA XMC1402-Q064X0128 00014093 07FF00FF 1E071FF7 100F900F 00000D00 00001000 00021000 10204083H AA XMC1402-Q064X0200 00014093 07FF00FF 1E071FF7 100F900F 00000D00 00001000 00033000 10204083H AA XMC1402-F064X0064 000140A3 07FF00FF 1E071FF7 100F900F 00000D00 00001000 00011000 10204083H AA XMC1402-F064X0128 000140A3 07FF00FF 1E071FF7 100F900F 00000D00 00001000 00021000 10204083H AA XMC1402-F064X0200 000140A3 07FF00FF 1E071FF7 100F900F 00000D00 00001000 00033000 10204083H AA XMC1403-Q040X0064 00014043 07CF00FF 1E071FF7 00B00000 00000D00 00001000 00011000 10204083H AA XMC1403-Q040X0128 00014043 07CF00FF 1E071FF7 00B00000 00000D00 00001000 00021000 10204083H AA XMC1403-Q040X0200 00014043 07CF00FF 1E071FF7 00B00000 00000D00 00001000 00033000 10204083H AA XMC1403-Q048X0064 00014083 07CF00FF 1E071FF7 00B00000 00000D00 00001000 00011000 10204083H AA XMC1403-Q048X0128 00014083 07CF00FF 1E071FF7 00B00000 00000D00 00001000 00021000 10204083H AA XMC1403-Q048X0200 00014083 07CF00FF 1E071FF7 00B00000 00000D00 00001000 00033000 10204083H AA XMC1403-Q064X0064 00014093 07CF00FF 1E071FF7 00B00000 00000D00 00001000 00011000 10204083H AA XMC1403-Q064X0128 00014093 07CF00FF 1E071FF7 00B00000 00000D00 00001000 00021000 10204083H AA Data Sheet 15 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Table 3 XMC1400 Chip Identification Number (cont'd) Derivative Value Marking XMC1403-Q064X0200 00014093 07CF00FF 1E071FF7 00B00000 00000D00 00001000 00033000 10204083H AA XMC1404-Q048X0064 00014083 07FF00FF 1E071FF7 30BFF00F 00000D00 00001000 00011000 10204083H AA XMC1404-Q048X0128 00014083 07FF00FF 1E071FF7 30BFF00F 00000D00 00001000 00021000 10204083H AA XMC1404-Q048X0200 00014083 07FF00FF 1E071FF7 30BFF00F 00000D00 00001000 00033000 10204083H AA XMC1404-Q064X0064 00014093 07FF00FF 1E071FF7 30BFF00F 00000D00 00001000 00011000 10204083H AA XMC1404-Q064X0128 00014093 07FF00FF 1E071FF7 30BFF00F 00000D00 00001000 00021000 10204083H AA XMC1404-Q064X0200 00014093 07FF00FF 1E071FF7 30BFF00F 00000D00 00001000 00033000 10204083H AA XMC1404-F064X0064 000140A3 07FF00FF 1E071FF7 30BFF00F 00000D00 00001000 00011000 10204083H AA XMC1404-F064X0128 000140A3 07FF00FF 1E071FF7 30BFF00F 00000D00 00001000 00021000 10204083H AA XMC1404-F064X0200 000140A3 07FF00FF 1E071FF7 30BFF00F 00000D00 00001000 00033000 10204083H AA Data Sheet 16 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family General Device Information 2 General Device Information This section summarizes the logic symbols and package pin configurations with a detailed list of the functional I/O mapping. 2.1 Logic Symbols VDDP VSSP (2) (2) Port 0 12 bit Port 0 / XTAL 4 bit XMC1400 Port 1 / High-current 6 bit TSSOP-38 Port 2 / Analog input 4 bit Port 2 / Analog input 8 bit Figure 2 Data Sheet XMC1400 Logic Symbol for TSSOP-38-9 17 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family General Device Information VDD VSS VDDP VSSP (1) (1) (2) (1) Exp. Die Pad (V SSP) Port 0 12 bit Port 0 / XTAL 4 bit XMC1400 VQFN-40 Port 1 / High-current 7 bit Port 2 / Analog input 4 bit Port 2 / Analog input 8 bit Figure 3 Data Sheet XMC1400 Logic Symbol for PG-VQFN-40-17 18 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family General Device Information VDD VSS VDDP VSSP (1) (1) (3) (1) Exp. Die Pad (VSSP) Port 0 12 bit Port 0 / XTAL 4 bit Port 1 / High-current 7 bit XMC1400 VQFN-48 Port 2 / Analog input 6 bit Port 2 / Analog input 8 bit Port 3 1 bit Port 4 4 bit Figure 4 Data Sheet XMC1400 Logic Symbol for PG-VQFN-48-73 19 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family General Device Information VDD VSS VDDP VSSP (1) (1) (4) (2) 1) VQFN64 only Exp. Die Pad (V SSP) 1) Port 0 12 bit Port 0 / XTAL 4 bit Port 1 / High-current 8 bit XMC1400 Port 1 1 bit VQFN-64 / LQFP-64 Port 2 / Analog input 6 bit Port 2 / Analog input 8 bit Port 3 5 bit Port 4 12 bit Figure 5 Data Sheet XMC1400 Logic Symbol for PG-LQFP-64-26 / PG-VQFN-64-6 20 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family General Device Information 2.2 Pin Configuration and Definition The following figures summarize all pins, showing their locations on the different packages. P2.4 1 38 P2.3 Top View Figure 6 Data Sheet P2.5 2 37 P2.2 P2.6 3 36 P2.1 P2.7 4 35 P2.0 P2.8 5 34 P0.15 P2.9 6 33 P0.14 P2.10 7 32 P0.13 P2.11 8 31 P0.12 VSSP /VSS 9 30 P0.11 VDDP/VDD 10 29 P0.10 P1.5 11 28 P0.9 P1.4 12 27 P0.8 P1.3 13 26 VDDP P1.2 14 25 VSSP P1.1 15 24 P0.7 P1.0 16 23 P0.6 P0.0 17 22 P0.5 P0.1 18 21 P0.4 P0.2 19 20 P0.3 XMC1400 PG-TSSOP-38-9 Pin Configuration (top view) 21 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family P0 .1 3 P0.12 P0.11 / XTAL 2 P0.10 / XTAL1 P0.9 / RTC_XTAL2 P0.8 / RTC_XTAL1 VDD P VS SP 37 36 35 34 33 32 31 P0 .14 39 38 P0 .1 5 40 General Device Information Analog input / P2.0 1 30 P0.7 P1.0 / High-current 21 P1.1 / High-current Figure 7 Data Sheet 20 22 10 P1.2 / High -cu rre nt 9 Analog input / P2.9 19 Analog input / P2.8 P1.3 / High -cu rre nt P0.0 18 8 Analog input / P2.7 P1.4 / High -cu rre nt P0.1 23 17 7 Analog input / P2.6 P1.5 / High -cu rre nt P0.2 24 16 6 15 P0.3 25 Analog input / P2.5 V DDP 26 P1.6 / High -cu rre nt 5 14 P0.4 Analog input / P2.4 V DD 27 13 4 V SS P0.5 Analog input / P2.3 12 P0.6 28 11 29 3 Analog input / P2.11 2 Analog input / P2.10 Analog input / P2.1 Analog input / P2.2 XMC1400 PG-VQFN-40-17 Pin Configuration (top view) 22 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family P0.10 / XTAL1 P0.9 / RTC_XTAL2 P0.8 / RTC_XTAL1 VDDP VS SP 39 38 37 P0.11 / XTAL2 42 40 P0.12 43 41 P0.14 P0.13 46 44 P0.15 47 45 P4.5 P4.4 48 General Device Information 9 28 P3.0 Analog input / P2.7 10 27 VDDP Analog input / P2.8 11 26 P1.0 / High-current Analog input / P2.9 12 25 P1.1 / High-current Figure 8 Data Sheet VDDP 24 P0.0 Analog input / P2.6 P1.2 / High-current 29 23 8 22 P0.1 Analog input / P2.5 P1.3 / High-current 30 P1.4 / High-current 7 21 P0.2 Analog input / P2.4 P1.5 / High-current 31 20 6 P1.6 / High-current P0.3 Analog input / P2.3 19 32 18 5 V DD P0.4 Analog input / P2.2 17 P0.5 33 16 34 4 15 3 Analog input / P2.1 Analog input / P2.13 V SS Analog input / P2.0 Analog input / P2.12 P0.6 14 P0.7 35 13 36 2 Analog input / P2.11 1 P4.7 Analog input / P2.10 P4.6 XMC1400 PG-VQFN-48-73 Pin Configuration (top view) 23 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family VDDP 49 P0.11 / XTAL2 54 VS SP P0.12 55 P0.8 / RTC_XTAL1 P0.13 56 50 P0.14 57 51 P0.15 58 P0.10 / XTAL1 P4.0 59 P0.9 / RTC_XTAL2 P4.1 60 52 P4.2 61 53 P4.4 P4.3 62 P4.5 63 64 General Device Information V SSP 1 48 P0.7 VDDP 2 47 P0.6 P4.6 3 46 P0.5 P4.7 4 45 P0.4 P4.8 5 44 P0.3 Figure 9 Data Sheet 32 P1.1 / High-current P1.2 / High-current 33 31 16 30 Analog input / P2.7 P1.3 / High-current P1.0 / High-current P1.4 / High-current 34 29 15 P1.5 / High-current V DDP Analog input / P2.6 28 35 P1.6 / High-current 14 27 P3.0 Analog input / P2.5 P1.7 / High-current 36 26 13 P1.8 P3.1 Analog input / P2.4 25 P3.2 37 VDDP 38 12 24 11 Analog input / P2.3 V DD Analog input / P2.2 23 P3.3 V SS 39 22 10 Analog input / P2.13 P3.4 Analog input / P2.1 21 40 20 9 Analog input / P2.11 P0.0 Analog input / P2.0 Analog input / P2.12 41 19 8 Analog input / P2.10 P0.1 P4.11 18 P0.2 42 17 43 7 Analog input / P2.8 6 Analog input / P2.9 P4.9 P4.10 XMC1400 PG-LQFP-64-26 / PG-VQFN-64-6 Pin Configuration (top view) 24 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family General Device Information 2.2.1 Package Pin Summary The following general building block is used to describe each pin: Table 4 Package Pin Mapping Description Function Package A Package B Px.y N N ... Pad Type Pad Class The table is sorted by the "Function" column, starting with the regular Port pins (Px.y), followed by the supply pins. The following columns, titled with the supported package variants, lists the package pin number to which the respective function is mapped in that package. The "Pad Type" indicates the employed pad type: * * * * * * STD_INOUT (standard bi-directional pads) STD_INOUT/AN (standard bi-directional pads with analog input) STD_INOUT/clock (standard bi-directional pads with oscillator function) High Current (high current bi-directional pads) STD_IN/AN (standard input pads with analog input) Power (power supply) Details about the pad properties are defined in the Electrical Parameter chapter. Table 5 Package Pin Mapping Function LQFP 64, VQFN 64 VQFN 48 VQFN 40 TSSOP 38 Pad Type P0.0 41 29 23 17 STD_INOUT P0.1 42 30 24 18 STD_INOUT P0.2 43 31 25 19 STD_INOUT P0.3 44 32 26 20 STD_INOUT P0.4 45 33 27 21 STD_INOUT P0.5 46 34 28 22 STD_INOUT P0.6 47 35 29 23 STD_INOUT P0.7 48 36 30 24 STD_INOUT P0.8/ RTC_ XTAL1 51 39 33 27 STD_INOUT /clock_IN Data Sheet 25 Notes V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family General Device Information Table 5 Package Pin Mapping (cont'd) Function LQFP 64, VQFN 64 VQFN 48 VQFN 40 TSSOP 38 Pad Type P0.9/ RTC_ XTAL2 52 40 34 28 STD_INOUT /clock_O P0.10/ XTAL1 53 41 35 29 STD_INOUT /clock_IN P0.11/ XTAL2 54 42 36 30 STD_INOUT /clock_O P0.12 55 43 37 31 STD_INOUT P0.13 56 44 38 32 STD_INOUT P0.14 57 45 39 33 STD_INOUT P0.15 58 46 40 34 STD_INOUT P1.0 34 26 22 16 High Current P1.1 33 25 21 15 High Current P1.2 32 24 20 14 High Current P1.3 31 23 19 13 High Current P1.4 30 22 18 12 High Current P1.5 29 21 17 11 High Current P1.6 28 20 16 - High Current P1.7 27 - - - High Current P1.8 26 - - - STD_INOUT P2.0 9 3 1 35 STD_INOUT /AN P2.1 10 4 2 36 STD_INOUT /AN P2.2 11 5 3 37 STD_IN/AN P2.3 12 6 4 38 STD_IN/AN P2.4 13 7 5 1 STD_IN/AN P2.5 14 8 6 2 STD_IN/AN P2.6 15 9 7 3 STD_IN/AN P2.7 16 10 8 4 STD_IN/AN Data Sheet 26 Notes V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family General Device Information Table 5 Package Pin Mapping (cont'd) Function LQFP 64, VQFN 64 VQFN 48 VQFN 40 TSSOP 38 Pad Type P2.8 17 11 9 5 STD_IN/AN P2.9 18 12 10 6 STD_IN/AN P2.10 19 13 11 7 STD_INOUT /AN P2.11 20 14 12 8 STD_INOUT /AN P2.12 21 15 - - STD_INOUT /AN P2.13 22 16 - - STD_INOUT /AN P3.0 36 28 - - STD_INOUT P3.1 37 - - - STD_INOUT P3.2 38 - - - STD_INOUT P3.3 39 - - - STD_INOUT P3.4 40 - - - STD_INOUT P4.0 59 - - - STD_INOUT P4.1 60 - - - STD_INOUT P4.2 61 - - - STD_INOUT P4.3 62 - - - STD_INOUT P4.4 63 47 - - STD_INOUT P4.5 64 48 - - STD_INOUT P4.6 3 1 - - STD_INOUT P4.7 4 2 - - STD_INOUT P4.8 5 - - - STD_INOUT P4.9 6 - - - STD_INOUT P4.10 7 - - - STD_INOUT P4.11 8 - - - STD_INOUT VSS 23 17 13 9 Power Data Sheet 27 Notes Supply GND, ADC reference GND V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family General Device Information Table 5 Package Pin Mapping (cont'd) Function LQFP 64, VQFN 64 VQFN 48 VQFN 40 TSSOP 38 Pad Type Notes VDD 24 18 14 10 Power Supply VDD, ADC reference voltage/ ORC reference voltage VDDP 25 19 15 10 Power When VDD is supplied, VDDP has to be supplied with the same voltage. VDDP 2 - - - Power I/O port supply VDDP 35 27 - - Power I/O port supply VDDP 50 38 32 26 Power I/O port supply VSSP 1 - - - Power I/O port ground VSSP 49 37 31 25 Power I/O port ground VSSP Exp. Exp. Pad Pad (in VQFN 64 only) Exp. Pad - Power Exposed Die Pad The exposed die pad is connected internally to VSSP. For proper operation, it is mandatory to connect the exposed pad to the board ground. For thermal aspects, please refer to the Package and Reliability chapter. Data Sheet 28 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family General Device Information 2.2.2 Port Pin for Boot Modes Port functions can be overruled by the boot mode selected. The type of boot mode is selected via BMI. Table 6 shows the port pins used for the various boot modes. Table 6 Pin Port Pin for Boot Modes Boot Boot Description P0.13 CS(O) SSC BSL mode P0.14 SWDIO_0 Debug mode (SWD) SPD_0 Debug mode (SPD) RX/TX ASC BSL half-duplex mode RX ASC BSL full-duplex mode P0.15 P1.2 RX CAN BSL mode SCLK(O) SSC BSL mode SWDCLK_0 Debug mode (SWD) TX ASC BSL full-duplex mode TX CAN BSL mode DATA(I/O) SSC BSL mode SWDCLK_1 Debug mode (SWD) TX ASC BSL full-duplex mode TX CAN BSL mode SWDIO_1 Debug mode (SWD) SPD_1 Debug mode (SPD) RX/TX ASC BSL half-duplex mode RX ASC BSL full-duplex mode RX CAN BSL mode P4.6 HWCON0 P4.7 HWCON1 Boot Pins (Boot from pins mode must be selected) P1.3 Data Sheet 29 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family General Device Information 2.2.3 Port I/O Function Description The following general building block is used to describe the I/O functions of each PORT pin: Table 7 Function Port I/O Function Description Outputs Inputs ALT1 P0.0 Pn.y ALTn Input MODA.OUT MODC.INA MODA.OUT Input MODA.INA MODC.INB Pn.y XMC1000 Control Logic PAD Input 0 MODA.INA MODA MODB MODB.OUT Input n HWI0 HWI1 SW Pn.y ALT1 ... ALTn HWO0 HWO1 Figure 10 VDDP ... GND Simplified Port Structure Pn.y is the port pin name, defining the control and data bits/registers associated with it. As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT defines the output value. Up to nine alternate output functions (ALT1 to ALT9) can be mapped to a single port pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective module, with the pin characteristics controlled by the port registers (within the limits of the connected pad). The port pin input can be connected to multiple peripherals. Most peripherals have an input multiplexer to select between different possible input sources. The input path is also active while the pin is configured as output. This allows to feedback an output to on-chip resources without wasting an additional external pin. Please refer to the Port I/O Functions table for the complete Port I/O function mapping. Data Sheet 30 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family General Device Information 2.2.4 Hardware Controlled I/O Function Description The following general building block is used to describe the hardware I/O and pull control functions of each PORT pin: Table 8 Hardware Controlled I/O Function Description Function Outputs Inputs Pull Control P0.0 HWO0 HWI0 HW0_PD HW0_PU MODB.OUT MODB.INA MODC.OUT MODC.OUT Pn.y By Pn_HWSEL, it is possible to select between different hardware "masters" (HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s). Hardware control overrules settings in the respective port pin registers. Additional hardware signals HW0_PD/HW1_PD and HW0_PU/HW1_PU controlled by the peripherals can be used to control the pull devices of the pin. Please refer to the Hardware Controlled I/O Functions table for the complete hardware I/O and pull control function mapping. Data Sheet 31 V1.2, 2016-08 Subject to Agreement on the Use of Product Information Data Sheet Port I/O Function Table Table 9 Port I/O Functions Function Outputs ALT1 ALT2 ALT3 ALT4 ALT5 Inputs ALT6 ALT7 ALT8 ALT9 Input Input Input Input Input Input Input Input Input Input Input 32 ERU0.P LEDTS0 ERU0.G CCU40. CCU80. USIC0_ USIC0_ CCU81. USIC1_ BCCU0. CCU40.I DOUT0 .LINE7 OUT0 OUT0 OUT00 CH0.SE CH1.SE OUT00 CH1.DO TRAPIN N0AC LO0 LO0 UT0 B USIC1_ USIC0_ CH1.DX CH0.D 0A X2A P0.1 ERU0.P LEDTS0 ERU0.G CCU40. CCU80. BCCU0. SCU.VD USIC1_ USIC1_ DOUT1 .LINE6 OUT1 OUT1 OUT01 OUT8 ROP CH1.SC CH1.DO LKOUT UT0 CCU40.I N1AC USIC1_ USIC1_ CH1.DX CH1.D 0B X1A P0.2 ERU0.P LEDTS0 ERU0.G CCU40. CCU80. VADC0. CCU80. USIC1_ USIC1_ DOUT2 .LINE5 OUT2 OUT2 OUT02 EMUX02 OUT10 CH0.SC CH0.DO LKOUT UT0 CCU40.I N2AC USIC1_ USIC1_ CH0.DX CH0.D 0A X1A P0.3 ERU0.P LEDTS0 ERU0.G CCU40. CCU80. VADC0. CCU80. USIC1_ USIC1_ OUT3 OUT03 EMUX01 OUT11 CH1.SC CH0.DO DOUT3 .LINE4 OUT3 LKOUT UT0 CCU40.I N3AC USIC1_ CH0.DX 0B P0.4 BCCU0. LEDTS0 LEDTS0 CCU40. CCU80. VADC0. WWDT. USIC1_ CAN.N0 OUT0 .LINE3 .COL3 OUT1 OUT13 EMUX00 SERVIC CH1.SE _TXD E_OUT LO0 CCU41.I CCU80.I N0AB N0AB CAN.N0 _RXDA P0.5 BCCU0. LEDTS0 LEDTS0 CCU40. CCU80. ACMP2. CCU80. VADC0. CAN.N0 OUT1 .LINE2 .COL2 OUT0 OUT12 OUT OUT01 EMUX10 _TXD CCU41.I CCU80.I N1AB N1AB CAN.N0 _RXDB P0.6 BCCU0. LEDTS0 LEDTS0 CCU40. CCU80. USIC0_ USIC0_ VADC0. CCU41. OUT2 .LINE1 .COL1 OUT0 OUT11 CH1.MC CH1.DO EMUX11 OUT0 LKOUT UT0 CCU40.I CCU41.I N0AB N2AB USIC0_ CH1.DX 0C P0.7 BCCU0. LEDTS0 LEDTS0 CCU40. CCU80. USIC0_ USIC0_ VADC0. CCU41. .LINE0 .COL0 OUT1 OUT10 CH0.SC CH1.DO EMUX12 OUT1 OUT3 LKOUT UT0 CCU40.I CCU41.I N1AB N3AB USIC0_ USIC0_ USIC0_ CH0.D CH1.DX CH1.DX X1C 0D 1C P0.8/ RTC_XTAL1 BCCU0. LEDTS1 LEDTS0 CCU40. CCU80. USIC0_ USIC0_ CCU81. CCU41. OUT4 .LINE0 .COLA OUT2 OUT20 CH0.SC CH1.SC OUT20 OUT2 LKOUT LKOUT CCU40.I N2AB USIC0_ CH0.D X1B USIC0_ CH1.DX 1B P0.9/ RTC_XTAL2 BCCU0. LEDTS1 LEDTS0 CCU40. CCU80. USIC0_ USIC0_ CCU81. CCU41. OUT5 .LINE1 .COL6 OUT3 OUT21 CH0.SE CH1.SE OUT21 OUT3 LO0 LO0 CCU40.I N3AB USIC0_ CH0.D X2B USIC0_ CH1.DX 2B P0.10/ XTAL1 BCCU0. LEDTS1 LEDTS0 ACMP0. CCU80. USIC0_ USIC0_ CCU81. OUT22 CH0.SE CH1.SE OUT22 OUT6 .LINE2 .COL5 OUT LO1 LO1 USIC0_ CH0.D X2C USIC0_ CH1.DX 2C P0.11/ XTAL2 BCCU0. LEDTS1 LEDTS0 USIC0_ CCU80. USIC0_ USIC0_ CCU81. OUT7 .LINE3 .COL4 CH0.MC OUT23 CH0.SE CH1.SE OUT23 LKOUT LO2 LO2 USIC0_ CH0.D X2D USIC0_ CH1.DX 2D P0.12 BCCU0. LEDTS1 LEDTS0 LEDTS1 CCU80. USIC0_ CCU80. OUT6 .LINE4 .COL3 .COL3 OUT33 CH0.SE OUT20 LO3 CCU80.I CCU81.I N2AB N2AB Input USIC0_ CH1.DX 2A CAN.N1 BCCU0. CCU40.I CCU40.I CCU40.I CCU81.I CCU40.I CCU80.I USIC0_ CCU80.I CCU80.I CAN.N1 CCU80.I _TXD TRAPIN N0AA N1AA N2AA N0AU N3AA N0AA CH0.D N1AA N2AA _RXDA N3AA A X2E XMCTM1400 AA-Step XMCTM1000 Family V1.2, 2016-08 Subject to Agreement on the Use of Product Information P0.0 Data Sheet Table 9 Port I/O Functions Function (cont'd) Outputs ALT1 ALT2 ALT3 ALT4 ALT5 Inputs ALT6 ALT7 ALT8 ALT9 Input Input Input Input Input Input Input CCU80.I CCU81.I POSIF0. N3AB N1AU IN0B Input Input Input USIC0_ CH0.D X2F Input 33 WWDT. LEDTS1 LEDTS0 LEDTS1 CCU80. USIC0_ CCU80. SERVIC .LINE5 .COL2 .COL2 OUT32 CH0.SE OUT21 E_OUT LO4 CAN.N1 _TXD P0.14 BCCU0. LEDTS1 LEDTS0 LEDTS1 CCU80. USIC0_ USIC0_ OUT7 .LINE6 .COL1 .COL1 OUT31 CH0.DO CH0.SC UT0 LKOUT CAN.N0 _TXD CCU81.I POSIF0. USIC0_ USIC0_ USIC1_ N2AU IN1B CH0.DX CH0.D CH1.DX 0A X1A 5B P0.15 BCCU0. LEDTS1 LEDTS0 LEDTS1 CCU80. USIC0_ USIC0_ OUT8 .LINE7 .COL0 .COL0 OUT30 CH0.DO CH1.MC UT0 LKOUT CAN.N0 _TXD CCU81.I POSIF0. USIC0_ N3AU IN2B CH0.DX 0B USIC1_ USIC1_ CAN.N0 CH1.DX CH1.DX _RXDD 3B 4B P1.0 BCCU0. CCU40. LEDTS0 LEDTS1 CCU80. ACMP1. USIC0_ CCU81. CAN.N0 OUT0 OUT0 .COL0 .COLA OUT00 OUT CH0.DO OUT00 _TXD UT0 POSIF0. USIC0_ IN2A CH0.DX 0C CAN.N0 _RXDG P1.1 ERU1.P CCU40. LEDTS0 LEDTS1 CCU80. USIC0_ USIC0_ CCU81. CAN.N0 DOUT1 OUT1 .COL1 .COL0 OUT01 CH0.DO CH1.SE OUT01 _TXD UT0 LO0 POSIF0. USIC0_ USIC0_ IN1A CH0.DX CH0.D 0D X1D P1.2 ERU1.P CCU40. LEDTS0 LEDTS1 CCU80. ACMP2. USIC0_ CCU81. CAN.N1 DOUT2 OUT2 .COL2 .COL1 OUT10 OUT CH1.DO OUT10 _TXD UT0 POSIF0. IN0A P1.3 ERU1.P CCU40. LEDTS0 LEDTS1 CCU80. USIC0_ USIC0_ CCU81. CAN.N1 DOUT3 OUT3 .COL3 .COL2 OUT11 CH1.SC CH1.DO OUT11 _TXD LKOUT UT0 P1.4 ERU1.P USIC0_ LEDTS0 LEDTS1 CCU80. USIC0_ USIC0_ CCU81. CCU41. DOUT0 CH1.SC .COL4 .COL3 OUT20 CH0.SE CH1.SE OUT20 OUT0 LKOUT LO0 LO1 P1.5 ERU1.P USIC0_ LEDTS0 BCCU0. CCU80. USIC0_ USIC0_ CCU81. CCU41. DOUT1 CH0.DO .COLA OUT1 OUT21 CH0.SE CH1.SE OUT21 OUT1 UT0 LO1 LO2 P1.6 ERU1.P USIC0_ LEDTS0 USIC0_ BCCU0. USIC0_ USIC0_ CCU81. CCU41. DOUT2 CH1.DO .COL5 CH0.SC OUT2 CH0.SE CH1.SE OUT30 OUT2 UT0 LKOUT LO2 LO3 POSIF1. USIC0_ IN2A CH0.DX 5F P1.7 BCCU0. CCU40. LEDTS0 LEDTS1 OUT8 OUT3 .COL6 .COL4 ACMP3. ERU1.P CCU81. CCU41. OUT DOUT3 OUT31 OUT3 POSIF1. USIC1_ IN1A CH0.DX 5B USIC1_ CH1.DX 2C P1.8 BCCU0. CCU40. USIC1_ VADC0. OUT0 OUT0 CH1.SC EMUX02 LKOUT ACMP1. ERU1.P CCU81. OUT DOUT0 OUT32 POSIF1. USIC1_ USIC1_ IN0A CH0.DX CH0.D 3B X4B USIC1_ CH1.DX 1C P2.0 ERU0.P CCU40. ERU0.G LEDTS1 CCU80. USIC0_ USIC0_ CCU81. CAN.N0 DOUT3 OUT0 OUT3 .COL5 OUT20 CH0.DO CH0.SC OUT20 _TXD UT0 LKOUT P2.1 ERU0.P CCU40. ERU0.G LEDTS1 CCU80. USIC0_ USIC0_ CCU81. CAN.N0 ACMP2.I VADC0. DOUT2 OUT1 OUT2 .COL6 OUT21 CH0.DO CH1.SC OUT21 _TXD NP G0CH6 UT0 LKOUT Input CAN.N1 _RXDB CAN.N0 _RXDC USIC0_ CAN.N0 CH1.DX _RXDH 2E USIC0_ CH1.DX 0B CAN.N1 _RXDG USIC0_ USIC0_ CAN.N1 CH1.DX CH1.DX _RXDH 0A 1A USIC0_ CH0.DX 5E USIC0_ CH1.DX 5E USIC0_ CH1.DX 5F VADC0. G0CH5 USIC0_ USIC0_ CH0.DX CH0.D 0E X1E USIC0_ CH0.DX 0F USIC0_ CAN.N0 ERU0.0 CH1.DX _RXDE B0 2F USIC0_ USIC0_ CAN.N0 ERU0.1 CH1.DX CH1.DX _RXDF B0 3A 4A XMCTM1400 AA-Step XMCTM1000 Family V1.2, 2016-08 Subject to Agreement on the Use of Product Information P0.13 Data Sheet Table 9 Port I/O Functions Function (cont'd) Outputs ALT1 ALT2 ALT3 ALT4 ALT5 Inputs ALT6 ALT7 ALT8 ALT9 P2.2 Input Input Input ACMP2.I VADC0. NN G0CH7 Input Input ORC0.AI USIC1_ N CH0.DX 5E Input Input Input Input Input USIC0_ USIC0_ USIC0_ CH0.DX CH0.D CH1.DX 3A X4A 5A Input Input ERU0.0 B1 P2.3 VADC0. ORC1.AI USIC1_ USIC1_ USIC1_ USIC0_ USIC0_ USIC0_ G1CH5 N CH0.DX CH0.DX CH1.DX CH0.D CH1.DX CH1.DX 3E 4E 5C X5B 3C 4C ERU0.1 B1 P2.4 VADC0. ORC2.AI USIC1_ USIC1_ USIC0_ USIC0_ USIC1_ USIC0_ G1CH6 N CH1.DX CH1.DX CH0.DX CH0.D CH0.DX CH1.DX 3C 4C 3B X4B 5F 5B ERU0.0 A1 P2.5 VADC0. ORC3.AI USIC1_ G1CH7 N CH1.DX 5D ERU0.1 A1 USIC0_ CH0.DX 5D USIC0_ USIC0_ CH1.DX CH1.DX 3E 4E 34 ACMP1.I VADC0. NN G0CH0 ORC4.AI USIC1_ USIC1_ USIC0_ USIC0_ USIC0_ N CH1.DX CH1.DX CH0.DX CH0.D CH1.DX 3E 4E 3E X4E 5D P2.7 ACMP1.I NP P2.8 ACMP0.I VADC0. VADC0. ORC6.AI NN G0CH1 G1CH0 N USIC0_ USIC0_ USIC0_ CH0.DX CH0.D CH1.DX 3D X4D 5C ERU0.3 B1 P2.9 ACMP0.I VADC0. VADC0. ORC7.AI NP G0CH2 G1CH4 N USIC0_ CH0.DX 5A ERU0.3 B0 VADC0. ORC5.AI USIC1_ CH1.DX G1CH1 N 5E USIC0_ USIC0_ CH1.DX CH1.DX 3D 4D USIC0_ USIC0_ CH1.DX CH1.DX 3B 4B ERU0.P CCU40. ERU0.G LEDTS1 CCU80. ACMP0. USIC0_ DOUT1 OUT2 OUT1 .COL4 OUT30 OUT CH1.DO UT0 CAN.N1 _TXD P2.11 ERU0.P CCU40. ERU0.G LEDTS1 CCU80. USIC0_ USIC0_ DOUT0 OUT3 OUT0 .COL3 OUT31 CH1.SC CH1.DO LKOUT UT0 CAN.N1 ACMP.R VADC0. VADC0. _TXD EF G0CH4 G1CH3 P2.12 BCCU0. VADC0. USIC1_ USIC1_ OUT3 EMUX00 CH0.SC CH1.SC LKOUT LKOUT ACMP2. USIC1_ LEDTS2 OUT CH1.DO .COL6 UT0 P2.13 BCCU0. CCU40. USIC1_ CCU81. OUT4 OUT3 CH0.MC OUT31 LKOUT VADC0. USIC1_ CCU81. CCU41. ACMP3.I EMUX01 CH1.DO OUT33 OUT3 NP UT0 P3.0 BCCU0. USIC1_ USIC1_ LEDTS2 CCU80. ACMP1. USIC1_ CCU81. CCU41. BCCU0. CCU41.I CCU41.I CCU41.I CCU41.I CCU81.I CCU81.I CCU81. USIC1_ USIC1_ CCU81.I ERU1.0 CH0.SE OUT21 OUT0 TRAPIN N0AA N1AA N2AA N3AA N0AA N1AA IN2AA CH1.DX CH1.DX N3AA A1 OUT0 CH1.DO CH1.SC .COLA OUT21 OUT LO1 C 0E 1D UT0 LKOUT P3.1 BCCU0. USIC1_ OUT1 CH1.DO UT0 ACMP3.I NN USIC0_ USIC0_ USIC0_ CH0.DX CH0.D CH1.DX 3C X4C 0F ERU0.3 A1 P2.10 LEDTS2 CCU80. ACMP3. USIC1_ CCU81. CCU41. .COL0 OUT20 OUT CH0.SE OUT20 OUT1 LO0 VADC0. VADC0. G0CH3 G1CH2 USIC0_ CH0.DX 5C ERU0.2 A1 CAN.N1 ERU0.2 _RXDE B0 USIC0_ USIC0_ CAN.N1 ERU0.2 CH1.DX CH1.DX _RXDF B1 0E 1E USIC1_ USIC1_ USIC1_ USIC1_ CH0.DX CH0.D CH1.DX CH1.DX 3A X4A 0C 1B ERU1.3 A2 USIC1_ CH0.DX 5A ERU1.3 A3 USIC1_ CH1.DX 0D USIC1_ USIC1_ CH0.D CH1.DX X2F 0F ERU1.1 A1 XMCTM1400 AA-Step XMCTM1000 Family V1.2, 2016-08 Subject to Agreement on the Use of Product Information P2.6 Data Sheet Table 9 Port I/O Functions Function (cont'd) Outputs ALT1 ALT2 ALT3 ALT4 ALT5 Inputs ALT6 ALT7 ALT8 ALT9 Input Input Input Input Input Input Input Input Input Input Input Input 35 BCCU0. USIC1_ OUT2 CH1.SC LKOUT LEDTS2 CCU80. ACMP2. USIC1_ CCU81. CCU41. .COL1 OUT11 OUT CH0.SC OUT11 OUT2 LKOUT USIC1_ USIC1_ USIC1_ USIC1_ CH0.DX CH0.D CH1.DX CH1.DX 3C X4C 3D 4D ERU1.2 A1 P3.3 BCCU0. USIC1_ OUT5 CH0.DO UT0 LEDTS2 CCU80. ACMP0. USIC1_ CCU81. CCU41. .COL2 OUT10 OUT CH1.SE OUT10 OUT3 LO0 USIC1_ CH0.DX 0E USIC1_ CH1.DX 2A ERU1.1 A3 P3.4 BCCU0. USIC1_ USIC1_ LEDTS2 CCU80. USIC1_ USIC1_ CCU81. OUT6 CH0.DO CH0.SC .COL3 OUT01 CH1.MC CH1.SE OUT01 UT0 LKOUT LKOUT LO1 USIC1_ USIC1_ CH0.DX CH0.D 0F X1E USIC1_ CH1.DX 2B ERU1.2 A3 P4.0 BCCU0. ERU1.P LEDTS2 ERU1.G CCU40. ACMP1. USIC1_ CCU81. CCU41. OUT0 DOUT0 .COL5 OUT0 OUT0 OUT CH1.SE OUT10 OUT0 LO1 CCU40.I CCU41.I CCU80.I N0BA N0AC N0AU P4.1 BCCU0. ERU1.P LEDTS2 ERU1.G CCU40. ACMP3. USIC1_ CCU81. CCU41. OUT8 DOUT1 .COL4 OUT1 OUT1 OUT CH1.SE OUT11 OUT1 LO2 CCU40.I CCU41.I CCU80.I N1BA N1AC N1AU P4.2 BCCU0. ERU1.P CCU81. ERU1.G CCU40. ACMP2. USIC1_ CCU81. CCU41. OUT4 DOUT2 OUT20 OUT2 OUT2 OUT CH1.SE OUT12 OUT2 LO3 CCU40.I CCU41.I CCU80.I CCU81.I POSIF1. USIC1_ N2BA N2AC N2AU N1AB IN1B CH0.DX 5D P4.3 BCCU0. ERU1.P CCU81. ERU1.G CCU40. ACMP0. USIC1_ CCU81. CCU41. OUT5 DOUT3 OUT21 OUT3 OUT3 OUT CH0.SC OUT13 OUT3 LKOUT CCU40.I CCU41.I CCU80.I N3BA N3AC N3AU P4.4 BCCU0. LEDTS2 .LINE0 OUT0 LEDTS1 CCU80. USIC1_ .COLA OUT00 CH0.DO UT0 CCU81. CCU41. OUT00 OUT0 CCU41.I N0AV USIC1_ CH0.DX 0C P4.5 BCCU0. LEDTS2 OUT8 .LINE1 LEDTS1 CCU80. USIC1_ USIC1_ CCU81. CCU41. .COL6 OUT01 CH0.DO CH0.SC OUT01 OUT1 UT0 LKOUT CCU41.I N1AV USIC1_ USIC1_ CH0.DX CH0.D 0D X1C ERU1.1 A2 P4.6 BCCU0. LEDTS2 CCU81. LEDTS1 CCU80. OUT2 .LINE2 OUT10 .COL5 OUT10 USIC1_ CCU81. CCU41. CH0.SC OUT02 OUT2 LKOUT CCU41.I N2AV USIC1_ CH0.D X1D ERU1.2 A2 P4.7 BCCU0. LEDTS2 CCU81. LEDTS1 CCU80. OUT5 .LINE3 OUT11 .COL4 OUT11 USIC1_ CCU81. CCU41. CH0.SE OUT03 OUT3 LO0 CCU41.I N3AV USIC1_ CH0.D X2A ERU1.0 A3 P4.8 BCCU0. LEDTS2 LEDTS2 LEDTS1 CCU80. CCU40. USIC1_ CCU81. CAN.N1 OUT7 .LINE4 .COL3 .COL3 OUT30 OUT0 CH0.SE OUT30 _TXD LO1 CCU40.I CCU41.I N0AV N0BA USIC1_ CH0.D X2B CAN.N1 _RXDC P4.9 BCCU0. LEDTS2 LEDTS2 LEDTS1 CCU80. CCU40. USIC1_ CCU81. CAN.N1 OUT3 .LINE5 .COL2 .COL2 OUT31 OUT1 CH0.SE OUT31 _TXD LO2 CCU40.I CCU41.I N1AV N1BA USIC1_ CH0.D X2C CAN.N1 _RXDD USIC1_ USIC1_ CH0.DX CH0.D 3D X4D POSIF1. USIC1_ IN0B CH0.DX 5C POSIF1. IN2B CCU81.I N0AB USIC1_ CH0.D X1B USIC1_ CH1.DX 5F ERU1.0 A2 XMCTM1400 AA-Step XMCTM1000 Family V1.2, 2016-08 Subject to Agreement on the Use of Product Information P3.2 Data Sheet Table 9 Port I/O Functions Function (cont'd) Outputs ALT1 ALT2 ALT3 ALT4 ALT5 Inputs ALT6 ALT7 ALT8 ALT9 Input Input Input P4.10 LEDTS2 LEDTS2 LEDTS1 CCU80. CCU40. USIC1_ CCU81. CCU81. BCCU0. CCU40.I CCU41.I .LINE6 .COL1 .COL1 OUT00 OUT2 CH0.SE OUT32 OUT00 TRAPIN N2AV N2BA LO3 D P4.11 LEDTS2 LEDTS2 LEDTS1 CCU80. CCU40. USIC1_ CCU81. CCU81. .LINE7 .COL0 .COL0 OUT01 OUT3 CH0.SE OUT33 OUT01 LO4 CCU40.I CCU41.I N3AV N3BA Input Input CCU81.I N3AB Input Input Input Input Input Input Input USIC1_ USIC1_ CH0.D CH1.DX X2D 5A USIC1_ USIC1_ USIC1_ CH0.D CH1.DX CH1.DX X2E 3A 4A 36 XMCTM1400 AA-Step XMCTM1000 Family V1.2, 2016-08 Subject to Agreement on the Use of Product Information Data Sheet Table 10 Function Hardware I/O Controlled Functions Outputs Outputs Inputs Inputs Pull Control Pull Control Pull Control Pull Control HWO0 HWO1 HWI0 HWI1 HW0_PD HW0_PU HW1_PD HW1_PU Reserved for LEDTS Scheme A: pull-down disabled always Reserved for LEDTS Scheme A: pull-down enabled always Reserved for LEDTS Scheme B: pull-up enabled and pull-down disabled, and vice versa LEDTS0.TSIN7 LEDTS0.TSIN7 P0.1 LEDTS0. EXTENDED6 LEDTS0.TSIN6 LEDTS0.TSIN6 P0.2 LEDTS0. EXTENDED5 LEDTS0.TSIN5 LEDTS0.TSIN5 P0.3 LEDTS0. EXTENDED4 LEDTS0.TSIN4 LEDTS0.TSIN4 P0.4 LEDTS0. EXTENDED3 LEDTS0.TSIN3 LEDTS0.TSIN3 P0.5 LEDTS0. EXTENDED2 LEDTS0.TSIN2 LEDTS0.TSIN2 P0.6 LEDTS0. EXTENDED1 LEDTS0.TSIN1 LEDTS0.TSIN1 P0.7 LEDTS0. EXTENDED0 LEDTS0.TSIN0 LEDTS0.TSIN0 P0.8 LEDTS1. EXTENDED0 LEDTS1.TSIN0 LEDTS1.TSIN0 P0.9 LEDTS1. EXTENDED1 LEDTS1.TSIN1 LEDTS1.TSIN1 P0.10 LEDTS1. EXTENDED2 LEDTS1.TSIN2 LEDTS1.TSIN2 P0.11 LEDTS1. EXTENDED3 LEDTS1.TSIN3 LEDTS1.TSIN3 P0.12 LEDTS1. EXTENDED4 LEDTS1.TSIN4 LEDTS1.TSIN4 P0.13 LEDTS1. EXTENDED5 LEDTS1.TSIN5 LEDTS1.TSIN5 P0.14 LEDTS1. EXTENDED6 LEDTS1.TSIN6 LEDTS1.TSIN6 P0.15 LEDTS1. EXTENDED7 LEDTS1.TSIN7 LEDTS1.TSIN7 V1.2, 2016-08 Subject to Agreement on the Use of Product Information P1.0 USIC0_CH0.DOUT0 USIC0_CH0.HWIN0 BCCU0.OUT2 BCCU0.OUT2 P1.1 USIC0_CH0.DOUT1 USIC0_CH0.HWIN1 BCCU0.OUT3 BCCU0.OUT3 P1.2 USIC0_CH0.DOUT2 USIC0_CH0.HWIN2 BCCU0.OUT4 BCCU0.OUT4 XMCTM1400 AA-Step XMCTM1000 Family LEDTS0. EXTENDED7 37 P0.0 Data Sheet Table 10 Hardware I/O Controlled Functions Outputs Outputs Inputs Inputs Pull Control Pull Control Pull Control Pull Control HWO0 HWO1 HWI0 HWI1 HW0_PD HW0_PU HW1_PD HW1_PU USIC0_CH0.HWIN3 BCCU0.OUT5 BCCU0.OUT5 P1.4 BCCU0.OUT6 BCCU0.OUT6 P1.5 BCCU0.OUT7 BCCU0.OUT7 P1.6 BCCU0.OUT8 BCCU0.OUT8 P2.0 BCCU0.OUT1 BCCU0.OUT1 P2.1 BCCU0.OUT6 BCCU0.OUT6 P2.2 BCCU0.OUT0 BCCU0.OUT0 CCU40.OUT3 CCU40.OUT3 P2.3 ACMP2.OUT ACMP2.OUT P2.4 BCCU0.OUT8 BCCU0.OUT8 P2.5 ACMP1.OUT ACMP1.OUT P2.6 BCCU0.OUT2 BCCU0.OUT2 CCU40.OUT3 CCU40.OUT3 P2.7 BCCU0.OUT8 BCCU0.OUT8 CCU40.OUT3 CCU40.OUT3 P2.8 BCCU0.OUT1 BCCU0.OUT1 CCU40.OUT2 CCU40.OUT2 P2.9 BCCU0.OUT7 BCCU0.OUT7 CCU40.OUT2 CCU40.OUT2 P2.10 BCCU0.OUT4 BCCU0.OUT4 P2.11 BCCU0.OUT5 BCCU0.OUT5 P2.12 BCCU0.OUT3 BCCU0.OUT3 CCU41.OUT0 CCU41.OUT0 P2.13 BCCU0.OUT4 BCCU0.OUT4 CCU41.OUT2 CCU41.OUT2 Function P1.3 USIC0_CH0.DOUT3 P1.7 P1.8 38 P3.1 USIC1_CH0.DOUT3 USIC1_CH0.HWIN3 P3.2 USIC1_CH0.DOUT2 USIC1_CH0.HWIN2 P3.3 USIC1_CH0.DOUT1 USIC1_CH0.HWIN1 P3.4 USIC1_CH0.DOUT0 USIC1_CH0.HWIN0 P4.0 P4.1 P4.2 P4.3 XMCTM1400 AA-Step XMCTM1000 Family V1.2, 2016-08 Subject to Agreement on the Use of Product Information P3.0 Data Sheet Table 10 Function Hardware I/O Controlled Functions Outputs Outputs Inputs Inputs Pull Control Pull Control Pull Control Pull Control HWO0 HWO1 HWI0 HWI1 HW0_PD HW0_PU HW1_PD HW1_PU Reserved for LEDTS Scheme A: pull-down disabled always Reserved for LEDTS Scheme A: pull-down enabled always Reserved for LEDTS Scheme B: pull-up enabled and pull-down disabled, and vice versa P4.4 LEDTS2. EXTENDED0 LEDTS2.TSIN0 LEDTS2.TSIN0 P4.5 LEDTS2. EXTENDED1 LEDTS2.TSIN1 LEDTS2.TSIN1 P4.6 LEDTS2. EXTENDED2 LEDTS2.TSIN2 LEDTS2.TSIN2 P4.7 LEDTS2. EXTENDED3 LEDTS2.TSIN3 LEDTS2.TSIN3 P4.8 LEDTS2. EXTENDED4 LEDTS2.TSIN4 LEDTS2.TSIN4 P4.9 LEDTS2. EXTENDED5 LEDTS2.TSIN5 LEDTS2.TSIN5 P4.10 LEDTS2. EXTENDED6 LEDTS2.TSIN6 LEDTS2.TSIN6 P4.11 LEDTS2. EXTENDED7 LEDTS2.TSIN7 LEDTS2.TSIN7 39 XMCTM1400 AA-Step XMCTM1000 Family V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3 Electrical Parameter This section provides the electrical parameter which are implementation-specific for the XMC1400. 3.1 General Parameters 3.1.1 Parameter Interpretation The parameters listed in this section represent partly the characteristics of the XMC1400 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the "Symbol" column: * * CC Such parameters indicate Controller Characteristics, which are distinctive feature of the XMC1400 and must be regarded for a system design. SR Such parameters indicate System Requirements, which must be provided by the application system in which the XMC1400 is designed in. Data Sheet 40 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.1.2 Absolute Maximum Ratings Stresses above the values listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 11 Absolute Maximum Rating Parameters Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition TJ SR -40 - TST SR -40 - VDDP SR -0.3 - 115 C - 125 C - 6 V - Voltage on any pin with respect to VSSP VIN VDDP + V whichever is lower Voltage on any analog input pin with respect to VAIN V whichever is lower Junction temperature Storage temperature Voltage on power supply pin with respect to VSSP SR -0.5 - 0.5 or max. 6 SR -0.5 - VDDP + 0.5 or max. 6 VSSP Input current on any pin during overload condition IIN SR -10 - 10 mA - Absolute sum of all input currents during overload condition |IIN| SR -50 - 50 mA - Analog comparator input voltage VCM -0.3 - VDDP + V Data Sheet SR 0.3 41 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.1.3 Pin Reliability in Overload When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification. Table 12 defines overload conditions that will not cause any negative reliability impact if all the following conditions are met: * * full operation life-time is not exceeded Operating Conditions are met for - pad supply levels (VDDP) - temperature If a pin current is outside of the Operating Conditions but within the overload conditions, then the parameters of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters. Note: An overload condition on one or more pins does not require a reset. Note: A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery. Table 12 Overload Parameters Parameter Symbol Values Min. Typ. Unit Note / Test Condition Max. -5 - 5 mA - 25 mA Input current on any port pin during overload condition IOV SR Absolute sum of all input circuit currents during overload condition IOVS SR - Figure 11 shows the path of the input currents during overload via the ESD protection structures. The diodes against VDDP and ground are a simplified representation of these ESD protection structures. Data Sheet 42 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter VDDP VDDP Pn.y IOVx GND ESD Figure 11 GND Pad Input Overload Current via ESD structures Table 13 and Table 14 list input voltages that can be reached under overload conditions. Note that the absolute maximum input voltages as defined in the Absolute Maximum Ratings must not be exceeded during overload. Table 13 Pad Type Standard, High-current, AN/DIG_IN Table 14 Pad Type Standard, High-current, AN/DIG_IN Data Sheet PN-Junction Characterisitics for positive Overload IOV = 5 mA, TJ = -40 C VIN = VDDP + 0.5 V IOV = 5 mA, TJ = 115 C VIN = VDDP + 0.5 V PN-Junction Characterisitics for negative Overload IOV = 5 mA, TJ = -40 C VIN = VSS - 0.5 V IOV = 5 mA, TJ = 115 C VIN = VSS - 0.5 V 43 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.1.4 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the XMC1400. All parameters specified in the following tables refer to these operating conditions, unless noted otherwise. Table 15 Operating Conditions Parameters Parameter Symbol Values Unit Note / Test Condition 85 C Temp. Range F Temp. Range X Min. Typ. Max. -40 - -40 Ambient Temperature TA SR - 105 C Digital supply voltage1) VDDP SR ISC SR 1.8 - 5.5 V -5 - 5 mA ISC_D SR - - 25 mA Short circuit current of digital outputs Absolute sum of short circuit currents of the device 1) See also the Supply Monitoring thresholds, Chapter 3.3.2. Data Sheet 44 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.2 DC Parameters 3.2.1 Input/Output Characteristics Table 16 provides the characteristics of the input/output pins of the XMC1400. Note: These parameters are not subject to production test, but verified by design and/or characterization. Note: Unless otherwise stated, input DC and AC characteristics, including peripheral timings, assume that the input pads operate with the standard hysteresis. Table 16 Input/Output Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Min. Output low voltage on port pins (with standard pads) VOLP Output low voltage on high current pads VOLP1 Output high voltage on port pins (with standard pads) VOHP Unit Test Conditions V IOL = 11 mA (5 V) IOL = 7 mA (3.3 V) IOL = 5 mA (5 V) IOL = 3.5 mA (3.3 V) IOL = 50 mA (5 V) IOL = 25 mA (3.3 V) IOL = 10 mA (5 V) IOL = 5 mA (3.3 V) IOH = -10 mA (5 V) IOH = -7 mA (3.3 V) IOH = -4.5 mA (5 V) IOH = -2.5 mA (3.3 V) IOH = -6 mA (5 V) V IOH = -8 mA (3.3 V) V IOH = -4 mA (3.3 V) 0.19 x V CMOS Mode (5 V, 3.3 V & 2.2 V) Max. CC - 1.0 V - 0.4 V CC - 1.0 V - 0.32 V - 0.4 V - V VDDP - - V CC VDDP 1.0 0.4 Output high voltage on high current pads VOHP1 CC VDDP - - 0.32 VDDP - - 1.0 VDDP - - 0.4 Input low voltage on port VILPS pins (Standard Hysteresis) SR VIHPS SR Input high voltage on port pins (Standard Hysteresis) Data Sheet - VDDP 0.7 x VDDP 45 - V CMOS Mode (5 V, 3.3 V & 2.2 V) V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Table 16 Input/Output Characteristics (Operating Conditions apply) (cont'd) Parameter Symbol Limit Values Min. Input low voltage on port VILPL pins (Large Hysteresis) SR Input high voltage on port pins (Large Hysteresis) VIHPL SR Rise/fall time on High Current Pad1) tHCPR, CC - tHCPF - Rise/fall time on Standard Pad1) Unit 0.08 x V - VDDP 0.85 x - Input Hysteresis on port HYS pin except P2.3 - P2.98) CMOS Mode (5 V, 3.3 V & 2.2 V) 9 ns 50 pF @ 5 V2) 12 ns 50 pF @ 3.3 V3) - 25 ns 50 pF @ 1.8 V4) CC - 12 ns 50 pF @ 5 V5) - 15 ns 50 pF @ 3.3 V6). - 31 ns 50 pF @ 1.8 V7). V CMOS Mode (5 V), Standard Hysteresis V CMOS Mode (3.3 V), Standard Hysteresis V CMOS Mode (2.2 V), Standard Hysteresis CC 0.08 x - VDDP 0.03 x - VDDP 0.02 x - VDDP Data Sheet CMOS Mode (5 V, 3.3 V & 2.2 V) V VDDP tR , tF Test Conditions Max. 0.5 x 0.75 x V VDDP VDDP 0.4 x 0.75 x V VDDP VDDP 0.2 x 0.65 x V VDDP VDDP 46 CMOS Mode(5 V), Large Hysteresis CMOS Mode(3.3 V), Large Hysteresis CMOS Mode(2.2 V), Large Hysteresis V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Table 16 Input/Output Characteristics (Operating Conditions apply) (cont'd) Parameter Symbol Limit Values Min. Input Hysteresis on port HYS_ pin P2.3 - P2.98) P2 Unit Test Conditions V CMOS Mode (5 V), Standard Hysteresis V CMOS Mode (3.3 V), Standard Hysteresis V CMOS Mode (2.2 V), Standard Hysteresis Max. CC 0.08 x - VDDP 0.03 x - VDDP 0.02 x - VDDP 0.35 x 0.75 x V VDDP VDDP 0.25 x 0.75 x V VDDP VDDP 0.15 x 0.65 x V VDDP VDDP Pin capacitance (digital inputs/outputs) CIO CC - 10 pF Pull-up current on port pins IPUP CC - -80 A - A Pull-down current on port pins Input leakage current except P0.119) -95 IPDP IOZP Input leakage current for IOZP1 P0.119) - -50 A -65 - A 40 A CC - 95 - A - 30 A 60 - A CC -1 1 A CC -10 1 A CMOS Mode(5 V), Large Hysteresis CMOS Mode(3.3 V), Large Hysteresis CMOS Mode(2.2 V), Large Hysteresis VIH,min (5 V) VIL,max (5 V) VIH,min (3.3 V) VIL,max (3.3 V) VIL,max (5 V) VIH,min (5 V) VIL,max (3.3 V) VIH,min (3.3 V) 0 < VIN < VDDP, TA 105 C 0 < VIN < VDDP, TA 105 C Voltage on any pin during VDDP power off VPO SR - 0.3 V 10) Maximum current per pin (excluding P1, VDDP and VSS) IMP SR -10 11 mA - Maximum current per high currrent pins IMP1A SR -10 50 mA - Data Sheet 47 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Table 16 Input/Output Characteristics (Operating Conditions apply) (cont'd) Parameter Symbol Limit Values Min. Unit Test Conditions Max. Maximum current into VDDP (VQFN64, LQFP64) IMVDD1 SR - 520 mA Maximum current into IMVDD2 SR - 390 mA IMVDD3 SR - 260 mA - 390 mA - 260 mA - 260 mA VDDP (VQFN48) Maximum current into VDDP (VQFN40) Maximum current out of IMVSS1 SR VSS (VQFN64, LQFP64) Maximum current out of IMVSS2 SR VSS (VQFN48) Maximum current out of IMVSS3 SR VSS (VQFN40) 1) Rise/Fall time parameters are taken with 10% - 90% of supply. 2) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.150 ns/pF at 5 V supply voltage. 3) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.205 ns/pF at 3.3 V supply voltage. 4) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.445 ns/pF at 1.8 V supply voltage. 5) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.225 ns/pF at 5 V supply voltage. 6) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.288 ns/pF at 3.3 V supply voltage. 7) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.588 ns/pF at 1.8 V supply voltage. 8) Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. 9) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. 10) However, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin when VDDP is powered off. Data Sheet 48 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.2.2 Analog to Digital Converters (ADC) Table 17 shows the Analog to Digital Converter (ADC) characteristics. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 17 ADC Characteristics (Operating Conditions apply)1) Parameter Symbol Supply voltage range VDD_int (internal reference) SR Supply voltage range VDD_ext (external reference) SR Analog input voltage range VAIN SR Auxiliary analog reference ground2) Values Unit Note / Test Condition Min. Typ. Max. 2.0 - 3.0 V SHSCFG.AREF = 11B; CALCTR.CALGNSTC = 0CH for fSH = 32 MHz, 12H for fSH = 48 MHz 3.0 - 5.5 V SHSCFG.AREF = 10B 3.0 - 5.5 V SHSCFG.AREF = 00B V VSSP - VDDP - 0.05 + 0.05 VREFGND VSSP - 1.0 V G0CH0 SR - 0.05 0.2 V G1CH0 VSSP - - 0.05 Internal reference voltage (full scale value) Switched capacitance of an analog input VREFINT CAINS V - 1.2 2 pF GNCTRxz.GAINy = 00B (unity gain) - 1.2 2 pF GNCTRxz.GAINy = 01B (gain g1) - 4.5 6 pF GNCTRxz.GAINy = 10B (gain g2) - 4.5 6 pF GNCTRxz.GAINy = 11B (gain g3) - - 10 pF - - 10 pF CC Total capacitance of an analog input CAINT Total capacitance of the reference input CAREFT Data Sheet 5 CC CC CC 49 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Table 17 ADC Characteristics (Operating Conditions apply)1) (cont'd) Parameter Symbol Values Min. Gain settings Sample Time GIN CC tsample Unit Note / Test Condition Typ. Max. 1 - GNCTRxz.GAINy = 00B (unity gain) 3 - GNCTRxz.GAINy = 01B (gain g1) 6 - GNCTRxz.GAINy = 10B (gain g2) 12 - GNCTRxz.GAINy = 11B (gain g3) 5 - - 3 - - 3 - - 30 - - CC Conversion time in fast compare mode tCF CC Conversion time in 12-bit mode tC12 CC Maximum sample rate in 12-bit mode4) fC12 CC 9 VDD = 5.0 V, fADC fADCI = 48 MHz 1/ VDD = 5.0 V, fADC fADCI = 32 MHz 1/ VDD = 3.3 V, fADC fADCI = 32 MHz 1/ VDD = 2.0 V, fADC fADCI = 32 MHz 1/ 1/ fADC 20 1/ fADC / - - 1 sample pending - 2 samples pending 1/ 3) 42.5 fADC / - 62.5 Conversion time in 10-bit mode tC10 CC Maximum sample rate in 10-bit mode4) fC10 CC 18 fADC - fADC / - - 1 sample pending - 2 samples pending 1/ 3) 40.5 - fADC / - 58.5 Data Sheet 3) fADC - - Conversion time in 8-bit mode 3) tC8 CC 16 fADC 50 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Table 17 ADC Characteristics (Operating Conditions apply)1) (cont'd) Parameter Maximum sample rate in 8-bit mode4) Symbol fC8 CC Values Unit Note / Test Condition Min. Typ. Max. - - fADC / - 1 sample pending - 2 samples pending 38.5 - fADC / - 54.5 RMS noise5) ENRMS - 1.5 - - 2.0 - LSB 12 - 4.0 - LSB 12 - 0.5 - % SHSCFG.AREF = 00B (calibrated) - 3.6 - % SHSCFG.AREF = 1XB (calibrated), -40C - 110C - 2.0 - % SHSCFG.AREF = 1XB (calibrated), 0C - 85C - 8.0 - mV Calibrated, VDD = 5.0 V CC DNL error EADNL CC INL error EAINL CC EAGAIN Gain error with external reference CC Gain error with internal reference6) CC Offset error EAGAIN EAOFF LSB DC input, 12 SHSCFG.AREF = 00B, GNCTRxz.GAINy = 00B (unity gain), VDD = 5.0 V, VAIN = 2.5 V, 25C CC 1) The parameters are defined for ADC clock frequencies fSH = 32 MHz for the full supply range, and fSH = 48 MHz at VDD_int , VDD_ext = 5 V. Usage of any other frequencies may affect the ADC performance. 2) The alternate reference ground connection is separate for each converter. This mode, therefore, provides the lowest noise impact. 3) No pending samples assumed, excluding sampling time and calibration. 4) Includes synchronization and calibration (average of gain and offset calibration). 5) This parameter can also be defined as an SNR value: SNR[dB] = 20 x log(AMAXeff / NRMS). With AMAXeff = 2N / 2, SNR[dB] = 20 x log ( 2048 / NRMS) [N = 12]. NRMS = 1.5 LSB12, therefore, equals SNR = 20 x log (2048 / 1.5) = 62.7 dB. 6) Includes error from the reference voltage. Data Sheet 51 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter VAIN SAR Converter : 0 VSS 1X VCAL 00 1 VREFGND VDD VREF VAGND CH7 . . CH0 VREFINT VAREF Internal Reference VDDint/ VDD VDDext CHNR REFSEL AREF MC_VADC_AREFPATHS Figure 12 Data Sheet ADC Voltage Supply 52 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.2.3 Out of Range Comparator (ORC) Characteristics The Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above VDDP on selected input pins (ORCx.AIN) and generates a service request trigger (ORCx.OUT). Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 18 Out of Range Comparator (ORC) Characteristics (Operating Conditions apply; VDDP = 3.0 V - 5.5 V; CL = 0.25pF) Parameter Symbol Values Min. Typ. DC Switching Level VODC CC - Hysteresis VOHYS CC 15 tOPDD CC 103 Unit Note / Test Condition Max. - 180 mV - 54 mV Never detected Overvoltage Pulse tOPDN CC - - 21 ns - - 11 ns Detection Delay tODD CC 39 - 132 ns 31 - 121 ns Release Delay tORD CC 44 - 240 ns 57 - 340 ns VAIN VDDP + 150 mV VAIN VDDP + 350 mV VAIN VDDP + 150 mV VAIN VDDP + 350 mV VAIN VDDP + 150 mV VAIN VDDP + 350 mV VAIN VDDP; VDDP = 5 V VAIN VDDP; VDDP = 3.3 V - 300 ns ORCCTRL.ENORCx = 1 88 tOED CC - - ns - ns VODC Enable Delay - VOH YS Always detected Overvoltage Pulse - VAIN VDDP + VODC VD D P VSS ORCx.AIN ORCx.OUT tOD D Figure 13 Data Sheet tOR D ORCx.OUT Trigger Generation 53 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter V AIN (V) T < tOPDN VDDP + 350 mV T < tOPDN VDDP + 150 mV tOPDN < T < tOPDD t OPDN < T < tOPDD T > tOPDD T > tOPDD T > tOPDD V DDP + 60 mV VDDP VSSA Never detected Overvoltage Pulse (Too low) Overvoltage may be detected (long enough, level uncertain ) Never detected Overvoltage Pulse (Too short) Overvoltage may be detected Always detected Overvoltage Pulse Never detected Overvoltage Pulse (Too short) Overvoltage may be detected Always detected Overvoltage Pulse t Figure 14 Data Sheet ORC Detection Ranges 54 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.2.4 Analog Comparator Characteristics Table 19 below shows the Analog Comparator characteristics. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 19 Analog Comparator Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Min. Typ. Max. Unit Notes/ Test Conditions Input Voltage VCMP Input Offset VCMPOFF CC - +/-3 - mV High power mode VCMP < 200 mV Propagation Delay1) tPDELAY CC - 25 - ns High power mode, VCMP = 100 mV - 80 - ns High power mode, VCMP = 25 mV - 250 - ns Low power mode, VCMP = 100 mV - 700 - ns Low power mode, VCMP = 25 mV CC - 100 - A First active ACMP in high power mode, VCMP > 30 mV - 66 - A Each additional ACMP in high power mode, VCMP > 30 mV - 10 - A First active ACMP in low power mode - 6 - A Each additional ACMP in low power mode CC - +/-15 - mV CC - 5 ns Current Consumption Input Hysteresis Filter Delay 1) IACMP VHYS tFDELAY SR -0.05 - VDDP + V 0.05 - 1) Total Analog Comparator Delay is the sum of Propagation Delay and Filter Delay. Data Sheet 55 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.2.5 Temperature Sensor Characteristics Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 20 Temperature Sensor Characteristics Parameter Measurement time Temperature sensor range Sensor Accuracy1) Start-up time Symbol Min. Typ. Values Max. Unit Note / Test Condition tM CC TSR SR TTSAL - - 10 ms -40 - 115 C -6 - 6 C CC -10 - 10 C - -/+8 - C - 15 s tTSST SR - TJ > 20C 0C TJ 20C TJ < 0C 1) The temperature sensor accuracy is independent of the supply voltage. Data Sheet 56 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.2.6 Oscillator Pins Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier. Note: These parameters are not subject to production test, but verified by design and/or characterization. The oscillator pins can be operated with an external crystal/resonator (see Figure 15) or in direct input mode (see Figure 16). XTAL1 f OSC GND XTAL2 Damping resistor may be needed for some crystals V VPPX_min VPPX VPPX_min VPPX VPPX_max tOSCS t Figure 15 Data Sheet Oscillator in Crystal Mode 57 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter External Clock Source Direct Input Mode XTAL1 not connected XTAL2 V VIHBX_max Inpu ltage h Vo t Hig tH Inpu igh V e oltag VIHBX_min VILBX_max VSS VILBX_min g Volta t Low Inpu e t Figure 16 Data Sheet Oscillator in Direct Input Mode 58 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Table 21 OSC_XTAL Parameters Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. fOSC SR 4 - 48 MHz Direct Input Mode 4 - 20 MHz External Crystal Mode - - 10 ms Input voltage at XTAL1 VIX SR -0.3 - 1.5 V External Crystal Mode -0.3 - 5.5 V Direct Input Mode - 1.7 V External Crystal Mode Input frequency Oscillator start-up time1)2) Input amplitude (peakto-peak) at XTAL12)3) tOSCS CC VPPX SR 0.6 1) tOSCS is defined from the moment the oscillator is enabled wih SCU_ANAOSCHPCTRL.MODE until the oscillations reach an amplitude at XTAL1 of 0.9 * VPPX. 2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and amplitude as recommended and specified by crystal suppliers. 3) If the shaper unit is enabled and not bypassed. Data Sheet 59 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Table 22 RTC_XTAL Parameters Parameter Symbol Values Min. Input frequency Oscillator start-up time1)2) fOSC SR - tOSCS - Typ. Unit Max. 32.768 - kHz - 5 s Note / Test Condition CC Input voltage at RTC_XTAL1 VIX SR -0.3 - 1.5 V Input amplitude (peakto-peak) at RTC_XTAL12)3) VPPX SR 0.2 - 1.2 V 1) tOSCS is defined from the moment the oscillator is enabled by the user with SCU_ANAOSCLPCTRL.MODE until the oscillations reach an amplitude at RTC_XTAL1 of 0.9 * VPPX. 2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and amplitude as recommended and specified by crystal suppliers. 3) If the shaper unit is enabled and not bypassed. Data Sheet 60 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.2.7 Power Supply Current The total power supply current defined below consists of a leakage and a switching component. Application relevant values are typically lower than those given in the following tables, and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations). Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 23 Power Supply parameter table; VDDP = 5V Parameter Symbol Values Min. Typ.1) Active mode current Peripherals enabled fMCLK / fPCLK in MHz2) IDDPAE CC - Max. Unit Note / Test Condition 14.1 20 mA 48 / 96 - 9.8 - mA 24 / 48 - 7.8 - mA 16 / 32 - 6.4 - mA 8 / 16 - 4.4 - mA 1/1 IDDPAD - 6.2 mA 48 / 96 CC - 4.6 - mA 24 / 48 - 3.6 - mA 16 / 32 - 3.1 - mA 8 / 16 - 1.8 - mA 1/1 - 9.6 - mA 48 / 96 Sleep mode current IDDPSE CC - Peripherals clock enabled - fMCLK / fPCLK in MHz4) - 11.0 - mA 48 / 96 7.6 - mA 24 / 48 6.4 - mA 16 / 32 - 5.3 - mA 8 / 16 - 4.2 - mA 1/1 Active mode current Peripherals disabled fMCLK / fPCLK in MHz3) Active mode current Code execution from RAM Flash is powered down fMCLK / fPCLK in MHz Data Sheet IDDPAR CC 61 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Table 23 Power Supply parameter table; VDDP = 5V Parameter Min. Typ.1) Max. Unit Note / Test Condition IDDPSD - 2.8 - mA 48 / 96 CC - 2.2 - mA 24 / 48 - 2.0 - mA 16 / 32 - 1.9 - mA 8 / 16 - 1.7 - mA 1/1 IDDPSR - 2.2 - mA 48 / 96 CC - 1.7 - mA 24 / 48 - 1.4 - mA 16 / 32 - 1.2 - mA 8 / 16 - 1.1 - mA 1/1 - 0.27 - mA Wake-up time from Sleep tSSA CC to Active mode8) - 6 - cycl es tDSA CC - 290 - sec Sleep mode current Peripherals clock disabled Flash active fMCLK / fPCLK in MHz5) Sleep mode current Peripherals clock disabled Flash powered down fMCLK / fPCLK in MHz6) Deep Sleep mode current7) Wake-up time from Deep Sleep to Active mode9) Symbol IDDPDS Values CC 1) The typical values are measured at TA = + 25 C and VDDP = 5 V. 2) CPU and all peripherals clock enabled, Flash is in active mode. 3) CPU enabled, all peripherals clock disabled, Flash is in active mode. 4) CPU in sleep, all peripherals clock enabled and Flash is in active mode. 5) CPU in sleep, Flash is in active mode. 6) CPU in sleep, Flash is powered down and code executed from RAM after wake-up. 7) CPU in sleep, peripherals clock disabled, Flash is powered down and code executed from RAM after wake-up. 8) CPU in sleep, Flash is in active mode during sleep mode. 9) CPU in sleep, Flash is in powered down mode during deep sleep mode. Data Sheet 62 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Figure 17 shows typical graphs for active mode supply current for VDDP = 5 V, VDDP = 3.3 V, VDDP = 1.8 V across different clock frequencies. 16.0 14.0 12.0 10.0 I (mA) 8.0 IDDPAE 5V / 3.3V 6.0 IDDPAE 1.8V 4.0 IDDPAD 5V / 3.3V /1.8V 2.0 0.0 1/1 8/16 16/32 24/48 48/96 MCLK / PCLK (MHz) Condition: 1. TA = +25 C Figure 17 Data Sheet Active mode, a) peripherals clocks enabled, b) peripherals clocks disabled: Supply current IDDPA over supply voltage VDDP for different clock frequencies 63 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Figure 18 shows typical graphs for sleep mode current for VDDP = 5 V, VDDP = 3.3 V, VDDP = 1.8 V across different clock frequencies. 2.5 2.0 1.5 I (mA) 1.0 IDDPSR 5V / 3.3V / 1.8V 0.5 0.0 1/1 8/16 16/32 24/48 32/64 MCLK / PCLK (MHz) Condition: 1. TA = +25 C Figure 18 Data Sheet Sleep mode, peripherals clocks disabled, Flash powered down: Supply current IDDPSD over supply voltage VDDP for different clock frequencies 64 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Table 24 provides the active current consumption of some modules operating at 5 V power supply at 25 C. The typical values shown are used as a reference guide on the current consumption when these modules are enabled. Table 24 Typical Active Current parameter table Active Current Consumption Symbol Limit Values Unit Test Condition Typ. Baseload current ICPUDDC 4.14 mA Modules including Core, SCU, PORT, memories, ANATOP1) VADC and SHS IADCDDC IUSIC0DDC ICCU40DDC ICCU80DDC IPIF0DDC ILTSxDDC IBCCU0DDC IMATHDDC IWDTDDC IRTCDDC IMCANDDC 3.73 mA Set CGATCLR0.VADC to 12) 1.35 mA Set CGATCLR0.USIC0 to 13) 0.99 mA Set CGATCLR0.CCU40 to 14) 1.00 mA Set CGATCLR0.CCU80 to 15) 1.05 mA Set CGATCLR0.POSIF0 to 16) 1.14 mA Set CGATCLR0.LEDTSx to 17) 0.29 mA Set CGATCLR0.BCCU0 to 18) 0.50 mA Set CGATCLR0.MATH to 19) 0.03 mA Set CGATCLR0.WDT to 110) 0.01 mA Set CGATCLR0.RTC to 111) 1.38 mA Set CGATCLR0.MCAN0 to 112) USICx CCU4x CCU8x POSIFx LEDTSx BCCU0 MATH WDT RTC MultiCAN 1) Baseload current is measured with device running in user mode, MCLK=PCLK=48 MHz, with an endless loop in the flash memory. The clock to the modules stated in CGATSTAT0 are gated. 2) Active current is measured with: module enabled, MCLK=48 MHz, running in auto-scan conversion mode 3) Active current is measured with: module enabled, each of the 2 USIC channels sending alternate messages at 57.6 kbaud every 200 ms 4) Active current is measured with: module enabled, MCLK=PCLK=48 MHz, 1 CCU4 slice for PWM switching at 20kHz with duty cycle varying at 10%-90%, 1 CCU4 slice in capture mode for reading period and duty cycle 5) Active current is measured with: module enabled, MCLK=PCLK=48 MHz, 3 CCU8 slices with PWM frequency at 20kHz and a period match interrupt used to toggle duty cycle between 10% and 90% 6) Active current is measured with: module enabled, MCLK=48 MHz, PCLK=96 MHz, hall sensor mode 7) Active current is measured with: module enabled, MCLK=48 MHz, 1 LED column, 6 LED/TS lines, Pad Scheme A with large pad hysteresis config, time slice duration = 1.048 ms 8) Active current is measured with: module enabled, MCLK=48 MHz, PCLK=96MHz, FCLK=0.8 MHz, Normal mode (BCCU clock = FCLK/4), 4 BCCU Channels with packers enabled and 1 Dimming Engine, change color or dim every 1s 9) Active current is measured with: module enabled, MCLK=48 MHz, PCLK=96 MHz, tangent calculation in while loop; CORDIC circular rotation, no keep, autostart; 32-by-32 bit signed DIV, autostart, DVS right shift by 11 Data Sheet 65 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 10) Active current is measured with: module enabled, MCLK=48 MHz, time-out mode; WLB = 0, WUB = 0x00008000; WDT serviced every 1 s 11) Active current is measured with: module enabled, MCLK=48 MHz, Periodic interrupt enabled 12) Active current is measured with: module enabled, MCLK=48 MHz, running at 20 MHz baudrate generator, 1 node activated, 1 transmit and 1 receive object active. Data Sheet 66 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.2.8 Flash Memory Parameters Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 25 Flash Memory Parameters Parameter Symbol Values Unit Min. Typ. Max. Erase time per page / sector tERASE CC 6.8 7.1 7.6 ms Program time per block tPSER CC 102 152 204 s Wake-Up time - 32.2 - s - 50 - ns Data Retention Time tWU CC ta CC tRET CC 10 - - years Flash Wait States 1) NWSFLASH CC 0 0 0 0 1 1 1 2 2 2 2 3 Read time per word Note / Test Condition Max. 100 erase / program cycles fMCLK fMCLK fMCLK fMCLK Erase Cycles NECYC CC - - 5*10 Total Erase Cycles NTECYC CC - - 2*106 cycles 4 = 8 MHz = 16 MHz = 32 MHz = 48 MHz cycles Sum of page and sector erase cycles 1) Flash wait states are automatically inserted by the Flash module during memory read when needed. Typical values are calculated from the execution of the Dhrystone benchmark program. Data Sheet 67 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family sector N_LOG_SEC-1 page 15 page 14 1 sector = 16 Pages = 4 KB NVM N_LOG_SEC 1) * 4 KB Electrical Parameter sector 1 sector 0 page 13 page 1 page 0 1 page = 16 data blocks = 256 Bytes data block 0 data block 1 data block 2 data block 14 data block 15 1 block = 4 words = 16 Bytes word 0 1) word 1 word 2 word 3 The number of sectors, N_LOG_SEC, depends on the Flash memory size of the product derivative. Figure 19 Data Sheet Logical Structure of the Flash 68 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.3 AC Parameters 3.3.1 Testing Waveforms VD D P VSS 90% 90% 10% 10% tR Figure 20 tF Rise/Fall Time Parameters VD D P VD D P / 2 Test Points VD D P / 2 VSS Figure 21 Testing Waveform, Output Delay VL OAD + 0.1V VL OAD - 0.1V Figure 22 Data Sheet Timing Reference Points VOH - 0.1V VOL + 0.1V Testing Waveform, Output High Impedance 69 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.3.2 Power-Up and Supply Threshold Characteristics Table 26 provides the characteristics of the supply threshold in XMC1400. The guard band between the lowest valid operating voltage and the brownout reset threshold provides a margin for noise immunity and hysteresis. The electrical parameters may be violated while VDDP is outside its operating range. The brownout detection triggers a reset within the defined range. The prewarning detection can be used to trigger an early warning and issue corrective and/or fail-safe actions in case of a critical supply voltage drop. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 26 Power-Up and Supply Threshold Parameters (Operating Conditions apply) Parameter Symbol Values Min. Unit Typ. Max. Note / Test Condition VDDP ramp-up time tRAMPUP SR VDDP/ - SVDDPrise 107 s VDDP slew rate SVDDPOP SR 0 - 0.1 V/s Slope during normal operation SVDDP10 SR 0 - 10 V/s Slope during fast transient within +/10% of VDDP SVDDPrise SR 0 - 10 V/s Slope during power-on or restart after brownout event SVDDPfall1) SR 0 - 0.25 V/s Slope during supply falling out of the +/-10% limits2) VDDPPW CC 2.1 2.25 2.4 V ANAVDEL.VDEL_ SELECT = 00B 2.85 3 3.15 V ANAVDEL.VDEL_ SELECT = 01B 4.2 4.4 4.6 V ANAVDEL.VDEL_ SELECT = 10B VDDP prewarning voltage Data Sheet 70 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Table 26 Power-Up and Supply Threshold Parameters (Operating Conditions apply) (cont'd) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition calibrated, before user code starts running VDDP brownout reset voltage VDDPBO CC 1.55 1.62 1.75 V VDDP voltage to ensure defined pad states VDDPPA CC - 1.0 - V Start-up time from power-on reset tSSW SR - 260 - s Time to the first user code instruction3) BMI program time tBMI SR - 8.25 - ms Time taken from a user-triggered system reset after BMI installation is is requested 1) A capacitor of at least 100 nF has to be added between VDDP and VSSP to fulfill the requirement as stated for this parameter. 2) Valid for a 100 nF buffer capacitor connected to supply pin where current from capacitor is forwarded only to the chip. A larger capacitor value has to be chosen if the power source sink a current. 3) This values does not include the ramp-up time. During startup firmware execution, MCLK is running at 48 MHz and the clocks to peripheral as specified in register CGATSTAT0 are gated. 5.0V } VDDP VDDPPW V DDPBO Figure 23 Data Sheet Supply Threshold Parameters 71 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.3.3 On-Chip Oscillator Characteristics Table 27 provides the characteristics of the 96 MHz digital controlled oscillator DCO1. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 27 96 MHz DCO1 Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Min. Nominal frequency fNOM CC - Accuracy with fLTX CC adjustment based on XTAL as reference fLT Accuracy CC Unit Test Conditions Typ Max. . 96 - MHz under nominal conditions1) after trimming -0.3 - 0.3 % with respect to fNOM(typ), over temperature (-40 C to 105 C) -1.7 - 3.4 % with respect to fNOM(typ), over temperature (0 C to 85 C) -3.9 - 4.0 % with respect to fNOM(typ), over temperature (-40 C to 105 C) 1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 C. Table 28 provides the characteristics of the 32 kHz digital controlled oscillator DCO2. Table 28 32 kHz DCO2 Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Min. Typ. Unit Test Conditions Max. Nominal frequency fNOM CC - 32.75 - kHz under nominal conditions1) after trimming Accuracy fLT CC -1.7 - 3.4 % with respect to fNOM(typ), over temperature (0 C to 85 C) -3.9 - 4.0 % with respect to fNOM(typ), over temperature (-40 C to 105 C)1) 1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 C. Data Sheet 72 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.3.4 Serial Wire Debug Port (SW-DP) Timing The following parameters are applicable for communication through the SW-DP interface. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 29 SWD Interface Timing Parameters(Operating Conditions apply) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. t1 SR t2 SR t3 SR 50 - 500000 ns - 50 - 500000 ns - 10 - - ns - SWDIO input hold t4 SR after SWDCLK rising edge 10 - - ns - SWDCLK high time SWDCLK low time SWDIO input setup to SWDCLK rising edge SWDIO output valid time t5 after SWDCLK rising edge CC - - 68 ns CL = 50 pF - - 62 ns CL = 30 pF t6 SWDIO output hold time from SWDCLK rising edge CC 4 - - ns t1 t2 SWDCLK t6 SWDIO (Output ) t5 t3 t4 SWDIO (Input ) Figure 24 Data Sheet SWD Timing 73 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.3.5 SPD Timing Requirements The optimum SPD decision time between 0B and 1B is 0.75 s. With this value the system has maximum robustness against frequency deviations of the sampling clock on tool and on device side. However it is not always possible to exactly match this value with the given constraints for the sample clock. For instance for a oversampling rate of 4, the sample clock will be 8 MHz and in this case the closest possible effective decision time is 5.5 clock cycles (0.69 s). Table 30 Optimum Number of Sample Clocks for SPD Sample Effective Remark Sample Sampling Sample Freq. Factor Clocks 0B Clocks 1B Decision Time1) 8 MHz 4 1 to 5 6 to 12 0.69 s The other closest option (0.81 s) for the effective decision time is less robust. 1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0B sample clocks) For a balanced distribution of the timing robustness of SPD between tool and device, the timing requirements for the tool are: * * Frequency deviation of the sample clock is +/- 5% Effective decision time is between 0.69 s and 0.75 s (calculated with nominal sample frequency) Data Sheet 74 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.3.6 Peripheral Timings Note: These parameters are not subject to production test, but verified by design and/or characterization. 3.3.6.1 Synchronous Serial Interface (USIC SSC) Timing The following parameters are applicable for a USIC channel operated in SSC mode. Note: Operating Conditions apply. Table 31 USIC SSC Master Mode Timing Parameter Symbol Values Min. SCLKOUT master clock period Unit Typ. Max. tCLK CC 4/MCLK - - ns Slave select output SELO t1 active to first SCLKOUT transmit edge CC tCLK/2 - 28 - - ns Slave select output SELO t2 inactive after last SCLKOUT receive edge CC 0 - - ns CC -28 - 28 ns Receive data input t4 DX0/DX[5:3] setup time to SCLKOUT receive edge SR 75 - - ns Data input DX0/DX[5:3] t5 hold time from SCLKOUT receive edge SR 0 - - ns Data output DOUT[3:0] valid time Table 32 t3 USIC SSC Slave Mode Timing Parameter Symbol Values Min. DX1 slave clock period Select input DX2 setup to first clock input DX1 transmit edge1) Data Sheet Note / Test Condition tCLK SR 4/MCLK - t10 SR 16 - 75 Unit Typ. Max. - ns - ns Note / Test Conditio n V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Table 32 USIC SSC Slave Mode Timing Parameter Symbol Values Unit Min. Typ. Max. 17 - - ns 21 - - ns Data input DX0/DX[5:3] hold t13 time from clock input DX1 SR receive edge1) 15 - - ns Data output DOUT[3:0] valid t14 time CC - - 71 ns Select input DX2 hold after t11 last clock input DX1 receive SR edge1) Receive data input DX0/DX[5:3] setup time to shift clock receive edge1) t12 Note / Test Conditio n SR 1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0). Data Sheet 76 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Master Mode Timing t1 Select Output SELOx t2 Inactive Inactive Active Clock Output SCLKOUT Receive Edge First Transmit Edge t3 Last Receive Edge Transmit Edge t3 Data Output DOUT[3:0] t4 Data Input DX0/DX[5:3] t4 t5 Data valid t5 Data valid Slave Mode Timing t1 0 Select Input DX2 Clock Input DX1 t1 1 Active Inactive Receive Edge First Transmit Edge t1 2 Data Input DX0/DX[5:3] Inactive Last Receive Edge Transmit Edge t1 2 t1 3 Data valid t13 Data valid t14 t1 4 Data Output DOUT[3:0] Transmit Edge: with this clock edge, transmit data is shifted to transmit data output. Receive Edge: with this clock edge, receive data at receive data input is latched . Drawn for BRGH .SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal. USIC_SSC_TMGX.VSD Figure 25 USIC - SSC Master/Slave Mode Timing Note: This timing diagram shows a standard configuration, for which the slave select signal is low-active, and the serial clock signal is not shifted and not inverted. Data Sheet 77 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter 3.3.6.2 Inter-IC (IIC) Interface Timing The following parameters are applicable for a USIC channel operated in IIC mode. Note: Operating Conditions apply. Table 33 USIC IIC Standard Mode Timing1) Parameter Symbol Values Unit Min. Typ. Max. Fall time of both SDA and t1 SCL CC/SR - - 300 ns Rise time of both SDA and t2 SCL CC/SR - - 1000 ns 0 - - s 250 - - ns 4.7 - - s 4.0 - - s 4.0 - - s 4.7 - - s 4.0 - - s 4.7 - - s - - 400 pF Data hold time t3 Note / Test Condition CC/SR Data set-up time t4 CC/SR LOW period of SCL clock t5 CC/SR HIGH period of SCL clock t6 CC/SR Hold time for (repeated) START condition t7 Set-up time for repeated START condition t8 Set-up time for STOP condition t9 Bus free time between a STOP and START condition t10 Capacitive load for each bus line Cb SR CC/SR CC/SR CC/SR CC/SR 1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s. Data Sheet 78 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter Table 34 USIC IIC Fast Mode Timing1) Parameter Symbol Values Min. Fall time of both SDA and t1 SCL CC/SR Typ. Unit Max. 20 + 0.1*Cb 300 ns 20 + 0.1*Cb 300 ns 0 - - s 100 - - ns 1.3 - - s 0.6 - - s 0.6 - - s 0.6 - - s 0.6 - - s 1.3 - - s - - 400 pF Note / Test Condition 2) Rise time of both SDA and t2 SCL CC/SR Data hold time t3 CC/SR Data set-up time t4 CC/SR LOW period of SCL clock t5 CC/SR HIGH period of SCL clock t6 CC/SR Hold time for (repeated) START condition t7 Set-up time for repeated START condition t8 Set-up time for STOP condition t9 Bus free time between a STOP and START condition t10 Capacitive load for each bus line Cb SR CC/SR CC/SR CC/SR CC/SR 1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s. 2) Cb refers to the total capacitance of one bus line in pF. Data Sheet 79 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter t1 SDA t2 t4 70% 30% t1 t3 t2 t6 SCL th t7 9 clock t5 t10 S SDA t8 t7 t9 SCL th 9 clock Sr Figure 26 3.3.6.3 P S USIC IIC Timing Inter-IC Sound (IIS) Interface Timing The following parameters are applicable for a USIC channel operated in IIS mode. Note: Operating Conditions apply. Table 35 USIC IIS Master Transmitter Timing Parameter Clock period Clock HIGH Symbol t1 CC t2 CC Values Unit Min. Typ. Max. 4/fMCLK - - ns 0.35 x - - ns - - ns 0 - - ns - - 0.15 x ns Note / Test Condition t1min Clock Low t3 CC 0.35 x t1min Hold time Clock rise time t4 CC t5 CC t1min Data Sheet 80 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Electrical Parameter t1 t2 t5 t3 SCK t4 WA/ DOUT Figure 27 USIC IIS Master Transmitter Timing Table 36 USIC IIS Slave Receiver Timing Parameter Symbol t6 SR t7 SR Clock period Clock HIGH Values Unit Min. Typ. Max. 4/fMCLK - - ns 0.35 x - - ns - - ns - - ns - - ns Note / Test Condition t6min t8 SR Clock Low 0.35 x t6min t9 SR Set-up time 0.3 x t6min t10 SR Hold time 15 t6 t7 t8 SCK t9 t10 WA/ DIN Figure 28 Data Sheet USIC IIS Slave Receiver Timing 81 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Package and Reliability 4 Package and Reliability The XMC1400 is a member of the XMCTM1000 Family of microcontrollers. It is also compatible to a certain extent with members of similar families or subfamilies. Each package is optimized for the device it houses. Therefore, there may be slight differences between packages of the same pin-count but for different device types. In particular, the size of the exposed die pad may vary. If different device types are considered or planned for an application, it must be ensured that the board layout fits all packages under consideration. 4.1 Package Parameters Table 37 provides the thermal characteristics of the packages used in XMC1400. Table 37 Thermal Characteristics of the Packages Parameter Symbol Limit Values Exposed Die Pad Dimensions Ex x Ey CC Thermal resistance Junction-Ambient RJA CC - Unit Package Types Min. Max. - 3.7 x 3.7 mm PG-VQFN-40-17 - 4.2 x 4.2 mm PG-VQFN-48-73 - 4.6 x 4.6 mm PG-VQFN-64-6 86.0 K/W PG-TSSOP-38-91) - 45.3 K/W PG-VQFN-40-171) - 44.9 K/W PG-VQFN-48-731) - 66.7 K/W PG-LQFP-64-261) - 44.7 K/W PG-VQFN-64-61) 1) Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered. Note: For electrical reasons, it is required to connect the exposed pad to the board ground VSSP, independent of EMC and thermal requirements. 4.1.1 Thermal Considerations When operating the XMC1400 in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage. The maximum heat that can be dissipated depends on the package and its integration into the target board. The "Thermal resistance RJA" quantifies these parameters. The power dissipation must be limited so that the average junction temperature does not exceed 115 C. Data Sheet 82 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Package and Reliability The difference between junction temperature and ambient temperature is determined by T = (PINT + PIOSTAT + PIODYN) x RJA The internal power consumption is defined as PINT = VDDP x IDDP (switching current and leakage current). The static external power consumption caused by the output drivers is defined as PIOSTAT = ((VDDP-VOH) x IOH) + (VOL x IOL) The dynamic external power consumption caused by the output drivers (PIODYN) depends on the capacitive load connected to the respective pins and their switching frequencies. If the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation: * * * * Reduce VDDP, if possible in the system Reduce the system frequency Reduce the number of output pins Reduce the load on active output drivers Data Sheet 83 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Package and Reliability 4.2 Figure 29 Data Sheet Package Outlines PG-TSSOP-38-9 84 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family Package and Reliability 9 x 0.4 = 3.6 5 A 0.4 0.9 MAX. 0.1 A C 2x B 21 0.1 C 0.1 B C 2x Index Marking C M A B C Index Marking 0.2 0.05 40x 0.07 0.05 M M A B C C 0.05 M A B C 31 3.6 0.1 20 0.4 0.05 SEATING PLANE 5 0.08 C 40x COPLANARITY 0.05 30 11 40 10 (0.2) 1 3.6 0.1 0.05 MAX. STANDOFF PG-VQFN-40-17 7 B 0.1 M A B C Figure 30 0.9 MAX. A 2x (0.203) 0.1 A 0.1 C 0.1 B Data Sheet 0.5 C 36 24 37 4.1 0.1 SEATING PLANE 7 2x Index Marking 11 x 0.5 = 5.5 25 48x 0.05 C COPLANARITY Figure 31 PG-VQFN-40-13, -14, -17-PO V05 4.1 0.1 0.1 M A B C 48 13 12 0.4 0.05 0.05 MAX. STAND OFF 1 Index Marking +0.05 0.25 -0.07 48x 0.1 M A B C 0.05 M C PG-VQFN-48-35, -73-PO V04 PG-VQFN-48-73 85 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family 0.5 0.6 0.15 0.08 C 64x COPLANARITY 0.22 0.05 2) C SEATING PLANE 0...7 H +0.05 0.15 -0.0 6 15 x 0.5 = 7.5 1.6 MAX. 0.1 0.05 STAND OFF 1.4 0.05 Package and Reliability 64x 0.08 M C A-B D 12 10 0.2 C A-B D 64x 1) 0.2 H A-B D 4x 10 B 12 A 1) D 64 1 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Does not include dambar protrusion of 0.08 max. per side PG-LQFP-64-10, -21, -26-PO V03 Figure 32 Data Sheet PG-LQFP-64-26 86 V1.2, 2016-08 Subject to Agreement on the Use of Product Information XMCTM1400 AA-Step XMCTM1000 Family 8 0.9 MAX. A 0.1 A C 2x B 0.1 M A B C Quality Declaration (0.2) 0.1 C SEATING PLANE 8 0.1 B C 2x 0.4 33 48 32 49 4.5 0.1 64x 0.08 C COPLANARITY 15 x 0.4 = 6 4.5 0.1 17 64 16 1 0.4 0.05 C 0.2 0.05 0.05 MAX. STAND OFF Index Marking 0.1 M A B C Index Marking 64x 0.07 0.05 M M A B C C PG-VQFN-64-6-PO V04 Figure 33 PG-VQFN-64-6 All dimensions in mm. 5 Quality Declaration Table 38 shows the characteristics of the quality parameters in the XMC1400. Table 38 Quality Parameters Parameter Symbol Limit Values Unit Notes 2000 V Conforming to EIA/JESD22A114-B - 500 V Conforming to JESD22-C101-C - 3 - JEDEC J-STD-020D - 260 C Profile according to JEDEC J-STD-020D Min. Max. ESD susceptibility VHBM according to Human Body SR Model (HBM) - VCDM ESD susceptibility SR according to Charged Device Model (CDM) pins MSL Moisture sensitivity level CC Soldering temperature TSDR SR Data Sheet 87 V1.2, 2016-08 Subject to Agreement on the Use of Product Information w w w . i n f i n e o n . c o m Published by Infineon Technologies AG