September 2003
Preliminary Information
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C3513B
3.3V 32K×16 CMOS SRAM
9/8/03, v.1.0 Alliance Semiconductor P. 1 of 9
Features
• Compatible to AS7C3513A
• Industrial and commercial temperature
• Organization: 32,768 words × 16 bits
• Center power and ground pins
•High speed
• 8/10/12/15/20 ns address access time
• 5, 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
• 306mW / max @ 8 ns
• Low power consumption: STANDBY
• 18 mW / max CMOS
• 6T 0.18m CMOS Technology
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• 44-pin JEDEC standard package
•400 mil SOJ
• 400 mil TSOP 2
• ESD protection > 2000 volts
• Latch-up current > 200 mA
Logic block diagram
32K × 16
Array
OE
CE
WE Column decoder
Row decoder
A0
A1
A2
A3
A4
A5
A7
VCC
GND
A8
A9
A10
A11
A12
A13
A14
Control circuit
I/O0–I/O7
I/O8–I/O15
UB
LB
I/O
buffer
A6
Pin arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A7
A8
A9
A10
NC
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A14
A13
A12
44-Pin SOJ, TSOP 2 (400 mil)
21
22
A11
NC
UB
LB
I/O15
I/O14
2A3
3A2
4A1
1NC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A5
A6
OE
A4
AS7C3513B
Selection guide
-8 -10 -12 -15 -20 Unit
Maximum address access time 810 121520ns
Maximum output enable access time 55 6 78ns
Maximum operating current 85 80 75 70 65 mA
Maximum CMOS standby current 55 5 55mA
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AS7C3513B
9/8/03, v.1.0 Alliance Semiconductor P. 2 of 9
Functional description
The AS7C3513B is a high performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as 32,768 words × 16
bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 8/10/12/15/20 ns with output enable access times (tOE) of 5, 5, 6, 7, 8 ns are ideal for
high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.
When CE is high, the device enters standby mode. If inputs are still toggling, the device consumes ISB power. If the bus is static, then the full
standby power is reached (ISB1). The AS7C3513B is guaranteed not to exceed 18mW power consumption under nominal full standby
conditions.
A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0 - I/O7,
and/or I/O8 – I/O15, is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices
should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0 – I/O7, and UB controls the higher bits, I/O8 – I/O15.
All chip inputs and outputs are TTL-compatible. The AS7C3513B is packaged in common industry standard packages.
Absolute maximum ratings
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t care; L = Low; H = High
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 –0.50 +5.0 V
Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V
Power dissipation PD–1.0W
Storage temperature (plastic) Tstg –65 +150 o C
Ambient temperature with VCC applied Tbias –55 +125 o C
DC current into outputs (low) IOUT –20mA
CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode
H X X X X High Z High Z Standby (ISB, ISBI)
LHLLHD
OUT High Z Read I/O0–I/O7 (ICC)
LHLHLHigh ZD
OUT Read I/O8–I/O15 (ICC)
LHLLLD
OUT DOUT Read I/O0–I/O15 (ICC)
LLXLL D
IN DIN Write I/O0–I/O15 (ICC)
LLXLH D
IN High Z Write I/O0–I/O7 (ICC)
LLXHLHigh ZD
IN Write I/O8–I/O15 (ICC)
L
L
H
X
H
X
X
H
X
HHigh Z High Z Output disable (ICC)
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AS7C3513B
9/8/03, v.1.0 Alliance Semiconductor P. 3 of 9
Recommended operating conditions
† VIL min = –3.0V for pulse width less than tRC/2.
DC operating characteristics (over the operating range)1
Capacitance (f = 1MHz, Ta = 25o C, VCC = NOMINAL)2
Read cycle (over the operating range) 3,9
Parameter Symbol Min Typical Max Unit
Supply voltage VCC 3.0 3.3 3.6 V
Input voltage VIH 2.0 – VCC + 0.5
VIL –0.5†–0.8V
Ambient operating temperature commercial TA0 – 70 ° C
industrial TA–40 – 85 ° C
Parameter Sym Test conditions
-8 -10 -12 -15 -20
UnitMin Max Min Max Min Max Min Max Min Max
Input leakage
current | ILI | VCC = Max
VIN = GND to VCC
- 1–1–1–1–1µA
Output
leakage
current
| ILO | VCC = Max
VOUT = GND to VCC
- 1–1–1–1–1µA
Operating
power supply
current
ICC VCC = Max, CE ≤ VIL
f = fMax , IOUT = 0mA - 85 – 80 – 75 – 70 – 65 mA
Standby
power supply
current
ISB VCC = Max, CE ≤ VIL
f = fMax , IOUT = 0mA - 30 – 30 – 25 – 20 – 20 mA
ISB1
VCC = Max, CE ≥ VCC–0.2V
VIN ≤ GND + 0.2V or
CMOS VIN ≥ VCC –0.2V, f = 0
- 5–5–5–5–5mA
Output
voltage
VOL IOL = 8 mA, VCC = Min - 0.4 – 0.4 – 0.4 – 0.4 – 0.4 V
VOH IOH = –4 mA, VCC = Min 2.4 - 2.4 – 2.4 – 2.4 – 2.4 – V
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE, WE, OE, LB, UB Vin = 0V 5 pF
I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF
Parameter
Symbo
l
-8 -10 -12 -15 -20
Unit
Note
s
Min Max Min Max Min Max Min Max Min Max
Read cycle time tRC 8 –10–12–15–20–ns
Address access time tAA – 8 –10–12–15–20ns3
Chip enable (CE) access
time tACE – 8 –10–12–15–20ns3
Output enable (OE) access
time tOE –5–5–6–7–8ns
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9/8/03, v.1.0 Alliance Semiconductor P. 4 of 9
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (CE, OE, UB, LB controlled)3,6,8,9
Output hold from address
change tOH 3–3–3–3–3–ns5
CE low to output in low Z tCLZ 3–3–3–3–3–ns4 , 5
CE high to output in high Z tCHZ –3–3–3–4–5ns4 , 5
OE low to output in low Z tOLZ 0–0–0–0–0–ns4 , 5
Byte select access time tBA –5–5–6–7–8ns
Byte select Low to low Z tBLZ 0–0–0–0–0–ns4 , 5
Byte select High to high Z tBHZ –4–5–6–6–8ns4 , 5
OE high to output in high Z tOHZ –4–5–6–7–8ns4 , 5
Power up time tPU 0–0–0–0–0–ns4 , 5
Power down time tPD – 8 – 10 – 12 – 15 20 ns 4 , 5
Parameter
Symbo
l
-8 -10 -12 -15 -20
Unit
Note
s
Min Max Min Max Min Max Min Max Min Max
Undefined output/don’t careFalling inputRising input
t
OH
t
AA
t
RC
t
OH
Data OUT
Address
Data validPrevious data valid
Data valid
tRC
tAA
tBLZ
tBA
tOE
tOLZ tOH
tOHZ
tHZ
tBHZ
tACE
tLZ
Address
OE
CE
LB, UB
Data OUT
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AS7C3513B
9/8/03, v.1.0 Alliance Semiconductor P. 5 of 9
Write cycle (over the operating range)11
Write waveform 1(WE controlled)11
Parameter Symbol
-8 -10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max Min Max
Write cycle time tWC 8 –10–12–15– 20 – ns
Chip enable (CE) to write
end tCW 7–8–9–10– 12 – ns
Address setup to write end tAW 7–8–9–10– 12 – ns
Address setup time tAS 0–0–0–0– 0 – ns
Write pulse width tWP 6–7–8–9– 12 – ns
Write recovery time tWR 0–0–0–0– 0 – ns
Address hold from end of
write tAH 0–0–0–0– 0 – ns
Data valid to write end tDW 5–5–6–8– 10 – ns
Data hold time tDH 0–0–0–0– 0 – ns 5
Write enable to output in
high Z tWZ –4–5–6–7 – 8 ns4 , 5
Output active from write
end tOW 1–1–1–1– 2 – ns4 , 5
Byte select low to end of
write tBW 6–7–8–9– 9 – ns
Address
LB, UB
WE
Data IN
Data OUT
tWC
tBW
tAW
tAS tWP
tDW tDH
tOW
tWZ
Data undefined High-Z
Data valid
tWR
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Write waveform 2 (CE controlled)11
AC test conditions
Notes
1During V
CC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4 These parameters are specified with CL = 5pF, as in Figure B. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6WE
is High for read cycle.
7CE
and OE are Low for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 Not applicable.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.
Address
CE
LB, UB
WE
Data IN
tWC
tCW
tBW
tWP
tDW tDH
tOW
tWZ
tAH
Data OUT Data undefined
High-Z High-Z
tAS
tAW
Data valid
tCLZ
tWR
&
350ΩC13
320Ω
Dout
GND
+3.3V
Figure B: 3.3V Output load
- Output load: see Figure B.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
168Ω
Thevenin equivalent:
Dout +1.728V
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
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AS7C3513B
9/8/03, v.1.0 Alliance Semiconductor P. 7 of 9
Package dimensions
Symbol
44-pin TSOP 2
Min
(mm)
Max
(mm)
A1.2
A10.05 0.15
A20.95 1.05
b 0.3 0.45
c0.120.21
d 18.31 18.52
e 10.06 10.26
He11.68 11.94
E 0.80 (typical)
l0.400.60
d
He
1234567891011121314
44 43 42 41 40 39 38 37 36 35 34 33 32 31
15 16
30 29
17 18 19 20
28 27 26 25 c
l
A1
A2
E
44-pin TSOP 2
0–5°
21
24
22
23
e
A
b
Symbol
44-pin SOJ
400 mil
Min Max
A 0.128 0.148
A1 0.025 -
A2 0.105 0.115
B 0.026 0.032
b 0.015 0.020
c 0.007 0.013
D 1.120 1.130
E 0.370 NOM
E1 0.395 0.405
E2 0.435 0.445
e 0.050 NOM
eD
E1
Pin 1
b
B
A1
A2
c
E
Seating
Plane
E2
A
44-pin SOJ
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AS7C3513B
9/8/03, v.1.0 Alliance Semiconductor P. 8 of 9
Ordering codes
Part numbering system
Package\Access time 8 ns 10 ns 12 ns 15 ns 20 ns
Plastic SOJ,
400 mil
Commercial AS7C3513B-8JC AS7C3513B-10JC AS7C3513B-12JC AS7C3513B-15JC AS7C3513B-20JC
Industrial AS7C3513B-10JI AS7C3513B-12JI AS7C3513B-15JI AS7C3513B-20JI
TSOP 2,
18.4×10.2 mm
Commercial AS7C3513B-8TC AS7C3513B-10TC AS7C3513B-12TC AS7C3513B-15TC AS7C3513B-20TC
Industrial AS7C3513B-10TI AS7C3513B-12TI AS7C3513B-15TI AS7C3513B-20TI
AS7C 3 513B –XX X C
SRAM
prefix
Voltage:
3.3V CMOS
Device
number Access time
Package:
J = SOJ 400 mil
T =TSOP 2 18.4×10.2 mm
Temperature range:
C = Commercial, 0°C to 70°C
I = Industrial, -40°C to 85°C
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: AS7C3513B
Document Version: v.1.0
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
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®
