FUJITSU MICROELECTRONICS DATA SHEET DS04-27263-1E ASSP for Power Management Applications (General-purpose DC/DC converter) 1ch PFM/PWM DC/DC converter IC with synchronous rectification MB39A135 DESCRIPTION MB39A135 is 1ch step-down DC/DC converter IC of the current mode N-ch/N-ch synchronous rectification method. It contains the enhanced protection features, and supports the ceramic capacitor. MB39A135 realizes rapid response, high efficiency, and low ripple voltage, and its high-frequency operation enables the miniaturization of inductor and I/O capacitors. FEATURES * * * * * * * * * * * * * * High efficiency For frequency setting by external resistor : 100 kHz to 1 MHz Error Amp threshold voltage : 0.7 V 1.0% Minimum output voltage value : 0.7 V Wide range of power-supply voltage : 4.5 V to 25 V PFM/PWM auto switching mode and fixed PWM mode selectable With built-in over voltage protection function With built-in under voltage protection function With built-in over current protection function With built-in overtemperature protection function With built-in soft start/stop circuit without load dependence With built-in synchronous rectification type output steps for N-ch MOS FET Standby current : 0 A (Typ) Small package : TSSOP-16 APPLICATIONS * * * * * * * * * Digital TV Photocopiers Surveillance cameras Set-top boxes (STB) DVD players, DVD recorders Projectors IP phones Vending machines Consoles and other non-portable devices Copyright(c)2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2008.8 MB39A135 PIN ASSIGNMENT (TOP VIEW) MODE 1 16 ILIM RT 2 15 COMP VREF 3 14 FB CTL 4 13 CS PGND 5 12 GND DRVL 6 11 CB VB 7 10 DRVH VCC 8 9 LX (FPT-16P-M08) PIN DESCRIPTIONS 2 Pin No. Pin Name I/O Description 1 MODE I 2 RT Resistor connection pin for oscillation frequency setting. 3 VREF O Reference voltage output pin. 4 CTL I Control pin. PFM/PWM switch pin. It becomes fixed PWM operation with the VREF connection, and it becomes PFM/PWM operation with the GND connection. 5 PGND Ground pin. 6 DRVL O Output pin for external low-side FET gate drive. 7 VB O Bias voltage output pin. 8 VCC Power supply pin for reference voltage and control circuit. 9 LX Inductor and external high-side FET source connection pin. 10 DRVH O Output pin for external high-side FET gate drive. 11 CB The connection pin for boot strap capacitor. 12 GND Ground pin. 13 CS I Soft-start time setting capacitor connection pin. 14 FB I Error amplifier inverted input pin. 15 COMP O Error amplifier (Error Amp) output pin. 16 ILIM I Over current detection level setting voltage input pin. DS04-27263-1E MB39A135 BLOCK DIAGRAM MODE RT 1 CS 13 <Soft-Start > ctl /uvp_out /otp_out 8 Clock generator Bias Reg. VREF /uvlo ovp_out COMP VCC 2 <PFM Comp. > - 5.5 A + VB 7 2.0 V 70 k 11 Hi-side Drive 15 10 FB <Error Amp> 14 - + + <I Comp.> - R Q + intref RS-FF CLK 9 Drive Logic S 6 LX 5 DRVL PGND Level Converter Vs 16 DRVH VB Lo-side Drive ILIM CB <Di Comp.> - + <OVP Comp.> - + 50 s delay S Q ovp_out R <UVLO> intref x 1.15 V uvlo <UVP Comp.> - + 512/fOSC delay S Q uvp_out VB UVLO VREF UVLO H : UVLO release R otp_out intref x 0.7 V VB intref OTP ctl <REF> <CTL> ON/OFF CTL 4 (3.3 V) 3 VREF DS04-27263-1E 12 GND 3 MB39A135 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Min Max Unit Power supply voltage VVCC VCC pin 27 V CB pin input voltage VCB CB pin 32 V LX pin input voltage VLX LX pin 27 V 7 V Voltage between CB and LX VCBLX VI CTL pin 27 V VFB FB pin VVREF + 0.3 V VILIM ILIM pin VVREF + 0.3 V VCS CS pin VVREF + 0.3 V VMODE MODE pin VVB + 0.3 V Output current IOUT DC, DRVL pin, DRVH pin 60 mA Power dissipation PD Ta + 25 C 1237 mW - 55 + 150 C Control input voltage Input voltage Storage temperature TSTG WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 4 DS04-27263-1E MB39A135 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Power supply voltage VVCC CB pin input voltage Reference voltage output current Value Unit Min Typ Max 4.5 25.0 V VCB 30 V IVREF - 100 A Bias output current IVB -1 mA CTL pin input voltage VI CTL pin 0 25 V VFB FB pin 0 VVREF V VILIM ILIM pin 0.3 1.94 V VCS CS pin 0 VVREF V MODE pin 0 VVREF V Input voltage VMODE Peak output current IOUT DRVH pin, DRVL pin Duty 5% (t = 1 / fOSC x Duty) - 1200 + 1200 mA Operation frequency range fOSC 100 500 1000 kHz Timing resistor RRT 47 k Soft start capacitor CCS 0.0075 0.0180 F CB pin capacitor CCB 0.1 1.0 F CVREF 0.1 1.0 F Bias voltage output capacitor CVB 1.0 10 F Operating ambient temperature Ta - 30 + 25 + 85 C Reference voltage output capacitor WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS04-27263-1E 5 MB39A135 ELECTRICAL CHARACTERISTICS (Ta = +25 C, VCC = 15 V, CTL = 5 V VREF = 0 A, VB = 0 A) Symbol Pin No. Condition Output voltage VVREF 3 Input stability VREF LINE 3 Load stability VREF LOAD Short-circuit output current Output voltage Parameter Reference Voltage Block [REF] Bias Voltage Block [VB Reg.] Unit Min Typ Max 3.24 3.30 3.36 V VCC = 4.5 V to 25 V 1 10 mV 3 VREF = 0 A to -100 A 1 10 mV VREF IOS 3 VREF = 0 V -14.5 -10.0 -7.5 mA VVB 7 4.85 5.00 5.15 V Input stability VB LINE 7 VCC = 6 V to 25 V 10 100 mV Load stability VB LOAD 7 VB = 0 A to -1 mA 10 100 mV Short-circuit output current VB IOS 7 VB = 0 V -130 -90 -65 mA VTLH1 7 VB 4.0 4.2 4.4 V VTHL1 7 VB 3.4 3.6 3.8 V VH1 7 VB 0.6* V VTLH2 3 VREF 2.7 2.9 3.1 V VTHL2 3 VREF 2.5 2.7 2.9 V Hysteresis width VH2 3 VREF 0.2* V Charge current ICS 13 CTL = 5 V, CS = 0 V -7.9 -5.5 -4.2 A Soft-start end voltage VCS 13 CTL = 5V 2.2 2.4 2.6 V Electrical discharge resistance at RDISCG soft-stop 13 CTL = 0 V, CS = 0.5 V 49 70 91 k Soft-stop end voltage VDISCG 13 CTL = 0 V 0.1* V Oscillation frequency fOSC 2 RT = 47 k 450 500 550 kHz fSHORT 2 RT = 47 k 62.5 kHz df/dT 2 Ta = -30 C to + 85 C 3* % Threshold voltage Under voltage Lockout Protec- Hysteresis width tion Circuit Block Threshold voltage [UVLO] Soft-start / Soft-stop Block [Soft-Start, Soft-Stop] Value Oscillation Clock frequency when Generator Block under voltage is [OSC] detected Frequency Temperature variation (Continued) 6 DS04-27263-1E MB39A135 (Ta = +25 C, VCC = 15 V, CTL = 5 V VREF = 0 A, VB = 0 A) Parameter Under-voltage Protection Circuit Block [UVP Comp.] Over-temperature Protection Circuit Block [OTP] PFM Control Circuit Block (MODE) [PFM] Condition EVTH 14 EVTHT Value Unit Typ Max 0.693 0.700 0.707 V 14 Ta = -30 C to + 85 C 0.689* 0.700* 0.711* V IFB 14 FB = 0 V -0.1 0 +0.1 A ISOURCE 15 FB = 0 V, COMP = 1 V -390 -300 -210 A ISINK 15 FB = VREF, COMP = 1 V 8.4 12.0 16.8 mA Output clamp voltage VILIM 15 FB = 0 V, ILIM = 1.5 V 1.35 1.50 1.65 V ILIM pin input current IILIM 16 FB = 0 V, ILIM = 1.5 V -1 0 +1 A Over-voltage detecting voltage VOVP 14 FB pin 0.776 0.805 0.835 V Over-voltage detection time tOVP 14 49 70 91 s Under-voltage detecting voltage VUVP 14 0.450 0.490 0.531 V Under-voltage detection time tUVP 14 512/ fOSC s TOTPH Junction temperature +160* C TOTPL Junction temperature +135* C Synchronous rectification stop voltage VTHLX 9 LX pin 0* mV PFM/PWM mode condition VPFM 1 MODE pin 0 1.4 V Fixed PWM mode condition VPWM 1 MODE pin 2.2 VVREF V MODE pin input current IMODE 1 MODE = 0 V -1 0 +1 A Input current Over-voltage Protection Circuit Block [OVP Comp.] Pin No. Min Threshold voltage Error Amp Block [Error Amp] Symbol Output current Detection temperature FB pin (Continued) DS04-27263-1E 7 MB39A135 (Continued) (Ta = +25 C, VCC = 15 V, CTL = 5 V VREF = 0 A, VB = 0 A) Symbol Pin No. High-side output on-resistance RON_MH 10 RON_ML Low-side output on-resistance Parameter Output source current Max DRVH = -100 mA 4 7 10 DRVH = 100 mA 1.0 3.5 RON_SH 6 DRVL = -100 mA 4 7 RON_SL 6 DRVL = 100 mA 0.75 1.70 ISOURCE 10,6 LX = 0 V, CB = 5 V DRVH, DRVL = 2.5 V DUTY 5% -0.5* A 10 LX = 0 V, CB = 5 V DRVH = 2.5 V DUTY 5% 0.9* A 6 LX = 0 V, CB = 5 V DRVL = 2.5 V DUTY 5% 1.2* A COMP = 1 V 250* ns 72 80 % LX = 0 V, CB = 5 V 60 ns VCC - LX 220* mV 10 Maximum on-duty DMAX 10 tD 10, 6 VRANGE 9 Voltage transduction gain ALV 9 5.4 6.8 8.2 V/V Offset voltage at voltage transduction VIO 9 300 mV Slope compensation SLOPE inclination 9 2* V/V LX pin input current ILX 9 LX = VCC 320 420 600 A ON condition VON 4 CTL pin 2 25 V OFF condition VOFF 4 CTL pin 0 0.8 V VH 4 CTL pin 0.4* V ICTLH 4 CTL = 5 V 25 40 A ICTLL 4 CTL = 0 V 0 1 A Standby current ICCS 8 CTL = 0 V 0 10 A Power-supply current ICC 8 LX = 0 V, F = 1.0 V MODE = VREF 1.9 2.7 mA Hysteresis width Input current General ISINK tON Maximum current sense voltage Control Block [CTL] Unit Typ Minimum on time Dead time Level Converter Block [LVCNV] Value Min Output Block [DRV] Output sink current Condition * : Standard design value 8 DS04-27263-1E MB39A135 TYPICAL CHARACTERISTICS * Power dissipation Power dissipation vs. Operating ambient temperature 2000 Power dissipation PD (mW) 1800 1600 1400 1237 1200 1000 800 600 400 200 0 -50 -25 0 +25 +50 +75 +100 +125 Operating ambient temperature Ta ( C) VREF bias voltage VVREF (V) 3.36 3.34 3.32 3.3 3.28 3.26 3.24 -40 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta ( C) Error Amp threshold voltage vs. Operating ambient temperature Error Amp threshold voltage EVTH (V) VREF bias voltage vs. Operating ambient temperature 0.71 VCC = 15 V fosc = 500 kHz 0.705 0.7 0.695 0.69 -40 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta ( C) (Continued) DS04-27263-1E 9 MB39A135 (Continued) Dead time vs. Operating ambient temperature 510 90 505 80 VCC = 15 V Dead time tD (ns) Oscillation frequency fOSC (kHz) Oscillation frequency vs. Operating ambient temperature 500 495 490 485 480 -40 -20 0 +20 +40 +60 Operating ambient temperature Ta( C) 40 -20 0 +20 +40 +60 +80 +100 5.5 VCC = 6 V VB bias voltage VVB (V) Oscillation frequency fOSC (kHz) 50 1000 Vcc = 15 V Ta = + 25C 100 10 100 5 4.5 VCC = 5 V 4 3.5 VCC = 4.5 V 3 fosc = 500 kHz Ta = + 25C 2.5 2 1000 -0.02 -0.015 -0.01 -0.005 0 Timing resistor value RRT (k) VB bias output current IVB (A) Maximum duty cycle vs. Power supply voltage Maximum duty cycle vs. Operating ambient temperature 80 Maximum duty cycle DMAX (%) 80 Maximum duty cycle DMAX (%) tD1 60 Operating ambient temperature Ta( C) tD1 : period from DRVL off to DRVH on tD2 : period from DRVH off to DRVL on VB bias voltage vs. VB bias output current Oscillation frequency vs. Timing resistor value 79 78 77 76 75 0 10 20 Power supply voltage VVCC (V) 10 70 30 -40 +100 +80 tD2 30 79 78 77 76 75 -40 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta ( C) DS04-27263-1E MB39A135 FUNCTION 1. Current Mode It uses the current waveform from the switching (Q1) as a control waveform to control the output voltage, as described below: 1: The clock (CK) from the internal clock generator (OSC) sets RS-FF and turns on the high-side FET. 2: Tunring on the high-side FET causes the inductor current (IL) rise. Generate Vs that converts this current into the voltage. 3: The current comparator (I Comp.) compares this Vs with the output (COMP) from the error amplifier (Error Amp) that is negative-feedback from the output voltage (Vo). 4: When I Comp. detects that Vs exceeds COMP, it resets RS-FF and turns off high side FET. 5: The clock (CK) from the clock generator (OSC) turns on the high-side FET again. Thus, switching is repeated. Operate so that the FB electrical potential may become INTREF electrical potential, and stabilize the output voltage as a feedback control. VIN <Error Amp> FB <I Comp.> - + - COMP + INTREF DRVH RS-FF R Q S Drive Logic CK Q1 Current Sense DRVL OSC IL VO Q2 Vs Rs 1 5 4 OSC(CK) IL 3 COMP Vs 2 toff DRVH ton DS04-27263-1E 11 MB39A135 (1) Reference Voltage Block (REF) The reference voltage circuit (REF) generates a temperature-compensated reference voltage (3.3 V typ) using the voltage supplied from the VCC pin. The voltage is used as the reference voltage for the IC's internal circuit. The reference voltage can be used to supply a load current of up to 100 A to an external device through the VREF pin. (2) Bias Voltage Block (VB Reg.) Bias Voltage Block (VB Reg.) generates the reference voltage used for IC's internal circuit, using the voltage supplied from the VCC pin. The reference voltage is a temperature-compensated stable voltage (5 V typ) to supply a current of up to 100 mA through the VB pin. (3) Under Voltage Lockout Protection Circuit Block (UVLO) The circuit protects against IC malfunction and system destruction/deterioration in a transitional state or a momentary drop when a bias voltage (VB) or an internal reference voltage (VREF) starts. It detects a voltage drop at the VB pin or the VREF pin and stops IC operation. When voltages at the VB pin and the VREF pin exceed the threshold voltage of the under voltage lockout protection circuit, the system is restored. (4) Soft-start/Soft-stop Block (Soft-Start, Soft-Stop) Soft-start It protects a rush current or an output voltage (VO) from overshooting at the output start. Since the lamp voltage generated by charging the capacitor connecting to the CS pin is used for the reference voltage of the error amplifier (Error Amp), it can set the soft-start time independent of a load of the output (VO). When the IC starts with "H" level of the CTL pin, the capacitor at the CS pin (CS) starts to be charged at 5.5 A. The output voltage (VO) during the soft-start period rises in proportion to the voltage at the CS pin generated by charging the capacitor at the CS pin. During the soft-start with, 0.8 V > voltage at CS pin, operations are as follows: * Fixed PWM operation only (fixed PWM even if MODE pin is set to "L") * Over-voltage protection function and under-voltage protection function are invalid. Soft-stop It discharges electrical charges stored in a smoothing capacitor at output stop. Setting the CTL pin to "L" level starts the soft-stop function independent of a load of output (Vo). Since the capacitor connecting to the CS pin starts to discharge through the IC-built-in soft-stop discharging resistance (70 k typ) when the CTL pin sets at "L" level enters its lamp voltage into the error amplifier (Error Amp.), the soft-stop time can be set independent of a load of output (VO). When discharging causes the voltage at the CS pin to drop below 100 mV (typ), the IC shuts down and changes to the stand-by state. In addition, the soft-stop function operates after the under-voltage protection circuit block (UVP Comp.) is latched or after the over-temperature protection circuit block (OTP) detects over-temperature. During the soft-stop with, 0.8 V > voltage at CS pin, operations are as follows: * Fixed PWM operation only (fixed PWM even if MODE pin is set to "L") * Over-voltage protection function and under-voltage protection function are invalid. (5) Clock Generator Block (OSC) The clock generator has the built-in oscillation frequency setting capacitor and generates a clock by connecting the oscillation frequency setting resistor to the RT pin. 12 DS04-27263-1E MB39A135 (6-1) Error Amp Block (Error Amp) The error amplifiers (Error Amp) detect the output voltage from the DC/DC converter and output to the current comparators (I Comp.). The output voltage setting resistor externally connected to FB allows an arbitrary output voltage to be set. In addition, since an external resistor and an external capacitor serially connected between COMP-FB allow an arbitrary loop gain to be set, it is possible for the system to compensate a phase stably. (6-2) Over Current Detection (Protection) Block (ILIM) It is the current detection circuit to restrict an output current (IO). The over current detection block (ILIM) compares an output waveform of the level converter (see Function description "(12) Level Converter Block") with the ILIM pin voltage in every cycle. As a load resistance (RO) drops, a load current (IO) increases. Therefore, the output waveform of the level converter exceeds the ILIM pin voltage At this time, the output current can be restricted by turning off FET on the high-side and suppressing a peak value of the inductor current. As a result, the output voltage (VO) should drop. Furthermore, if the output voltage drops and the electrical potential at the FB pin drops below 0.3 V, the oscillation frequency (fOSC) drops to 1/8. (7) Over-voltage Protection Circuit Block (OVP Comp.) The circuit protects a device connecting to the output when the output voltage (VO) rises. It compares 1.15 times (typ) of the internal reference voltage (INTREF) (0.7 V) that is non-inverting-entered into the error amplifier with the feed-back voltage that is inverting-entered into the error amplifier and if it detects the state where the latter is higher than the former by 50 s (typ). It stops the voltage output by setting the RS latch, setting the DRVH pin to "L" level, setting the DRVL pin to "H" level, turning off the high side FET and turning on the low-side FET. The conditions below cancel the protection function: * Setting CTL to "L". * Setting the power supply voltage below the UVLO threshold voltage (VTHL1 and VTHL2). (8) Under-voltage Protection Circuit Block (UVP Comp.) It protects a device connecting to the output by stopping the output when the output voltage (VO) drops. It compares 0.7 times (typ) of the internal reference voltage (INTREF) (0.7 V) that is non-inverting-entered into the error amplifier with the feed-back voltage that is inverting-entered into the error amplifier and if it detects the state where the latter is lower than the former by 512/fOSC s (typ), it stops the voltage output by setting the RS latch. The conditions below cancel the protection function: * Setting CTL to "L". * Setting the power supply voltage below the UVLO threshold voltage (VTHL1 and VTHL2). (9) Over temperature Protection Circuit Block (OTP) The circuit protects an IC from heat-destruction. If the temperature at the joint part reaches +160 C, the circuit stops the voltage output by discharging the capacitor connecting to the CS pin through the soft-stop discharging resistance (70 k typ) in the IC. In addition, if the temperature at the joint part drops to +135 C, the output restarts again through the soft-start function. Therefore, make sure to design the DC/DC power supply system so that the over temperature protection does not start frequently. DS04-27263-1E 13 MB39A135 (10) PFM Control Circuit Block (MODE) It sets the control mode of the IC and makes control at automatic PFM/PWM switching. MODE pin Control mode Features connection "L" (GND) "H" (VREF) Automatic PFM/ PWM switching Fixed PWM Highly-efficient at light load Stable oscillation frequency Stable switching ripple voltage Excellent in rapid load change characteristic at heavy load to light load Automatic PFM/PWM switching mode operation It compares the LX pin voltage with GND electrical potential at Di Comp. In the comparison, the negative voltage at the LX pin causes low-side FET to set on, positive voltage causes it to set off (Di Comp. method). As a result, the method restricts the back flow of the inductor current at a light load and makes the switching of the inductor current discontinuous (DCM). Such an operation allows the oscillation frequency to drop, resulting in high efficiency at a light load. (11) Output Block (DRV) The output circuit is configured in CMOS type for both of the high-side and the low-side, allowing the external N-ch MOS FET to drive. (12) Level Converter Block (LVCNV) The circuit detects and converts the current when the high-side FET turns on. It converts the voltage waveform between source side(VCC pin voltage) and the drain side (LX pin voltage) on the high-side FET into the voltage waveform for GND reference. (13) Control Block (CTL) The circuit controls on/off of the output from the IC. Control function table CTL DC/DC converter 14 Remarks L OFF Standby H ON DS04-27263-1E MB39A135 PROTECTION FUNCTION TABLE The following table shows the state of each pins when each protection function operates. Output of each pin after detection Protection Detection DC/DC output dropping function condition operation VREF VB DRVH DRVL Under Voltage Lock Out VB < 3.6 V (UVLO) VREF < 2.7 V < 2.7 V < 3.6V L L Self-discharge by load Under Voltage Protection (UVP) FB < 0.49V 3.3 V 5V L L Electrical discharge by soft-stop function Over Voltage Protection (OVP) FB > 0.805V 3.3 V 5V L H 0 V clamping Over current protection COMP > ILIM (ILIM) 3.3 V 5V Over Temperature Protection (OTP) Tj > + 160 C 3.3 V 5V L L CONTROL (CTL) CTL : HL (CS > 0.1 V) 3.3 V 5V L L DS04-27263-1E The output voltage is dropswitching switching ping to keep constant output current. Electrical discharge by soft-stop function 15 MB39A135 I/O PIN EQUIVALENT CIRCUIT DIAGRAM CTL pin VREF pin VCC VB CTL VREF ESD protection element GND GND VB pin CS pin VCC VREF VB CS GND FB pin VREF GND COMP pin VREF FB COMP GND GND (Continued) 16 DS04-27263-1E MB39A135 (Continued) ILIM pin RT pin VREF VREF VREF VB ILIM ILIM RT GND GND GND MODE pin CB, DRVH, LX pins VREF CB VREF VREF DRVH DRVH MODE LX LX GND DRVL pin GND GND VB DRVL PGND GND DS04-27263-1E 17 MB39A135 EXAMPLE APPLICATION CIRCUIT R21 VREF VIN (4.5 V to 25 V) MODE CS 13 C7 A R23 COMP R8-1 R8-2 <Soft-Start > ctl /uvp_out /otp_out VCC RT 1 2 8 Clock generator Bias Reg. C13 VREF /uvlo ovp_out <PFM Comp. > 5.5 A - + VB 7 11 Hi-side Drive 15 10 C9 FB <Error Amp> 14 R9 - + + <I Comp.> - + intref CLK RS-FF RQ 9 Drive Logic ILIM 6 5 L1 Vo Q1 C2-1 C2-2 C2-3 C5 DRVH LX DRVL PGND C14 C1-1 C1-2 Level Converter Vs 16 Q1 CB VB S Lo-side Drive R11 A D2 2.0 V 70 k <Di comp.> R12 - + <OVP Comp.> - + 50 s delay SQ ovp_out R <UVLO> intref x 1.15 V uvlo <UVP Comp.> - + VB UVLO 512/fOSC delay SQ R uvp_out VREF UVLO H : UVLO release otp_out intref x 0.7 V VB intref MB39A135 OTP ctl <REF> <CTL> ON/OFF CTL 4 (3.3 V) 3 12 VREF GND C15 18 DS04-27263-1E MB39A135 PARTS LIST Component Item Specification Q1 N-ch FET VDS = 30 V, ID = 8 A, Ron = 21 m D2 Diode VF = 0.35 V at IF = 0.2 A L1 Inductor 1.5 H (6.2 m, 8.9 A) Vendor Package NEC SO-8 Parts Name PA2755 Remark Dual type (2 elements) Onsemi SOD-523 BAT54XV2T1G TDK VLF10040T-1R5N C1-1 C1-2 Ceramic capacitor 22 F (25 V) Ceramic capacitor 22 F (25 V) TDK TDK 3225 3225 C3225JB1E226M 2 capacitors C3225JB1E226M in parallel C2-1 C2-2 C2-3 Ceramic capacitor 22 F (10 V) Ceramic capacitor 22 F (10 V) Ceramic capacitor 22 F (10 V) TDK TDK TDK 3216 3216 3216 C3216JB1A226M 3 capacitors C3216JB1A226M in parallel C3216JB1A226M C5 Ceramic capacitor 0.1 F (50 V) TDK 1608 C1608JB1H104K C7 Ceramic capacitor 0.022 F (50 V) TDK 1608 C1608JB1H223K C9 Ceramic capacitor 820 pF (50 V) TDK 1608 C1608CH1H821J C13 Ceramic capacitor 0.01 F (50 V) TDK 1608 C1608JB1H103K C14 Ceramic capacitor 1.0 F (16 V) TDK 1608 C1608JB1C105K C15 Ceramic capacitor 0.1 F (50 V) TDK 1608 C1608JB1H104K R8-1 R8-2 Resistor Resistor 1.6 k 9.1 k SSM SSM 1608 1608 RR0816P162D RR0816P912D R9 Resistor 15 k SSM 1608 RR0816P153D R11 Resistor 56 k SSM 1608 RR0816P563D R12 Resistor 56 k SSM 1608 RR0816P463D R21 Resistor 82 k SSM 1608 RR0816P823D R23 Resistor 22 k SSM 1608 RR0816P223D NEC Onsemi TDK SSM 2 resistors in serial : NEC Electronics Corporation : ON Semiconductor Corporation : TDK Corporation : SUSUMU Co., LTD DS04-27263-1E 19 MB39A135 APPLICATION NOTE Setting method for PFM/PWM and fixed PWM modes For the setting method for each mode, see "Function description (10) PFM Control Circuit Block (MODE)". Cautions at PFM/PWM mode If a load current drops rapidly because of rapid load change and others, it tends to take a lot of time to restore overshooting of an output voltage. As a result, the over-voltage protection may operate. In this case, solution are possible by the addition of the load resistance of value to be able to restore the output voltage in the over-voltage detection time. Setting method of output voltage Set it by adjusting the output voltage setting zero-power resistance ratio. VO = R1 + R2 x 0.7 R2 VO R1, R2 : Output setting voltage [V] : Output setting resistor value [] VO R1 FB R2 Make sure that the setting does not exceed the maximum on-duty. Calculate the on-duty by the following formula. DMAX_Min = DMAX_Min VIN VO RON_Main RON_Sync IOMAX 20 VO + RON_Main x IOMAX VIN - RON_Main x IOMAX + RON_Sync x IOMAX : Minimum value of the maximum on-duty cycle : Power supply voltage of switching system [V] : Output setting voltage [V] : High-side FET ON resistance [] : Low-side FET ON resistance [] : Maximum load current [A] DS04-27263-1E MB39A135 Oscillation frequency setting method Set it by adjusting the RT pin resistor value. fOSC = 1.09 RRT x 40 x 10 - 12 + 300 x 10 - 9 RRT fOSC : RT resistor value [] : Oscillation frequency [Hz] The oscillation frequency must set for on-time (tON) to become 300 ns or more. Calculate the on-time by the following formula. tON = VO VIN x fOSC tON VIN VO fOSC DS04-27263-1E : On-time [s] : Power supply voltage of switching system [V] : Output setting voltage [V] : Oscillation frequency [Hz] 21 MB39A135 Setting method of soft-start time Calculate the soft-start time by the following formula. tS = 1.4 x 105 x CCS ts CCS : Soft-start time [s] (Time to becoming output 100%) : CS pin capacitor value [F] Calculate delay time until the soft-start beginning by the following formula: td1 = 30 x CVB + 290 x CVREF + 1.455 x 104 x CCS td1 CCS CVB CVREF : Delay time including VB voltage and VREF voltage starts [s] : CS pin capacitor value [F] : VB pin capacitor value [F] : VREF pin capacitor value [F] (0.1 F Typ) Calculate the discharge time at the soft-stop by the following formula: tdis = 1.44 x 105 x CCS tdis CCS : Discharge time [s] : CS pin capacitor value [F] In addition, calculate the delay time to the discharge starting by the following formula: td3 = 7.87 x 104 x CCS td3 CCS : Delay time until discharge start [s] : CS pin capacitor value [F] ts tdis CTL VO td1 22 td3 DS04-27263-1E MB39A135 Setting method of over current detection value It is possible to set it by adjusting the over current detection setting zero-power resistance ratio when over current detection (ILIM) is used. Calculate the over current detection setting resistor value by the following formula. 3.3 x R2 -0.3 R1 + R2 6.8 x RON ILIM = + VIN - VO L x (200 x 10 - 9 - VO 2 x fOSC x VIN ) 200 x 103 R1 + R2 30 x 103 ILIM R1, R2 L VIN VO fOSC RON : Over current detection value [A] : ILIM setting resistor value []* : Inductor value [H] : Power supply voltage of switching system [V] : Output setting voltage [V] : Oscillation frequency [Hz] : High-side FET ON resistance [] * : Since the over current detection value depends on the on-resistance of FET, the over current detection setting resistor value ratio should be adjusted in consideration of the temperature characteristics of the on-resistance. When the temperature at the FET joint part rises by + 100 C, the on-resistance of FET increases to about 1.5 times. Inductor current VREF Over current detection value ILIM R1 IO ILIM* R2 0 Time * : If the over current detection function is not used, connect the ILIM pin to the VREF pin. DS04-27263-1E 23 MB39A135 Selection of smoothing inductor The inductor value selects the value that the ripple current peak-to-peak value of the inductor becomes 50% or less of the maximum load current as a rough standard. Calculate the inductor value in this case by the following formula. L VIN - VO LOR x IOMAX L IOMAX LOR VIN VO fOSC x VO VIN x fOSC : Inductor value [H] : Maximum load current [A] : Ripple current peak-to-peak value of Maximum load current ratio (=0.5) : Power supply voltage of switching system [V] : Output setting voltage [V] : Oscillation frequency [Hz] An inductor ripple current value limited on the principle of operation is necessary for this device. However, when it uses the high-side FET of the low Ron resistance, the switching ripple voltage become small, and the ripple current value be insufficient. This should be solved by the oscillation frequency or reducing the inductor value. Select the one of the inductor value that meets a requirement listed below. L VIN - VO VRON L VIN VO fOSC VRON RON x VO VIN x fOSC x RON : Inductor value [H] : Power supply voltage of switching system [V] : Output setting voltage [V] : Oscillation frequency [Hz] : Ripple voltage [V] (20 mV or more is recommended) : High-side FET ON resistance [] It is necessary to calculate the maximum current value that flows to the inductor to judge whether the electric current that flows to the inductor is a rated value or less. Calculate the maximum current value of the inductor by the following formula. ILMAX IoMAX + ILMAX IoMAX IL L VIN VO fOSC 24 IL 2 , IL = VO VIN - VO x L VIN x fOSC : Maximum current value of inductor [A] : Maximum load current [A] : Ripple current peak-to-peak value of inductor [A] : Inductor value [H] : Power supply voltage of switching system [V] : Output setting voltage [V] : Oscillation frequency [Hz] DS04-27263-1E MB39A135 Inductor current ILMAX IoMAX IL t 0 DS04-27263-1E 25 MB39A135 Selection of SWFET The switching ripple voltage generated between drain and sources on high-side FET is necessary for this device operation. Select the one of the SWFET of on-resistance that satisfies the following formula. RON_Main VRON_Main , RON_Main IL RON_Main IL VRON_Main ILIM VRONMAX VRONMAX IL ILIM + 2 : High-side FET ON resistance [] : Ripple current peak-to-peak value of inductor [A] : High-side FET ripple voltage [V] (20 mV or more is recommended) : Over current detection value [A] : Maximum current sense voltage [V] (240 mV or less is recommended) Select FET ratings with a margin enough for the input voltage and the load current. Ratings with the over-current detection setting value or more are recommended. Calculate a necessary rated value of high side FET and low-side FET by the following formula. ID > IoMAX + ID IoMAX IL IL 2 : Rated drain current [A] : Maximum load current [A] : Ripple current peak-to-peak value of inductor [A] VDS > VIN VDS VIN : Rated voltage between drain and source [V] : Power supply voltage of switching system [V] VGS > VB VGS VB : Rated voltage between gate and source [V] : VB voltage [V] Moreover, it is necessary to calculate the loss of SWFET to judge whether a permissible loss of SWFET is a rated value or less. Calculate the loss on high-side FET by the following formula. PMainFET = PRON_Main + PSW_Main PMainFET PRON_Main PSW_Main 26 : High-side FET loss [W] : High-side FET conduction loss [W] : High-side FET SW loss [W] DS04-27263-1E MB39A135 High-side FET conduction loss VO VIN PRON_Main = IoMAX2 x PRON_Main IOMAX VIN VO RON_Main x RON_Main : High-side FET conduction loss [W] : Maximum load current [A] : Power supply voltage of switching system [V] : Output voltage [V] : High-side FET ON resistance [] High-side FET SW loss PSW_Main = VIN x fOSC x (Ibtm x tr + Itop x tf) 2 PSW_Main VIN fOSC Ibtm Itop tr tf : High-side FET SW loss [W] : Power supply voltage of switching system [V] : Oscillation frequency (Hz) : Ripple current bottom value of inductor [A] : Ripple current top value of inductor [A] : Turn-on time on high-side FET [s] : Turn-off time on high-side FET [s] Calculate the Ibtm, Itop, tr and the tf simply by the following formula. IL 2 Ibtm = IoMAX - IL 2 Itop = IoMAX - tr = Qgd x 4 5 - Vgs (on) IOMAX IL Qgd Vgs (on) DS04-27263-1E tf = Qgd x 1 Vgs (on) : Maximum load current [A] : Ripple current peak-to-peak value of inductor [A] : Quantity of charge between gate and drain on high-side FET [C] : Voltage between gate and sources in Qgd on high-side FET [V] 27 MB39A135 Calculate the loss on low-side FET by the following formula. PSyncFET = PRon_Sync* = IoMAX2 x (1 - PSyncFET PRon_Sync IOMAX VIN VO Ron_Sync VO ) x Ron_Sync VIN : Low-side FET loss [W] : Low-side FET conduction loss [W] : Maximum load current [A] : Power supply voltage of switching system [V] : Output voltage [V] : Low-side FET on-resistance [] * : The transition voltage of the voltage between drain and source on low-side FET is generally small, and the switching loss is omitted here for the small one as it is possible to disregard it. The gate drive power of SWFET is supplied by LDO in IC, therefore all of SWFET allowable maximum total charge (QgTotalMax) is determined by the following formula. 0.095 fOSC QgTotalMax QgTotalMax fOSC : SWFET allowable maximum total charge [C] : Oscillation frequency [Hz] Selection of fly-back diode When the conversion efficiency is valued, the improved property of the conversion efficiency is possible by the addition of the fly-back diode. thought it is usally unnecessary. The effect is achieved in the condition where the oscillation frequency is high or output voltage is lower. Select schottky barrier diode (SBD) that the forward current is as small as possible. In this DC/DC control IC, the period for the electric current flows to fly-back diode is limited to synchronous rectification period (60 ns x 2) because of using the synchronous rectification method. Therefore, select the one that the electric current of fly-back diode doesn't exceed ratings of forward current surge peak (IFSM).Calculate the forward current surge peak ratings of fly-back diode by the following formula. IFSM IoMAX + IFSM IoMAX IL 28 IL 2 : Forward current surge peak ratings of fly-back diode [A] : Maximum load current [A] : Ripple current peak-to-peak value of inductor [A] DS04-27263-1E MB39A135 Calculate ratings of the fly-back diode by the following formula: VR_Fly > VIN VR_Fly VIN : Reverse voltage of fly-back diode direct current [V] : Power supply voltage of switching system [V] Selection of output capacitor This device supports a small ceramic capacitor of the ESR. The ceramic capacitor that is low ESR is an ideal to reduce the ripple voltage compared with other capacitor. Use the tantalum capacitor and the polymer capacitor of the low ESR when a mass capacitor is needed as the ceramic capacitor can not support. To the output voltage, the ripple voltage by the switching operation of DC/DC is generated. Discuss the lower bound of output capacitor value according to an allowable ripple voltage. Calculate the output ripple voltage from the following formula. VO = ( 1 2 x fOSC x CO VO ESR IL CO fOSC + ESR) x IL : Switching ripple voltage [V] : Series resistance component of output capacitor [] : Ripple current peak-to-peak value of inductor [A] : Output capacitor value [F] : Oscillation frequency [Hz] Notes: * The ripple voltage can be reduced by raising the oscillation frequency and the inductor value besides capacitor. * Capacitor has frequency characteristic, the temperature characteristic, and the electrode bias characteristic, etc. The effective capacitor value might become extremely small depending on the condition. Note the effective capacitor value in the condition. Calculate ratings of the output capacitor by the following formula: VCO > VO VCO VO : Withstand voltage of the output capacitor [V] : Output voltage [V] Note: Select the capacitor rating with withstand voltage allowing a margin enough for the output voltage. DS04-27263-1E 29 MB39A135 In addition, use the allowable ripple current with an enough margin, if it has a rating. Calculate an allowable ripple current of the output capacitor by the following formula. IL Irms 23 Irms IL : Allowable ripple current (effective value) [A] : Ripple current peak-to-peak value of inductor [A] Selection of input capacitor Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the tantalum capacitor and the polymer capacitor of the low ESR when a mass capacitor is needed as the ceramic capacitor can not support. To the power supply voltage, the ripple voltage by the switching operation of DC/DC is generated. Discuss the lower bound of input capacitor according to an allowable ripple voltage. Calculate the ripple voltage of the power supply from the following formula. IOMAX CIN VIN = VIN IOMAX CIN VIN VO fOSC ESR IL x VO VIN x fOSC + ESR x (IOMAX + IL 2 ) : Switching system power supply ripple voltage peak-to-peak value [V] : Maximum load current value [A] : Input capacitor value [F] : Power supply voltage of switching system [V] : Output setting voltage [V] : Oscillation frequency [Hz] : Series resistance component of input capacitor [] : Ripple current peak-to-peak value of inductor [A] Notes: * The ripple voltage can be reduced by raising the oscillation frequency besides capacitor. * Capacitor has frequency characteristic, the temperature characteristic, and the electrode bias characteristic, etc. The effective capacitor value might become extremely small depending on the condition. Note the effective capacitor value in the condition. Calculate ratings of the input capacitor by the following formula: VCIN > VIN VCIN VIN : Withstand voltage of the input capacitor [V] : Power supply voltage of switching system [V] Note: Select the capacitor rating with withstand voltage with margin enough for the input voltage. 30 DS04-27263-1E MB39A135 In addition, use the allowable ripple current with an enough margin, if it has a rating. Calculate an allowable ripple current by the following formula. Irms IOMAX x Irms IOMAX VIN VO VO x (VIN - VO) VIN : Allowable ripple current (effective value) [A] : Maximum load current value [A] : Power supply voltage of switching system [V] : Output voltage [V] Selection of boot strap diode Select Schottky barrier diode (SBD), that forward current is as small as possible. The electric current that drives the gate of high-side FET flows to SBD of the bootstrap circuit. Calculate the mean current by the following formula. Select it so as not to exceed the electric current ratings. ID Qg x fOSC ID Qg fOSC : Forward current [A] : Total quantity of charge of gate on high-side FET [C] : Oscillation frequency [Hz] Calculate ratings of the boot strap diode by the following formula: VR_BOOT > VIN VR_BOOT VIN : Reverse voltage of boot strap diode direct current [V] : Power supply voltage of switching system [V] Selection of boot strap capacitor To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a minimum value as a target is assumed the capacitor which can store electric charge 10 times that of the Qg on high-side FET. And select the boot strap capacitor. CBOOT 10 x CBOOT Qg VB Qg VB : Boot strap capacitor value [F] : Amount of gate charge on high-side FET [C] : VB voltage [V] Calculate ratings of the boot strap capacitor by the following formula: VCBOOT > VIN VCBOOT VIN DS04-27263-1E : Withstand voltage of the boot strap capacitor [V] : Power supply voltage of switching system [V] 31 MB39A135 Design of phase compensation circuit Assume the phase compensation circuit of 1pole-1zero to be a standard in this device. 1pole-1zero phase compensation circuit VO Rc R1 FB Cc + R2 INTREF To I Comp. COMP Error Amp As for crossover frequency (fCO) that shows the band width of the control loop of DC/DC. The higher it is, the more excellent the rapid response becomes, however, the possibility of causing the oscillation due to phase margin shortage increases. Though this crossover frequency (fCO) can be arbitrarily set, make 1/10 of the oscillation frequencies (fosc) a standard, and set it to the upper limit. Moreover, set the phase margin at least to 30, and 45 or more if possible as a reference. Set the constants of Rc and Cc of the phase compensation circuit using the following formula as a target: RC = CC = 32 (VIN - VO) ALVCNV x RON_Main x fCO x 2 x CO x VO VIN x fOSC x L x IOMAX x R1 CO x VO RC x IOMAX RC CC VIN VO fOSC IOMAX L CO RON_Main R1 ALVCNV : Phase compensation resistor value [] : Phase compensation capacitor value [F] : Power supply voltage of switching system [V] : Output setting voltage [V] : Oscillation frequency [Hz] : Maximum load current value [A] : Inductor value [H] : Output capacitor value [F] : High-side FET ON resistance [] : Output setting resistor value [] fCO : Cross-over frequency (arbitrary setting) [Hz] : Level converter voltage gain [V/V] On-duty 50% : ALVCNV = 6.8 On-duty > 50% : ALVCNV = 13.6 DS04-27263-1E MB39A135 VB pin capacitor 1 F is assumed to be a standard, and when Qg of SWFET used is large, it is necessary to adjust it. To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a minimum value as a target is assumed the capacitor which can store electric charge 100 times that of the Qg on high-side FET. And select it. CVB 100 x CVB Qg VB Qg VB : VB pin capacitor value [F] : Total amount of gate charge of high-side FET and low-side FET [C] : VB voltage [V] Calculate ratings of the VB pin capacitor by the following formula: VCVB > VB VCVB VB DS04-27263-1E : Withstand voltage of the VB pin capacitor [V] : VB voltage [V] 33 MB39A135 VB regulator In the condition for which the potential difference between VCC and VB is insufficient, the decrease in the voltage of VB happens because of power output on-resistance and load current (mean current of all external FET gate driving current and load current of internal IC) of the VB regulator. Stop the switching operation when the voltage of VB decreases and it reaches threshold voltage (VTHL1) of the under voltage lockout protection circuit. Therefore, set oscillation frequency or external FET or I/O potential difference of the VB regulator using the following formula as a target when you use this IC. VCC VB (VTHL1) + (Qg x fOSC + ICC) x RVB VCC VB (VTHL1) Qg fOSC ICC RVB : Power supply voltage [V] (VIN) : Threshold voltage of VB under-voltage lockout protection circuit [V](3.8 [V] (Max)) : Total amount of gate charge of high-side FET and low-side FET [C] : Oscillation frequency [Hz] : Power supply current [A] (2.7 x 10 - 3 [A] =: Load current of VB (LDO)) : VB output on-resistance [] (100 (The reference value at VCC = 4.5 V)) If the I/O potential difference is small, the problem can be solved by connecting the VB pin and the VCC pin. The conditions of the input voltage range are as follows: VIN input voltage ranges: 4.5 V 25 V 6.0 V (1) (3) (1) For 4.5 V < VIN < 6.0 V Connect VB pin to VCC. (2) When the input voltage range steps over 6.0 V Normal use (VCC to VB not connected) (2) (3) For 6.0 V VIN Normal use (VCC to VB not connected) Note that if the I/O potential difference is not enough when used, use the actual machine to check carefully the operations at the normal operation, start operation, and stop operation. In particular, care is needed when the input voltage range over 6 V. 34 DS04-27263-1E MB39A135 Power dissipation and the thermal design As for this IC, considerations of the power dissipation and thermal design are not necessary in most cases because of its high efficiency. However, they are necessary for the use at the conditions of a high power supply voltage, a high oscillation frequency, high load, and the high temperature. Calculate IC internal loss (PIC) by the following formula. PIC = VCC x (ICC + Qg x fOSC) PIC VCC ICC Qg fOSC : IC internal loss [W] : Power supply voltage (VIN) [V] : Power supply current [A] (2.7 mA Max) : All SWFET total quantity of charge [C] (Total with Vgs = 5 V) : Oscillation frequency [Hz] Calculate junction temperature (Tj) by the following formula. Tj = Ta + ja x PIC Tj Ta ja PIC DS04-27263-1E : Junction temperature [ C] (150 C Max) : Ambient temperature [ C] : TSSOP-16 Package thermal resistance (101 C/W) : IC internal loss [W] 35 MB39A135 Board layout Consider the points listed below and do the layout design. * Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor connected with the VCC and VB pins, and GND pin of the switching system parts with switching system GND (PGND). Connect other GND connection pins with control system GND (AGND), and separate each GND, and try not to pass the heavy current path through the control system GND (AGND) as much as possible. In that case, connect control system GND (AGND) and switching system GND (PGND) right under IC. * Connect the switching system parts as much as possible on the surface. Avoid the connection through the through-hole as much as possible. * As for GND pins of the switching system parts, provide the through hole at the proximal place, and connect it with GND of internal layer. * Pay the most attention to the loop composed of input capacitor (CIN), SWFET, and fly-back diode (SBD). Consider making the current loop as small as possible. * Place the boot strap capacitor (CBOOT) proximal to CB and LX pins of IC as much as possible. * This device monitors the voltage between drain and source on high-side FET as voltage between VCC and LX pins. Place the input capacitor (CIN) and the high-side FET proximally as much as possible. Draw out the wiring to VCC pin from the proximal place to the input capacitor. As for the net of the LX pin, draw it out from the proximal place to the source pin on high-side FET. Moreover, a large electric current flows momentary in the net of the LX pin. Wire the linewidth of about 0.8 mm to be a standard, as short as possible. * Large electric current flows momentary in the net of DRVH and DRVL pins connected with the gate of SWFET. Wire the linewidth of about 0.8mm to be a standard, as short as possible. * By-pass capacitor (CVCC, CVREF, CVB) connected with VREF, VCC, and VB, and the resistor (RRT) connected with the RT pin should be placed close to the pin as much as possible. Also connect the GND pin of the bypass capacitor with GND of internal layer in the proximal through-hole. * Consider the net connected with RT, FB, and the COMP pins to keep away from a SW system parts as much as possible because it is sensitive to the noise. Moreover, place the output voltage setting resistor and the phase compensation circuit element connected with this net close to the IC as much as possible, and try to make the net as short as possible. In addition, for the internal layer right under the installing part, provide the control system GND (AGND) of few ripple and few spike noises, or provide the ground plane of the power supply voltage as much as possible. Switching system parts : Input capacitor (CIN), SWFET, Fly-back diode (SBD), Inductor (L), Output capacitor (CO) Layout example of IC Layout example of switching components To the VCC pin Through-hole High-side FET AGND Through-hole 1pin AGND RRT VIN To the LX pin CIN Low-side FET CVREF CVB PGND CBOOT CVCC SBD(option) CO L PGND Surface 36 Internal layer PGND Vo Output voltage Vo feedback DS04-27263-1E MB39A135 REFERENCE DATA Conversion Efficiency Conversion Efficiency vs. Load Current Load Regulation Output Voltage vs. Load Current 1.30 VIN = 12 V VO = 1.2 V fosc = 300 kHz Ta = + 25C 95 90 85 80 PFM/PWM 75 70 VIN =12 V VO =1.2 V MODE = VREF fosc = 300 kHz Ta = + 25C 1.28 Output Voltage VO (V) Conversion Efficiency (%) 100 Fixed PWM 65 1.26 1.24 1.22 1.20 1.18 1.16 1.14 1.12 60 0.01 0.1 1 10 1.10 0 1 Load Current IO (A) 2 3 4 5 Load Current IO (A) Load Sudden Change Waveform IO : 1 A/div 2A VIN = 12 V VO = 1.2 V IO = 0 2 A fOSC = 300 kHz, Ta = + 25 C 0A 100 s/div VO : 200 mV/div (1.2 V offset) CTL Start-up Waveform CTL Stop Waveform CTL : 5 V/div CTL : 5 V/div VO: 1V/div 1 ms/div VO: 1V/div VIN = 12 V, VO = 1.2 V, Io = 5 A (0.24 ) fosc = 300 kHz, Ta = + 25 C,Soft start setting time = 3.0 ms 1 ms/div (Continued) DS04-27263-1E 37 MB39A135 (Continued) Nomal operation Over current protection Under voltage protection operation waveform VO : 0.5 V/div 1 VIN = 12 V VO = 1.2 V fOSC = 300 kHz Ta = + 25 C CS : 2 V/div 2 LX : 10 V/div 3 IO : 10 A/div 4 500 s/div Nomal operation 38 Over current Under voltage protection protection operation operation DS04-27263-1E MB39A135 USAGE PRECAUTION 1. Do not configure the IC over the maximum ratings. If the IC is used over the maximum ratings, the LSI may be permanently damaged. It is preferable for the device to normally operate within the recommended usage conditions. Usage outside of these conditions can have an adverse effect on the reliability of the LSI. 2. Use the device within the recommended operating conditions. The recommended values guarantee the normal LSI operation under the recommended operating conditions. The electrical ratings are guaranteed when the device is used within the recommended operating conditions and under the conditions stated for each item. 3. Printed circuit board ground lines should be set up with consideration for common impedance. 4. Take appropriate measures against static electricity. * * * * Containers for semiconductor materials should have anti-static protection or be made of conductive material. After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. Work platforms, tools, and instruments should be properly grounded. Working personnel should be grounded with resistance of 250 k to 1 M in serial body and ground. 5. Do not apply negative voltages. The use of negative voltages below - 0.3 V may make the parasitic transistor activated, and can cause malfunctions. ORDERING INFORMATION Part number MB39A135PFT-E1 Package Remarks 16-pin plastic TSSOP (FPT-16P-M08) Lead Free version EV BOARD ORDERING INFORMATION Part number EV board version No. Remarks MB39A135EVB-01 MB39A135EVB-01 Rev2.0 TSSOP-16P RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION The LSI products of Fujitsu Microelectronics with "E1" are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE). A product whose part number has trailing characters "E1" is RoHS compliant. DS04-27263-1E 39 MB39A135 MARKING FORMAT (Lead Free version) 39A135 1XXX INDEX 40 Lead Free version DS04-27263-1E MB39A135 LABELING SAMPLE (Lead free version) Lead free mark JEITA logo MB123456P - 789 - GE1 (3N) 1MB123456P-789-GE1 1000 (3N)2 1561190005 107210 JEDEC logo G Pb QC PASS PCS 1,000 MB123456P - 789 - GE1 2006/03/01 ASSEMBLED IN JAPAN MB123456P - 789 - GE1 1/1 0605 - Z01A 1000 1561190005 The part number of a lead-free product has the trailing characters "E1". DS04-27263-1E 41 MB39A135 PACKAGE DIMENSIONS 16-pin plastic TSSOP Lead pitch 0.65 mm Package width x package length 4.40 mm x 4.96 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.20 mm Max Weight 0.06 g (FPT-16P-M08) 16-pin plastic TSSOP (FPT-16P-M08) Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) * : These dimensions do not include resin protrusion. *4.960.10(.195.004) 16 0.1450.045 (.0057.0018) 9 *4.400.10 6.400.20 (.173.004) (.252.008) INDEX Details of "A" part +0.10 1.10 -0.15 (Mounting height) +0.04 .043 -0.06 LEAD No. 1 8 0.65(.026) "A" 0.240.08 (.009.003) 0.13(.005) M 0~8 0.600.15 (.024.006) 0.100.05 (.004.002) (Stand off) 0.10(.004) C 42 2007-2008 FUJITSU MICROELECTRONICS LIMITED F16021S-c-1-4 Dimensions in mm (inches). Note: The values in parentheses are reference values. DS04-27263-1E MB39A135 MEMO DS04-27263-1E 43 MB39A135 FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. 151 Lorong Chuan, #05-08 New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm.3102, Bund Center, No.222 Yan An Road(E), Shanghai 200002, China Tel: +86-21-6335-1560 Fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road Tsimshatsui, Kowloon Hong Kong Tel: +852-2377-0226 Fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business & Media Promotion Dept.