MB39A135PFT-XXE1 - Fujitsu Limited

FUJITSU MICROELECTRONICS

DATA SHEET

2008.8

ASSP for Power Management Applications

(General-purpose DC/DC converter)

1ch PFM/PWM DC/DC converter IC

with synchronous rectification

MB39A135

■DESCRIPTION

MB39A135 is 1ch step-down DC/DC converter IC of the current mode N-ch/N-ch synchronous rectification meth-

od.

It contains the enhanced protection features, and supports the ceramic capacitor. MB39A135 realizes rapid

response, high efficiency, and low ripple voltage, and its high-frequency operation enables the miniaturization of

inductor and I/O capacitors.

■FEATURES

• High efficiency

• For frequency setting by external resistor : 100 kHz to 1 MHz

• Error Amp threshold voltage : 0.7 V ± 1.0%

• Minimum output voltage value : 0.7 V

• Wide range of power-supply voltage : 4.5 V to 25 V

• PFM/PWM auto switching mode and fixed PWM mode selectable

• With built-in over voltage protection function

• With built-in under voltage protection function

• With built-in over current protection function

• With built-in overtemperature protection function

• With built-in soft start/stop circuit without load dependence

• With built-in synchronous rectification type output steps for N-ch MOS FET

• Standby current : 0 µA (Typ)

• Small package : TSSOP-16

■APPLICATIONS

• Digital TV

• Photocopiers

• Surveillance cameras

• Set-top boxes (STB)

• DVD players, DVD recorders

•Projectors

• IP phones

• Vending machines

• Consoles and other non-portable devices

DS04-27263-1E

MB39A135

2DS04-27263-1E

■PIN ASSIGNMENT

■PIN DESCRIPTIONS

Pin No. Pin Name I/O Description

1MODEI

PFM/PWM switch pin.

It becomes fixed PWM operation with the VREF connection, and it

becomes PFM/PWM operation with the GND connection.

2RT⎯Resistor connection pin for oscillation frequency setting.

3 VREF O Reference voltage output pin.

4 CTL I Control pin.

5PGND⎯Ground pin.

6DRVLO

Output pin for external low-side FET gate drive.

7VBO

Bias voltage output pin.

8VCC⎯Power supply pin for reference voltage and control circuit.

9LX⎯Inductor and external high-side FET source connection pin.

10 DRVH O Output pin for external high-side FET gate drive.

11 CB ⎯The connection pin for boot strap capacitor.

12 GND ⎯Ground pin.

13 CS I Soft-start time setting capacitor connection pin.

14 FB I Error amplifier inverted input pin.

15 COMP O Error amplifier (Error Amp) output pin.

16 ILIM I Over current detection level setting voltage input pin.

(TOP VIEW)

(FPT-16P-M08)

MODE ILIM

RT COMP

VREF FB

CTL CS

PGND GND

DRVL CB

VB DRVH

VCC

8LX

MB39A135

DS04-27263-1E 3

■BLOCK DIAGRAM

−

COMP

ILIM

VREF

5.5 µA

<Soft-Start >

/uvlo

ovp_out

ctl

/uvp_out

/otp_out

70 kΩ

intref

intref

x 1.15 V

intref

x 0.7 V

50 µs

delay

512/fOSC

delay

ovp_out

uvp_out

<REF> <CTL>intref

(3.3 V)

312

ON/OFF

GNDVREF

CTL

ctl

UVLO

<UVLO>

VREF

UVLO

uvlo

H : UVLO

release

OTP

otp_out

Drive

Logic VB

Lo-side

Drive

Level

Converter

CLK

RS-FF

Drive

Hi-side

Bias

Reg.

Clock

generator

2.0

VCC

MODE

DRVH

DRVL

PGND

MB39A135

4DS04-27263-1E

■ABSOLUTE MAXIMUM RATINGS

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter Symbol Condition Rating Unit

Min Max

Power supply voltage VVCC VCC pin ⎯27 V

CB pin input voltage VCB CB pin ⎯32 V

LX pin input voltage VLX LX pin ⎯27 V

Voltage between CB and LX VCBLX ⎯⎯7V

Control input voltage VICTL pin ⎯27 V

Input voltage

VFB FB pin ⎯VVREF + 0.3 V

VILIM ILIM pin ⎯VVREF + 0.3 V

VCS CS pin ⎯VVREF + 0.3 V

VMODE MODE pin ⎯VVB + 0.3 V

Output current IOUT

DC,

DRVL pin,

DRVH pin

⎯60 mA

Power dissipation PDTa ≤ + 25 °C⎯1237 mW

Storage temperature TSTG ⎯ − 55 + 150 °C

MB39A135

DS04-27263-1E 5

■RECOMMENDED OPERATING CONDITIONS

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

Parameter Symbol Condition Value Unit

Min Typ Max

Power supply voltage VVCC ⎯4.5 ⎯25.0 V

CB pin input voltage VCB ⎯⎯⎯30 V

Reference voltage output

current IVREF ⎯ − 100 ⎯⎯µA

Bias output current IVB ⎯ − 1 ⎯⎯mA

CTL pin input voltage VICTL pin 0 ⎯25 V

Input voltage

VFB FB pin 0 ⎯VVREF V

VILIM ILIM pin 0.3 ⎯1.94 V

VCS CS pin 0 ⎯VVREF V

VMODE MODE pin 0 ⎯VVREF V

Peak output current IOUT DRVH pin, DRVL pin

Duty ≤ 5% (t = 1 / fOSC × Duty) − 1200 ⎯ + 1200 mA

Operation frequency range fOSC ⎯100 500 1000 kHz

Timing resistor RRT ⎯⎯47 ⎯kΩ

Soft start capacitor CCS ⎯0.0075 0.0180 ⎯µF

CB pin capacitor CCB ⎯⎯0.1 1.0 µF

Reference voltage output

capacitor CVREF ⎯⎯0.1 1.0 µF

Bias voltage output

capacitor CVB ⎯⎯1.0 10 µF

Operating ambient

temperature Ta ⎯ − 30 + 25 + 85 °C

MB39A135

6DS04-27263-1E

■ELECTRICAL CHARACTERISTICS

(Ta = +25 °C, VCC = 15 V, CTL = 5 V VREF = 0 A, VB = 0 A)

(Continued)

Parameter Sym-

bol

No. Condition Value Unit

Min Typ Max

Reference

Voltage Block

[REF]

Output voltage VVREF 3⎯3.24 3.30 3.36 V

Input stability VREF

LINE 3VCC = 4.5 V to 25 V ⎯110mV

Load stability VREF

LOAD 3VREF = 0 A to −100 µA⎯110mV

Short-circuit

output current

VREF

IOS 3VREF = 0 V −14.5 −10.0 −7.5 mA

Bias Voltage

Block

[VB Reg.]

Output voltage VVB 7⎯4.85 5.00 5.15 V

Input stability VB

LINE 7VCC = 6 V to 25 V ⎯10 100 mV

Load stability VB

LOAD 7VB = 0 A to −1 mA ⎯10 100 mV

Short-circuit

output current

IOS 7VB = 0 V −130 −90 −65 mA

Under voltage

Lockout Protec-

tion Circuit Block

[UVLO]

Threshold voltage VTLH1 7 VB 4.0 4.2 4.4 V

VTHL1 7 VB 3.4 3.6 3.8 V

Hysteresis width VH1 7VB ⎯0.6* ⎯V

Threshold voltage VTLH2 3 VREF 2.7 2.9 3.1 V

VTHL2 3 VREF 2.5 2.7 2.9 V

Hysteresis width VH2 3VREF ⎯0.2* ⎯V

Soft-start /

Soft-stop Block

[Soft-Start,

Soft-Stop]

Charge current ICS 13 CTL = 5 V, CS = 0 V −7.9 −5.5 −4.2 µA

Soft-start

end voltage VCS 13 CTL = 5V 2.2 2.4 2.6 V

Electrical discharge

resistance at

soft-stop

RDISCG 13 CTL = 0 V, CS = 0.5 V 49 70 91 kΩ

Soft-stop

end voltage VDISCG 13 CTL = 0 V ⎯0.1* ⎯V

Clock

Generator Block

[OSC]

Oscillation

frequency fOSC 2RT = 47 kΩ450 500 550 kHz

Oscillation

frequency when

under voltage is

detected

fSHORT 2RT = 47 kΩ⎯62.5 ⎯kHz

Frequency

Temperature

variation

df/dT 2 Ta = −30 °C to + 85 °C⎯3* ⎯%

MB39A135

DS04-27263-1E 7

(Ta = +25 °C, VCC = 15 V, CTL = 5 V VREF = 0 A, VB = 0 A)

(Continued)

Parameter Sym-

bol

No. Condition Value Unit

Min Typ Max

Error Amp

Block

[Error Amp]

Threshold

voltage

EVTH 14 ⎯0.693 0.700 0.707 V

EVTHT 14 Ta = −30 °C to + 85 °C 0.689* 0.700* 0.711* V

Input current IFB 14 FB = 0 V −0.1 0 +0.1 µA

Output current ISOURCE 15 FB = 0 V, COMP = 1 V −390 −300 −210 µA

ISINK 15 FB = VREF, COMP = 1 V 8.4 12.0 16.8 mA

Output clamp

voltage VILIM 15 FB = 0 V, ILIM = 1.5 V 1.35 1.50 1.65 V

ILIM pin

input current IILIM 16 FB = 0 V, ILIM = 1.5 V −10+1µA

Over-voltage

Protection

Circuit Block

[OVP Comp.]

Over-voltage

detecting voltage VOVP 14 FB pin 0.776 0.805 0.835 V

Over-voltage

detection time tOVP 14 ⎯49 70 91 µs

Under-voltage

Protection

Circuit Block

[UVP Comp.]

Under-voltage

detecting voltage VUVP 14 FB pin 0.450 0.490 0.531 V

Under-voltage

detection time tUVP 14 ⎯⎯

512/

fOSC ⎯s

Over-tempera-

ture Protection

Circuit Block

[OTP]

Detection

temperature

TOTPH ⎯Junction temperature ⎯+160* ⎯ °C

TOTPL ⎯Junction temperature ⎯+135* ⎯ °C

PFM Control

Circuit Block

(MODE)

[PFM]

Synchronous

rectification stop

voltage

VTHLX 9LX pin ⎯0* ⎯mV

PFM/PWM mode

condition VPFM 1MODE pin 0 ⎯1.4 V

Fixed PWM mode

condition VPWM 1MODE pin 2.2 ⎯VVREF V

MODE pin input

current IMODE 1MODE = 0 V −10+1µA

MB39A135

8DS04-27263-1E

(Continued)

(Ta = +25 °C, VCC = 15 V, CTL = 5 V VREF = 0 A, VB = 0 A)

* : Standard design value

Parameter Sym-

bol Pin No. Condition Value Unit

Min Typ Max

Output Block

[DRV]

High-side output

on-resistance

RON_MH 10 DRVH = −100 mA ⎯47Ω

RON_ML 10 DRVH = 100 mA ⎯1.0 3.5 Ω

Low-side

output on-resistance

RON_SH 6DRVL = −100 mA ⎯47Ω

RON_SL 6DRVL = 100 mA ⎯0.75 1.70 Ω

Output source

current ISOURCE 10,6

LX = 0 V, CB = 5 V

DRVH, DRVL = 2.5 V

DUTY ≤ 5%

⎯−0.5* ⎯A

Output sink current ISINK

LX = 0 V, CB = 5 V

DRVH = 2.5 V

DUTY ≤ 5%

⎯0.9* ⎯A

LX = 0 V, CB = 5 V

DRVL = 2.5 V

DUTY ≤ 5%

⎯1.2* ⎯A

Minimum on time tON 10 COMP = 1 V ⎯250* ⎯ns

Maximum on-duty DMAX 10 ⎯72 80 ⎯%

Dead time tD10, 6 LX = 0 V, CB = 5 V ⎯60 ⎯ns

Level

Converter

Block

[LVCNV]

Maximum current

sense voltage VRANGE 9VCC − LX ⎯220* ⎯mV

Voltage transduction

gain ALV 9⎯5.4 6.8 8.2 V/V

Offset voltage at

voltage transduction VIO 9⎯⎯300 ⎯mV

Slope compensation

inclination SLOPE 9 ⎯⎯2* ⎯V/V

LX pin input current ILX 9LX = VCC 320 420 600 µA

Control Block

[CTL]

ON condition VON 4CTL pin 2 ⎯25 V

OFF condition VOFF 4CTL pin 0 ⎯0.8 V

Hysteresis width VH4CTL pin ⎯0.4* ⎯V

Input current ICTLH 4CTL = 5 V ⎯25 40 µA

ICTLL 4CTL = 0 V ⎯01µA

General

Standby current ICCS 8CTL = 0 V ⎯010µA

Power-supply

current ICC 8LX = 0 V, F = 1.0 V

MODE = VREF ⎯1.9 2.7 mA

MB39A135

DS04-27263-1E 9

■TYPICAL CHARACTERISTICS

• Power dissipation

(Continued)

200

400

600

800

1000

1200

1400

1600

1800

2000

−50 −25 0 +25 +50 +75 +100 +125

1237

VREF bias voltage vs.

Operating ambient temperature

Error Amp threshold voltage vs.

Operating ambient temperature

VREF bias voltage VVREF (V)

Error Amp threshold voltage EVTH (V)

Operating ambient temperature Ta ( °C) Operating ambient temperature Ta ( °C)

3.24

3.26

3.28

3.3

3.32

3.34

3.36

-40 -20 0 +20 +40 +60 +80+100 0.69

0.695

0.7

0.705

0.71

VCC = 15 V

fosc = 500 kHz

-40 -20 0 +20 +40 +60 +80+100

Power dissipation vs. Operating ambient temperature

Operating ambient temperature Ta ( °C)

Power dissipation PD (mW)

MB39A135

10 DS04-27263-1E

(Continued)

Oscillation frequency vs.

Operating ambient temperature

Dead time vs.

Operating ambient temperature

Oscillation frequency fOSC (kHz)

Dead time tD (ns)

Operating ambient temperature Ta( °C) Operating ambient temperature Ta( °C)

tD1 : period from DRVL off to DRVH on

tD2 : period from DRVH off to DRVL on

Oscillation frequency vs. Timing resistor value VB bias voltage vs. VB bias output current

Oscillation frequency fOSC (kHz)

VB bias voltage VVB (V)

Timing resistor value RRT (kΩ) VB bias output current IVB (A)

Maximum duty cycle vs. Power supply voltage

Maximum duty cycle vs.

Operating ambient temperature

Maximum duty cycle DMAX (%)

Power supply voltage VVCC (V) Operating ambient temperature Ta ( °C)

480

485

490

495

500

505

510

VCC = 15 V

-40 -20 0 +20 +40 +60 +80+100

tD1

tD2

-40 -20 0 +20 +40 +60 +80 +100

Vcc = 15 V

Ta = + 25°C

1000

10010 100 1000 -0.02 -0.015 -0.01 -0.005 0

5.5

VCC = 6 V

VCC = 5 V

fosc = 500 kHz

Ta = + 25°C

VCC = 4.5 V

4.5

3.5

2.5

010203075

-40 -20 0 +20 +40 +60 +80 +100

MB39A135

DS04-27263-1E 11

■FUNCTION

1. Current Mode

It uses the current waveform from the switching (Q1) as a control waveform to control the output voltage, as

described below:

1: The clock (CK) from the internal clock generator (OSC) sets RS-FF and turns on the high-side FET.

2: Tunring on the high-side FET causes the inductor current (IL) rise. Generate Vs that converts this current

into the voltage.

3: The current comparator (I Comp.) compares this Vs with the output (COMP) from the error amplifier (Error

Amp) that is negative-feedback from the output voltage (Vo).

4: When I Comp. detects that Vs exceeds COMP, it resets RS-FF and turns off high side FET.

5: The clock (CK) from the clock generator (OSC) turns on the high-side FET again.

Thus, switching is repeated.

Operate so that the FB electrical potential may become INTREF electrical potential, and stabilize the output

voltage as a feedback control.

INTREF

VIN

COMP

RS-FF

DRVH

DRVL

OSC

Drive

Logic

SQCurrent

Sense

−

ton

COMP

toff

OSC(CK)

DRVH

MB39A135

12 DS04-27263-1E

(1) Reference Voltage Block (REF)

The reference voltage circuit (REF) generates a temperature-compensated reference voltage (3.3 V typ) using

the voltage supplied from the VCC pin. The voltage is used as the reference voltage for the IC's internal circuit.

The reference voltage can be used to supply a load current of up to 100 µA to an external device through the

VREF pin.

(2) Bias Voltage Block (VB Reg.)

Bias Voltage Block (VB Reg.) generates the reference voltage used for IC's internal circuit, using the voltage

supplied from the VCC pin. The reference voltage is a temperature-compensated stable voltage (5 V typ) to

supply a current of up to 100 mA through the VB pin.

(3) Under Voltage Lockout Protection Circuit Block (UVLO)

The circuit protects against IC malfunction and system destruction/deterioration in a transitional state or a

momentary drop when a bias voltage (VB) or an internal reference voltage (VREF) starts. It detects a voltage

drop at the VB pin or the VREF pin and stops IC operation. When voltages at the VB pin and the VREF pin

exceed the threshold voltage of the under voltage lockout protection circuit, the system is restored.

(4) Soft-start/Soft-stop Block (Soft-Start, Soft-Stop)

Soft-start

It protects a rush current or an output voltage (VO) from overshooting at the output start. Since the lamp voltage

generated by charging the capacitor connecting to the CS pin is used for the reference voltage of the error

amplifier (Error Amp), it can set the soft-start time independent of a load of the output (VO). When the IC starts

with “H” level of the CTL pin, the capacitor at the CS pin (CS) starts to be charged at 5.5 µA. The output voltage

(VO) during the soft-start period rises in proportion to the voltage at the CS pin generated by charging the capacitor

at the CS pin.

During the soft-start with, 0.8 V > voltage at CS pin, operations are as follows:

• Fixed PWM operation only (fixed PWM even if MODE pin is set to “L”)

• Over-voltage protection function and under-voltage protection function are invalid.

Soft-stop

It discharges electrical charges stored in a smoothing capacitor at output stop. Setting the CTL pin to “L” level

starts the soft-stop function independent of a load of output (Vo). Since the capacitor connecting to the CS pin

starts to discharge through the IC-built-in soft-stop discharging resistance (70 kΩ typ) when the CTL pin sets at

“L” level enters its lamp voltage into the error amplifier (Error Amp.), the soft-stop time can be set independent

of a load of output (VO). When discharging causes the voltage at the CS pin to drop below 100 mV (typ), the IC

shuts down and changes to the stand-by state. In addition, the soft-stop function operates after the under-voltage

protection circuit block (UVP Comp.) is latched or after the over-temperature protection circuit block (OTP) detects

over-temperature.

During the soft-stop with, 0.8 V > voltage at CS pin, operations are as follows:

• Fixed PWM operation only (fixed PWM even if MODE pin is set to “L”)

• Over-voltage protection function and under-voltage protection function are invalid.

(5) Clock Generator Block (OSC)

The clock generator has the built-in oscillation frequency setting capacitor and generates a clock by connecting

the oscillation frequency setting resistor to the RT pin.

MB39A135

DS04-27263-1E 13

(6-1) Error Amp Block (Error Amp)

The error amplifiers (Error Amp) detect the output voltage from the DC/DC converter and output to the current

comparators (I Comp.). The output voltage setting resistor externally connected to FB allows an arbitrary output

voltage to be set.

In addition, since an external resistor and an external capacitor serially connected between COMP-FB allow an

arbitrary loop gain to be set, it is possible for the system to compensate a phase stably.

(6-2) Over Current Detection (Protection) Block (ILIM)

It is the current detection circuit to restrict an output current (IO). The over current detection block (ILIM) compares

an output waveform of the level converter (see Function description “(12) Level Converter Block”) with the ILIM

pin voltage in every cycle. As a load resistance (RO) drops, a load current (IO) increases. Therefore, the output

waveform of the level converter exceeds the ILIM pin voltage At this time, the output current can be restricted

by turning off FET on the high-side and suppressing a peak value of the inductor current.

As a result, the output voltage (VO) should drop.

Furthermore, if the output voltage drops and the electrical potential at the FB pin drops below 0.3 V, the oscillation

frequency (fOSC) drops to 1/8.

(7) Over-voltage Protection Circuit Block (OVP Comp.)

The circuit protects a device connecting to the output when the output voltage (VO) rises.

It compares 1.15 times (typ) of the internal reference voltage (INTREF) (0.7 V) that is non-inverting-entered into

the error amplifier with the feed-back voltage that is inverting-entered into the error amplifier and if it detects the

state where the latter is higher than the former by 50 µs (typ). It stops the voltage output by setting the RS latch,

setting the DRVH pin to “L” level, setting the DRVL pin to “H” level, turning off the high side FET and turning on

the low-side FET.

The conditions below cancel the protection function:

• Setting CTL to “L”.

• Setting the power supply voltage below the UVLO threshold voltage (VTHL1 and VTHL2).

(8) Under-voltage Protection Circuit Block (UVP Comp.)

It protects a device connecting to the output by stopping the output when the output voltage (VO) drops.

It compares 0.7 times (typ) of the internal reference voltage (INTREF) (0.7 V) that is non-inverting-entered into

the error amplifier with the feed-back voltage that is inverting-entered into the error amplifier and if it detects the

state where the latter is lower than the former by 512/fOSC s (typ), it stops the voltage output by setting the RS latch.

The conditions below cancel the protection function:

• Setting CTL to “L”.

• Setting the power supply voltage below the UVLO threshold voltage (VTHL1 and VTHL2).

(9) Over temperature Protection Circuit Block (OTP)

The circuit protects an IC from heat-destruction. If the temperature at the joint part reaches +160 °C, the circuit

stops the voltage output by discharging the capacitor connecting to the CS pin through the soft-stop discharging

resistance (70 kΩ typ) in the IC.

In addition, if the temperature at the joint part drops to +135 °C, the output restarts again through the soft-start

function.

Therefore, make sure to design the DC/DC power supply system so that the over temperature protection does

not start frequently.

MB39A135

14 DS04-27263-1E

(10) PFM Control Circuit Block (MODE)

It sets the control mode of the IC and makes control at automatic PFM/PWM switching.

Automatic PFM/PWM switching mode operation

It compares the LX pin voltage with GND electrical potential at Di Comp. In the comparison, the negative voltage

at the LX pin causes low-side FET to set on, positive voltage causes it to set off (Di Comp. method). As a result,

the method restricts the back flow of the inductor current at a light load and makes the switching of the inductor

current discontinuous (DCM). Such an operation allows the oscillation frequency to drop, resulting in high

efficiency at a light load.

(11) Output Block (DRV)

The output circuit is configured in CMOS type for both of the high-side and the low-side, allowing the external

N-ch MOS FET to drive.

(12) Level Converter Block (LVCNV)

The circuit detects and converts the current when the high-side FET turns on. It converts the voltage waveform

between source side(VCC pin voltage) and the drain side (LX pin voltage) on the high-side FET into the voltage

waveform for GND reference.

(13) Control Block (CTL)

The circuit controls on/off of the output from the IC.

Control function table

MODE pin

connection Control mode Features

“L” (GND) Automatic PFM/

PWM switching Highly-efficient at light load

“H” (VREF) Fixed PWM

Stable oscillation frequency

Stable switching ripple voltage

Excellent in rapid load change characteristic at heavy load to light

load

CTL DC/DC converter Remarks

L OFF Standby

HON ⎯

MB39A135

DS04-27263-1E 15

■PROTECTION FUNCTION TABLE

The following table shows the state of each pins when each protection function operates.

Protection

function

Detection

condition

Output of each pin after detection DC/DC output dropping

operation

VREF VB DRVH DRVL

Under Voltage Lock Out

(UVLO)

VB < 3.6 V

VREF < 2.7 V < 2.7 V < 3.6V L L Self-discharge by load

Under Voltage

Protection

(UVP)

FB < 0.49V 3.3 V 5 V L L Electrical discharge by

soft-stop function

Over Voltage

Protection

(OVP)

FB > 0.805V 3.3 V 5 V L H 0 V clamping

Over current protection

(ILIM) COMP > ILIM 3.3 V 5 V switching switching

The output voltage is drop-

ping to keep constant out-

put current.

Over Temperature

Protection

(OTP)

Tj > + 160 °C 3.3 V 5 V L L Electrical discharge by

soft-stop function

CONTROL

(CTL)

CTL : H→L

(CS > 0.1 V) 3.3 V 5 V L L

MB39A135

16 DS04-27263-1E

■I/O PIN EQUIVALENT CIRCUIT DIAGRAM

(Continued)

VCC

GND

VREF

GND

VCC

GND

CTL

VREF

GND

VREF

GND

VREF

GND

COMP

VB pin CS pin

VREF pin CTL pin

FB pin COMP pin

ESD protection element

MB39A135

DS04-27263-1E 17

(Continued)

DRVL

VREF

GND

VREF

GND

DRVH

GND

ILIM

VREF

GND

MODE

VREF

GND

PGND

ILIM

VREF

GND

DRVH

VREF

GND

MODE pin CB, DRVH, LX pins

ILIM pin RT pin

DRVL pin

MB39A135

18 DS04-27263-1E

■EXAMPLE APPLICATION CIRCUIT

−

VREF

5.5 µA

<Soft-Start >

/uvlo

ovp_out

ctl

/uvp_out

/otp_out

70 kΩ

intref

intref

x 1.15 V

intref

x 0.7 V

50 µs

delay

512/f

OSC

delay SQ

ovp_out

uvp_out

<REF> <CTL>intref

(3.3 V)

312

ON/OFF

VB ctl

UVLO

<UVLO>

VREF

UVLO

uvlo

H : UVLO

release

OTP

otp_out

Drive

Logic VB

Lo-side

Drive

Level

Converter

CLK

RS-FF

Drive

Hi-side

Bias

Reg.

Clock

generator

2.0

821

R8-1

R8-2

(4.5 V

25 V)

COMP

R23

ILIM

R11

R12

MB39A135

GNDVREF

C15

DRVH

DRVL

CTL

PGND

C2-1

C2-2

C2-3

C1-1

C1-2

C14

VCC

RTMODE

VREF

R21

C13

MB39A135

DS04-27263-1E 19

■PARTS LIST

NEC : NEC Electronics Corporation

Onsemi : ON Semiconductor Corporation

TDK : TDK Corporation

SSM : SUSUMU Co., LTD

Component Item Specification Vendor Package Parts Name Remark

Q1 N-ch FET

VDS = 30 V,

ID = 8 A,

Ron = 21 mΩ

NEC SO-8 µPA2755 Dual type

(2 elements)

D2 Diode VF = 0.35 V

at IF = 0.2 A Onsemi SOD-523 BAT54XV2T1G

L1 Inductor 1.5 µH

(6.2 mΩ, 8.9 A) TDK ⎯VLF10040T-1R5N

C1-1

C1-2

Ceramic capacitor

22 µF (25 V)

TDK

3225

C3225JB1E226M

2 capacitors

in parallel

C2-1

C2-2

C2-3

Ceramic capacitor

22 µF (10 V)

TDK

3216

C3216JB1A226M

3 capacitors

in parallel

C5 Ceramic capacitor 0.1 µF (50 V) TDK 1608 C1608JB1H104K

C7 Ceramic capacitor 0.022 µF (50 V) TDK 1608 C1608JB1H223K

C9 Ceramic capacitor 820 pF (50 V) TDK 1608 C1608CH1H821J

C13 Ceramic capacitor 0.01 µF (50 V) TDK 1608 C1608JB1H103K

C14 Ceramic capacitor 1.0 µF (16 V) TDK 1608 C1608JB1C105K

C15 Ceramic capacitor 0.1 µF (50 V) TDK 1608 C1608JB1H104K

R8-1

R8-2

Resistor

1.6 kΩ

9.1 kΩ

SSM

1608

RR0816P162D

RR0816P912D

2 resistors in

serial

R9 Resistor 15 kΩSSM 1608 RR0816P153D

R11 Resistor 56 kΩSSM 1608 RR0816P563D

R12 Resistor 56 kΩSSM 1608 RR0816P463D

R21 Resistor 82 kΩSSM 1608 RR0816P823D

R23 Resistor 22 kΩSSM 1608 RR0816P223D

MB39A135

20 DS04-27263-1E

■APPLICATION NOTE

Setting method for PFM/PWM and fixed PWM modes

For the setting method for each mode, see “Function description (10) PFM Control Circuit Block (MODE)“.

Cautions at PFM/PWM mode

If a load current drops rapidly because of rapid load change and others, it tends to take a lot of time to restore

overshooting of an output voltage.

As a result, the over-voltage protection may operate.

In this case, solution are possible by the addition of the load resistance of value to be able to restore the output

voltage in the over-voltage detection time.

Setting method of output voltage

Set it by adjusting the output voltage setting zero-power resistance ratio.

Make sure that the setting does not exceed the maximum on-duty.

Calculate the on-duty by the following formula.

VO = R1 + R2 × 0.7

VO : Output setting voltage [V]

R1, R2 : Output setting resistor value [Ω]

DMAX_Min = VO + RON_Main × IOMAX

VIN − RON_Main × IOMAX + RON_Sync × IOMAX

DMAX_Min : Minimum value of the maximum on-duty cycle

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

RON_Main : High-side FET ON resistance [Ω]

RON_Sync : Low-side FET ON resistance [Ω]

IOMAX : Maximum load current [A]

MB39A135

DS04-27263-1E 21

Oscillation frequency setting method

Set it by adjusting the RT pin resistor value.

The oscillation frequency must set for on-time (tON) to become 300 ns or more.

Calculate the on-time by the following formula.

fOSC = 1.09

RRT × 40 × 10 − 12 + 300 × 10 − 9

RRT : RT resistor value [Ω]

fOSC : Oscillation frequency [Hz]

tON = VO

VIN × fOSC

tON : On-time [s]

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

MB39A135

22 DS04-27263-1E

Setting method of soft-start time

Calculate the soft-start time by the following formula.

tS = 1.4 × 105 × CCS

Calculate delay time until the soft-start beginning by the following formula:

td1 = 30 × CVB + 290 × CVREF + 1.455 × 104 × CCS

Calculate the discharge time at the soft-stop by the following formula:

tdis = 1.44 × 105 × CCS

In addition, calculate the delay time to the discharge starting by the following formula:

td3 = 7.87 × 104 × CCS

ts : Soft-start time [s] (Time to becoming output 100%)

CCS : CS pin capacitor value [F]

td1 : Delay time including VB voltage and VREF voltage starts [s]

CCS : CS pin capacitor value [F]

CVB : VB pin capacitor value [F]

CVREF : VREF pin capacitor value [F] (0.1 µFTyp)

tdis : Discharge time [s]

CCS : CS pin capacitor value [F]

td3 : Delay time until discharge start [s]

CCS : CS pin capacitor value [F]

CTL

dis

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DS04-27263-1E 23

Setting method of over current detection value

It is possible to set it by adjusting the over current detection setting zero-power resistance ratio when over current

detection (ILIM) is used.

Calculate the over current detection setting resistor value by the following formula.

200 × 103 ≥ R1 + R2 ≥ 30 × 103

* : Since the over current detection value depends on the on-resistance of FET, the over current detection setting

resistor value ratio should be adjusted in consideration of the temperature characteristics of the on-resistance.

When the temperature at the FET joint part rises by + 100 °C, the on-resistance of FET increases to about 1.5

times.

* : If the over current detection function is not used, connect the ILIM pin to the VREF pin.

3.3 × R2 −0.3

ILIM = R1 + R2 + VIN − VO × (200 × 10 − 9 − VO)

6.8 × RON L2 × fOSC × VIN

ILIM : Over current detection value [A]

R1, R2 : ILIM setting resistor value [Ω]*

L : Inductor value [H]

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

RON : High-side FET ON resistance [Ω]

VREF

ILIM*

LIM

Inductor current

Time

Over current

detection value

MB39A135

24 DS04-27263-1E

Selection of smoothing inductor

The inductor value selects the value that the ripple current peak-to-peak value of the inductor becomes 50% or

less of the maximum load current as a rough standard. Calculate the inductor value in this case by the following

formula.

An inductor ripple current value limited on the principle of operation is necessary for this device. However, when

it uses the high-side FET of the low Ron resistance, the switching ripple voltage become small, and the ripple cur-

rent value be insufficient. This should be solved by the oscillation frequency or reducing the inductor value.

Select the one of the inductor value that meets a requirement listed below.

It is necessary to calculate the maximum current value that flows to the inductor to judge whether the electric

current that flows to the inductor is a rated value or less. Calculate the maximum current value of the inductor by

the following formula.

L ≥ VIN − VO × VO

LOR × IOMAX VIN × fOSC

L : Inductor value [H]

IOMAX : Maximum load current [A]

LOR : Ripple current peak-to-peak value of Maximum load current ratio (=0.5)

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

L ≤ VIN − VO × VO × RON

∆VRON VIN × fOSC

L : Inductor value [H]

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

∆VRON : Ripple voltage [V] (20 mV or more is recommended)

RON : High-side FET ON resistance [Ω]

ILMAX ≥ IoMAX + ∆IL , ∆IL = VIN − VO

2LVIN × fOSC

ILMAX : Maximum current value of inductor [A]

IoMAX : Maximum load current [A]

∆IL : Ripple current peak-to-peak value of inductor [A]

L : Inductor value [H]

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

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DS04-27263-1E 25

∆IL

MAX

Inductor current

MB39A135

26 DS04-27263-1E

Selection of SWFET

The switching ripple voltage generated between drain and sources on high-side FET is necessary for this device

operation. Select the one of the SWFET of on-resistance that satisfies the following formula.

Select FET ratings with a margin enough for the input voltage and the load current. Ratings with the over-current

detection setting value or more are recommended.

Calculate a necessary rated value of high side FET and low-side FET by the following formula.

VDS > VIN

VGS > VB

Moreover, it is necessary to calculate the loss of SWFET to judge whether a permissible loss of SWFET is a

rated value or less. Calculate the loss on high-side FET by the following formula.

PMainFET = PRON_Main + PSW_Main

RON_Main ≥ ∆VRON_Main , RON_Main ≤ VRONMAX

∆IL ILIM + ∆IL

RON_Main : High-side FET ON resistance [Ω]

∆IL : Ripple current peak-to-peak value of inductor [A]

∆VRON_Main : High-side FET ripple voltage [V] (20 mV or more is recommended)

ILIM : Over current detection value [A]

VRONMAX : Maximum current sense voltage [V] (240 mV or less is recommended)

ID > IoMAX + ∆IL

ID : Rated drain current [A]

IoMAX : Maximum load current [A]

∆IL : Ripple current peak-to-peak value of inductor [A]

VDS : Rated voltage between drain and source [V]

VIN : Power supply voltage of switching system [V]

VGS : Rated voltage between gate and source [V]

VB : VB voltage [V]

PMainFET : High-side FET loss [W]

PRON_Main : High-side FET conduction loss [W]

PSW_Main : High-side FET SW loss [W]

MB39A135

DS04-27263-1E 27

High-side FET conduction loss

High-side FET SW loss

Calculate the Ibtm, Itop, tr and the tf simply by the following formula.

PRON_Main = IoMAX2 × VO × RON_Main

VIN

PRON_Main : High-side FET conduction loss [W]

IOMAX : Maximum load current [A]

VIN : Power supply voltage of switching system [V]

VO : Output voltage [V]

RON_Main : High-side FET ON resistance [Ω]

PSW_Main = VIN × fOSC × (Ibtm × tr + Itop × tf)

PSW_Main : High-side FET SW loss [W]

VIN : Power supply voltage of switching system [V]

fOSC : Oscillation frequency (Hz)

Ibtm : Ripple current bottom value of inductor [A]

Itop : Ripple current top value of inductor [A]

tr : Turn-on time on high-side FET [s]

tf : Turn-off time on high-side FET [s]

Ibtm = IoMAX − ∆IL

Itop = IoMAX − ∆IL

tr = Qgd × 4 tf = Qgd × 1

5 − Vgs (on) Vgs (on)

IOMAX : Maximum load current [A]

∆IL : Ripple current peak-to-peak value of inductor [A]

Qgd : Quantity of charge between gate and drain on high-side FET [C]

Vgs (on) : Voltage between gate and sources in Qgd on high-side FET [V]

MB39A135

28 DS04-27263-1E

Calculate the loss on low-side FET by the following formula.

* : The transition voltage of the voltage between drain and source on low-side FET is generally small, and the

switching loss is omitted here for the small one as it is possible to disregard it.

The gate drive power of SWFET is supplied by LDO in IC, therefore all of SWFET allowable maximum total

charge (QgTotalMax) is determined by the following formula.

Selection of fly-back diode

When the conversion efficiency is valued, the improved property of the conversion efficiency is possible by the

addition of the fly-back diode. thought it is usally unnecessary. The effect is achieved in the condition where the

oscillation frequency is high or output voltage is lower. Select schottky barrier diode (SBD) that the forward

current is as small as possible. In this DC/DC control IC, the period for the electric current flows to fly-back diode

is limited to synchronous rectification period (60 ns × 2) because of using the synchronous rectification method.

Therefore, select the one that the electric current of fly-back diode doesn't exceed ratings of forward current

surge peak (IFSM).Calculate the forward current surge peak ratings of fly-back diode by the following formula.

PSyncFET = PRon_Sync* = IoMAX2 × (1 − VO) × Ron_Sync

VIN

PSyncFET : Low-side FET loss [W]

PRon_Sync : Low-side FET conduction loss [W]

IOMAX : Maximum load current [A]

VIN : Power supply voltage of switching system [V]

VO : Output voltage [V]

Ron_Sync : Low-side FET on-resistance [Ω]

QgTotalMax ≤ 0.095

fOSC

QgTotalMax : SWFET allowable maximum total charge [C]

fOSC : Oscillation frequency [Hz]

IFSM ≥ IoMAX + ∆IL

IFSM : Forward current surge peak ratings of fly-back diode [A]

IoMAX : Maximum load current [A]

∆IL : Ripple current peak-to-peak value of inductor [A]

MB39A135

DS04-27263-1E 29

Calculate ratings of the fly-back diode by the following formula:

VR_Fly > VIN

Selection of output capacitor

This device supports a small ceramic capacitor of the ESR. The ceramic capacitor that is low ESR is an ideal

to reduce the ripple voltage compared with other capacitor. Use the tantalum capacitor and the polymer capacitor

of the low ESR when a mass capacitor is needed as the ceramic capacitor can not support. To the output voltage,

the ripple voltage by the switching operation of DC/DC is generated. Discuss the lower bound of output capacitor

value according to an allowable ripple voltage. Calculate the output ripple voltage from the following formula.

Notes: • The ripple voltage can be reduced by raising the oscillation frequency and the inductor value besides

capacitor.

• Capacitor has frequency characteristic, the temperature characteristic, and the electrode bias character-

istic, etc. The effective capacitor value might become extremely small depending on the condition. Note

the effective capacitor value in the condition.

Calculate ratings of the output capacitor by the following formula:

VCO > VO

Note: Select the capacitor rating with withstand voltage allowing a margin enough for the output voltage.

VR_Fly : Reverse voltage of fly-back diode direct current [V]

VIN : Power supply voltage of switching system [V]

∆VO = ( 1 + ESR) × ∆IL

2π × fOSC × CO

∆VO : Switching ripple voltage [V]

ESR : Series resistance component of output capacitor [Ω]

∆IL : Ripple current peak-to-peak value of inductor [A]

CO : Output capacitor value [F]

fOSC : Oscillation frequency [Hz]

VCO : Withstand voltage of the output capacitor [V]

VO : Output voltage [V]

MB39A135

30 DS04-27263-1E

In addition, use the allowable ripple current with an enough margin, if it has a rating. Calculate an allowable

ripple current of the output capacitor by the following formula.

Selection of input capacitor

Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the tantalum

capacitor and the polymer capacitor of the low ESR when a mass capacitor is needed as the ceramic capacitor

can not support. To the power supply voltage, the ripple voltage by the switching operation of DC/DC is generated.

Discuss the lower bound of input capacitor according to an allowable ripple voltage. Calculate the ripple voltage

of the power supply from the following formula.

Notes: • The ripple voltage can be reduced by raising the oscillation frequency besides capacitor.

• Capacitor has frequency characteristic, the temperature characteristic, and the electrode bias character-

istic, etc. The effective capacitor value might become extremely small depending on the condition. Note

the effective capacitor value in the condition.

Calculate ratings of the input capacitor by the following formula:

VCIN > VIN

Note: Select the capacitor rating with withstand voltage with margin enough for the input voltage.

Irms ≥ ∆IL

2√3

Irms : Allowable ripple current (effective value) [A]

∆IL : Ripple current peak-to-peak value of inductor [A]

∆VIN = IOMAX × VO + ESR × (IOMAX + ∆IL )

CIN VIN × fOSC 2

∆VIN : Switching system power supply ripple voltage peak-to-peak value [V]

IOMAX : Maximum load current value [A]

CIN : Input capacitor value [F]

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

ESR : Series resistance component of input capacitor [Ω]

∆IL : Ripple current peak-to-peak value of inductor [A]

VCIN : Withstand voltage of the input capacitor [V]

VIN : Power supply voltage of switching system [V]

MB39A135

DS04-27263-1E 31

In addition, use the allowable ripple current with an enough margin, if it has a rating. Calculate an allowable

ripple current by the following formula.

Selection of boot strap diode

Select Schottky barrier diode (SBD), that forward current is as small as possible. The electric current that drives

the gate of high-side FET flows to SBD of the bootstrap circuit. Calculate the mean current by the following

formula. Select it so as not to exceed the electric current ratings.

ID ≥ Qg × fOSC

Calculate ratings of the boot strap diode by the following formula:

VR_BOOT > VIN

Selection of boot strap capacitor

To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a

minimum value as a target is assumed the capacitor which can store electric charge 10 times that of the Qg on

high-side FET. And select the boot strap capacitor.

Calculate ratings of the boot strap capacitor by the following formula:

VCBOOT > VIN

Irms ≥ IOMAX × √VO × (VIN − VO)

VIN

Irms : Allowable ripple current (effective value) [A]

IOMAX : Maximum load current value [A]

VIN : Power supply voltage of switching system [V]

VO : Output voltage [V]

ID : Forward current [A]

Qg : Total quantity of charge of gate on high-side FET [C]

fOSC : Oscillation frequency [Hz]

VR_BOOT : Reverse voltage of boot strap diode direct current [V]

VIN : Power supply voltage of switching system [V]

CBOOT ≥ 10 × Qg

CBOOT : Boot strap capacitor value [F]

Qg : Amount of gate charge on high-side FET [C]

VB : VB voltage [V]

VCBOOT : Withstand voltage of the boot strap capacitor [V]

VIN : Power supply voltage of switching system [V]

MB39A135

32 DS04-27263-1E

Design of phase compensation circuit

Assume the phase compensation circuit of 1pole-1zero to be a standard in this device.

1pole-1zero phase compensation circuit

As for crossover frequency (fCO) that shows the band width of the control loop of DC/DC. The higher it is, the

more excellent the rapid response becomes, however, the possibility of causing the oscillation due to phase

margin shortage increases. Though this crossover frequency (fCO) can be arbitrarily set, make 1/10 of the

oscillation frequencies (fosc) a standard, and set it to the upper limit. Moreover, set the phase margin at least

to 30°, and 45° or more if possible as a reference.

Set the constants of Rc and Cc of the phase compensation circuit using the following formula as a target:

RC = (VIN − VO) ALVCNV × RON_Main × fCO × 2π × CO × VO × R1

VIN × fOSC × L × IOMAX

CC = CO × VO

RC × IOMAX

RC : Phase compensation resistor value [Ω]

CC : Phase compensation capacitor value [F]

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

IOMAX : Maximum load current value [A]

L : Inductor value [H]

CO : Output capacitor value [F]

RON_Main : High-side FET ON resistance [Ω]

R1 : Output setting resistor value [Ω]

ALVCNV : Level converter voltage gain [V/V]

On-duty ≤ 50% : ALVCNV = 6.8

On-duty > 50% : ALVCNV = 13.6

fCO : Cross-over frequency (arbitrary setting) [Hz]

INTREF

COMP

Rc Cc

Error

Amp

+To I Comp.

MB39A135

DS04-27263-1E 33

VB pin capacitor

1 µF is assumed to be a standard, and when Qg of SWFET used is large, it is necessary to adjust it. To drive

the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a minimum value

as a target is assumed the capacitor which can store electric charge 100 times that of the Qg on high-side FET.

And select it.

Calculate ratings of the VB pin capacitor by the following formula:

VCVB > VB

CVB ≥ 100 × Qg

CVB : VB pin capacitor value [F]

Qg : Total amount of gate charge of high-side FET and low-side FET [C]

VB : VB voltage [V]

VCVB : Withstand voltage of the VB pin capacitor [V]

VB : VB voltage [V]

MB39A135

34 DS04-27263-1E

VB regulator

In the condition for which the potential difference between VCC and VB is insufficient, the decrease in the voltage

of VB happens because of power output on-resistance and load current (mean current of all external FET gate

driving current and load current of internal IC) of the VB regulator. Stop the switching operation when the voltage

of VB decreases and it reaches threshold voltage (VTHL1) of the under voltage lockout protection circuit. Therefore,

set oscillation frequency or external FET or I/O potential difference of the VB regulator using the following formula

as a target when you use this IC.

VCC ≥ VB (VTHL1) + (Qg × fOSC + ICC) × RVB

If the I/O potential difference is small, the problem can be solved by connecting the VB pin and the VCC pin.

The conditions of the input voltage range are as follows:

Note that if the I/O potential difference is not enough when used, use the actual machine to check carefully the

operations at the normal operation, start operation, and stop operation. In particular, care is needed when the

input voltage range over 6 V.

VCC : Power supply voltage [V] (VIN)

VB (VTHL1) : Threshold voltage of VB under-voltage lockout protection circuit [V](3.8 [V] (Max))

Qg : Total amount of gate charge of high-side FET and low-side FET [C]

fOSC : Oscillation frequency [Hz]

ICC : Power supply current [A] (2.7 × 10 - 3 [A] := Load current of VB (LDO))

RVB : VB output on-resistance [Ω] (100 Ω (The reference value at VCC = 4.5 V))

6.0 V

4.5 V 25 V

(2)

(3)(1)

(1) For 4.5 V < VIN < 6.0 V

→ Connect VB pin to VCC.

(2) When the input voltage range steps over 6.0 V

→ Normal use (VCC to VB not connected)

(3) For 6.0 V ≤ VIN

→ Normal use (VCC to VB not connected)

VIN input voltage ranges:

MB39A135

DS04-27263-1E 35

Power dissipation and the thermal design

As for this IC, considerations of the power dissipation and thermal design are not necessary in most cases

because of its high efficiency. However, they are necessary for the use at the conditions of a high power supply

voltage, a high oscillation frequency, high load, and the high temperature.

Calculate IC internal loss (PIC) by the following formula.

PIC = VCC × (ICC + Qg × fOSC)

Calculate junction temperature (Tj) by the following formula.

Tj = Ta + θja × PIC

PIC : IC internal loss [W]

VCC : Power supply voltage (VIN) [V]

ICC : Power supply current [A] (2.7 mA Max)

Qg : All SWFET total quantity of charge [C] (Total with Vgs = 5 V)

fOSC : Oscillation frequency [Hz]

Tj : Junction temperature [ °C] (150 °C Max)

Ta : Ambient temperature [ °C]

θja : TSSOP-16 Package thermal resistance (101 °C/W)

PIC : IC internal loss [W]

MB39A135

36 DS04-27263-1E

Board layout

Consider the points listed below and do the layout design.

• Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor connected

with the VCC and VB pins, and GND pin of the switching system parts with switching system GND (PGND).

Connect other GND connection pins with control system GND (AGND), and separate each GND, and try not

to pass the heavy current path through the control system GND (AGND) as much as possible. In that case,

connect control system GND (AGND) and switching system GND (PGND) right under IC.

• Connect the switching system parts as much as possible on the surface. Avoid the connection through the

through-hole as much as possible.

• As for GND pins of the switching system parts, provide the through hole at the proximal place, and connect it

with GND of internal layer.

• Pay the most attention to the loop composed of input capacitor (CIN), SWFET, and fly-back diode (SBD).

Consider making the current loop as small as possible.

• Place the boot strap capacitor (CBOOT) proximal to CB and LX pins of IC as much as possible.

• This device monitors the voltage between drain and source on high-side FET as voltage between VCC and

LX pins.

Place the input capacitor (CIN) and the high-side FET proximally as much as possible. Draw out the wiring to

VCC pin from the proximal place to the input capacitor. As for the net of the LX pin, draw it out from the proximal

place to the source pin on high-side FET. Moreover, a large electric current flows momentary in the net of the

LX pin. Wire the linewidth of about 0.8 mm to be a standard, as short as possible.

• Large electric current flows momentary in the net of DRVH and DRVL pins connected with the gate of SWFET.

Wire the linewidth of about 0.8mm to be a standard, as short as possible.

• By-pass capacitor (CVCC, CVREF, CVB) connected with VREF, VCC, and VB, and the resistor (RRT) connected

with the RT pin should be placed close to the pin as much as possible. Also connect the GND pin of the by-

pass capacitor with GND of internal layer in the proximal through-hole.

• Consider the net connected with RT, FB, and the COMP pins to keep away from a SW system parts as much

as possible because it is sensitive to the noise. Moreover, place the output voltage setting resistor and the

phase compensation circuit element connected with this net close to the IC as much as possible, and try to

make the net as short as possible. In addition, for the internal layer right under the installing part, provide the

control system GND (AGND) of few ripple and few spike noises, or provide the ground plane of the power

supply voltage as much as possible.

Switching system parts : Input capacitor (CIN), SWFET, Fly-back diode (SBD), Inductor (L),

Output capacitor (CO)

PGND

AGND

1pin AGND

CVREF

CVB

CVCC

CBOOT

VIN

PGND

SBD(option)

Layout example of IC Layout example of switching components

Through-hole

Surface Internal

layer

Low-side FET

High-side FET

To the VCC pin Through-hole

Output voltage

Vo feedback

To the LX pin

MB39A135

DS04-27263-1E 37

■REFERENCE DATA

(Continued)

Conversion Efficiency Load Regulation

Conversion Efficiency vs. Load Current Output Voltage vs. Load Current

Conversion Efficiency η (%)

Output Voltage VO (V)

Load Current IO (A) Load Current IO (A)

= 12 V

= 1.2 V

fosc = 300 kHz

Ta = + 25°C

PFM/PWM

0.01 0.1 1 10

100

Fixed PWM

012345

=12 V

=1.2 V

MODE = VREF

fosc = 300 kHz

Ta = + 25°C

1.10

1.12

1.14

1.16

1.18

1.20

1.22

1.24

1.26

1.28

1.30

CTL : 5 V/div

VO: 1V/div

1 ms/div

CTL : 5 V/div

: 1V/div

1 ms/div

Load Sudden Change Waveform

CTL Start-up Waveform CTL Stop Waveform

VIN = 12 V, VO = 1.2 V, Io = 5 A (0.24 Ω)

fosc = 300 kHz, Ta = + 25 °C,Soft start setting time = 3.0 ms

2 A

0 A

VO : 200 mV/div (1.2 V offset)

100 µs/div

IO : 1 A/div

VIN = 12 V

VO = 1.2 V

IO = 0 ←→ 2 A

fOSC = 300 kHz,

Ta = + 25 °C

MB39A135

38 DS04-27263-1E

(Continued)

VO : 0.5 V/div

CS : 2 V/div

LX : 10 V/div

IO : 10 A/div

500 µs/div

Nomal operation → Over current protection →

Under voltage protection operation waveform

Nomal operation

VIN = 12 V

VO = 1.2 V

fOSC = 300 kHz

Ta = + 25 °C

Over current

protection operation

Under voltage protection

operation

MB39A135

DS04-27263-1E 39

■USAGE PRECAUTION

1. Do not configure the IC over the maximum ratings.

If the IC is used over the maximum ratings, the LSI may be permanently damaged.

It is preferable for the device to normally operate within the recommended usage conditions. Usage outside of

these conditions can have an adverse effect on the reliability of the LSI.

2. Use the device within the recommended operating conditions.

The recommended values guarantee the normal LSI operation under the recommended operating conditions.

The electrical ratings are guaranteed when the device is used within the recommended operating conditions

and under the conditions stated for each item.

3. Printed circuit board ground lines should be set up with consideration for common imped-

ance.

4. Take appropriate measures against static electricity.

• Containers for semiconductor materials should have anti-static protection or be made of conductive material.

• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.

• Work platforms, tools, and instruments should be properly grounded.

• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in serial body and ground.

5. Do not apply negative voltages.

The use of negative voltages below − 0.3 V may make the parasitic transistor activated, and can cause

malfunctions.

■ORDERING INFORMATION

■EV BOARD ORDERING INFORMATION

■RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION

The LSI products of Fujitsu Microelectronics with “E1” are compliant with RoHS Directive, and has observed the

standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and polybromi-

nated diphenyl ethers (PBDE). A product whose part number has trailing characters “E1” is RoHS compliant.

Part number Package Remarks

MB39A135PFT-❏❏❏E1 16-pin plastic TSSOP

(FPT-16P-M08) Lead Free version

Part number EV board version No. Remarks

MB39A135EVB-01 MB39A135EVB-01 Rev2.0 TSSOP-16P

MB39A135

40 DS04-27263-1E

■MARKING FORMAT (Lead Free version)

INDEX

39A135

1XXX

Lead Free version

MB39A135

DS04-27263-1E 41

■LABELING SAMPLE (Lead free version)

2006/03/01

ASSEMBLED IN JAPAN

QC PASS

(3N) 1MB123456P-789-GE1

1000

(3N)2 1561190005 107210

1,000

PCS

0605 - Z01A

1000

1/1

1561190005

MB123456P - 789 - GE1

JEITA logo JEDEC logo

The part number of a lead-free product has the trailing characters “E1”.

Lead free mark

MB39A135

42 DS04-27263-1E

■PACKAGE DIMENSIONS

16-pin plastic TSSOP Lead pitch 0.65 mm

Package width

package length

4.40 mm × 4.96 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.20 mm Max

Weight 0.06 g

16-pin plastic TSSOP

(FPT-16P-M08)

2007-2008 FUJITSU MICROELECTRONICS LIMITED F16021S-c-1-4

*4.96±0.10(.195±.004)

*4.40±0.10 6.40±0.20

(.252±.008)(.173±.004)

0.10(.004)

0.65(.026) 0.24±0.08

(.009±.003)

16 9

"A"

0.145±0.045

(.0057±.0018)

0.13(.005)

Details of "A" part

0~8°

(.024±.006)

0.60±0.15

0.10±0.05

(Stand off)

LEAD No.

INDEX

.043

1.10 (Mounting height)

(.004±.002)

+0.04

–0.06

+0.10

–0.15

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) Pins width and pins thickness include plating thickness.

Note 2) Pins width do not include tie bar cutting remainder.

Note 3)* : These dimensions do not include resin protrusion.

MB39A135

DS04-27263-1E 43

MEMO

MB39A135

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen,

Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

206 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD.

151 Lorong Chuan, #05-08 New Tech Park,

Singapore 556741

Tel: +65-6281-0770 Fax: +65-6281-0220

http://www.fujitsu.com/sg/services/micro/semiconductor/

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm.3102, Bund Center, No.222 Yan An Road(E),

Shanghai 200002, China

Tel: +86-21-6335-1560 Fax: +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road

Tsimshatsui, Kowloon

Hong Kong

Tel: +852-2377-0226 Fax: +852-2376-3269

http://cn.fujitsu.com/fmc/tw

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-

ing the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect

to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in

nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in

weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited Business & Media Promotion Dept.