REV. Pr C
Preliminary Technical Data
PRELIMINARY TECHNICAL DATA
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7946*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2004
14-BIT, 500kSPS ADC in ␮SO/CSP
FUNCTIONAL BLOCK DIAGRAM
SDO
GND
OVDD
REF
IN-
SWITCHED
CAP DAC
AD7946
IN+
SCK
CONTROL
LOGIC
CNV
CLOCK
SDI
VDD
FEATURES
14-bit Resolution with No Missing Codes
Throughput: 500kSPS (Warp mode)
450kSPS (Normal mode)
380kSPS (Impulse mode)
INL: ⴞⴞ
ⴞⴞ
ⴞ0.4LSB Typ, ⴞⴞ
ⴞⴞ
ⴞ1LSB Max (ⴞⴞ
ⴞⴞ
ⴞ0.0061 % of FSR)
DNL: ⴞⴞ
ⴞⴞ
ⴞ0.25LSB Typ, ⴞⴞ
ⴞⴞ
ⴞ0.7LSB Max
S/(N+D): 85dB Typ @ 20kHz
THD: –100dB Typ @ 20kHz
Pseudo-Differential Analog input range:
0V to VREF with VREF up to VDD
No Pipeline Delay
Single Supply Operation 2V to 5.5V with
1.8V/2.5V/3V/5V logic interface
Daisy Chain Multiple ADCs and Busy Indicator
Programmable Input Bandwidth
Serial Interface SPI/QSPI/␮Wire/DSP compatible
Typical Power Dissipation:
2mW @ 3V/100kSPS, 20mW @ 5V/380ksps,
1.6␮W @ 2.5V/100SPS
Stand-by current: 1 nA Typ
10-pin Package: ␮-SOIC ( ␮-SO8 size ) and
CSP ( 3mm x 3mm same space as SOT-23 )
Pin-for-Pin Compatible with the 16-bit AD7686
APPLICATIONS
Battery Powered Equipment
Data Acquisition
Instrumentation
Medical Instruments
Process Control
GENERAL DESCRIPTION
The AD7946 is a 14-bit, 500kSPS, charge redistribution
successive-approximation, Analog-to-Digital Converter
which operates from a single power supply, VDD, be-
tween 2V to 5.5V. It contains a very low power high-speed
14-bit sampling ADC with no missing codes, an internal
conversion clock and a versatile serial interface port. The
part also contains a low noise, wide bandwidth, very short
aperture delay track/hold circuit. On the CNV rising
edge, it samples an analog input IN+ between 0V to REF
with respect to a ground sense IN-. The reference voltage
REF is applied externally and can be set up to the supply
voltage.
It features a very high sampling rate mode (Warp) for
synchronous applications, a fast mode (Normal) for asyn-
chronous applications and a reduced power mode
(Impulse) where the power scales linearly with through-
put.
The SPI compatible serial interface also features the abil-
ity, using the SDI input, to “Daisy chain” several ADCs
on a single 3 wire bus and provides an optional Busy indi-
cator. It is compatible with 1.8V, 2.5V, 3V or 5V logic
using the separate supply OVDD.
The AD7946 is housed in a 10-lead ␮SOIC or 10-lead
CSP (Chip Scale package) with operation specified from
–40°C to +85°C.
*Patent pending.
␮␮
␮␮
␮SO, CSP/SOT23 16 and 14 Bit ADC
Type 100 kSPS 250 kSPS 500 kSPS
16 Bit True AD7684 AD7687 AD7688
Differential
16 Bit Pseudo AD7683 AD7685 AD7686
Differential
16 Bit Unipolar AD7680
14 Bit True AD7944 AD7947
Differential
14 Bit Pseudo AD7942 AD7946
Differential
14 Bit Unipolar AD7940
PRELIMINARY TECHNICAL DATA
REV. Pr C –2–
AD7946–SPECIFICATIONS
Parameter Conditions Min Typ Max Unit
RESOLUTION 14 Bits
ANALOG INPUT
Voltage Range IN+ - IN- 0 VREF V
Absolute Input Voltage I N + –0.1 VDD + 0.3 V
IN- –0.1 TBD V
Analog Input CMRR fIN = TBD kHz T B D d B
Leakage Current at 25 ⴗC acquisition phase T B D nA
Input Impedance See Analog Input Section
DC ACCURACY
No Missing Codes 14 Bits
Differential Linearity Error –0.7 ±0.25 +0.7 LSB1
Integral Linearity Error – 1 ±0.4 +1 LSB
Transition Noise REF = VDD = 5V 0.33 LSB
Gain Error2, TMIN to TMAX ±TBD % of FSR
Gain Error Temperature Drift ±TBD ppm/°C
Offset Error2, TMIN to TMAX high bandwidth ±TBD ±TBD LSB
Offset Temperature Drift ±TBD ppm/°C
Power Supply Sensitivity VDD = VDD ± 5% ±TBD LSB
REFERENCE
Voltage Range 0.5 VDD+0.3 V
Load Current 500kSPS, VIN+-VIN- = VREF/2 TBD µA
SAMPLING DYNAMICS
–3 dB Input Bandwidth Low Bandwidth 2 M H z
High Bandwidth 9 M H z
Aperture Delay TBD ns
Aperture Jitter T B D ps rms
DIGITAL INPUTS
Logic Levels
VIL – 0 . 3 0.3 * OVDD V
VIH 0.7 * OVDD OVDD + 0.3 V
IIL –1 +1 µA
IIH –1 +1 µA
DIGITAL OUTPUTS
Data Format Serial 14-Bits Straight Binary
Pipeline Delay Conversion Results Available Immediately
After Completed Conversion
VOL ISINK = 500 µA 0.4 V
VOH ISOURCE = –500 µA OVDD – 0.3 V
POWER SUPPLIES
VDD Specified Performance 2 . 3 5 . 5 V
OVDD Specified Performance 2.3 VDD + 0.3 V
VDD Range 2 5.5 V
OVDD Range 1.8 5.5 V
Operating Current 500 kSPS Throughput3
V D D VDD = 5V T B D m A
OVDD OVDD = 3.3V T B D µ A
Standby Current4,5 VDD and OVDD = 5V, 25°C 1 T B D nA
Power Dissipation VDD= 2.5V, 100SPS Throughput41.6 µ W
VDD= 3V, 100 kSPS Throughput42 TBD m W
VDD= 5V, 380 kSPS Throughput420 TBD m W
VDD= 5V, 500 kSPS Throughput3TBD TBD m W
TEMPERATURE RANGE6
Specified Performance TMIN to TMAX –40 +85 °C
NOTES
1
LSB means Least Significant Bit. With the 5 V input range, one LSB is 305.2 µV.
2
See Definition of Specifications section. These specifications do include full temperature range variation but do not include the error contribution
from the external reference.
3
In Warp mode.
4
In Impulse mode. With all digital inputs forced to OVDD or GND as required.
5
During acquisition phase in Impulse mode only.
6
Contact Analog Devices for extended temperature range.
Specifications subject to change without notice.
( VDD = 2.3V to 5.5 V, OVDD = 2.3V to VDD, VREF = VDD, TA = -40ⴗⴗ
ⴗⴗ
ⴗC to +85ⴗⴗ
ⴗⴗ
ⴗC, unless
otherwise noted.)
PRELIMINARY TECHNICAL DATA
REV. Pr C
–3–
AD7946
Parameter Conditions Min Typ Max Unit
THROUGHPUT7
Conversion rate Warp Mode 2 µ s
1 500 kSPS
Conversion rate Normal Mode 2.3 µ s
0 450 kSPS
Conversion rate Impulse Mode 2.6 µ s
0 380 kSPS
Transient Response Full-Scale Step 400 ns
AC ACCURACY
Signal-to-Noise fIN = 20 kHz, 8 3 8 5 dB8
Spurious Free Dynamic Range fIN = 20 kHz 1 00 d B
Total Harmonic Distortion fIN = 20 kHz –100 TB D dB
Signal-to-(Noise+Distortion) fIN = 20 kHz 8 3 8 5 d B
f
IN = 20 kHz,–60 dB Input 2 5 d B
Intermodulation Distortion
Second Order Terms T B D d B
Third Order Terms T B D d B
NOTES
7
Using high bandwidth. See timing specifications for low bandwidth.
8
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
Specifications subject to change without notice.
(TA = -40ⴗⴗ
ⴗⴗ
ⴗC to +85ⴗⴗ
ⴗⴗ
ⴗC, VREF = 5V, OVDD = 2.3V to VDD, unless otherwise noted.)
VDD = 5 V
Parameter Conditions Min Typ Max Unit
THROUGHPUT SPEED7
Conversion rate Warp Mode T B D µ s
1 TBD kSPS
Conversion rate Normal Mode T B D µ s
0 TBD kSPS
Conversion rate Impulse Mode T B D µ s
0 TBD kSPS
Transient Response Full-Scale Step T B D ns
AC ACCURACY
Signal-to-Noise fIN = 20 kHz, T B D T B D dB8
Spurious Free Dynamic Range fIN = 20 kHz 1 00 d B
Total Harmonic Distortion fIN = 20 kHz –100 TB D dB
Signal-to-(Noise+Distortion) fIN = 20 kHz T B D T B D d B
f
IN = 20 kHz,–60 dB Input T B D d B
Intermodulation Distortion
Second Order Terms TBD dB
Third Order Terms T B D d B
(TA = -40ⴗⴗ
ⴗⴗ
ⴗC to +85ⴗⴗ
ⴗⴗ
ⴗC, VREF = 2.5V, OVDD = 2.3V to VDD, unless otherwise noted.)
VDD = 2.5V
PRELIMINARY TECHNICAL DATA
REV. Pr C –4–
AD7946–SPECIFICATIONS
NOTES
1
In Warp mode, the maximum time between conversion is 1ms; otherwise, there is no required maximum time.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data available t
CONV
0.7/0.9/1.1 1.6/1.9/2.2 µs
high bandwidth, (Warp mode / Normal mode / Impulse mode)
Acquisition Time: high Bandwidth t
ACQ
400 ns
low Bandwidth 1.5 µs
Time Between Conversions t
CYC
2/2.3/2.6 note 1 µs
high bandwidth, (Warp mode / Normal mode / Impulse mode)
CNV Pulse width ( CS mode ) t
CNVH
5ns
SCK Period t
SCK
15 ns
SCK Low Time t
SCKH
7ns
SCK High Time t
SCKL
7ns
SCK Falling Edge to Data remains Valid t
HSDO
5ns
SCK Falling Edge to Data Valid delay t
DSDO
OVDD above 4.75V 13 ns
OVDD above 3V 20 ns
OVDD above 2.7V 27 ns
OVDD above 2.3V TBD ns
CNV or SDI Low to SDO D15 MSB Valid (CS mode) t
EN
OVDD above 4.75V 15 ns
OVDD above 2.7V 30 ns
OVDD above 2.3V TBD ns
CNV or SDI High or last SCK Falling Edge
to SDO High Impedance (CS mode) t
DIS
30 ns
SDI valid Setup Time from CNV rising edge (CS mode) t
SSDICNV
8ns
SDI valid Hold Time from CNV rising edge (CS mode) t
HSDICNV
0ns
SCK valid Setup Time from CNV rising edge (Chain mode) t
SSCKCNV
8ns
SCK valid Hold Time from CNV rising edge (Chain mode) t
HSCKCNV
5ns
SDI valid Setup Time from SCK falling edge (Chain mode) t
SSDISCK
8ns
SDI valid Hold Time from SCK falling edge (Chain mode) t
HSDISCK
0ns
SDI High to SDO High (Chain mode with Busy indicator) t
DSDOSDI
OVDD above 4.75V 15 ns
OVDD above 2.7V 30 ns
OVDD above 2.3V TBD ns
(–40OC to +85OC, VDD = 4.5 V to 5.5V, OVDD = 2.3 V to 5.5 V, unless otherwise stated)
PRELIMINARY TECHNICAL DATA
REV. Pr C
–5–
AD7946
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7946 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of
functionality.
ABSOLUTE MAXIMUM RATINGS
1
Analog Inputs
IN+
2
, IN-
2
, REF, . . . . . GND –0.3 V to VDD + 0.3 V
Supply Voltages
VDD, OVDD to GND . . . . . . . . . . . . . . . . -0.3 V to 7 V
VDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
7 V
Digital Inputs to GND . . . . . . –0.3 V to OVDD + 0.3 V
Digital Outputs to GND . . . . –0.3 V to OVDD + 0.3 V
Storage Temperature Range . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
θ
JA
Thermal Impedance . . . . . . . . . . 200°C/W (␮SOIC-10)
θ
JC
Thermal Impedance . . . . . . . . . . . 44°C/W (␮SOIC-10)
TBD°C/W (CSP-10)
Lead Temperature Range
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
See Analog Input section.
AD7946 PIN CONFIGURATION
10-Lead ␮SOIC and 10-Lead CSP
10
9
8
7
6
OVDD
SDI
SCK
SDO
CNV
1
2
3
4
5
REF
VDD
IN+
IN-
GND
AD7946
To SDO
IOL
CL
50pF
IOH
+1.4V
500µA
500µA
Figure 1. Load Circuit for Digital Interface Timing.
30% OVDD
70% OVDD
2V or OVDD-0.5V
1
0.8V or 0.5V
2
0.8V or 0.5V
2
2V or OVDD-0.5V
1
t
DELAY
t
DELAY
Note
1
: 2V if OVDD above 2.5V, OVDD-0.5V if OVDD below 2.5V.
Note
2
: 0.8V if OVDD above 2.5V, 0.5V if OVDD below 2.5V.
Figure 2. Voltage Reference Levels for Timing.
WARNING!
ING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model Temperature Range Package Description Package Option Brand
AD7946BRM –40°C to +85°C ␮SOIC-10 RM-10 C1E
AD7946BRMRL7 –40°C to +85°C ␮SOIC-10 RM-10 (reel) C 1 E
AD7946BCP –40°C to +85°C CSP-10 C1E
EVAL-AD7946CB1Evaluation Board
EVAL-CONTROL BRD22Controller Board
EVAL-CONTROL BRD32Controller Board
NOTES
1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration
purposes.
2
These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–6–
Pin # Mnemonic Function
1 R E F A I Reference Input Voltage. The REF range is from 0.5V to VDD. It is referred to the
GND pin. This pin should be decoupled closely to the pin with a 10␮F capacitor.
2 V D D P Power Supply.
3 I N + A I Analog Input. It is referred to IN-. The voltage range, i.e. the difference between IN+
and IN-, is 0V to VREF.
4 I N - A I Analog Input Ground Sense. To be connected to the analog ground plane or to a remote
sense ground.
5 G N D P Power Supply Ground.
6 C N V D I Convert Input. This input has multiple functions. On its leading edge, it initiates the
conversions and selects the interface mode of the part, Chain or CS mode. In CS mode, it
enables the SDO pin when low. In Chain mode, the data should be read when CNV is
high.
7 S D O D O Serial Data Output. The conversion result or the programming configuration word are
ouput on this pin. It is synchronized to SCK.
8 S C K D I Serial Data Clock Input. When the part is selected, the conversion result is shifted out by
this clock. If less than 14 pulses are applied during selection, the programming
configuration is updated.
9 S D I D I Serial Data Input. This input provides multiple features. It selects the interface mode of
the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is
used as a data input to daisy chain the conversion results of two or more ADCs onto a
single SDO line. The digital data level on SDI is output on SDO with a delay of 14 SCK
cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI
or CNV can enable the serial output signals when low and if SDI or CNV is low when the
conversion is complete, the busy indicator feature is enabled.
10 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host
interface (1.8V, 2.5V, 3V or 5V).
NOTES
AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power
PIN FUNCTION DESCRIPTIONS
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–7–
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL)
Linearity error refers to the deviation of each individual
code from a line drawn from “negative full scale” through
“positive full scale”. The point used as “negative full
scale” occurs 1/2 LSB before the first code transition.
“Positive full scale” is defined as a level 1 1/2 LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line (figure 4).
DIFFERENTIAL NONLINEARITY ERROR (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differ-
ential nonlinearity is the maximum deviation from this
ideal value. It is often specified in terms of resolution for
which no missing codes are guaranteed.
OFFSET ERROR
The first transition should occur at a level 1/2 LSB above
analog ground (152.6 ␮V for the
0 V to 5
V range). The
offset error is the deviation of the actual transition from
that point.
GAIN ERROR
The last transition (from 111 . . . 10 to 111 . . . 11)
should occur for an analog voltage 1 1/2 LSB below the
nominal full scale (4.999542 V for the
0 V to 5
V range).
The gain error is the deviation of the actual level of the
last transition from the ideal level after the offset has been
adjusted out.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The difference, in decibels (dB), between the rms ampli-
tude of the input signal and the peak spurious signal.
EFFECTIVE NUMBER OF BITS (ENOB)
ENOB is a measurement of the resolution with a sine
wave input. It is related to S/(N+D) by the following for-
mula:
ENOB = (S/[N+D]
dB
– 1.76)/6.02)
and is expressed in bits.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first five har-
monic components to the rms value of a full-scale input
signal and is expressed in dB.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding harmonics and dc. The
value for SNR is expressed in dB.
SIGNAL TO (NOISE + DISTORTION) RATIO
(S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input
signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but
excluding dc. The value for S/(N+D) is expressed in dB.
APERTURE DELAY
Aperture delay is a measure of the acquisition performance
and is the time between the rising edge of the CNV input
and when the input signal is held for a conversion.
TRANSIENT RESPONSE
The time required for the AD7946 to accurately acquire
its input after a full-scale step function was applied.
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–8–
CIRCUIT INFORMATION
The AD7946 is a fast, low-power, single-supply, precise
14-bit analog-to-digital converter (ADC) using a succes-
sive approximation architecture.
It features different modes to optimize performance ac-
cording to the application.
In Warp mode, the AD7946 is capable of converting
500,000 samples per second (500kSPS).
In Impulse mode, the AD7946 is capable of converting
380,000 samples per second (380kSPS) and powers down
between conversions. When operating at 100SPS, for ex-
ample, it consumes typically 1.6␮W with a 2.5V supply,
ideal for battery-powered applications.
The AD7946 provides the user with an on-chip track/hold
and does not exhibit any pipeline delay or latency, making
it ideal for multiple multiplexed channel applications.
The AD7946 can be operated from a single 2V to 5.5V
supply, specified from 2.3V to 5.5V, and can be interfaced
to either 5 V or 3.3 V or 2.5 V or 1.8V digital logic. It is
housed in a 10-lead ␮SO or a tiny 10-lead CSP (chip
scale package) that combines space savings and allows
flexible configurations.
It is pin-for-pin-compatible with the 16-bit AD7686.
CONVERTER OPERATION
The AD7946 is a successive approximation ADC based on
a charge redistribution DAC. Figure 3 shows the simpli-
fied schematic of the ADC. The capacitive DAC consists
of two identical arrays of 14 binary weighted capacitors
which are connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to
the comparator’s input are connected to GND via SW+
and SW-. All independent switches are connected to the
analog inputs. Thus, the capacitor arrays are used as sam-
pling capacitors and acquire the analog signal on the IN+
and IN- inputs. When the acquisition phase is complete
and the CNV input goes high, a conversion phase is initi-
ated. When the conversion phase begins, SW+
and SW-
SW
+
MSB
8,192C 4,096C 4C 2C C C
IN+
LSB
COMP
SW
-
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
MSB
8,192C 4,096C 4C 2C C C
IN -
LSB
Figure 3. ADC Simplified Schematic
are opened first. The two capacitor arrays are then discon-
nected from the inputs and connected to the GND input.
Therefore, the differential voltage between the inputs IN+
and IN- captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator
to become unbalanced. By switching each element of the
capacitor array between GND or REF, the comparator
input varies by binary weighted voltage steps (V
REF
/2,
V
REF
/4 . . . V
REF
/16384). The control logic toggles these
switches, starting with the MSB, in order to bring the
comparator back into a balanced condition. After the
completion of this process, the part returns to the acquisi-
tion phase and the control logic generates the ADC output
code and a BUSY signal indicator.
Because the AD7946 has an on-board conversion clock,
the serial clock SCK is not required for the conversion
process.
Modes of Operation
The AD7946 features three modes of operations, Warp,
Normal, and Impulse. Each of these modes is optimized
for specific applications.
- Warp mode allows the fastest conversion rate up to
500kSPS. However, in this mode, and this mode only, the
full specified accuracy is guaranteed only when the time
between conversion does not exceed 1ms. If the time be-
tween two consecutive conversions is longer than 1ms, for
instance, after power-up, the first conversion result should
be ignored. This mode makes the AD7946 ideal for appli-
cations where fast sample rates are required.
- Normal mode is the fastest mode (450kSPS) without any
limitation in the time between conversions. This mode
makes the AD7946 ideal for asynchronous applications
such as data acquisition systems, where both high accu-
racy and fast sample rates are required.
- Impulse mode, the lowest power dissipation mode, pow-
ers down between conversions. The maximum throughput
in this mode is 380kSPS. When operating at 100SPS and
2.5V, for example, it typically consumes only 1.6µW.
This feature makes the AD7946 ideal for battery-powered
applications.
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–9–
The mode of operation is unknown at power-up and must
be selected using a programming sequence (see table II).
Transfer Functions
The ideal transfer characteristic for the AD7946 is shown
in Figure 4 and Table I.
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE - Straight Binary
ANALOG INPUT
+FS-1.5 LSB
+FS-1 LSB
-FS+1 LSB-FS
-FS+0.5 LSB
Figure 4. ADC Ideal Transfer Function
Table I. Output Codes and Ideal Input Voltages
D
escription Analog Digital Output Code
Input Hexa
V
REF
= 5V
FSR –1 LSB 4.999695V 3FFF
1
Midscale + 1 LSB 2.500305V 2001
Midscale 2.5 V 2000
Midscale – 1 LSB 2.499695V 1FFF
–FSR + 1 LSB 305.2µV 0001
–FSR 0 V 0000
2
NOTES
1
This is also the code for an overranged analog input (V
IN+
– V
IN-
above V
REF
– V
GND
).
2
This is also the code for an underranged analog input (V
IN+
– V
IN-
below V
GND
).
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–10–
DIGITAL INTERFACE
Though the AD7946 has a reduced number of pins, it
offers flexibility in its serial interface modes:
The AD7946, when in “CS mode”, is compatible with
SPI, QSPI digital hosts and DSPs (e.g.Blackfin ADSP-
BF53x or ADSP-219x). This interface can use either 3 or
4 wires. A three wire interface using the CNV, SCK and
SDO signals, minimizes wiring connections useful, for
instance, in isolated applications. A four wire interface
using the SDI, CNV, SCK and SDO signals allows CNV,
which initiates the conversions, to be independent of the
readback timing (SDI). This is useful in low jitter sam-
pling or simultaneous sampling applications.
The AD7946, when in “Chain mode”, provides a “daisy
chain” feature using the SDI input for cascading multiple
ADCs on a single data line similar to a shift register.
The mode in which the part operates depends on the SDI
level when the CNV rising edge occurs. The CS mode is
selected if SDI is high and the chain mode is selected if
SDI is low. The SDI hold time is such that when SDI and
CNV are connected together, the chain mode is always
selected.
In either mode, the AD7946 offers the flexibility to op-
tionally force a start bit in front of the data bits. This start
bit can be used as a busy signal indicator to interrupt the
digital host and trigger the data reading. Otherwise, with-
out a busy indicator, the user must time out the maximum
conversion time prior to readback.
The busy indicator feature is enabled as follows:
In CS mode, if CNV or SDI is low when the ADC con-
version ends (figure 8 and 12).
In Chain mode, if SCK is high during the CNV rising
edge (figure 16).
SDO D13 D12 D11 D1 D0
tDIS
SCK 1 2 3 12 13 14
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
tEN
CONVERSIONACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI = 1
tCNVH
Figure 6.
CS
mode 3 wires, no busy indicator serial interface timing ( SDI high ).
CSCS
CSCS
CS MODE 3 wires, no Busy indicator
This mode is usually used when a single AD7946 is con-
nected to an SPI compatible digital host. The connection
diagram is shown in figure 5 and the corresponding tim-
ing is given in figure 6.
With SDI tied to OVDD, a rising edge on CNV initiates
a conversion, selects the CS mode and forces SDO to
high impedance. Once a conversion is initiated, it will
continue to completion irrespective of the state of CNV.
For instance, it could be useful to bring CNV low to se-
lect other SPI devices such as analog multiplexers but
CNV must be returned high before the minimum conver-
sion time and held high until the maximum conversion
time to avoid the generation of the busy signal indicator.
When the conversion is complete, the AD7946 enters the
acquisition phase and powers down if in impulse mode.
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are then clocked by subsequent SCK
driving edges. The driving edge can be either falling or
rising depending on how the part is programmed (see
table II). The data is valid on both SCK edges. Although
the non-driving edge can be used to capture the data, a
digital host also using the SCK driving edge will allow a
faster reading rate provided it has an acceptable hold time.
After the 14th SCK driving edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDOSDI DATA IN
CLK
CONVERT
OVDD
Digital Host
AD7946
Figure 5.
CS
mode 3 wires, no busy indicator connection
diagram ( SDI high ).
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–11–
SDO D13 D12 D1 D0
tDIS
SCK 1 2 3 13 14 15
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSIONACQUISITION
tCONV
tCYC
tCNVH
tACQ
ACQUISITION
SDI = 1
Figure 8.
CS
mode 3 wires with busy indicator serial interface timing ( SDI high ).
CSCS
CSCS
CS MODE 3 wires with Busy indicator
This mode is usually used when a single AD7946 is con-
nected to an SPI compatible digital host having an
interrupt input.
The connection diagram is shown in figure 7 and the cor-
responding timing is given in figure 8.
With SDI tied to OVDD, a rising edge on CNV initiates
a conversion, selects the CS mode and forces SDO to
high impedance. SDO is maintained in high impedance
until the completion of the conversion irrespective of the
state of CNV. Prior to the minimum conversion time,
CNV could be used to select other SPI devices such as
analog multiplexers but CNV must be returned low before
the minimum conversion time and held low until the
maximum conversion time to guarantee the generation of
the busy signal indicator. When the conversion is com-
plete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by
the digital host. The AD7946 then enters the acquisition
phase and powers down if in impulse mode. The data bits
are then clocked out, MSB first, by subsequent SCK driv-
ing edges. The SCK driving edge, either falling or rising,
can be selected using a programming sequence (see table
II). The data is valid on both SCK edges. Although the
non-driving edge can be used to capture the data, a digital
host also using the SCK driving edge will allow a faster
reading rate provided it has an acceptable hold time. After
the optional 15th SCK driving edge or when CNV goes
high whichever is earlier, SDO returns to high imped-
ance.
IRQ
CNV
SCK
SDOSDI DATA IN
CLK
CONVERT
OVDD
47k⍀OVDD
Digital Host
AD7946
Figure 7.
CS
mode 3 wires with busy indicator connection
diagram ( SDI high ).
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–12–
CNV
SCK
SDOSDI
DATA IN
CLK
CONVERT
Digital Host
AD7946
CNV
SCK
SDOSDI
AD7946
CS1
CS2
Figure 9.
CS
mode 4 wires, no busy indicator connection diagram.
SDO D13 D12 D11 D1 D0
tDIS
SCK 123 26 27 28
tHSDO
tDSDO
tEN
CONVERSIONACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI(CS1)
CNV
tSSDICNV
tHSDICNV
D1
12 13
tSCK
tSCKL
tSCKH
D0 D13 D12
15 1614
SDI(CS2)
Figure 10.
CS
mode 4 wires, no busy indicator serial interfacetiming.
CSCS
CSCS
CS MODE 4 wires, no Busy indicator
This mode is usually used when multiple AD7946’s are
connected to an SPI compatible digital host.
A connection diagram example using two AD7946’s is
shown in figure 9 and the corresponding timing is given in
figure 10.
With SDI high, a rising edge on CNV initiates a conver-
sion, selects the CS mode and forces SDO to high
impedance. In this mode, CNV must be held high during
the conversion phase and the subsequent data readback (if
SDI and CNV are low, SDO is driven low). Prior to the
minimum conversion time, SDI could be used to select
other SPI devices, such as analog multiplexers but SDI
must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the busy signal indicator. When
the conversion is complete, the AD7946 enters the acqui-
sition phase and powers down if in impulse mode. Each
ADC result can be read by bringing low its SDI input
which consequently outputs the MSB onto SDO. The
remaining data bits are then clocked by subsequent SCK
driving edges. The SCK driving edge, either falling or
rising, can be selected using a programming sequence (see
table II). The data is valid on both SCK edges. Although
the non-driving edge can be used to capture the data, a
digital host also using the SCK driving edge will allow a
faster reading rate provided it has an acceptable hold time.
After the 14th SCK driving edge or when SDI goes high
whichever is earlier, SDO returns to high impedance and
another AD7946 can be read.
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–13–
SDO
D13 D12 D1 D0
t
DIS
SCK
1 2 3 13 14 15
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI
CNV
t
SSDICNV
t
HSDICNV
Figure 12.
CS
mode 4 wires with busy indicator serial interface timing.
CSCS
CSCS
CS MODE 4 wires with Busy indicator
This mode is usually used when a single AD7946 is con-
nected to an SPI compatible digital host having an
interrupt input and it is desired to keep CNV, used to
sample the analog input, independent of the signal used to
select the data reading. This requirement is particularly
important in applications where low jitter on CNV is de-
sired.
The connection diagram is shown in figure 11 and the
corresponding timing is given in figure 12.
With SDI high, a rising edge on CNV initiates a conver-
sion, selects the CS mode and forces SDO to high
impedance. In this mode, CNV must be held high during
the conversion phase and the subsequent data readback (if
SDI and CNV are low, SDO is driven low). Prior to the
minimum conversion time, SDI could be used to select
other SPI devices, such as analog multiplexers but SDI
must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
impedance to low. With a pull-up on SDO line, this tran-
sition can be used as an interrupt signal to intiate the data
readback controlled by the digital host. The AD7946 then
enters the acquisition phase and powers down if in impulse
mode. The data bits are then clocked out, MSB first, by
subsequent SCK driving edges. The SCK driving edge,
either falling or rising, can be selected using a program-
ming sequence (see table II). The data is valid on both
SCK edges. Although the non-driving edge can be used to
capture the data, a digital also host using the SCK driving
edge will allow a faster reading rate provided it has an
acceptable hold time. After the optional 15th SCK driving
edge or SDI going high, whichever is earlier, the SDO
returns to high impedance.
CNV
SCK
SDOSDI DATA IN
CLK
CONVERT
OVDD
47k⍀
Digital Host
AD7946
CS1
IRQ
Figure 11.
CS
mode 4 wires with busy indicator connection
diagram .
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–14–
CNV
SCK
SDOSDI DATA IN
CLK
CONVERT
Digital Host
AD7946
CNV
SCK
SDOSDI
AD7946
AB
Figure 13. Chain mode, no busy indicator connection diagram .
SDOA = SDIB
DA13 DA12 DA11
SCK
1 2 3 26 27 28
t
SSDISCK
t
HSDISC
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV
DA1
12 13
t
SCK
t
SCKL
t
SCKH
DA0
15 1614
SDIA = 0
SDOB
DB13 DB12 DB11 DA1D
A0DB1 DB0D
A13 DA12
t
HSDO
t
DSDO
t
SSCKCNV
t
HSCKCNV
Figure 14. Chain mode, no busy indicator Serial InterfaceTiming.
Chain MODE, no Busy indicator
This mode can be used to “daisy-chain” multiple
AD7946’s on a 3 wire serial interface. This feature is
useful for reducing component count and wiring connec-
tions e.g. in isolated multiconverter applications or for
systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register.
A connection diagram example using two AD7946’s is
shown in figure 13 and the corresponding timing is given
in figure 14.
When SDI and CNV are low, SDO is driven low. With
SCK low, a rising edge on CNV initiates a conversion,
selects Chain mode and disables the busy indicator. In this
mode, CNV is held high during the conversion phase and
the subsequent data readback. When the conversion is
complete, the MSB is output onto SDO and the AD7946
enters the acquisition phase and powers down if in impulse
mode. The remaining data bits stored in the internal shift
register are then clocked by subsequent SCK driving
edges. The SCK driving edge, either falling or rising, can
be selected using a programming sequence (see table II).
For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK driving edge. Each
ADC in the chain output its data MSB first, and 14*N
clocks are required to readback the N ADCs. The data is
valid on both SCK edges. Although the non-driving edge
can be used to capture the data, a digital host also using
the SCK driving edge will allow a faster reading rate and,
consequently more AD7946s in the chain provided the
digital host has an acceptable hold time. The maximum
conversion rate may be reduced due to the total readback
time. For instance, with a 5ns digital host set-up time and
5V interface, up to four AD7946’s running at a conversion
rate of 370 kSPS in warp mode can be daisy-chained on a
3 wire port.
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–15–
CNV
SCK
SDOSDI DATA IN
CLK
CONVERT
Digital Host
AD7946
CNV
SCK
SDOSDI
AD7946
A C
IRQ
CNV
SCK
SDOSDI
AD7946
B
Figure 15. Chain mode with busy indicator connection diagram .
SDOA = SDIB
DA13 DA12 DA11
SCK
123 31 41 42
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV = SDIA
DA1
413
t
SCK
t
SCKH
t
SCKL
DA0
15 3013
SDOB = SDIC
DB13 DB12 DB11 DA1D
A0DB1 DB0D
A13 DA12
43
t
SSDISCK
t
HSDISC
t
HSDO
t
DSDO
SDOC
DC13 DC12 DC13 DA1D
A0DC1 DC0D
A13 DA12
17 27 2816 29
DB1D
B0DB13 DB12
t
DSDOSDI
t
SSCKCNV
t
HSCKCNV
Figure 16. Chain mode with busy indicator serial interface timing.
Chain MODE with Busy indicator
This mode can also be used to “daisy-chain” multiple
AD7946’s on a 3 wire serial interface while providing a
busy indicator. This feature is useful for reducing compo-
nent count and wiring connections e.g. in isolated
multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clock-
ing a shift register.
A connection diagram example using three AD7946’s is
shown in figure 15 and the corresponding timing is given
in figure 16.
When SDI and CNV are low, SDO is driven low. With
SCK high, a rising edge on CNV initiates a conversion,
selects Chain mode and enables the busy indicator feature.
In this mode, CNV is held high during the conversion
phase and the subsequent data readback. When all ADCs
in the chain have completed their conversions, the “near-
end” ADC ( ADC C in figure 15 ) SDO will be driven
high. This transition on SDO can be used as a busy indi-
cator to trigger the data readback controlled by the digital
host. The AD7946 then enters the acquisition phase and
powers down in impulse mode. The data bits stored in the
internal shift register are then clocked out, MSB first, by
subsequent SCK driving edges. The SCK driving edge,
either falling or rising, can be selected using a program-
ming sequence (see table II). For each ADC, SDI feeds
the input of the internal shift register and is clocked by the
SCK driving edge. Each ADC in the chain outputs its
data MSB first, and 14*N +1 clocks are required to
readback the N ADCs. Although the non-driving edge can
be used to capture the data, a digital host also using the
SCK driving edge will allow a faster reading rate and,
consequently more AD7946s in the chain provided the
digital host has an acceptable hold time. For instance,
with a 5ns digital host set-up time and 5V interface, up to
four AD7946’s running at a conversion rate of 370 kSPS
in warp mode can be daisy-chained to a single 3 wire port.
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–16–
Programming the configuration of the AD7946
The AD7946 offers the following features which can be
selected by the user via a truncated readback:
- The modes of operation: Warp, Normal or Impulse.
- An internal input low pass filter with selectable band-
width for anti-aliasing and external noise filtering.
- The driving edge polarity used to output the data on
SDO.
- Synchronizing the busy indicator to SCK.
- A single command “reset to default settings”.
- Current configuration readback.
The programming configuration is modified only if less
than 14 rising edges are applied on the SCK input after
the conversion while the part is selected. The configura-
tion is actually updated when the part is deselected. The
number of SCK rising edges programs the feature selec-
tion according to table II.
In Chain mode (figure 17):
- The SCK rising edges are counted after the completion
of the conversion when CNV is high.
- The AD7946 is deselected and the configuration is up-
dated when CNV goes low.
- Only one single change of the configuration can be done
per conversion.
In CSCS
CSCS
CS mode, 3 wire (figure 18):
- While SDI is high, the SCK rising edges are counted
after the completion of the conversion when CNV is taken
low.
- The AD7946 is deselected and the configuration is up-
dated when CNV is taken high.
- If CNV and SDI are simultaneously low, SDO is forced
low, any SCK rising edges are ignored and the configura-
tion is not changed when the part is deselected.
- Only one single change of the configuration can be done
per conversion.
SDI=1
SCK
CONVERSIONACQUISITION ACQUISITION
CNV
SDO D13 D12 D11 D6D7
Reset
D10 D8D9
Figure 18. Programming example using CNV in
CS
mode
( “Reset to default settings”).
SDI=0
SCK
CONVERSIONACQUISITION ACQUISITION
CNV
SDO D13 D12 D11 D6D7
Reset
D10 D8D9
Figure 17. Programming example using in Chain mode
( “Reset to default settings”).
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–17–
SDI
SCK
CONVERSIONACQUISITION ACQUISITION
CNV
SDO D13 D12 D11 D11 D10 D10 D9
D8
D0D1D6D7D8
ACQUISITIONCONVERSION
Reset Synchronous Busy Readback
Figure 19. Programming example using SDI in
CS
mode
( high bandwidth, synchronous busy indicator, falling SCK driving edge, warp mode followed by a configuration readback).
In CSCS
CSCS
CS mode, 4 wire (figure 19):
- While CNV is high, the SCK rising edges are counted
after the completion of the conversion when SDI is taken
low.
- The AD7946 is deselected and the configuration is up-
dated every time SDI is taken high.
- In this mode, the selected feature depends on the total
number of SCK rising edges seen since the end of conver-
sion.
- If CNV and SDI are simultaneously low, SDO is forced
low, any SCK rising edges are ignored and the configura-
tion is not changed when the part is deselected.
- A complete new configuration could be selected during a
single conversion. The data on the SDO output is still the
valid ADC result and the complete 14 bit result can be
read. In the example shown in figure 19, the selected con-
figuration is high bandwidth, synchronous busy indicator,
falling SCK driving edge, warp mode and the configura-
tion is be readback after the subsequent conversion.
Programming details (all modes):
The settings are undefined at power-up, therefore a “reset
to default settings” programming of the AD7946 must be
done after power-up.
However, a “Reset to default settings” command ( 3 or 8
SCK pulses ) changes the configuration to a factory pre-
defined state ( warp mode, high bandwidth, asynchronous
busy indicator and falling SCK driving edge ). SPI com-
patible digital hosts offer the possibility to send 8 SCK
pulses by software.
A truncated valid ADC result is still available on the SDO
output.
When the mode of operation is changed to warp mode, the
next conversion result should be ignored.
When the mode of operation is changed to normal mode,
the next conversion should be initiated after a t
ACQ
delay
to provide a valid result otherwise the next conversion
result should be ignored.
When the mode of operation is changed to impulse mode,
the next conversion can be initiated immediately and pro-
vides a valid result.
When the readback command is selected, the configura-
tion will be output on the SDO pin in place of the ADC
result during the readback of the following conversion as
shown in figure 19. The configuration can also be
changed when it is readback.
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–18–
Number Program Readback Value Default Settings
of SCK rising Feature at Reset
edges
0 No effect
1 No effect 1 (D13=MSB)
2 No effect ( do not use ) 1 (D12)
3 Reset to Default settings 0 (D11)
4 Toggle Bandwidth High Bandwidth = 1, High Bandwidth
Low Bandwidth = 0
5 Toggle Busy Indicator Synchronous = 1, Asynchronous
synchronisation Asynchronous = 0
6 Toggle SCK Driving edge Rising = 1, Falling edge
synchronisation Falling = 0
7 Readback content 0 (D7)
8 Reset to Default settings 0 (D6)
9 Set Impulse Impulse = 1, 0, Warp
Warp or Normal = 0
10 No effect 0 (D5)
11 Set Normal Normal = 1, 0, Warp
Impulse or Warp = 0
12 No effect X
13 Set Warp Warp = 1, 1, Warp
Impulse or Normal = 0
14 No effect X
>14 No effect X
Table II. Programming Configuration
PRELIMINARY TECHNICAL DATA
REV. Pr C
AD7946
–19–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
10-Lead ␮SOIC
(RM-10)
0.011 (0.28)
0.003 (0.08)
0.120 (3.05)
0.112 (2.84)
0.022 (0.56)
0.021 (0.53)
6˚
˚
0˚
˚
10 6
5
1
0.0197 (0.50) BSC
0.124 (3.15)
0.112 (2.84)
0.124 (3.15)
0.112 (2.84)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.122 (3.10)
0.110 (2.79)
0.006 (0.15)
0.002 (0.05)
0.016 (0.41)
0.006 (0.15)
0.038 (0.97)
0.030 (0.76)
SEATING
PLANE
0.043 (1.09)
0.037 (0.94)
10-Lead CSP
(CP-10)
Dimensions shown in mm.
3.00
BSC SQ
INDEX
AREA
TOP VIEW
1.50
BCS SQ
0.20 R
1.00
0.90
0.80 0.05 MAX
0.02 NOM
SEATING
PLANE 0.30
0.23
0.18
0.20 REF
1.00 MAX
0.65 TYP
1.74
1.64
1.49
2.48
2.38
2.23
15
10 6
0.50 BSC 0.50
0.40
0.30
0.23
EXPOSED PAD
(BOTTOM VIEW)