A Combined Single Pulse and Repetitive UIS Rating System Application Note Title N93 ) ubct (A omned ngle lse d epetie S ating sm) utho ) eyords nter- A rating system for Unclamped Inductive Switching in PowerMOS transistors already widely accepted and implemented on Intersil PowerMOS transistor data sheets can be applied to a wide range of applications very easily and expanded to cover repetitive UIS pulses by the simple technique of superposition. This allows PowerMOS transistor users to determine if their application lies within the rated capability of a power transistor. Two examples are given of the analysis of UIS stress level in representative applications. The ability of PowerMOS transistors to withstand unclamped inductive switching (UIS) has been recognized since 1985. Although Blackburn has clearly shown [1] UIS stress level is not directly related to energy, many manufacturers of PowerMOS transistors persist in rating their devices in terms of energy capability. Since the energy capability varies with the operating conditions, this rating is valid only at the condition specified and the PowerMOS transistor user has no way to calculate whether the particular application exceeds the device rating. Ronan has defined a rating system [3], herein after called simply the UIS Rating System, which allows manufacturers to specify the capability of their PowerMOS transistors for single pulse UIS in such a way that users can easily determine if their application exposes the device to more UIS stress than is guaranteed in the device data sheet. October 1999 analysis is needed. If the time and current plotted on the rating chart falls between the 25oC and the maximum junction temperature lines further analysis is required. To analyze those cases where the starting temperature and time in avalanche fall between the 25oC and maximum temperature line, first we must determine the junction temperature of the PowerMOS transistor at the start of the UIS pulse. If the UIS stress occurs after a long period in conduction it may be sufficient to just measure the case temperature of the device and calculate the temperature rise between the case and junction from the dissipation and thermal resistance of the device. Any other approach may be used. Once the junction temperature at the start of the pulse has been determined we can extrapolate between the two published rating curves to determine the UIS capability at that starting junction temperature. Ronan [3], Stoltenburg [2] and Blackburn [1] have all indicated that the UIS capability I2AS xtAV is a simple linear function of temperature. Using this allows a straight line extrapolation of the UIS capability of the device at the calculated junction temperature. Then simply compare the calculated capability to the stress determined to determine if the device is within ratings. This simple approach allows users to find out if their application is safe for any single UIS pulse. 300 The Single Pulse UIS Rating System omned ngle lse d epetie S ating sm) This UIS Rating System, requires the user to determine only the peak current through the PowerMOS transistor (IAS), the junction temperature at the start of the UIS pulse (TJ) and the time the transistor remains in avalanche (tAV). It allows the easy determination of the conformance of any application to a specified UIS capability where the worst case conditions can be simulated. It is also quite feasible to calculate the UIS stresses for circuits not yet constructed or conditions not easily simulated. The UIS rating for a PowerMOS transistor (see Figure 1) is presented as a chart with a vertical axis of (IAS) maximum avalanche current vs (tAV) time in avalanche as the horizontal axis. Two lines are shown, one for 25oC and one for the maximum junction temperature. It is fairly easy in most applications to determine the avalanche current and time in avalanche in an existing application by using a current probe. If the time in avalanche and avalanche current plotted on the UIS rating curve fall above and to the right of the 25oC line, the application is beyond the UIS rating of the device and the user stands a risk of device failure. If the time and current plotted on the rating curve fall below and to the left of the maximum junction temperature line the application is within the UIS rating of the device. In either case no further (c)2001 Fairchild Semiconductor Corporation IF R = 0 tAV = (L)(lAS)/(1.3 RATED BVDSS - VDD) IF R 0 tAV = (L/R) ln[(IASxR)/(1.3 RATED BVDSS - VDD) + 1] IDN 100 IAS (A) orpoion, minctor, AN-7515 STARTING TJ = 25oC STARTING TJ = 150oC RFP70N06 10 0.01 0.10 1.00 tAV , TIME IN AVALANCHE (ms) 10.00 FIGURE 1. UNCLAMPED-INDUCTIVE-SWITCHING (SINGLE PULSE UIS) Multiple or Repetitive UIS The handling of repetitive UIS pulses has been ignored by the PowerMOS transistor manufacturers except for an attempt by one manufacturer to rate repetitive UIS at 0.01% of the 25oC power rating with no further qualifications. The UIS rating system outlined in Ronan's paper [3] is quite applicable to repetitive pulses by using the technique of superposition as is commonly done in evaluating repetitive SOA pulses. Each UIS pulse is considered a separate event Application Note 7515 Rev. A Application Note 7515 Example 1 DRAIN SOLENOID and evaluated as if no other pulse existed. It is necessary only to determine IAV (avalanche current), tAV (time in avalanche) and TJ (junction temperature at the start of the pulse), just as in the single pulse case. Usually the last pulse in a series occurs at the highest junction temperature and is therefore the most severe stress. If the PowerMOS transistor is within the specified UIS rating for that pulse, it is certainly within the UIS ratings for previous pulses which occurred at a lower junction temperature. GATE VOLTAGE L RL Usually the junction temperature variation of a PowerMOS transistor over a full repetitive period is very small. The device has a thermal capacitance and does not change temperature instantaneously, so usually using the average junction temperature for the starting temperature to evaluate the avalanche stress does not result in appreciable error. In those cases where the period is long other means must be used to determine the junction temperature at the start of the UIS pulse. GATE SOURCE VDD SCHEMATIC PULSE DURATION = 250s, VGS = 10V ID = 70A NORMALIZED rDS(ON) 2.5 Solenoid Driver: Single Pulse Given: 2.0 1.5 1.0 0.5 0.0 -50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 2. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE Examples The two examples shown below are intended only to illustrate the techniques used to calculate whether a PowerMOS transistor is within its UIS rating or not. Since UIS capability is an interactive function of other environmental stresses, it is necessary to include some calculation of other operating conditions as part of this analysis. The operating conditions in both examples are calculated rather than measured since the determination of UIS capability using measured values for IAV and tAV seemed trivial and self explanatory. The first example is a "single" pulse stress with sufficient time between stresses so that there is no interaction between subsequent pulses, and the second has a period short enough so that the temperature variation over a period is small. (c)2001 Fairchild Semiconductor Corporation VDD = 28V RL = 2.5 Pulse width = Steady state "on" Transistor = RFP70N06 Gate "on" drive = 10V Maximum TJ = 150oC TAMBIENT = 90oC Calculate: L (Maximum allowable inductance) CA (Required case to ambient thermal resistance) RTOTAL = RL + rDS(ON) = 2.5 + (0.014 x 1.8) See Figure 2 RTOTAL = 2.525 IAVALANCHE = 28/2.525 = 11.09A (Peak avalanche current) Using the rule of thumb that the avalanche voltage is equal to the rated breakdown rating multiplied by 1.3 we can write: VAVALANCHE = 60 x 1.3 = 78V tAVALANCHE = (L/R) x ln[(IAV x R)/(VAV - VDD) +1] tAVALANCHE = (L/2.525) x ln[(11.09 x 2.525)/(78 - 28) +1] L = tAVALANCHE /0.176 Application Note 7515 Rev. A Application Note 7515 +10 +10 GATE VOLTAGE GATE VOLTAGE 0 11.09 DRAIN CURRENT IAS DRAIN CURRENT +78V DRAIN VOLTAGE +28V VDS +78V DRAIN VOLTAGE 19.79 AMP +48V WAVEFORM Entering the Unclamped Inductive Switching Chart (See Figure 1) at 150oC and 11.09A we read an allowable tAVALANCHE of 1.5ms. This gives us a maximum allowable L of: L = (1.5E-3)/0.176 = 8.53mH maximum allowable inductance WAVEFORM Determine: Is the PowerMOS transistor within UIS rating? What CA is required? IAVALANCHE = VDD/(RL + rDS(ON)) Now to calculate the required heat sink thermal resistance: IAVALANCHE = 48/(2.4 +(0.014 x 1.8)) See Figure 2 Pd = (I2 x rDS(ON)) = (11.092) x 0.025 = 3.07W IAVALANCHE = 19.79A CA = [TJMAX - PD x JC - TAMBIENT]/PD tAVALANCHE = (L/R) x ln[(IAV x (RL + rDS(ON)))/VAV - VDD) +1] CA = [150 - (3.07 x 1.0) - 40]/3.07 tAVALANCHE = (1E-6/2.425) x ln[19.79 x 2.425/(78 - 48) +1] CA = 18.5 oC/W required thermal resistance, case to ambient. Example 2 tAVALANCHE = 0.395s Entering the Unclamped Inductive Switching Curve (See Figure 1) at 19.79A, we find the device has a tAVALANCHE capability at 150oC of 500s. Obviously this application does not challenge the UIS capability of the RFP70N06. Now to calculate the required heat sink thermal resistance: 2.4 1H DRAIN GATE EAVALANCHE = (VAVALANCHE x IAVALANCHE x tAVALANCHE) /2 EAV = ((60 x 1.3) x 19.79 x (0.395 e-6))/2 EAV = 304.8J per avalanche PAVALANCHE = EAVALANCHE x Frequency SOURCE VDD PAVALANCHE = 304.8e-6 x 100e3 PAVALANCHE = 30.4W SCHEMATIC Switching Regulator - 100kHz Given: Frequency = 100kHz Duty Cycle = 50% RL = 2.4 VDD = 48V TAMBIENT = 40oC TJUNCTION = 150oC Maximum junction temperature L = 1H (Leakage Inductance) PowerMOS transistor = RFP70N06 (c)2001 Fairchild Semiconductor Corporation PCONDUCTION = (IAV2 x rDS(ON))/2 PC = ((19.79)2 x 0.025)/2 PC = 4.90W PTOTAL = PAV + PC PTOTAL = 30.4 + 4.9 PTOTAL = 35.3W CA = [TJMAX - (PTOTAL x JC) - TAMBIENT]/PTOTAL CA = [150 - (35.3 x 1.0) - 40]/35.3 CA = 2.12oC/W Obviously the heat sink is more of a problem than the UIS capability. Application Note 7515 Rev. A Application Note 7515 Application to Other Circuits References Usually the designer of a circuit has carefully determined the temperature of the devices in his circuit over the entire range of operating conditions. Using only the junction temperature of the device at the start of a UIS pulse, the duration of the pulse and the current level of the pulse the designer can determine whether or not his/her application exceeds the UIS rating on the device. These quantities are easily measured or calculated. By superposition this rating can be applied to multiple or repetitive pulses as illustrated in the two examples shown. Any circuit can be analyzed for UIS stress using this approach. There is no need for a separate repetitive UIS rating. For Intersil documents available on the internet, see web site http://www.intersil.com/Intersil AnswerFAX (321) 724-7800. (c)2001 Fairchild Semiconductor Corporation [1] D.L. Blackburn, "Turn-off Failure of Power MOSFETS," Proc. 1985 IEEE Power Electronics Specialists Conference, pp 429-435, June, 1985. [2] Rodney R. Stoltenburg, "Boundary of Power-MOSFET Unclamped Inductive Switching (UIS) Avalanche Current Capability," Proc. 1989 Applied Power Electronics Conference, pp 359-364, March 1989. [3] Harold R. Ronan, "Rating System Compares Single Pulse Unclamped Inductive Switching for MOSFETS," Power Conversion and Intelligent Motion, pp 32-40, September 1991. Application Note 7515 Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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