Contents
1. Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview...............................3
1.1. Intel Stratix 10 MX Devices.....................................................................................4
1.2. Innovations in Intel Stratix 10 MX Devices................................................................ 5
1.3. Intel Stratix 10 MX Features Summary..................................................................... 7
1.4. Intel Stratix 10 MX Block Diagram........................................................................... 9
1.5. Intel Stratix 10 MX Family Plan................................................................................9
1.5.1. Available Options..................................................................................... 13
1.6. Heterogeneous 3D Stacked HBM2 DRAM Memory..................................................... 13
1.7. Intel Hyperflex Core Architecture........................................................................... 14
1.8. Heterogeneous 3D SiP Transceiver Tiles.................................................................. 16
1.9. Intel Stratix 10 MX Transceivers.............................................................................17
1.9.1. PMA Features......................................................................................... 17
1.9.2. PCS Features..........................................................................................19
1.10. PCI Express Gen1/Gen2/Gen3 Hard IP.................................................................. 21
1.11. 100G Ethernet MAC, Reed-Solomon FEC Hard IP, and KP-FEC Hard IP....................... 21
1.12. 10G Ethernet Hard IP......................................................................................... 21
1.13. Interlaken PCS Hard IP....................................................................................... 21
1.14. External Memory and General Purpose I/O............................................................ 22
1.15. Adaptive Logic Module (ALM)............................................................................... 23
1.16. Core Clocking.................................................................................................... 24
1.17. Fractional Synthesis PLLs and I/O PLLs..................................................................25
1.18. Internal Embedded Memory.................................................................................25
1.19. Variable Precision DSP Block................................................................................ 26
1.20. Power Management............................................................................................ 29
1.21. Device Configuration and Secure Device Manager (SDM)......................................... 29
1.22. Device Security..................................................................................................31
1.23. Configuration via Protocol Using PCI Express..........................................................31
1.24. Partial and Dynamic Reconfiguration..................................................................... 32
1.25. Fast Forward Compile......................................................................................... 32
1.26. Single Event Upset (SEU) Error Detection and Correction.........................................32
1.27. Revision History for the Intel Stratix 10 MX (DRAM System-in-Package) Device
Overview ........................................................................................................ 33
Contents
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1. Intel® Stratix® 10 MX (DRAM System-in-Package)
Device Overview
Delivering over 10X higher memory bandwidth compared to discrete DRAM solutions,
Intel® Stratix® 10 MX DRAM System-in-Package (SiP) devices meet the memory
bandwidth requirements of your next-generation designs.
Intel Stratix 10 MX devices integrate 3D stacked High-Bandwidth DRAM Memory
(HBM2) alongside a high-performance monolithic 14 nm FPGA fabric die, and multiple
high-speed transceiver tiles, all inside a single flip-chip FBGA package.
This new class of device offers the highest memory bandwidth available in an FPGA,
eliminating the memory bandwidth bottlenecks in high-performance systems such as
data center, broadcast, wireline networking and high-performance computing systems.
Intel Stratix 10 MX devices enable you to achieve the highest memory bandwidth and
lowest system power, giving you the best bandwidth per watt metric.
Intel Stratix 10 MX devices feature several groundbreaking innovations such as the
new HyperFlex® core architecture, dual mode 57.8 Gbps PAM4 / 28.9 Gbps Non-
Return to Zero (NRZ) transceivers, and advanced packaging technology based on
Intel’s Embedded Multi-die Interconnect Bridge (EMIB). These devices demonstrate
Intel's leadership in high-performance programmable devices and our commitment to
deliver the most advanced solutions to your most challenging system problems.
Important innovations in Intel Stratix 10 MX devices include:
• All new Intel Hyperflex™ core architecture delivering 2X the core performance
compared to previous generation high-performance FPGAs
• Hard HBM2 controller designed to provide the highest levels of performance
• Intel 14 nm tri-gate (FinFET) technology
• Heterogeneous 3D System-in-Package (SiP) technology
• Integrated 3D stacked High-Bandwidth DRAM Memory (HBM2)
• Monolithic core fabric with up to 2.1 million logic elements (LEs)
• Up to 96 full duplex transceiver channels on heterogeneous 3D SiP transceiver
tiles
• Transceiver data rates up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ for chip-to-chip,
chip-to-module, and backplane driving
• Embedded eSRAM (47.25 Mbit) and M20K (20 Kb) internal SRAM memory blocks
• Fractional synthesis and ultra-low jitter LC tank based transmit phase locked loops
(PLLs)
• Hard PCI Express* Gen3 x16 intellectual property (IP) blocks
• Hard 100G Ethernet MAC, 100G Reed-Solomon FEC, and KP-FEC blocks
• Hard memory controllers and PHY supporting DDR4 rates up to 2666 Mbps per pin
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accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
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information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
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*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
• Hard fixed-point and IEEE 754 compliant hard floating-point variable precision
digital signal processing (DSP) blocks with up to 6.5 TFLOP compute performance
with a power efficiency of 80 GFLOP per Watt
• Programmable clock tree synthesis for flexible, low power, low skew clock trees
• Dedicated secure device manager (SDM) for:
— Enhanced device configuration and security
— AES-256, SHA-256/384 and ECDSA-256/384 encrypt/decrypt accelerators and
authentication
— Multi-factor authentication
— Physically Unclonable Function (PUF) service and software programmable
device configuration capability
• Advanced power saving features delivering up to 70% lower core power compared
to previous generation high-performance FPGAs
With these capabilities, Intel Stratix 10 MX devices are ideally suited for the highest
memory bandwidth applications in diverse markets such as:
•Compute and Storage—for custom servers, cloud computing and data center
acceleration
•Networking—for Terabit, 400G and multi-100G bridging, aggregation, packet
processing and traffic management
•Optical Transport Networks—for OTU4, 2xOTU4, 4xOTU4
•Broadcast—for high-end studio distribution, headend encoding/decoding, edge
QAM
•Military—for radar, electronic warfare, and secure communications
•Medical—for diagnostic scanners and diagnostic imaging
•Test and Measurement—for protocol analyzers and application testers
•Wireless—for next-generation 5G networks
1.1. Intel Stratix 10 MX Devices
In addition to delivering up to 512 Gigabyte/s of 3D stacked HBM2 DRAM memory
bandwidth in a single package, Intel Stratix 10 MX devices offer up to 1 GHz core
fabric performance and contain up to 2.1 million LEs in a monolithic fabric. They also
feature up to 96 general purpose transceivers on separate transceiver tiles, and 2666
Mbps DDR4 external memory interface performance. The dual mode transceivers are
capable of data rates up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ for both short reach and
backplane driving applications.
These devices are optimized for FPGA applications that require the highest memory
and transceiver bandwidth, and the highest core fabric performance, with the power
efficiency of Intel 14 nm tri-gate process technology.
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The high-performance monolithic FPGA fabric is based on the new Intel Hyperflex core
architecture that includes additional Hyper-Registers everywhere throughout the
interconnect routing and at the inputs of all functional blocks. The core fabric also
contains an enhanced logic array utilizing Intel's adaptive logic module (ALM) and a
rich set of high performance building blocks including:
• eSRAM (47.25 Mbit) embedded memory blocks
• M20K (20 Kb) embedded memory blocks
• Variable precision DSP blocks with IEEE 754 compliant hard floating-point
• Fractional synthesis and integer PLLs
• Hard memory controllers and PHY for external memory interfaces
• General purpose IO cells
To clock these building blocks, Intel Stratix 10 MX devices use programmable clock
tree synthesis, which uses dedicated clock tree routing to synthesize only those
branches of the clock trees required for the application. All devices support in-system,
fine-grained partial reconfiguration of the logic array, allowing logic to be added and
subtracted from the system while it is operating. The high speed serial transceivers
contain both the physical medium attachment (PMA) and the physical coding sublayer
(PCS), which can be used to implement a variety of industry standard and proprietary
protocols. In addition to the hard PCS, Intel Stratix 10 MX devices contain hard PCI
Express IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane
configurations, and 100G Ethernet MAC, 100G Reed-Solomon FEC, and KP-FEC hard
IP, which free up valuable core logic resources, save power, and increase your
productivity.
1.2. Innovations in Intel Stratix 10 MX Devices
Intel Stratix 10 MX devices deliver many significant improvements over the previous
generation high-performance Stratix V FPGAs.
Table 1. Key Features of Intel Stratix 10 MX Devices Compared to Stratix V Devices
Feature Stratix V FPGAs Intel Stratix 10 MX Devices
Core fabric process technology 28 nm TSMC (planar
transistor)
14 nm Intel tri-gate (FinFET)
Core architecture Conventional core architecture
with conventional interconnect
Intel Hyperflex core architecture with
Hyper-Registers in the interconnect
Core performance 500 MHz 1 GHz
Power dissipation 1x As low as 0.3x
Logic density 952 KLE (monolithic) 2,100 KLE (monolithic)
Integrated 3D stacked HBM2 DRAM
memory
None Up to 16 GB density / 512 GByte per
second bandwidth with 2 HBM2 DRAM
stacks
Embedded memory (eSRAM) None 94.5 Mbits
Embedded memory (M20K) 52 Mbits 134 Mbits
18x19 multipliers 3,926
Note: Multiplier is 18x18 in
Stratix V devices.
7,920
Note: Multiplier is 18x19 in Intel
Stratix 10 MX devices.
continued...
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Feature Stratix V FPGAs Intel Stratix 10 MX Devices
Floating point DSP capability Up to 1 TFLOP, requires soft
floating point adder and
multiplier
Up to 6.5 TFLOP, hard IEEE 754
compliant single precision floating
point adder and multiplier
Maximum transceivers 66 96
Maximum transceiver data rate (chip-to-
chip)
28.05 Gbps Dual mode 57.8 Gbps PAM4 / 28.9
Gbps NRZ
Maximum transceiver data rate (backplane) 12.5 Gbps Dual mode 57.8 Gbps PAM4 / 28.9
Gbps NRZ
Hard memory controller None DDR4 @ 1333 MHz/2666 Mbps
DDR3 @ 1067 MHz/2133 Mbps
Hard protocol IP PCIe* Gen3 x8 PCIe Gen3 x16
100G Ethernet MAC, 100G Reed-
Solomon FEC hard IP, and KP-FEC
hard IP
Core clocking and PLLs Global, quadrant and regional
clocks supported by fractional-
synthesis fPLLs
Programmable clock tree synthesis
supported by fractional synthesis
fPLLs and integer IO PLLs
Register state readback and writeback Not available Non-destructive register state
readback and writeback for ASIC
prototyping and other applications
These innovations result in the following improvements:
•Improved Core Logic Performance: The Intel Hyperflex core architecture
combined with Intel 14-nm Tri-Gate technology allows Intel Stratix 10 MX devices
to achieve 2X the core performance compared to the previous generation
•Lower Power: Intel Stratix 10 MX devices use up to 70% lower power compared
to the previous generation, enabled by Intel 14 nm tri-gate technology, the Intel
Hyperflex core architecture, and optional power savings features built into the
architecture
•Higher Density: Intel Stratix 10 MX devices offer over two times the level of
integration, with up to 2,100K logic elements (LEs) in a monolithic fabric, 94.5
Mbits of embedded eSRAM blocks, over 134 Mbits of embedded M20K memory
blocks, and 7,920 18x19 multipliers
•Improved Transceiver Performance: With up to 96 transceiver channels
implemented in heterogeneous 3D SiP transceiver tiles, Intel Stratix 10 MX
devices support data rates up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ for chip-to-
chip and backplane driving with signal conditioning circuits capable of equalizing
over 30 dB of system loss
•Improved DSP Performance: The variable precision DSP block in Intel Stratix
10 MX devices features hard fixed and floating point capability, with up to 6.5
TFLOP IEEE754 single-precision floating point performance
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•Additional Hard IP: Intel Stratix 10 MX devices include many more hard IP
blocks than previous generation devices, with a hard memory controller included
in each bank of 48 general purpose IOs, hard PCS, PCIe Gen3x16 full protocol
stack, 100 GbE MAC, Reed-Solomon FEC hard IP, and KP-FEC hard IP to support
the transceivers
•Enhanced Core Clocking: Intel Stratix 10 MX devices feature programmable
clock tree synthesis; clock trees are only synthesized where needed, increasing
the flexibility and reducing the power dissipation of the clocking solution
•Additional Core PLLs: The core fabric in Intel Stratix 10 MX devices is supported
by both integer IO PLLs and fractional synthesis fPLLs, resulting in a greater total
number of PLLs than the previous generation
1.3. Intel Stratix 10 MX Features Summary
Table 2. Intel Stratix 10 MX Device Features
Feature Description
Core process technology • 14 nm Intel tri-gate (FinFET) process technology
• SmartVID controlled core voltage, standard power devices
Low power serial
transceivers
• Up to 96 total transceivers available
• Continuous operating range of 1 Gbps to 57.8 Gbps PAM4 / 28.9 Gbps NRZ
• Backplane support up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ
• Extended range down to 125 Mbps with oversampling
• ATX transmit PLLs with user-configurable fractional synthesis capability
• XFP, SFP+, QSFP/QSFP28, CFP/CFP2/CFP4 optical module support
• Adaptive linear and decision feedback equalization
• Transmit pre-emphasis and de-emphasis
• Dynamic partial reconfiguration of individual transceiver channels
• On-chip instrumentation (Eye Viewer non-intrusive data eye monitoring)
General purpose I/Os • Up to 656 total GPIO available
• 1.6 Gbps LVDS—every pair can be configured as an input or output
• 1333 MHz/2666 Mbps DDR4 external memory interface
• 1067 MHz/2133 Mbps DDR3 external memory interface
• 1.2 V to 3.0 V single-ended LVCMOS/LVTTL interfacing
• On-chip termination (OCT)
Embedded hard IP • PCIe Gen1/Gen2/Gen3 complete protocol stack, x1/x2/x4/x8/x16 end point and root
port
• 100 GbE MAC, Reed-Solomon FEC hard IP, and KP-FEC hard IP
• DDR4/DDR3 hard memory controller (RLDRAM3/QDR II+/QDR IV using soft memory
controller)
• Multiple hard IP instantiations in each device
Transceiver hard IP • 10GBASE-KR/40GBASE-KR4 FEC
• 10G Ethernet PCS
• PCI Express PIPE interface
• Interlaken PCS
• Gigabit Ethernet PCS
• Deterministic latency support for Common Public Radio Interface (CPRI) PCS
• Fast lock-time support for Gigabit Passive Optical Networking (GPON) PCS
• 8B/10B, 64B/66B, 64B/67B encoders and decoders
• Custom mode support for proprietary protocols
Power management • SmartVID controlled core voltage, standard power devices
• Intel Quartus® Prime Pro Edition integrated power analysis
continued...
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Feature Description
High performance monolithic
core fabric
• Intel Hyperflex core architecture with Hyper-Registers everywhere throughout the
interconnect routing and at the inputs of all functional blocks
• Monolithic fabric minimizes compile times and increases logic utilization
• Enhanced adaptive logic module (ALM)
• Improved multi-track routing architecture reduces congestion and improves compile
times
• Hierarchical core clocking architecture with programmable clock tree synthesis
• Fine-grained partial reconfiguration
Internal memory blocks • eSRAM—47.25 Mbit with hard ECC support
• M20K—20 Kb with hard ECC support
• MLAB—640 bit distributed LUTRAM
Variable precision DSP
blocks
• IEEE 754-compliant hard single-precision floating point capability
• Supports signal processing with precision ranging from 18x19 up to 54x54
• Native 27x27 and 18x19 multiply modes
• 64 bit accumulator and cascade for systolic FIRs
• Internal coefficient memory banks
• Pre-adder/subtractor improves efficiency
• Additional pipeline register increases performance and reduces power
Phase locked loops (PLL) • Fractional synthesis PLLs (fPLL) support both fractional and integer modes
• Fractional mode with third-order delta-sigma modulation
• Precision frequency synthesis
• Integer PLLs adjacent to general purpose I/Os, support external memory, and LVDS
interfaces, clock delay compensation, zero delay buffering
Core clock networks • 1 GHz fabric clocking
• 667 MHz external memory interface clocking, supports 2666 Mbps DDR4 interface
• 800 MHz LVDS interface clocking, supports 1600 Mbps LVDS interface
• Programmable clock tree synthesis, backwards compatible with global, regional and
peripheral clock networks
• Clocks only synthesized where needed, to minimize dynamic power
Configuration • Dedicated Secure Device Manager
• Software programmable device configuration
• Serial and parallel flash interface
• Configuration via protocol (CvP) using PCI Express Gen1/Gen2/Gen3
• Fine-grained partial reconfiguration of core fabric
• Dynamic reconfiguration of transceivers and PLLs
• Comprehensive set of security features including AES-256, SHA-256/384, and
ECDSA-256/384 accelerators, and multi-factor authentication
• Physically Unclonable Function (PUF) service
Packaging • Intel Embedded Multi-die Interconnect Bridge (EMIB) packaging technology
• Multiple devices with identical package footprints allows seamless migration across
different device densities
• 1.0 mm ball-pitch FBGA packaging
• Lead and lead-free package options
Software and tools • Intel Quartus Prime Pro Edition design suite with new compiler and Hyper-Aware design
flow
• Fast Forward compiler to allow Intel Hyperflex architecture performance exploration
• Transceiver toolkit
• Platform Designer system integration tool
• DSP Builder advanced blockset
• OpenCL™ support
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1.4. Intel Stratix 10 MX Block Diagram
Figure 1. Intel Stratix 10 MX Architecture Block Diagram
Transceiver Tile
(24 Channels)
PCIe Gen3 Hard IP
100GbE Hard IP
EMIB
Transceiver Tile
(24 Channels)
EMIB
Variable-Precision, Hard Floating-Point DSP Blocks
M20K Embedded Memory Blocks
Hard Memory Controllers, I/O PLLs General-Purpose I/O Cells, LVDS
HyperFlex Core Logic Fabric
Variable-Precision, Hard Floating-Point DSP Blocks
M20K Embedded Memory Blocks
HyperFlex Core Logic Fabric
SDM
Hard Memory Controllers, I/O PLLs General-Purpose I/O Cells, LVDS
Variable-Precision, Hard Floating-Point DSP Blocks
M20K Embedded Memory Blocks
Transceiver Tile
(24 Channels)
100GbE Hard IP
EMIB
Transceiver Tile
(24 Channels)
100GbE Hard IP
EMIB
Package
Substrate
SDM: Secure Device Manager
EMIB: Embedded Multi-Die Interconnect Bridge
eSRAM: Embedded SRAM Memory Block
HBM2: High Bandwidth Memory
UIB: Universal Interface Bus
UIBeSRAM
EMIB
DRAM (HBM2)
UIBeSRAM
EMIB
DRAM (HBM2)
100GbE Hard IP
1.5. Intel Stratix 10 MX Family Plan
(1) The number of 27x27 multipliers is one-half the number of 18x19 multipliers.
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Table 3. Intel Stratix 10 MX Family Plan—FPGA Core (part 1)
Intel
Stratix 10
MX Device
Name
Logic Ele-
ments (KLE)
eSRAM
Blocks
eSRAM
Mbits
M20K
Blocks
M20K
Mbits
MLAB
Counts
MLAB
Mbits
18x19
Multi-
pliers (1)
HPS
Quad
Core
MX 1650 1679 2 94.5 6,162 120 14,230 9 6,652 —
MX 2100 2073 2 94.5 6,847 134 17,568 11 7,920 —
Table 4. Intel Stratix 10 MX Family Plan—Interconnects, PLLs, Hard IP, and HBM2
(part 2)
Intel
Stratix 10
MX Device
Name
Interconnects PLLs Hard IP HBM2 Tile
Layout
Maximum
GPIOs
Maximum
XCVR
fPLLs I/O PLLs PCIe
Hard IP
Blocks
100GbE
MACs
Bandwidth
(GByte/s)
Density
(GB)
MX 1650 656 96 32 16 4 4 512 8 2
MX 1650 656 96 32 16 4 4 512 16 3
MX 1650 584 96 8 16 1 13 512 8 4
MX 2100 640 48 16 16 2 2 512 8 1
MX 2100 656 96 32 16 4 4 512 8 2
MX 2100 656 96 32 16 4 4 512 16 3
MX 2100 584 96 8 16 1 13 512 8 4
Table 5. Intel Stratix 10 MX Package Plan
Cell legend: General Purpose I/Os, High-Voltage I/Os, LVDS Pairs, Transceivers, HBM2 Density Gbytes, HBM2
Bandwidth Gbytes/s, tile layout (2) (3) (4) (5) (6)
Stratix 10 MX Device Name F1760
NF43
(42.5x42.5 mm2)
F2597
NF53/UF53
(52.5x52.5 mm2)
F2912
UF55
(55x55 mm2)
MX 2100 N/A 640, 16, 312, 48
8, 512, tile layout 1
N/A
MX 1650 N/A 656, 32, 312, 96
8, 512, tile layout 2
584, 8, 288, 96
8, 512, tile layout 4
MX 2100 N/A 656, 32, 312, 96 584, 8, 288, 96
continued...
(2) All packages are ball grid arrays with 1.0 mm pitch.
(3) High-Voltage I/O pins are used for 3 V and 2.5 V interfacing.
(4) Each LVDS pair can be configured as either a differential input or a differential output.
(5) High-Voltage I/O pins and LVDS pairs are included in the General Purpose I/O count.
Transceivers are counted separately.
(6) Each package column offers pin migration (common circuit board footprint) for all devices in
the column.
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Stratix 10 MX Device Name F1760
NF43
(42.5x42.5 mm2)
F2597
NF53/UF53
(52.5x52.5 mm2)
F2912
UF55
(55x55 mm2)
8, 512, tile layout 2 8, 512, tile layout 4
MX 1650 N/A 656, 32, 312, 96
16, 512, tile layout 3
N/A
MX 2100 N/A 656, 32, 312, 96
16, 512, tile layout 3
N/A
Figure 2. Tile Layout 1: Intel Stratix 10 MX Device with 2 H-Tiles (48 Transceiver
Channels) and Two 4 GByte HBM2
H-Tile
(24 Channels)
Package Substrate
EMIB
Core Fabric
®
MX 2100 NF53 (F2597B)
H-Tile
(24 Channels)
EMIB
HBM2
HBM2 4 GByte
4 GByte
Figure 3. Tile Layout 2: Intel Stratix 10 MX Device with 4 H-Tiles (96 Transceiver
Channels) and Two 4 GByte HBM2
H-Tile
(24 Channels)
Package Substrate
EMIBEMIB
Core Fabric
®
MX 1650 UF53 (F2597A)
HBM2
H-Tile
(24 Channels)
H-Tile
(24 Channels)
EMIBEMIB
HBM2
MX 2100 UF53 (F2597A)
H-Tile
(24 Channels)
4 GByte
4 GByte
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Figure 4. Tile Layout 3: Intel Stratix 10 MX Device with 4 H-Tiles (96 Transceiver
Channels) and Two 8 GByte HBM2
H-Tile
(24 Channels)
Package Substrate
EMIBEMIB
Core Fabric
®
MX 1650 UF53 (F2597C)
HBM2
H-Tile
(24 Channels)
H-Tile
(24 Channels)
EMIBEMIB
HBM2
MX 2100 UF53 (F2597C)
H-Tile
(24 Channels)
8 GByte
8 GByte
Figure 5. Tile Layout 4: Intel Stratix 10 MX Device with 3 E-Tiles, 1 H-Tile (96
Transceiver Channels) and Two 4 GByte HBM2
E-Tile
(24 Channels)
Package Substrate
EMIBEMIB
Core Fabric
®
MX 1650 UF55 (F2912)
HBM2
E-Tile
(24 Channels)
EMIBEMIB
HBM2
MX 2100 UF55 (F2912)
E-Tile
(24 Channels)
H-Tile
(24 Channels)
4 GByte
4 GByte
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1.5.1. Available Options
Figure 6. Sample Ordering Code and Available Options for Stratix 10 MX Devices
Family Signature
Transceiver Tile SiP Configuration
Transceiver
Channel Count
Transceiver Speed (GXT/GXE)
Package Type
Operating Temperature
FPGA Fabric
Speed Grade
Optional Suffix
Indicates specific device
options or shipment method
M : MX variant
1S : Stratix 10
21 : 2,100K logic elements
H : H-Tile
E : 3 x E-Tile + 1 H-Tile
N : 48
U : 96
F : FBGA
E : Extended (TJ = 0° C to 100° C)
1 (fastest)
2
3
Power Option
V : SmartVID standard power
RoHS
G : RoHS6 (1)
P: Leaded (2)
S<n> : Engineering sample
1S M 3
21 HU2F 53 ES1V
Logic Density
Family Variant
16 : 1,650K logic elements
C
HBM2Code
B :
C :
Note:
Stack Count Height Density
2
3
4-H
8-H
8 GB
16 GB
H-Tile Max Data Rate
E-Tile Max Data Rate
-1 -2
28.3 Gbps 26.0 Gbps 17.4 Gbps
57.8 Gbps PAM-4
30.0 Gbps NRZ
56.0 Gbps PAM-4
28.3 Gbps NRZ
32 Gbps PAM-4
17.4 Gbps NRZ
Package Body Size
53 : 2597 pins, 52.5x52.5 mm
55 : 2912 pins, 55x55 mm
G
-3
2. Leaded devices use eutectic solder balls, 63% Tin and 37% Lead. Contact Intel for availability.
1. Lead-free RoHS6 devices use SAC405 solder balls, 95.5% Tin, 4.0% Silver, and 0.5% Copper.
1.6. Heterogeneous 3D Stacked HBM2 DRAM Memory
Intel Stratix 10 MX devices integrate 3D stacked High-Bandwidth DRAM Memory
(HBM2) alongside a high-performance monolithic 14 nm FPGA fabric die, and multiple
high-speed transceiver tiles, all inside a single flip-chip FBGA package.
This results in a “near memory” implementation where the high-density stacked DRAM
is integrated very close to the FPGA in the same package. In this configuration the in-
package memory is able to deliver up to 512 GByte/s of total aggregate bandwidth
which represents over a 10X increase in bandwidth compared to traditional “far
memory” implemented in separate devices on the board. A near memory configuration
also reduces system power by reducing traces between the FPGA and memory, while
also reducing board area.
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Figure 7. Heterogeneous 3D Stacked HBM2 DRAM Architecture
128 128 128 128 128 128 128 128
128 bits Wide x 8 Channels
DRAM (HBM2)
EMIB
UIBeSRAM
Intel Stratix 10 MX devices integrate two 3D stacked HBM2 DRAM memories inside the
package. Each of these DRAM stacks has:
• 4 GB or 8 GB total density
• 256 GB per second total aggregate bandwidth
• 8 independent channels, each 128 bits wide, or 16 independent pseudo channels,
each 64 bits wide (in pseudo channel mode)
• Data transfer rates up to 2 Gbps, per signal, between core fabric and HBM2 DRAM
• Half-rate transfer to core fabric
Intel Stratix 10 MX devices use embedded hard memory controllers to access the
HBM2 DRAM.
1.7. Intel Hyperflex Core Architecture
Intel Stratix 10 MX devices are based on a monolithic core fabric featuring the new
Intel Hyperflex core architecture. The Intel Hyperflex core architecture delivers 2X the
clock frequency performance and up to 70% lower power compared to previous
generation high-end FPGAs. Along with this performance breakthrough, the Intel
Hyperflex core architecture delivers a number of advantages including:
•Higher Throughput—Capitalizes on 2X core clock frequency performance to
obtain throughput breakthroughs
•Improved Power Efficiency—Uses reduced IP size, enabled by Intel Hyperflex,
to consolidate designs which previously spanned multiple devices into a single
device, thereby reducing power by up to 70% versus previous generation devices
•Greater Design Functionality—Uses faster clock frequency to reduce bus widths
and reduce IP size, freeing up additional FPGA resources to add greater
functionality
•Increased Designer Productivity—Boosts performance with less routing
congestion and fewer design iterations using Hyper-Aware design tools, obtaining
greater timing margin for more rapid timing closure
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In addition to the traditional user registers found in the Adaptive Logic Modules (ALM),
the Intel Hyperflex core architecture introduces additional bypassable registers
everywhere throughout the fabric of the FPGA. These additional registers, called
Hyper-Registers are available on every interconnect routing segment and at the inputs
of all functional blocks.
Figure 8. Bypassable Hyper-Register
clk CRAM
Config
CRAM
Config
CRAM
Config
Interconnect
Interconnect
Stratix 10 HyperFlex
Routing Multiplexer
(with Hyper-Register)
Conventional
Routing Multiplexer
The Hyper-Registers enable the following key design techniques to achieve the 2X core
performance increases:
• Fine grain Hyper-Retiming to eliminate critical paths
• Zero latency Hyper-Pipelining to eliminate routing delays
• Flexible Hyper-Optimization for best-in-class performance
By implementing these techniques in your design, the Hyper-Aware design tools
automatically make use of the Hyper-Registers to achieve maximum core clock
frequency.
Figure 9. Intel Hyperflex Core Architecture
ALM ALM ALM
ALM ALM ALM
ALM ALM ALM
New Hyper-Registers throughout the core fabric
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1.8. Heterogeneous 3D SiP Transceiver Tiles
Intel Stratix 10 MX devices feature power efficient, high bandwidth, low latency
transceivers. The transceivers are implemented on heterogeneous 3D System-in-
Package (SiP) transceiver tiles, each containing 24 full-duplex transceiver channels. In
addition to providing a high-performance transceiver solution to meet current
connectivity needs, this allows for future flexibility and scalability as data rates,
modulation schemes, and protocol IPs evolve.
Figure 10. Monolithic Core Fabric, Heterogeneous 3D SiP Transceiver Tiles, Stacked
HBM2 DRAM Memory
Transceiver Tile
(24 Channels) (1)
Transceiver Tile
(24 Channels)
Package
Substrate
EMIBEMIB
EMIBEMIB
Core Fabric
eSRAM
eSRAM
EMIB
UIB
DRAM (HBM2)
UIB
EMIB
DRAM (HBM2)
Note:
1. Supports KP-FEC hard IP in addition to the RS-FEC already present.
Transceiver Tile
(24 Channels) (1)
Transceiver Tile
(24 Channels) (1)
Each transceiver tile contains:
• 24 full-duplex transceiver channels (PMA and PCS)
• Reference clock distribution network
• Transmit PLLs
• High-speed clocking and bonding networks
• PCI Express, 100G Ethernet MAC, 100G Reed-Solomon FEC, and KP-FEC hard IP
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Figure 11. Heterogeneous 3D SiP Transceiver Tile Architecture
Transceiver PLLs, RX, and TX CLocks
Transceivers (24 Channels)
100G Ethernet Hard IP
Transceiver Bonding
Transceiver Reference Clocks
Transceiver
Bank
(6 Channels)
Transceiver PLLs, RX, and TX CLocks
Transceiver
Bank
(6 Channels)
Transceiver
Bank
(6 Channels)
Transceiver
Bank
(6 Channels)
PCIe Gen3 x16 Hard IP
Transceiver Bonding
Transceiver Reference Clocks
Transceiver Tile
(24 Channels)
PCIe Gen3 Hard IP
100GbE Hard IP
EMIB
Transceiver Tile
(24 Channels)
100GbE Hard IP
EMIB
100 GbE Hard IP
Transceiver H-Tile Transceiver E-Tile
1.9. Intel Stratix 10 MX Transceivers
Intel Stratix 10 MX devices offer up to 96 total full-duplex transceiver channels. These
channels provide continuous data rates from 125 Mbps to 57.8 Gbps PAM4 / 28.9
Gbps NRZ for chip-to-chip, chip-to-module, and backplane applications. For longer-
reach backplane driving applications, advanced adaptive equalization circuits are used
to equalize over 30 dB of system loss.
All transceiver channels feature a dedicated Physical Medium Attachment (PMA) and a
hardened Physical Coding Sublayer (PCS).
• The PMA provides primary interfacing capabilities to physical channels.
• The PCS typically handles encoding/decoding, word alignment, and other pre-
processing functions before transferring data to the FPGA core fabric.
Within each transceiver tile, the transceivers are arranged in four banks of six PMA-
PCS groups. A wide variety of bonded and non-bonded data rate configurations are
possible within each bank, and within each tile, using a highly configurable clock
distribution network.
1.9.1. PMA Features
PMA channels are comprised of transmitter (TX), receiver (RX), and high speed
clocking resources.
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Intel Stratix 10 MX transmitter (TX) features provide exceptional signal integrity at
data rates up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ. Clocking options include ultra-low
jitter LC tank-based (ATX) PLLs with optional fractional synthesis capability, channel
PLLs operating as clock multiplier units (CMUs), and fractional synthesis PLLs (fPLLs).
•ATX PLL—can be configured in integer mode, or optionally, in a new fractional
synthesis mode. Each ATX PLL spans the full frequency range of the supported
data rate range providing a stable, flexible clock source with the lowest jitter.
•CMU PLL—when not being used as a transceiver, select PMA channels can be
configured as channel PLLs operating as CMUs to provide an additional master
clock source within the transceiver bank.
•fPLL—In addition, dedicated fPLLs are available with precision frequency synthesis
capabilities. fPLLs can be used to synthesize multiple clock frequencies from a
single reference clock source and replace multiple reference oscillators for multi-
protocol and multi-rate applications.
On the receiver side, each PMA has an independent channel PLL that allows analog
tracking for clock-data recovery. Each PMA also has advanced equalization circuits that
compensate for transmission losses across a wide frequency spectrum.
•Variable Gain Amplifier (VGA)—to optimize the receiver's dynamic range
•Continuous Time Linear Equalizer (CTLE)—to compensate for channel losses
with lowest power dissipation
•Decision Feedback Equalizer (DFE)—to provide additional equalization
capability on backplanes even in the presence of crosstalk and reflections
•On-Die Instrumentation (ODI)—to provide on-chip eye monitoring capabilities
(Eye Viewer). This capability helps to optimize link equalization parameters during
board bring-up and supports in-system link diagnostics and equalization margin
testing
Figure 12. Intel Stratix 10 MX Receiver Block Features
∑
VGA CDR
DFE Eye Viewer
CTLE
Adaptive Parametric Tuning Engine
Deserializer
All link equalization parameters feature automatic adaptation using the new Advanced
Digital Adaptive Parametric Tuning (ADAPT) circuit. This circuit is used to dynamically
set DFE tap weights, adjust CTLE parameters, and optimize VGA gain and threshold
voltage. Finally, optimal and consistent signal integrity is ensured by using the new
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hardened Precision Signal Integrity Calibration Engine (PreSICE) to automatically
calibrate all transceiver circuit blocks on power-up. This gives the most link margin
and ensures robust, reliable, and error-free operation.
Table 6. Transceiver PMA Features
Feature Capability
Chip-to-Chip Data Rates 1 Gbps (7) to 57.8 Gbps PAM4 / 28.9 Gbps NRZ
Backplane Support Drive backplanes at data rates up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ, including
10GBASE-KR compliance
Optical Module Support SFP+/SFP, XFP, CXP, QSFP/QSFP28, QSFPDD, CFP/CFP2/CFP4
Cable Driving Support SFP+ Direct Attach, PCI Express over cable, eSATA
Transmit Pre-Emphasis 5-tap transmit pre-emphasis and de-emphasis to compensate for system channel loss
Continuous Time Linear
Equalizer (CTLE)
Dual mode, high-gain, and high-data rate, linear receive equalization to compensate for
system channel loss
Decision Feedback Equalizer
(DFE)
15 fixed tap DFE to equalize backplane channel loss in the presence of crosstalk and noisy
environments
Advanced Digital Adaptive
Parametric Tuning (ADAPT)
Fully digital adaptation engine to automatically adjust all link equalization parameters—
including CTLE, DFE, and VGA blocks—that provide optimal link margin without intervention
from user logic
Precision Signal Integrity
Calibration Engine (PreSICE)
Hardened calibration controller to quickly calibrate all transceiver control parameters on
power-up, which provides the optimal signal integrity and jitter performance
ATX Transmit PLLs Low jitter ATX (inductor-capacitor) transmit PLLs with continuous tuning range to cover a
wide range of standard and proprietary protocols, with optional fractional frequency
synthesis capability
Fractional PLLs On-chip fractional frequency synthesizers to replace on-board crystal oscillators and reduce
system cost
Digitally Assisted Analog
CDR
Superior jitter tolerance with fast lock time
On-Die Instrumentation—
Eye Viewer and Jitter Margin
Tool
Simplify board bring-up, debug, and diagnostics with non-intrusive, high-resolution eye
monitoring (Eye Viewer). Also inject jitter from transmitter to test link margin in system.
Dynamic Reconfiguration Allows for independent control of each transceiver channel Avalon memory-mapped
interface for the most transceiver flexibility.
Multiple PCS-PMA and PCS-
Core to FPGA fabric interface
widths
8, 10, 16, 20, 32, 40, or 64 bit interface widths for flexibility of deserialization width,
encoding, and reduced latency
1.9.2. PCS Features
Intel Stratix 10 MX PMA channels interface with core logic through configurable and
bypassable PCS interface layers.
The PCS contains multiple gearbox implementations to decouple the PMA and PCS
interface widths. This feature provides the flexibility to implement a wide range of
applications with 8, 10, 16, 20, 32, 40, or 64 bit interface width between each
transceiver and the core logic.
(7) Stratix 10 transceivers can support data rates below 1 Gbps with over sampling.
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The PCS also contains hard IP to support a variety of standard and proprietary
protocols across a wide range of data rates and encoding schemes. The Standard PCS
mode provides support for 8B/10B encoded applications up to 12.5 Gbps. The
Enhanced PCS mode supports 64B/66B and 64B/67B encoded applications up to 17.4
Gbps. The enhanced PCS mode also includes an integrated 10GBASE-KR/40GBASE-
KR4 Forward Error Correction (FEC) circuit. For highly customized implementations, a
PCS Direct mode provides an interface up to 64 bits wide to allow for custom encoding
and support for data rates up to 28.9 Gbps.
For more information about the PCS-Core interface or the double rate transfer mode,
refer to the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide, and the Intel
Stratix 10 E-Tile Transceiver PHY User Guide.
Table 7. Transceiver PCS Features
PCS Protocol
Support
Data Rate (Gbps) Transmitter Data Path Receiver Data Path
Standard PCS 1 to 12.5 Phase compensation FIFO, byte
serializer, 8B/10B encoder, bit-slipper,
channel bonding
Rate match FIFO, word-aligner, 8B/10B
decoder, byte deserializer, byte
ordering
PCI Express
Gen1/Gen2 x1,
x2, x4, x8, x16
2.5 and 5.0 Same as Standard PCS plus PIPE 2.0
interface to core
Same as Standard PCS plus PIPE 2.0
interface to core
PCI Express Gen3
x1, x2, x4, x8,
x16
8.0 Phase compensation FIFO, byte
serializer, encoder, scrambler, bit-
slipper, gear box, channel bonding, and
PIPE 3.0 interface to core, auto speed
negotiation
Rate match FIFO (0-600 ppm mode),
word-aligner, decoder, descrambler,
phase compensation FIFO, block sync,
byte deserializer, byte ordering, PIPE
3.0 interface to core, auto speed
negotiation
CPRI 0.6144 to 9.8 Same as Standard PCS plus
deterministic latency serialization
Same as Standard PCS plus
deterministic latency deserialization
Enhanced PCS 2.5 to 17.4 FIFO, channel bonding, bit-slipper, and
gear box
FIFO, block sync, bit-slipper, and gear
box
10GBASE-R 10.3125 FIFO, 64B/66B encoder, scrambler,
FEC, and gear box
FIFO, 64B/66B decoder, descrambler,
block sync, FEC, and gear box
Interlaken 4.9 to 17.4 FIFO, channel bonding, frame
generator, CRC-32 generator,
scrambler, disparity generator, bit-
slipper, and gear box
FIFO, CRC-32 checker, frame sync,
descrambler, disparity checker, block
sync, and gear box
SFI-S/SFI-5.2 11.3 FIFO, channel bonding, bit-slipper, and
gear box
FIFO, bit-slipper, and gear box
IEEE 1588 1.25 to 10.3125 FIFO (fixed latency), 64B/66B encoder,
scrambler, and gear box
FIFO (fixed latency), 64B/66B decoder,
descrambler, block sync, and gear box
SDI up to 12.5 FIFO and gear box FIFO, bit-slipper, and gear box
GigE 1.25 Same as Standard PCS plus GigE state
machine
Same as Standard PCS plus GigE state
machine
PCS Direct up to 28.9 Custom Custom
Related Information
Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide
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1.10. PCI Express Gen1/Gen2/Gen3 Hard IP
Intel Stratix 10 MX devices contain embedded PCI Express hard IP designed for
performance, ease-of-use, increased functionality, and designer productivity.
The PCI Express hard IP consists of the PHY, Data Link, and Transaction layers. It also
supports PCI Express Gen1/Gen2/Gen3 end point and root port, in x1/x2/x4/x8/x16
lane configurations. The PCI Express hard IP is capable of operating independently
from the core logic (autonomous mode). This feature allows the PCI Express link to
power up and complete link training in less than 100 ms, while the rest of the device
is still in the process of being configured. The hard IP also provides added
functionality, which makes it easier to support emerging features such as Single Root
I/O Virtualization (SR-IOV) and optional protocol extensions.
The PCI Express hard IP has improved end-to-end data path protection using Error
Checking and Correction (ECC). In addition, the hard IP supports configuration of the
device via protocol (CvP) across the PCI Express bus at Gen1/Gen2/Gen3 rates.
1.11. 100G Ethernet MAC, Reed-Solomon FEC Hard IP, and KP-FEC
Hard IP
Intel Stratix 10 MX devices contain multiple instances of 100G Ethernet MAC hard IP,
100G Reed-Solomon FEC hard IP, and KP-FEC hard IP simplifying the design of
complex multi-port Ethernet systems.
1.12. 10G Ethernet Hard IP
Intel Stratix 10 MX devices include IEEE 802.3 10-Gbps Ethernet (10GbE) compliant
10GBASE-R PCS and PMA hard IP. The scalable 10GbE hard IP supports multiple
independent 10GbE ports while using a single PLL for all the 10GBASE-R PCS
instantiations, which saves on core logic resources and clock networks.
The integrated serial transceivers simplify multi-port 10GbE systems compared to 10
GbE Attachment Unit Interface (XAUI) interfaces that require an external XAUI-to-10G
PHY. Furthermore, the integrated transceivers incorporate signal conditioning circuits,
which enable direct connection to standard 10G XFP and SFP+ pluggable optical
modules. The transceivers also support backplane Ethernet applications and include a
hard 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) circuit that can be
used for both 10G and 40G applications. The integrated 10G Ethernet hard IP and 10G
transceivers save external PHY cost, board space and system power. The 10G Ethernet
PCS hard IP and 10GBASE-KR FEC are present in every transceiver channel.
1.13. Interlaken PCS Hard IP
Intel Stratix 10 MX devices have integrated Interlaken PCS hard IP supporting rates up
to 17.4 Gbps per lane.
The Interlaken PCS hard IP is based on the proven functionality of the PCS developed
for Intel’s previous generation FPGAs, which has demonstrated interoperability with
Interlaken ASSP vendors and third-party IP suppliers. The Interlaken PCS hard IP is
present in every transceiver channel in Intel Stratix 10 MX devices.
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1.14. External Memory and General Purpose I/O
In addition to the bandwidth delivered by the in-package HBM2 DRAM near memory,
Intel Stratix 10 MX devices offer substantial external memory bandwidth, supporting
DDR4 memory interfaces running at up to 2666 Mbps.
This bandwidth is provided along with the ease of design, lower power, and resource
efficiencies of hardened high-performance memory controllers. The external memory
interfaces can be configured up to a maximum width of 144 bits when using either
hard or soft memory controllers.
Figure 13. Hard Memory Controller
AXI/Avalon IF
Memory Controller
PHY Interface
Hard PHY
Hard Nios II
(Callibration/Control)
I/O Interface
ECCDQ/DQSCMD/ADDR
User Design
Core Fabric
Stratix 10 FPGA
Hard
Memory
Controller
Each I/O bank contains 48 general purpose I/Os and a high-efficiency hard memory
controller capable of supporting many different memory types, each with different
performance capabilities. The hard memory controller is also capable of being
bypassed and replaced by a soft controller implemented in the user logic. The I/Os
each have a hardened double data rate (DDR) read/write path (PHY) capable of
performing key memory interface functionality such as:
• Read/write leveling
• FIFO buffering to lower latency and improve margin
• Timing calibration
• On-chip termination
The timing calibration is aided by the inclusion of hard microcontrollers based on
Intel’s Nios® II technology, specifically tailored to control the calibration of multiple
memory interfaces. This calibration allows the Intel Stratix 10 MX device to
compensate for any changes in process, voltage, or temperature either within the
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device itself, or within the external memory device. The advanced calibration
algorithms ensure maximum bandwidth and robust timing margin across all operating
conditions.
Table 8. External Memory Interface Performance
The listed speeds are for the 1-rank case.
Interface Controller Type Performance
DDR4 Hard 2666 Mbps
DDR3 Hard 2133 Mbps
QDRII+ Soft 1,100 Mtps
QDRII+ Xtreme Soft 1,266 Mtps
QDRIV Soft 2,133 Mtps
RLDRAM III Soft 2400 Mbps
RLDRAM II Soft 533 Mbps
In addition to parallel memory interfaces, Intel Stratix 10 MX devices support serial
memory technologies such as the Hybrid Memory Cube (HMC). The HMC is supported
by the high-speed serial transceivers, which connect up to four HMC links, with each
link running at data rates of 15 Gbps (HMC short reach specification).
Intel Stratix 10 MX devices also feature general purpose I/Os capable of supporting a
wide range of single-ended and differential I/O interfaces. LVDS rates up to 1.6 Gbps
are supported, with each pair of pins having both a differential driver and a differential
input buffer. This enables configurable direction for each LVDS pair.
1.15. Adaptive Logic Module (ALM)
Intel Stratix 10 MX devices use a similar adaptive logic module (ALM) as the previous
generation Intel Arria® 10 and Stratix V FPGAs, allowing for efficient implementation
of logic functions and easy conversion of IP between the devices.
The ALM block diagram shown in the following figure has eight inputs with a
fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated
registers.
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Figure 14. ALM Block Diagram
Reg
Reg
1
2
3
4
5
6
7
8
Reg
Reg
4 Registers per ALM
Full
Adder
Full
Adder
Adaptive
LUT
Key features and capabilities of the ALM include:
• High register count with 4 registers per 8-input fracturable LUT, operating in
conjunction with the new Intel Hyperflex architecture, enables Intel Stratix 10 MX
devices to maximize core performance at very high core logic utilization
• Implements select 7-input logic functions, all 6-input logic functions, and two
independent functions consisting of smaller LUT sizes (such as two independent 4-
input LUTs) to optimize core logic utilization
The Intel Quartus Prime software takes advantage of the ALM logic structure to deliver
the highest performance, optimal logic utilization, and lowest compile times. The Intel
Quartus Prime software simplifies design reuse as it automatically maps legacy
designs into the Intel Stratix 10 MX ALM architecture.
1.16. Core Clocking
Core clocking in Intel Stratix 10 MX devices makes use of programmable clock tree
synthesis.
This technique uses dedicated clock tree routing and switching circuits, and allows the
Intel Quartus Prime software to create the exact clock trees required for your design.
Clock tree synthesis minimizes clock tree insertion delay, reduces dynamic power
dissipation in the clock tree and allows greater clocking flexibility in the core while still
maintaining backwards compatibility with legacy global and regional clocking schemes.
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The core clock network in Intel Stratix 10 MX devices supports the new Intel Hyperflex
core architecture at clock rates up to 1 GHz. It also supports the hard memory
controllers up to 2666 Mbps with a quarter rate transfer to the core. The core clock
network is supported by dedicated clock input pins, fractional clock synthesis PLLs,
and integer I/O PLLs.
1.17. Fractional Synthesis PLLs and I/O PLLs
Intel Stratix 10 MX devices have up to 32 fractional synthesis PLLs (fPLL) available for
use with transceivers or in the core fabric.
The fPLLs are located in the 3D SiP transceiver L-tiles and H-tiles, eight per tile,
adjacent to the transceiver channels. The fPLLs can be used to reduce both the
number of oscillators required on the board and the number of clock pins required, by
synthesizing multiple clock frequencies from a single reference clock source. In
addition to synthesizing reference clock frequencies for the transceiver transmit PLLs,
the fPLLs can also be used directly for transmit clocking. Each fPLL can be
independently configured for conventional integer mode, or enhanced fractional
synthesis mode with third-order delta-sigma modulation.
In addition to the fPLLs, Intel Stratix 10 MX devices contain 16 integer I/O PLLs
(IOPLLs) available for general purpose use in the core fabric and for simplifying the
design of external memory interfaces and high-speed LVDS interfaces. The IOPLLs are
located in each bank of 48 general purpose I/O, one per I/O bank, adjacent to the
hard memory controllers and LVDS SerDes in each I/O bank. This makes it easier to
close timing because the IOPLLs are tightly coupled with the I/Os that need to use
them. The IOPLLs can be used for general purpose applications in the core such as
clock network delay compensation and zero-delay clock buffering.
1.18. Internal Embedded Memory
Intel Stratix 10 MX devices contain three types of embedded memory blocks: eSRAM
(47.25 Mbit), M20K (20 Kb), and MLAB (640 bit). This variety of on-chip memory
provides fast access times and low latency for applications such as wide and deep
FIFOs and variable buffers. Combined with the in-package memory provided by the
HBM2 DRAM stacks, the internal embedded memory completes the memory hierarchy
in Intel Stratix 10 MX devices.
The eSRAM blocks are a new innovation in Intel Stratix 10 devices. These large
embedded SRAM blocks are tightly coupled to the core fabric and are directly
accessible with no need for a separate memory controller. Each eSRAM block is
arranged as 8 channels, 42 banks per channel, with a total capacity of 47.25 Mbits
running at clock rates up to 750 MHz. Within the eSRAM block, each channel has a bus
width of 72 bit read and 72 bit write, and has one READ and one WRITE per channel.
This allows each eSRAM block to support a total aggregate bandwidth (read + write)
of up to 864 Gbps.
The eSRAM block is implemented as a simple dual port memory with concurrent read
and write access per channel, and includes integrated hard ECC generation and
checking. Compared to an off-chip SRAM solution, the eSRAM block allows you to
reduce system power and save board space and cost.
The M20K and MLAB blocks are familiar block sizes carried over from previous Intel
device families. The MLAB blocks are ideal for wide and shallow memories, while the
M20K blocks are intended to support larger memory configurations and include hard
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ECC. Both M20K and MLAB embedded memory blocks can be configured as a single-
port or dual-port RAM, FIFO, ROM, or shift register. These memory blocks are highly
flexible and support a number of memory configurations as shown in Table 9 on page
26.
Table 9. Internal Embedded Memory Block Configurations
MLAB (640 bits) M20K (20 Kb)
64 x 10 (supported through emulation)
32 x 20
2K x 10 (or x8)
1K x 20 (or x16)
512 x 40 (or x32)
1.19. Variable Precision DSP Block
The Intel Stratix 10 MX DSP blocks are based upon the Variable Precision DSP
Architecture used in Intel’s previous generation devices. They feature hard fixed point
and IEEE 754 compliant floating point capability.
The DSP blocks can be configured to support signal processing with precision ranging
from 18x19 up to 54x54. A pipeline register has been added to increase the maximum
operating frequency of the DSP block and reduce power consumption.
Figure 15. DSP Block: Standard Precision Fixed Point Mode
Multiplier
18 x 19
4418
Input Registers
+/–
+/–
Coefficient
Registers
Coefficient
Registers
Pipeline
Register
Pipeline
Register
Pipeline
Register
Pipeline
Register
Multiplier
18 x 19
+
–
Systolic
Register
Systolic
Register
Multiplexer and Pipeline Register
Feedback
Register
Output
Register
44
64
74
18
108
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Figure 16. DSP Block: High Precision Fixed Point Mode
64
Input Registers
+/–
Coefficient
Registers
Pipeline
Register
Pipeline
Register
Multiplier
27 x 27
Pipeline Register
Feedback
Register
Output
Register
64
64
74
108
Pre-Adder
Figure 17. DSP Block: Single Precision Floating Point Mode
32
Input Registers
Pipeline
Register
Pipeline
Register IEEE-754
Single-Precision
Floating-Point
Multiplier
Output
Register
32
32
96
Pipeline
Register
Pipeline
Register
Pipeline
Register
Pipeline
Register
IEEE-754 Single-Precision
Floating-Point Adder
Each DSP block can be independently configured at compile time as either dual 18x19
or a single 27x27 multiply accumulate. With a dedicated 64 bit cascade bus, multiple
variable precision DSP blocks can be cascaded to implement even higher precision
DSP functions efficiently.
In floating point mode, each DSP block provides one single precision floating point
multiplier and adder. Floating point additions, multiplications, mult-adds and mult-
accumulates are supported.
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The following table shows how different precisions are accommodated within a DSP
block, or by utilizing multiple blocks.
Table 10. Variable Precision DSP Block Configurations
Multiplier Size DSP Block Resources Expected Usage
18x19 bits 1/2 of Variable Precision DSP Block Medium precision fixed point
27x27 bits 1 Variable Precision DSP Block High precision fixed point
19x36 bits 1 Variable Precision DSP Block with external
adder
Fixed point FFTs
36x36 bits 2 Variable Precision DSP Blocks with external
adder
Very high precision fixed point
54x54 bits 4 Variable Precision DSP Blocks with external
adder
Double Precision floating point
Single Precision
floating point
1 Single Precision floating point adder, 1 Single
Precision floating point multiplier
Floating point
Complex multiplication is very common in DSP algorithms. One of the most popular
applications of complex multipliers is the FFT algorithm. This algorithm has the
characteristic of increasing precision requirements on only one side of the multiplier.
The Variable Precision DSP block supports the FFT algorithm with proportional increase
in DSP resources as the precision grows.
Table 11. Complex Multiplication With Variable Precision DSP Block
Complex Multiplier
Size
DSP Block Resources FFT Usage
18x19 bits 2 Variable Precision DSP Blocks Resource optimized FFT
27x27 bits 4 Variable Precision DSP Blocks Highest precision FFT
For FFT applications with high dynamic range requirements, the Intel FFT IP Core
offers an option of single precision floating point implementation with resource usage
and performance similar to high precision fixed point implementations.
Other features of the DSP block include:
• Hard 18 bit and 25 bit pre-adders
• Hard floating point multipliers and adders
• 64 bit dual accumulator (for separate I, Q product accumulations)
• Cascaded output adder chains for 18 and 27 bit FIR filters
• Embedded coefficient registers for 18 and 27 bit coefficients
• Fully independent multiplier outputs
• Inferability using HDL templates supplied by the Intel Quartus Prime software for
most modes
The Variable Precision DSP block is ideal to support the growing trend towards higher
bit precision in high performance DSP applications. At the same time, it can efficiently
support the many existing 18 bit DSP applications, such as high definition video
processing and remote radio heads. With the Variable Precision DSP block architecture
and hard floating point multipliers and adders, Intel Stratix 10 MX devices can
efficiently support many different precision levels up to and including floating point
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implementations. This flexibility can result in increased system performance, reduced
power consumption, and reduce architecture constraints on system algorithm
designers.
1.20. Power Management
Intel Stratix 10 MX devices leverage the advanced Intel 14 nm tri-gate process
technology, the all new Intel Hyperflex core architecture to enable Hyper-Folding,
power gating, and optional power reduction techniques to reduce total power
consumption by as much as 70% compared to previous generation high-performance
Stratix V devices.
Intel Stratix 10 standard power devices (-V) are SmartVID devices. The core voltage
supplies (VCC and VCCP) for each SmartVID device must be driven by a PMBus
voltage regulator dedicated to that Intel Stratix 10 device. Use of a PMBus voltage
regulator for each SmartVID (-V) device is mandatory; it is not an option. A code is
programmed into each SmartVID device during manufacturing that allows the PMBus
voltage regulator to operate at the optimum core voltage to meet the device
performance specifications.
With the new Intel Hyperflex core architecture, designs can run 2X faster than
previous generation FPGAs. With 2X performance and same required throughput,
architects can cut the data path width in half to save power. This optimization is called
Hyper-Folding. Additionally, power gating reduces static power of unused resources in
the FPGA by powering them down. The Intel Quartus Prime software automatically
powers down specific unused resource blocks such as DSP and M20K blocks, at
configuration time.
Furthermore, Intel Stratix 10 MX devices feature Intel’s low power transceivers and
include a number of hard IP blocks that not only reduce logic resources but also
deliver substantial power savings compared to soft implementations. In general, hard
IP blocks consume up to 50% less power than the equivalent soft logic
implementations.
1.21. Device Configuration and Secure Device Manager (SDM)
All Intel Stratix 10 MX devices contain a Secure Device Manager (SDM), which is a
dedicated triple-redundant processor that serves as the point of entry into the device
for all JTAG and configuration commands. The SDM also bootstraps the HPS in SoC
devices ensuring that the HPS can boot using the same security features that the
FPGA devices have.
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Figure 18. SDM Block Diagram
Secure Device Manager
(SDM)
Dedicated Config I/O
FPGA
Sector
LSM
FPGA
Sector
LSM
FPGA
Sector
LSM
FPGA
Sector
LSM
Dual Purpose I/O
Configuration
Network
Customizable secure boot process
Private, public, and PUF-based
key support
Security Features
Interface bus used to transport
configuration data from SDM
throughout FPGA
Sectors can be selectively
configured and cleared of
sensitive parameters
Sectors configured in parallel
to reduce configuration time
LSM: Local Sector Manager
PUF: Physically Unclonable Function
During configuration, Intel Stratix 10 MX devices are divided into logical sectors, each
of which is managed by a local sector manager (LSM). The SDM passes configuration
data to each of the LSMs across the on-chip configuration network. This allows the
sectors to be configured independently, one at a time, or in parallel. This approach
achieves simplified sector configuration and reconfiguration, as well as reduced overall
configuration time due to the inherent parallelism. The same sector-based approach is
used to respond to single-event upsets and security attacks.
While the sectors provide a logical separation for device configuration and
reconfiguration, they overlay the normal rows and columns of FPGA logic and routing.
This means there is no impact to the Intel Quartus Prime software place and route,
and no impact to the timing of logic signals that cross the sector boundaries.
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The SDM enables robust, secure, fully-authenticated device configuration. It also
allows for customization of the configuration scheme, which can enhance device
security. For configuration and reconfiguration, this approach offers a variety of
advantages:
• Dedicated secure configuration manager
• Reduced device configuration time, because sectors are configured in parallel
• Updateable configuration process
• Reconfiguration of one or more sectors independent of all other sectors
• Zeroization of individual sectors or the complete device
The SDM also provides additional capabilities such as register state readback and
writeback to support ASIC prototyping and other applications.
1.22. Device Security
Building on top of the robust security features present in the previous generation
devices, Intel Stratix 10 MX devices include a number of new and innovative security
enhancements. These features are also managed by the SDM, tightly coupling device
configuration and reconfiguration with encryption, authentication, key storage and
anti-tamper services.
Security services provided by the SDM include:
• Bitstream encryption
• Multi-factor authentication
• Hard encryption and authentication acceleration; AES-256, SHA-256/384,
ECDSA-256/384
• Volatile and non-volatile encryption key storage and management
• Physically Unclonable Function (PUF) service
• Updateable configuration process
• Secure device maintenance and upgrade functions
• Side channel attack protection
• Scripted response to sensor inputs and security attacks, including selective sector
zeroization
• Readback, JTAG and test mode disable
• Enhanced response to single-event upsets (SEU)
The SDM and associated security services provide a robust, multi-layered security
solution for your Intel Stratix 10 MX design.
1.23. Configuration via Protocol Using PCI Express
Configuration via protocol using PCI Express allows the FPGA to be configured across
the PCI Express bus, simplifying the board layout and increasing system integration.
Making use of the embedded PCI Express hard IP operating in autonomous mode
before the FPGA is configured, this technique allows the PCI Express bus to be
powered up and active within the 100 ms time allowed by the PCI Express
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specification. Intel Stratix 10 MX devices also support partial reconfiguration across
the PCI Express bus which reduces system down time by keeping the PCI Express link
active while the device is being reconfigured.
1.24. Partial and Dynamic Reconfiguration
Partial reconfiguration allows you to reconfigure part of the FPGA while other sections
continue running. This capability is required in systems where uptime is critical,
because it allows you to make updates or adjust functionality without disrupting
services.
In addition to lowering power and cost, partial reconfiguration also increases the
effective logic density by removing the necessity to place in the FPGA those functions
that do not operate simultaneously. Instead, these functions can be stored in external
memory and loaded as needed. This reduces the size of the required FPGA by allowing
multiple applications on a single FPGA, saving board space and reducing power. The
partial reconfiguration process is built on top of the proven incremental compile design
flow in the Intel Quartus Prime design software
Dynamic reconfiguration in Intel Stratix 10 MX devices allows transceiver data rates,
protocols and analog settings to be changed dynamically on a channel-by-channel
basis while maintaining data transfer on adjacent transceiver channels. Dynamic
reconfiguration is ideal for applications that require on-the-fly multiprotocol or multi-
rate support. Both the PMA and PCS blocks within the transceiver can be reconfigured
using this technique. Dynamic reconfiguration of the transceivers can be used in
conjunction with partial reconfiguration of the FPGA to enable partial reconfiguration of
both core and transceivers simultaneously.
1.25. Fast Forward Compile
The innovative Fast Forward Compile feature in the Intel Quartus Prime software
identifies performance bottlenecks in your design and provides detailed, step-by-step
performance improvement recommendations that you can then implement. The
Compiler reports estimates of the maximum operating frequency that can be achieved
by applying the recommendations. As part of the new Hyper-Aware design flow, Fast
Forward Compile maximizes the performance of your Intel Stratix 10 MX design and
achieves rapid timing closure.
Previously, this type of optimization required multiple time-consuming design
iterations, including full design re-compilation to determine the effectiveness of the
changes. Fast Forward Compile enables you to make better decisions about where to
focus your optimization efforts, and how to increase your design performance and
throughput. This technique removes much of the guesswork of performance
exploration, resulting in fewer design iterations and as much as 2X core performance
gains for Intel Stratix 10 MX designs.
1.26. Single Event Upset (SEU) Error Detection and Correction
Intel Stratix 10 MX devices offer robust SEU error detection and correction circuitry.
The detection and correction circuitry includes protection for Configuration RAM
(CRAM) programming bits and user memories. The CRAM is protected by a
continuously running parity checker circuit with integrated ECC that automatically
corrects one or two bit errors and detects higher order multibit errors.
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The physical layout of the CRAM array is optimized to make the majority of multi-bit
upsets appear as independent single-bit or double-bit errors which are automatically
corrected by the integrated CRAM ECC circuitry. In addition to the CRAM protection,
the user memories also include integrated ECC circuitry and are layout optimized for
error detection and correction.
The SEU error detection and correction hardware is supported by both soft IP and the
Intel Quartus Prime software to provide a complete SEU mitigation solution. The
components of the complete solution include:
• Hard error detection and correction for CRAM and user eSRAM and M20K memory
blocks
• Optimized physical layout of memory cells to minimize probability of SEU
• Sensitivity processing soft IP that reports if CRAM upset affects a used or unused
bit
• Fault injection soft IP with the Intel Quartus Prime software support that changes
state of CRAM bits for testing purposes
• Hierarchy tagging in the Intel Quartus Prime software
• Triple Mode Redundancy (TMR) used for the Secure Device Manager and critical
on-chip state machines
In addition to the SEU mitigation features listed above, the Intel 14 nm tri-gate
process technology used for Intel Stratix 10 MX devices is based on FinFET transistors
which have reduced SEU susceptibility versus conventional planar transistors.
1.27. Revision History for the Intel Stratix 10 MX (DRAM System-in-
Package) Device Overview
Document
Version
Changes
2019.08.19 Made the following change:
• Added composition details for the leaded and lead-free contact device options.
2019.03.13 Made the following changes:
• Updated maximum transceiver data rates from 30 Gbps NRZ to 28.9 Gbps NRZ.
• Updated data in the "Intel Stratix 10 MX Family Plan—Interconnects, PLLs, Hard IP, and HBM2 (part
2)" table.
2019.02.15 Made the following changes:
• Changed the number of eSRAM memory block to 47.25 Mbit and the number of embedded memory
to 94.5 Mbits.
• Changed the number of maximum transceiver data rate to 57.8 Gbps.
• Removed the descriptions of the Hard Processor System (HPS) block.
• Removed the MX 1100 density device from family and package plans.
2018.08.09 Made the following changes:
• Changed the direction arrow from the coefficient registers block in the "DSP Block: High Precision
Fixed Point Mode" figure.
• Changed the descriptions for the core process technology and power management features in the
"Intel Stratix 10 MX Device Features" table.
• Changed the power option description in the "Sample Ordering Code and Available Options for Intel
Stratix 10 MX Devices" figure.
• Changed the description of the SmartVID in the "Power Management" section.
2018.04.18 Made the following change:
continued...
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Document
Version
Changes
• Changed the description of the logic densities in the "Sample Ordering Code and Available Options
for Intel Stratix 10 MX Devices" figure.
2018.03.05 Made the following change:
• Changed the number of eSRAM banks per channel to 42 in the "Internal Embedded Memory"
section.
2018.02.27 Made the following change:
• Corrected the package body size for the F2597 package in the "Intel Stratix 10 MX Package Plan"
table.
2017.10.30 Made the following changes:
• Changed the description for the Embedded Memory (M20K) feature in the "Key Features of Intel
Stratix 10 MX Devices Compared to Stratix V Devices" table.
• Changed the number of 18x19 multipliers in the "Key Features of Intel Stratix 10 MX Devices
Compared to Stratix V Devices" table.
• Changed the total number of General purpose I/Os available in the "Intel Stratix 10 MX Device
Features" table.
• Changed the resource availabilities for the MX 1650 and MX2100 devices in the "Intel Stratix 10 MX
Family Plan—FPGA Core (part 1)" table.
• Changed the maximum GPIOs and Maximum XCVR availabilities for the MX 1650 and MX 2100
devices in the "Intel Stratix 10 MX Family Plan—Interconnects, PLLs, Hard IP, and HBM2 (part 2)"
table.
• Changed the resource counts for the F2597 package in the "Intel Stratix 10 MX Package Plan" table.
2017.07.17 Initial release.
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