Supertex inc.
Supertex inc.
www.supertex.com
HV2701
Doc.# DSFP-HV2701
E012412
Features
►HVCMOS technology for high performance
►Integrated bleed resistors on the outputs
►16-channel high voltage analog switch
►3.3V input logic level compatible
►20MHz data shift clock frequency
►Very low quiescent power dissipation (-10µA)
►Low parasitic capacitance
►DC to 50MHz small signal frequency response
►-60dB typical OFF-isolation at 5.0MHz
►CMOS logic circuitry for low power
►Excellent noise immunity
►Cascadable serial data register with latches
►Flexible operating supply voltages
Applications
►Medical ultrasound imaging
►NDT metal aw detection
►Piezoelectric transducer drivers
►Optical MEMS modules
General Description
The Supertex HV2701 is a low charge injection, 16-channel, high
voltage, analog switch integrated circuit (IC) with bleed resistors.
The device can be used in applications requiring high voltage
switching controlled by low voltage control signals, such as medical
ultrasound imaging and piezoelectric transducer drivers. The bleed
resistors eliminate voltage built up on capacitive loads such as
piezoelectric transducers.
Input data are shifted into a 16-bit shift register that can then be
retained in a 16-bit latch. To reduce any possible clock feed-through
noise, the latch enable bar should be left high until all bits are
clocked in. Data is clocked in during the rising edge of the clock.
Using HVCMOS technology, this device combines high voltage
bilateral DMOS switches and low power CMOS logic to provide
efcient control of high voltage analog signals.
The device is suitable for various combinations of high voltage
supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V.
Block Diagram
Low Charge Injection 16-Channel
High Voltage Analog Switch with Bleed Resistors
D
LE
CLR
Latches
Level
Shifters
Output
Switches
SW0
SW1
SW2
SW14
SW15
16-Bit
Shift
Register
RGND
VPP
VNN
CLR
LE
VDD GND
D
LE
CLR
D
LE
CLR
D
LE
CLR
D
LE
CLR
DOUT
CLK
DIN
2
HV2701
Supertex inc.
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Doc.# DSFP-HV2701
E012412
Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device at
the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Parameter Value
VDD logic supply -0.5V to +7.0V
VPP-VNN differential supply 220V
VPP positive supply -0.5V to VNN+200V
VNN negative supply +0.5V to -200V
Logic input voltage -0.5V to VDD +0.3V
Analog signal range VNN to VPP
Peak analog signal current/channel 3.0A
Storage temperature -65°C to 150°C
Power dissipation:
42-Ball Bumped Die (BD)
48-Lead LQFP (FG)
48-Ball fpBGA (GA)
1.5W
1.0W
1.0W
Sym Parameter Value
VDD Logic power supply voltage 3.0V to 5.5V
VPP Positive high voltage supply +40V to VNN +200V
VNN Negative high voltage supply -40V to -160V
VIH High level input voltage 0.9VDD to VDD
VIL Low level input voltage 0V to 0.1VDD
VSIG
Analog signal voltage
peak-to-peak VNN+10V to VPP-10V
TAOperating free air temperature 0°C to 70°C
Recommended Operating Conditions
Notes:
1. Power up/down sequence is arbitrary except GND must be powered-up rst
and powered-down last.
2. VSIG must be within VNN and VPP or oating during power up/down transition.
3. Rise and fall times of power supplies VDD, VPP
, and VNN should not be less than
1.0msec.
Product Marking
Pin Congurations
48-Lead LQFP (FG)
(top view)
1
48
42-Ball Bumped Die (BD)
(top view)
1
2
3
8
9
10 12
13
4
5
6
7
11
18 17 16 15 14
25
26
21
22
23
24
19
20
41
42
33
34
39
40
31
32
37
38
29
30
35
36
27
28
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW
HV2701FG
LLLLLLLLL
CCCCCCCC
AAA
48-Lead LQFP (FG)
42-Ball Bumped Die (BD)
YY = Year Sealed
WW = Week Sealed
L = Lot Number
LLLLLLL
YYWW
HV2701BD
Package may or may not include the following marks: Si or
Package may or may not include the following marks: Si or
A
B
C
D
E
F
G
H
1 2 3 4 5 6
48-Ball fpBGA (GA)
(top view)
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YYWW
HV2701GA
LLLLLLLLL
48-Ball fpBGA (GA)
Packages may or may not include the following marks: Si or
-G indicates package is RoHS compliant (‘Green’).
Bumped Die package is RoHS compliant (‘Green’).
M936 species product in tape and reel.
Ordering Information
Device
Package Options
42-Ball Bumped Die
5.29x5.30mm body
1.01mm height (max)
0.52 / 0.60mm pitch
48-Lead LQFP
7.00x7.00mm body
1.60mm height (max)
0.50mm pitch
48-Ball fpBGA
7.00x8.00mm body
1.20mm height (max)
0.75mm pitch
HV2701 HV2701BD M936 HV2701FG-G HV2701GA-G
3
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Supertex inc.
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Doc.# DSFP-HV2701
E012412
Sym Parameter
0°C +25°C +70°C
Units Conditions
Min Max Min Typ Max Min Max
RONS
Small signal switch
ON-resistance
- 30 - 26 38 - 48
Ω
ISIG = 5.0mA VPP = +40V
VNN = -160V
- 25 - 22 27 - 32 ISIG = 200mA
- 25 - 22 27 - 30 ISIG = 5.0mA VPP = +100V
VNN = -100V
- 18 - 18 24 - 27 ISIG = 200mA
- 23 - 20 25 - 30 ISIG = 5.0mA VPP = +160V
VNN = -40V
- 22 - 16 25 - 27 ISIG = 200mA
∆RONS
Small signal switch
ON-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5.0mA, VPP = +100V,
VNN = -100V
RONL
Large signal switch
ON-resistance - - - 15 - - - ΩVSIG= VPP -10V, ISIG = 1.0A
RINT Value of output bleed resistor - - 20 35 50 - - kΩ Output Switch to RGND
IRINT = 0.5mA
ISOL
Switch OFF leakage per
switch* - 5.0 - 1.0 10 - 15 µA VSIG = VPP -10V and VNN +10V
VOS
DC offset switch OFF* - 300 - 100 300 - 300 mV No Load
DC offset switch ON* - 500 - 100 500 - 500 mV
IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches OFF
INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches OFF
IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches ON, ISW = 5.0mA
INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches ON, ISW = 5.0mA
ISW Switch output peak current - 3.0 - 3.0 2.0 - 2.0 A VSIG duty cycle < 0.1%
fSW Output switching frequency - - - - 50 - - kHz Duty cycle = 50%
IPP Average VPP supply current
- 6.5 - - 7.0 - 8.0
mA
VPP = +40V
VNN = -160V All output
switches are
turning ON
and OFF at
50kHz with
no load.
VPP = +100V
VNN = -100V
- 4.0 - - 5.5 - 5.5
VPP = +160V
VNN = -40V
- 4.0 - - 5.0 - 5.5
INN Average VNN supply current
- 6.5 - - 7.0 - 8.0
mA
VPP = +40V
VNN = -160V All output
switches are
turning ON
and OFF at
50kHz with
no load.
VPP = +100V
VNN = -100V
- 4.0 - - 5.0 - 5.5
VPP = +160V
VNN= -40V
- 4.0 - - 5.0 - 5.5
IDD Average VDD supply current - 4.0 - - 4.0 - 4.0 mA fCLK = 5.0MHz, VDD = 5.0V
IDDQ Quiescent VDD supply current - 10 - - 10 - 10 µA All logic inputs are static
ISOR Data out source current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = VDD - 0.7V
ISINK Data out sink current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = 0.7V
CIN Logic input capacitance - 10 - - 10 - 10 pF ---
DC Electrical Characteristics
(over recommended operating conditions unless otherwise noted)
* See Test Circuits on page 5
4
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Supertex inc.
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Doc.# DSFP-HV2701
E012412
AC Electrical Characteristics
(over recommended operating conditions, VDD= 5.0V, tR = tF ≤ 5.0ns, 50% duty cycle, CLOAD = 20pF, unless otherwise noted)
Sym Parameter 0°C +25°C +70°C Units Conditions
Min Max Min Typ Max Min Max
tSD Set up time before LE rises 25 - 25 - - 25 - ns ---
tWLE Time width of LE 56 - - 56 - 56 - ns VDD = 3.0V
12 - - 12 - 12 - VDD = 5.0V
tDO Clock delay time to data out 50 100 50 78 100 50 100 ns VDD = 3.0V
15 40 15 30 40 15 40 VDD= 5.0V
tWCLR Time width of CLR 55 - 55 - - 55 - ns ---
tSU Set up time data to clock 21 - - 21 - 21 - ns VDD= 3.0V
7.0 - - 7.0 - 7.0 - VDD= 5.0V
tHHold time data from clock 2.0 - 2.0 - - 2.0 - ns VDD= 3.0 or 5.0V
fCLK Clock frequency - 8.0 - - 8.0 - 8.0
MHz
VDD= 3.0V
- 20 - - 20 - 20 VDD= 5.0V
tR,tFClock rise and fall times - 50 - - 50 - 50 ns ----
TON Turn ON time* - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RLOAD = 10kΩ
TOFF Turn OFF time* - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RLOAD = 10kΩ
dv/dt Maximum VSIG slew rate
- 20 - - 20 - 20
v/ns
VPP = +40V, VNN = -160V
- 20 - - 20 - 20 VPP = +100V, VNN = -100V
- 20 - - 20 - 20 VPP = +160V, VNN = -40V
KOOFF isolation* -30 - -30 -33 - -30 - dB f = 5.0MHz, 1.0kΩ//15pF load
-58 - -58 - - -58 - f = 5.0MHz, 50Ω load
KCR Switch crosstalk* -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load
IID
Output switch isolation
diode current - 300 - - 300 - 300 mA 300ns pulse width,
2.0% duty cycle
CSG(OFF) OFF capacitance SW to GND 5.0 17 5.0 12 17 5.0 17 pF 0V, f = 1.0MHz
CSG(ON) ON capacitance SW to GND 25 50 25 38 50 25 50 pF 0V, f = 1.0MHz
+VSPK
Output voltage spike*
- - - - 150 - -
mV
VPP = +40V, VNN = -160V,
RLOAD = 50Ω
-VSPK
+VSPK - - - - 150 - - VPP = +100V, VNN = -100V,
RLOAD = 50Ω
-VSPK
+VSPK - - - - 150 - - VPP = +160V, VNN = -40V,
RLOAD = 50Ω
-VSPK
QC Charge injection*
- - - 820 - - -
pC
VPP= +40V, VNN= -160V,
VSIG= 0V
- - - 600 - - - VPP= +100V, VNN= -100V,
VSIG= 0V
- - - 350 - - - VPP= +160V, VNN= -40V,
VSIG= 0V
* See Test Circuits on page 5
5
HV2701
Supertex inc.
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Doc.# DSFP-HV2701
E012412
HV2701 Test Circuits
RGND
RGND
RGND
RGND
RGND
RGND
RGND
DC Offset Switch
ON/OFF
V
PP 5V
VNN
VPP
VNN
VDD
GND
VOUT
T
ON
/T
OFF
Test Circuit
5V
GND
V
PP
-10V
10kΩ
VOUT
Output Switch
Isolation Diode Current
I
ID
5V
GND
VNN
VSIG
Switch Crosstalk
V
IN = 10VP-P
@5MHz
NC
5V
GND
50Ω
Output Voltage Spike
5V
GND
V
OUT
1kΩ
RLOAD 50Ω
+VSPK
–VSPK
OFF Isolation
K
O = 20Log VOUT
VIN
VIN = 10VP-P
@5MHz
5V
GND
VOUT 50Ω
RLOAD
RLOAD
VPP
VNN
VPP
VNN
VDD
VPP
VNN
VPP
VNN
VDD
VPP
VNN
VPP
VNN
VDD
VPP
VNN
VPP
VNN
VDD
VPP
VNN
VPP
VNN
VDD
KCR = 20Log VOUT
VIN
V
PP
-10V
Switch Off Leakage
per Switch
RGND
Open
Q = 1000pF x ΔV
OUT
Charge Injection
5V
GND
VPP
VNN
VPP
VNN
VDD
VPP 5V
VNN
VPP
VNN
VDD
Open
I
SOL
GND
VOUT
ΔVOUT
1000pF
VSIG
6
HV2701
Supertex inc.
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Doc.# DSFP-HV2701
E012412
Logic Function Table
Notes:
1. The 16 switches operate independently.
2. Serial data is clocked in on the L to H transition of the CLK.
3. All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data ow through the
latch.
4. DOUT is high when data in the shift register 15 is high.
5. Shift registers clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
Logic Timing Waveforms
DATA IN
DIN
LE
CLOCK
CLK
DATA OUT
DOUT
OFF
VOUT
(typ)
ON
CLR
50% 50%
50% 50%
t
WLE
t
SD
t
SU
t
h
50%
50%
t
OFF
50%
t
DO
DO
t
ON
t
WCL
D
N+1
D
N
D
N-1
50%50%
90%
10%
D0 D1 ... D7 D8 ... D15 LE CLR SW0 SW1 ... SW7 SW8 ... SW15
L -
...
- -
...
- L L OFF -
...
- -
...
-
H - - - - L L ON - - - -
- L - - - L L - OFF - - -
- H - - - L L - ON - - -
- - - - - L L - - - - -
- - - - - L L - - - - -
- - L - - L L - - OFF - -
- - H - - L L - - ON - -
- - - L - L L - - - OFF -
- - - H - L L - - - ON -
- - - - - L L - - - - -
- - - - - L L - - - - -
- - - - - L L - - - - -
- - - - - L L - - - - -
- - - - L L L - - - - OFF
- - - - H L L - - - - ON
X X X X X X X H L HOLD PREVIOUS STATE
X X X X X X X X H ALL SWITCHES OFF
7
HV2701
Supertex inc.
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Doc.# DSFP-HV2701
E012412
Ball # Ball Name Ball Coordinates*
X Y
1 RGND +2100.00 -2239.50
2 VPP -1500.00 -2239.50
3 VNN -2100.00 -2239.50
4 DOUT +1200.00 -1719.75
5 CLR +600.00 -1719.75
6 CLK 0.00 -1719.75
7 GND -600.00 -1719.75
8 SW15A +1500.00 -1200.00
9 SW15B +900.00 -1200.00
10 LE +300.00 -1200.00
11 VDD -300.00 -1200.00
12 SW0A -900.00 -1200.00
13 SW0B -1500.00 -1200.00
14 SW14A +1500.00 -600.00
15 SW14B +900.00 -600.00
16 DIN 0.00 -680.25
17 SW1A -900.00 -600.00
18 SW1B -1500.00 -600.00
19 SW13A +1500.00 0.00
20 SW13B +900.00 0.00
21 SW2A -900.00 0.00
Ball # Ball Name Ball Coordinates*
X Y
22 SW2B -1500.00 0.00
23 SW12A +1500.00 +600.00
24 SW12B +900.00 +600.00
25 SW3A -900.00 +600.00
26 SW3B -1500.00 +600.00
27 SW11A +2100.00 +1200.00
28 SW11B +1500.00 +1200.00
29 SW9B +900.00 +1200.00
30 SW8B +300.00 +1200.00
31 SW7A -300.00 +1200.00
32 SW6A -900.00 +1200.00
33 SW4A -1500.00 +1200.00
34 SW4B -2100.00 +1200.00
35 SW10B +2100.00 +1800.00
36 SW10A +1500.00 +1800.00
37 SW9A +900.00 +1800.00
38 SW8A +300.00 +1800.00
39 SW7B -300.00 +1800.00
40 SW6B -900.00 +1800.00
41 SW5B -1500.00 +1800.00
42 SW5A -2100.00 +1800.00
Ball Description
42-Ball Bumped Die Package Outline (BD)
Note:
* Referenced from center of package (µm).
Ball Conguration
1
2
3
8
9
10 12
13
4
5
6
7
11
18 17 16 15 14
25
26
21
22
23
24
19
20
41
42
33
34
39
40
31
32
37
38
29
30
35
36
27
28
42-Ball Bumped Die (BD)
(top view)
8
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Supertex inc.
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Doc.# DSFP-HV2701
E012412
Pin Description
48-Lead LQFP (FG)
Pin # Function
1 NC
2 NC
3 SW4B
4 SW4A
5 SW3B
6 SW3A
7 SW2B
8 SW2A
9 SW1B
10 SW1A
11 SW0B
12 SW0A
Pin # Function
13 VNN
14 NC
15 VPP
16 NC
17 GND
18 VDD
19 DIN
20 CLK
21 LE
22 CLR
23 DOUT
24 RGND
Pin # Function
25 SW15B
26 SW15A
27 SW14B
28 SW14A
29 SW13B
30 SW13A
31 SW12B
32 SW12A
33 SW11B
34 SW11A
35 NC
36 NC
Pin # Function
37 SW10B
38 SW10A
39 SW9B
40 SW9A
41 SW8B
42 SW8A
43 SW7B
44 SW7A
45 SW6B
46 SW6A
47 SW5B
48 SW5A
Ball # Function
A1 SW5A
A2 SW5B
A3 SW7A
A4 SW7B
A5 SW9A
A6 SW9B
B1 SW6A
B2 SW6B
B3 SW8A
B4 SW8B
B5 SW10A
B6 SW10B
Ball # Function
C1 SW4B
C2 SW3B
C3 SW2B
C4 SW13A
C5 SW12A
C6 SW11A
D1 SW4A
D2 SW3A
D3 SW2A
D4 SW13B
D5 SW12B
D6 SW11B
Ball # Function
E1 SW1B
E2 SW0B
E3 SW15B
E4 SW15A
E5 SW14B
E6 SW14A
F1 SW1A
F2 SW0A
F3 NC
F4 NC
F5 VDD
F6 RGND
Ball # Function
G1 NC
G2 GND
G3 NC
G4 DIN
G5 CLK
G6 DOUT
H1 VNN
H2 NC
H3 VPP
H4 NC
H5 LE
H6 CLR
NC = No Internal Connection
Pin Conguration
48-Ball fpBGA (GA)
9
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Supertex inc.
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Doc.# DSFP-HV2701
E012412
42-Ball Bumped Die Package Outline (BD)
5.29x5.30mm body, 1.01mm height (max), 0.52 / 0.60mm pitch
Symbol A A1 A2 b D D1 E E1 E2 e e1
Dimension
(mm)
MIN 0.89 0.21 0.68 0.29 5.19 4.20
BSC
5.20 4.04
BSC
0.68
BSC
0.60
BSC
0.52
BSC
NOM 0.95 0.24 0.71 0.32 5.29 5.30
MAX 1.01 0.27 0.74 0.35 5.39 5.40
Drawings not to scale.
Supertex Doc. #: DSPD-42BumpedDieBD, Version A030211.
Top View View B
Side View
A2
A1
Seating
Plane
View A View B
Bottom View
D
View A
b
E
A
Note 1
(Ball 1
Index Area
D/4 x E/4)
0,0
E1
e1
E2
e D1
e
e1
e1
e
C/L
C/L
1
42
1
42
Notes:
1. Ball 1 identier must be located in the index area indicated. Ball 1 identier can be: a molded mark/identier; an embedded metal marker; or a
printed indicator.
10
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Doc.# DSFP-HV2701
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48-Lead LQFP Package Outline (FG)
7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch
Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ
Dimension
(mm)
MIN 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80*
0.50
BSC
0.45
1.00
REF
0.25
BSC
0O
NOM - - 1.40 0.22 9.00 7.00 9.00 7.00 0.60 3.5O
MAX 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* 0.75 7O
JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001.
* This dimension is not specied in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-48LQFPFG Version, D041309.
1
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
Seating
Plane
Top View
Side View
Note 1
(Index Area
D1/4 x E1/4)
48
A2A
A1
b
D
D1
E
E1
e
Note:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013
Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
11
HV2701
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV2701
E012412
48-Ball fpBGA Package Outline (GA)
7.00x8.00mm body, 1.16mm height (max), 0.75mm pitch
Symbol A A1 A2 b D D1 E E1 e
Dimension
(mm)
MIN 0.86 0.18 0.68 0.25 6.90 3.75
BSC
7.90 5.25
BSC
0.75
BSC
NOM 1.01 0.23 0.78 0.30 7.00 8.00
MAX 1.16 0.28 0.88 0.35 7.10 8.10
Drawings not to scale.
Supertex Doc. #: DSPD-48fpBGAGA, Version C020309.
Top View View B
e
Side View
A2
A1
Seating
Plane
View A View B
Bottom View
D
View A
Φb
e
E
A
D1
E1
Note 1
(Ball A1
Index Area
D/4 x E/4)
Note 2
6 5 4 3 2 1
A
B
C
D
E
F
G
H
Notes:
1. Ball A1 identier must be located in the index area indicated. Ball A1 identier can be: a molded mark/identier; an embedded metal marker; or a
printed indicator.
2. Corner A1 identier (actual shape may vary).