Supertex inc. HV2701 Low Charge Injection 16-Channel High Voltage Analog Switch with Bleed Resistors Features HVCMOS technology for high performance Integrated bleed resistors on the outputs 16-channel high voltage analog switch 3.3V input logic level compatible 20MHz data shift clock frequency Very low quiescent power dissipation (-10A) Low parasitic capacitance DC to 50MHz small signal frequency response -60dB typical OFF-isolation at 5.0MHz CMOS logic circuitry for low power Excellent noise immunity Cascadable serial data register with latches Flexible operating supply voltages Applications Medical ultrasound imaging NDT metal flaw detection Piezoelectric transducer drivers Optical MEMS modules The Supertex HV2701 is a low charge injection, 16-channel, high voltage, analog switch integrated circuit (IC) with bleed resistors. The device can be used in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging and piezoelectric transducer drivers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. Input data are shifted into a 16-bit shift register that can then be retained in a 16-bit latch. To reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. Data is clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V. Block Diagram Latches D LE CLR DIN CLK General Description 16-Bit Shift Register Level Shifters Output Switches SW0 D LE CLR SW1 D LE CLR SW2 D LE CLR SW14 D LE CLR SW15 DOUT VDD GND Doc.# DSFP-HV2701 E012412 LE CLR VNN VPP RGND Supertex inc. www.supertex.com HV2701 Pin Configurations Ordering Information Package Options Device 3 42-Ball Bumped Die 48-Lead LQFP HV2701 7.00x7.00mm body 1.60mm height (max) 0.50mm pitch 7.00x8.00mm body 1.20mm height (max) 0.75mm pitch HV2701BD M936 HV2701FG-G HV2701GA-G -G indicates package is RoHS compliant (`Green'). Bumped Die package is RoHS compliant (`Green'). M936 specifies product in tape and reel. 1 -0.5V to VDD +0.3V 19 24 23 9 8 15 14 34 33 32 31 30 29 28 27 42 41 40 39 38 37 36 35 48 (top view) 3.0A 2 3 4 5 6 A -65C to 150C B C 1.5W 1.0W 1.0W D E F G H 48-Ball fpBGA (GA) (top view) Recommended Operating Conditions Value VDD Logic power supply voltage 3.0V to 5.5V VPP Positive high voltage supply +40V to VNN +200V VNN Negative high voltage supply VIH High level input voltage 0.9VDD to VDD VIL Low level input voltage 0V to 0.1VDD VSIG Analog signal voltage peak-to-peak Operating free air temperature 20 25 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. TA 21 16 48-Lead LQFP (FG) VNN to VPP Power dissipation: 42-Ball Bumped Die (BD) 48-Lead LQFP (FG) 48-Ball fpBGA (GA) Parameter 22 26 11 +0.5V to -200V Peak analog signal current/channel Sym 17 220V Logic input voltage Storage temperature 12 18 Value -0.5V to VNN+200V Analog signal range 13 -0.5V to +7.0V VPP positive supply VNN negative supply 10 4 (top view) Parameter VPP-VNN differential supply 5 42-Ball Bumped Die (BD) Absolute Maximum Ratings VDD logic supply 1 6 7 48-Ball fpBGA 5.29x5.30mm body 1.01mm height (max) 0.52 / 0.60mm pitch 2 -40V to -160V VNN+10V to VPP-10V 0C to 70C Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be within VNN and VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Product Marking LLLLLLL YYWW HV2701BD YY = Year Sealed WW = Week Sealed L = Lot Number Package may or may not include the following marks: Si or 42-Ball Bumped Die (BD) Top Marking YY = Year Sealed WW = Week Sealed L = Lot Number Bottom Marking C = Country of Origin* A = Assembler ID* = "Green" Packaging CCCCCCCC YYW W HV2701FG LLLLLLLLL AAA *May be part of top marking Package may or may not include the following marks: Si or 48-Lead LQFP (FG) YY = Year Sealed WW = Week Sealed L = Lot Number = "Green" Packaging Packages may or may not include the following marks: Si or YYWW HV2701GA LLLLLLLLL 48-Ball fpBGA (GA) Doc.# DSFP-HV2701 E012412 2 Supertex inc. www.supertex.com HV2701 DC Electrical Characteristics (over recommended operating conditions unless otherwise noted) Sym Parameter 0C +25C +70C Units Conditions Min Max Min Typ Max Min Max - 30 - 26 38 - 48 ISIG = 5.0mA - 25 - 22 27 - 32 ISIG = 200mA - 25 - 22 27 - 30 - 18 - 18 24 - 27 - 23 - 20 25 - 30 ISIG = 5.0mA - 22 - 16 25 - 27 ISIG = 200mA Small signal switch ON-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5.0mA, VPP = +100V, VNN = -100V RONL Large signal switch ON-resistance - - - 15 - - - VSIG= VPP -10V, ISIG = 1.0A RINT Value of output bleed resistor - - 20 35 50 - - k Output Switch to RGND IRINT = 0.5mA ISOL Switch OFF leakage per switch* - 5.0 - 1.0 10 - 15 A VSIG = VPP -10V and VNN +10V DC offset switch OFF* - 300 - 100 300 - 300 mV DC offset switch ON* - 500 - 100 500 - 500 mV IPPQ Quiescent VPP supply current - - - 10 50 - - A All switches OFF INNQ Quiescent VNN supply current - - - -10 -50 - - A All switches OFF IPPQ Quiescent VPP supply current - - - 10 50 - - A All switches ON, ISW = 5.0mA INNQ Quiescent VNN supply current - - - -10 -50 - - A All switches ON, ISW = 5.0mA ISW Switch output peak current - 3.0 - 3.0 2.0 - 2.0 A VSIG duty cycle < 0.1% fSW Output switching frequency - - - - 50 - - kHz - 6.5 - - 7.0 - 8.0 - 4.0 - - 5.5 - 5.5 - 4.0 - - 5.0 - 5.5 VPP = +160V VNN = -40V - 6.5 - - 7.0 - 8.0 VPP = +40V VNN = -160V - 4.0 - - 5.0 - 5.5 - 4.0 - - 5.0 - 5.5 RONS RONS VOS IPP INN Small signal switch ON-resistance Average VPP supply current Average VNN supply current VPP = +40V VNN = -160V ISIG = 5.0mA VPP = +100V VNN = -100V ISIG = 200mA VPP = +160V VNN = -40V No Load Duty cycle = 50% VPP = +40V VNN = -160V mA mA All output switches are turning ON and OFF at 50kHz with no load. VPP = +100V VNN = -100V All output switches are turning ON and OFF at 50kHz with no load. VPP = +100V VNN = -100V VPP = +160V VNN= -40V IDD Average VDD supply current - 4.0 - - 4.0 - 4.0 mA fCLK = 5.0MHz, VDD = 5.0V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 A All logic inputs are static ISOR Data out source current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = VDD - 0.7V ISINK Data out sink current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = 0.7V CIN Logic input capacitance - 10 - - 10 - 10 pF --- * See Test Circuits on page 5 Doc.# DSFP-HV2701 E012412 3 Supertex inc. www.supertex.com HV2701 AC Electrical Characteristics (over recommended operating conditions, VDD= 5.0V, tR = tF 5.0ns, 50% duty cycle, CLOAD = 20pF, unless otherwise noted) Sym Parameter tSD Set up time before LE rises tWLE Time width of LE tDO Clock delay time to data out tWCLR Time width of CLR tSU Set up time data to clock tH Hold time data from clock fCLK Clock frequency tR,tF 0C +25C +70C Min Max Min Typ Max Min Max 25 - 25 - - 25 - 56 - - 56 - 56 - 12 - - 12 - 12 - 50 100 50 78 100 50 100 15 40 15 30 40 15 40 55 - 55 - - 55 - 21 - - 21 - 21 - 7.0 - - 7.0 - 7.0 - 2.0 - 2.0 - - 2.0 - - 8.0 - - 8.0 - 8.0 Units ns ns ns ns ns ns Conditions --VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD= 5.0V --VDD= 3.0V VDD= 5.0V VDD= 3.0 or 5.0V VDD= 3.0V - 20 - - 20 - 20 MHz Clock rise and fall times - 50 - - 50 - 50 ns ---- TON Turn ON time* - 5.0 - - 5.0 - 5.0 s VSIG = VPP -10V, RLOAD = 10k TOFF Turn OFF time* - 5.0 - - 5.0 - 5.0 s VSIG = VPP -10V, RLOAD = 10k - 20 - - 20 - 20 - 20 - - 20 - 20 - 20 - - 20 - 20 -30 - -30 -33 - -30 - -58 - -58 - - -58 - -60 - -60 -70 - -60 - dB f = 5.0MHz, 50 load - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle dv/dt Maximum VSIG slew rate KO OFF isolation* KCR Switch crosstalk* IID Output switch isolation diode current VDD= 5.0V VPP = +40V, VNN = -160V v/ns VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V dB f = 5.0MHz, 1.0k//15pF load f = 5.0MHz, 50 load CSG(OFF) OFF capacitance SW to GND 5.0 17 5.0 12 17 5.0 17 pF 0V, f = 1.0MHz CSG(ON) ON capacitance SW to GND 25 50 25 38 50 25 50 pF 0V, f = 1.0MHz - - - - 150 - - - - - - 150 - - - - - - 150 - - VPP = +160V, VNN = -40V, RLOAD = 50 - - - 820 - - - VPP= +40V, VNN= -160V, VSIG= 0V - - - 600 - - - - - - 350 - - - +VSPK -VSPK +VSPK -VSPK Output voltage spike* +VSPK -VSPK QC Charge injection* VPP = +40V, VNN = -160V, RLOAD = 50 mV pC VPP = +100V, VNN = -100V, RLOAD = 50 VPP= +100V, VNN= -100V, VSIG= 0V VPP= +160V, VNN= -40V, VSIG= 0V * See Test Circuits on page 5 Doc.# DSFP-HV2701 E012412 4 Supertex inc. www.supertex.com HV2701 HV2701 Test Circuits VPP -10V VPP -10V ISOL 10k RLOAD VOUT VOUT Open Open RGND RGND VPP VPP VDD VNN VNN GND 5V RGND VPP VPP VDD VNN VNN GND Switch Off Leakage per Switch 5V VPP VPP VDD VNN VNN GND 5V TON/TOFF Test Circuit DC Offset Switch ON/OFF VIN = 10VP-P @5MHz VIN = 10VP-P @5MHz VSIG IID VOUT VNN RLOAD NC 50 50 RGND RGND RGND VPP VPP VDD VNN VNN GND KO = 20Log 5V VPP VPP VDD VNN VNN GND VPP VPP VDD VNN VNN GND VOUT KCR = 20Log VIN Output Switch Isolation Diode Current OFF Isolation 5V VOUT VIN Switch Crosstalk +VSPK VOUT VOUT -VSPK 1000pF VOUT RLOAD VSIG RGND 50 RGND 1k VPP VPP VDD VNN VNN GND 5V Q = 1000pF x VOUT Charge Injection Doc.# DSFP-HV2701 E012412 5V VPP VPP VDD VNN VNN GND 5V Output Voltage Spike 5 Supertex inc. www.supertex.com HV2701 Logic Function Table D0 D1 L ... D7 D8 - - H - - D15 LE CLR SW0 SW1 SW7 SW8 - - L L OFF - - - - - - - L L ON - - - - L - - - L L - OFF - - - - H - - - L L - ON - - - - - - - - L L - - - - - - - - - - L L - - - - - - - L - - L L - - OFF - - - - H - - L L - - ON - - - - L - L L - - - OFF - - - H - L L - - - ON - - - - - - L L - - - - - - - - - - L L - - - - - - - - - - L L - - - - - - - - - - L L - - - - - - - - - L L L - - - - OFF - - - - H L L - - - - ON X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF ... ... ... ... ... ... ... SW15 - Notes: 1. The 16 switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch. 4. DOUT is high when data in the shift register 15 is high. 5. Shift registers clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. Logic Timing Waveforms DN+1 DN DATA IN DIN 50% LE 50% DN-1 50% 50% tWLE tSD CLOCK CLK 50% tSU tDO DATA OUT DOUT VOUT (typ) th DO 50% tOFF OFF tON 90% 10% ON CLR Doc.# DSFP-HV2701 E012412 50% 50% tWCL 50% 6 Supertex inc. www.supertex.com HV2701 Ball Description 42-Ball Bumped Die Package Outline (BD) Ball # Ball Name 1 Ball Coordinates* Ball # Ball Name X Y RGND +2100.00 -2239.50 22 2 VPP -1500.00 -2239.50 3 VNN -2100.00 4 DOUT 5 Ball Coordinates* X Y SW2B -1500.00 0.00 23 SW12A +1500.00 +600.00 -2239.50 24 SW12B +900.00 +600.00 +1200.00 -1719.75 25 SW3A -900.00 +600.00 CLR +600.00 -1719.75 26 SW3B -1500.00 +600.00 6 CLK 0.00 -1719.75 27 SW11A +2100.00 +1200.00 7 GND -600.00 -1719.75 28 SW11B +1500.00 +1200.00 8 SW15A +1500.00 -1200.00 29 SW9B +900.00 +1200.00 9 SW15B +900.00 -1200.00 30 SW8B +300.00 +1200.00 10 LE +300.00 -1200.00 31 SW7A -300.00 +1200.00 11 VDD -300.00 -1200.00 32 SW6A -900.00 +1200.00 12 SW0A -900.00 -1200.00 33 SW4A -1500.00 +1200.00 13 SW0B -1500.00 -1200.00 34 SW4B -2100.00 +1200.00 14 SW14A +1500.00 -600.00 35 SW10B +2100.00 +1800.00 15 SW14B +900.00 -600.00 36 SW10A +1500.00 +1800.00 16 DIN 0.00 -680.25 37 SW9A +900.00 +1800.00 17 SW1A -900.00 -600.00 38 SW8A +300.00 +1800.00 18 SW1B -1500.00 -600.00 39 SW7B -300.00 +1800.00 19 SW13A +1500.00 0.00 40 SW6B -900.00 +1800.00 20 SW13B +900.00 0.00 41 SW5B -1500.00 +1800.00 21 SW2A -900.00 0.00 42 SW5A -2100.00 +1800.00 Note: * Referenced from center of package (m). Ball Configuration 3 2 1 6 7 13 12 5 10 11 16 4 9 8 15 14 18 17 22 21 20 19 26 25 24 23 34 33 32 31 30 29 28 27 42 41 40 39 38 37 36 35 42-Ball Bumped Die (BD) (top view) Doc.# DSFP-HV2701 E012412 7 Supertex inc. www.supertex.com HV2701 Pin Description 48-Lead LQFP (FG) Pin # Function Pin # Function Pin # Function Pin # Function 1 NC 13 VNN 25 SW15B 37 SW10B 2 NC 14 NC 26 SW15A 38 SW10A 3 SW4B 15 VPP 27 SW14B 39 SW9B 4 SW4A 16 NC 28 SW14A 40 SW9A 5 SW3B 17 GND 29 SW13B 41 SW8B 6 SW3A 18 VDD 30 SW13A 42 SW8A 7 SW2B 19 DIN 31 SW12B 43 SW7B 8 SW2A 20 CLK 32 SW12A 44 SW7A 9 SW1B 21 LE 33 SW11B 45 SW6B 10 SW1A 22 CLR 34 SW11A 46 SW6A 11 SW0B 23 DOUT 35 NC 47 SW5B 12 SW0A 24 RGND 36 NC 48 SW5A Pin Configuration 48-Ball fpBGA (GA) Ball # Function Ball # Function Ball # Function Ball # Function A1 SW5A C1 SW4B E1 SW1B G1 NC A2 SW5B C2 SW3B E2 SW0B G2 GND A3 SW7A C3 SW2B E3 SW15B G3 NC A4 SW7B C4 SW13A E4 SW15A G4 DIN A5 SW9A C5 SW12A E5 SW14B G5 CLK A6 SW9B C6 SW11A E6 SW14A G6 DOUT B1 SW6A D1 SW4A F1 SW1A H1 VNN B2 SW6B D2 SW3A F2 SW0A H2 NC B3 SW8A D3 SW2A F3 NC H3 VPP B4 SW8B D4 SW13B F4 NC H4 NC B5 SW10A D5 SW12B F5 VDD H5 LE B6 SW10B D6 SW11B F6 RGND H6 CLR NC = No Internal Connection Doc.# DSFP-HV2701 E012412 8 Supertex inc. www.supertex.com HV2701 42-Ball Bumped Die Package Outline (BD) 5.29x5.30mm body, 1.01mm height (max), 0.52 / 0.60mm pitch D1 e 42 C/L 42 e 0,0 C/L E Note 1 (Ball 1 Index Area D/4 x E/4) E2 E1 e1 e1 e1 1 1 D e View B Top View Side View Bottom View View A b A2 A A1 Seating Plane View A View B Notes: 1. Ball 1 identifier must be located in the index area indicated. Ball 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A A1 A2 b D MIN 0.89 0.21 0.68 0.29 5.19 NOM 0.95 0.24 0.71 0.32 5.29 MAX 1.01 0.27 0.74 0.35 5.39 D1 4.20 BSC E 5.20 5.30 5.40 E1 E2 e e1 4.04 BSC 0.68 BSC 0.60 BSC 0.52 BSC Drawings not to scale. Supertex Doc. #: DSPD-42BumpedDieBD, Version A030211. Doc.# DSFP-HV2701 E012412 9 Supertex inc. www.supertex.com HV2701 48-Lead LQFP Package Outline (FG) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch D D1 E1 E Note 1 (Index Area D1/4 x E1/4) 48 1 e b Top View View B A A2 L2 Seating Plane L L1 A1 Gauge Plane Seating Plane View B Side View Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b D D1 E E1 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80* - - 1.40 0.22 9.00 7.00 9.00 7.00 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* e 0.50 BSC L 0.45 0.60 0.75 L1 L2 1.00 REF 0.25 BSC 0O 3.5O 7O JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-48LQFPFG Version, D041309. Doc.# DSFP-HV2701 E012412 10 Supertex inc. www.supertex.com HV2701 48-Ball fpBGA Package Outline (GA) 7.00x8.00mm body, 1.16mm height (max), 0.75mm pitch 6 Note 1 (Ball A1 Index Area D/4 x E/4) 5 4 3 D1 2 1 Note 2 A e B C E E1 D E F G H e D View B Top View View A Side View A2 Bottom View b A A1 Seating Plane View A View B Notes: 1. Ball A1 identifier must be located in the index area indicated. Ball A1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Corner A1 identifier (actual shape may vary). Symbol Dimension (mm) A A1 A2 b D MIN 0.86 0.18 0.68 0.25 6.90 NOM 1.01 0.23 0.78 0.30 7.00 MAX 1.16 0.28 0.88 0.35 7.10 D1 E 3.75 BSC 7.90 8.00 8.10 E1 e 5.25 BSC 0.75 BSC Drawings not to scale. Supertex Doc. #: DSPD-48fpBGAGA, Version C020309. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate "product liability indemnification insurance agreement." Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. (c)2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV2701 E012412 11 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com