U2783B-FS - Temic Semiconductors

TELEFUNKEN Semiconductors U2783B-FS

Preliminary Information 1

Rev. A2: 14.03.1995

1250 MHz / 400 MHz Twin PLL

Description

The IC U2783B is a low power twin PLL manufactured

with TELEFUNKEN’s advanced UHF process. The

maximum operating frequency is 1250 MHz and 400 MHz

respectively. It features a wide supply voltage range from

2.7 to 5.5 V. Prescaler and power down function for both

PLL’s is integrated. Applications are CT1, CT2, GSM,

IS54 etc.

Features

Very low current consumption (typical 3 V/10 mA)

Supply voltage range 2.7 V – 5.5 V

Maximum input frequency PLL1: 1250 MHz,

PLL2: 400 MHz

2 pins for separate power down functions

Output for PLL lock status

Prescaler 64/65 for PLL1 and 32/33 for PLL2

SSO-20 package

ESD protected according to MIL-STD 833

method 3015 cl.2

Benefits

Low current consumption leads to extended talk time

Twin PLL saves costs and space

One foot print for all TEMIC twin PLL’s saves design-

in time

Block Diagram

12 bit reference divider 2

12 bit latch 2

15 bit latch 2

15 bit main divider 2

17 bit

Shift register

17 bit latch 1

17 bit main divider 1

12 bit reference divider 1

12 bit latch 1

16 bit latch

Control functions

Oscillator

on / off

divide by 2

64 / 65 Prescaler 1

32 / 33 Prescaler 2

3 bit

Load control

Phase

detector 1

Phase

detector 2

Charge

pump 1

Charge

pump 2

Pump

bias

Lock

select

Ports

Power

down Test

5I/Port 0

HPD1/Port 1

HPD2/Port 4

Port3

Lock Port2

CP1

VScp

Iset

CP2

VS analog

VS digital

DGND

AGND

OSCi

OSCo

RFi1

Clock

Data

Enable

RFi2

94 8918

TELEFUNKEN Semiconductors

U2783B-FS

Preliminary Information

2Rev. A2: 14.03.1995

Pin Description

20 Port 3

Iset

CP 2

VScp

RFi 2

GNDA

HPD2/Port 4

Enable

Data

Clock

5I/Port 0

VS digital

CP 1

VS analog

RFi 1

GNDD

OSCi

OSCo

HPD1/Port 1

Lock/Port 2

95 9622

Pin Symbol Function

15I/Port 0 5I – Control input / o.c.output

2 VS digital Power supply digital section

3CP 1 Charge pump output of

synthesizer 1

4 VS analog Power supply analog section

5RFi 1 RF divider input synthesizer

6 GNDDGround for digital section

7 OSCiReference oscillator input

8 OSCoReference oscillator output

9HPD 1/

Port 1 Hardware power down input of

synthesizer 1 / o.c.output

10 Lock/

Port 2 Lock output / o.c.output /

testmode output

11 Clock 3-wire-bus: serial clock input

12 Data 3-wire-bus: serial data input

13 Enable 3-wire-bus: serial enable input

14 HPD 2/

Port 4 Hardware power down input of

synthesizer 2 / o.c.output

15 GNDAGround for analog section

16 RFi 2 RF divider input synthesizer 2

17 VScp Charge pump supply voltage

18 CP 2 Charge pump output of

synthesizer 2

19 Iset Reference pin for charge pump

currents

20 Port 3 o.c.output

Absolute Maximum Ratings

Parameters Symbol Value Unit

Supply voltage Pins 2, 4 and 17 VS, VScp 6 V

Input voltage Pins 1, 3, 5, 8, 9, 10, 11, 12, 13,

14, 15, 16, 18 and 20 Vi0 to VSV

Junction temperature Tj125 °C

Storage temperature range Tstg –40 to +125 °C

Operating Range

Parameters Symbol Value Unit

Supply voltage Pins 2, 4 and 17 VS, VScp 2.7 to 5.5 V

Ambient temperature range Tamb –30 to +85 °C

Thermal Resistance

Parameters Symbol Value Unit

Junction ambient SSO-20 Rthja 140 K/W

TELEFUNKEN Semiconductors U2783B-FS

Preliminary Information 3

Rev. A2: 14.03.1995

Electrical Characteristics

Tamb = 25_C, VS = 2.7 to 5.5 V, VScp = 5 V, unless otherwise specified

Parameters Test Conditions Symbol Min. Typ. Max. Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DC Supply

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

Supply current

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

VS = 3 V

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

Supply current CP

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

VCP = 5 V, PLL in lock

condition

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ICP

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

µA

PLL 1

Input voltage fRFi1 = 200 – 1250 MHz VRFi1 20 200 mVRMS

Scaling factor prescaler SPSC 64/65

Scaling factor main counter SM5 2047

Scaling factor swallow

counter SS0 63

Reference counter SR5 4096

PLL 2

Input voltage fRFi2 = 50 MHz VRFi2 40

200

mVRMS

fRFi2 = 100 – 400 MHz 20 200

Scaling factor prescaler SPSC 32/33

Scaling factor main counter SM5 1023

Scaling factor swallow SS0 31

Reference counter SR5 4096

Reference oscillator

Recommended crystal

series resistance 10 200 

External reference input

frequency AC coupled sinewave

RF/2 = 0

RF/2 = 1

OSCi1

120

40 MHz

External reference input

amplitude AC coupled sinewave 2) OSCi100 mVRMS

Logic input levels (Clock, Data, Enable, HPD1, HPD2, 5I)

High input level ViH 1.5 V

Low input level ViL 00.4 V

High input current IiH –5 5 A

Low input current IiL –5 5 A

Logic output levels (Port 0, 1, 2, 3, 4, Lock)

Leakage current VOH = 5.5 V IL10 A

Saturation voltage IOL = 0.5 mA VSL 0.4 V

Charge pump output (Rset = tbd.)

Source current VCP  VScp/2 PLL2

5I = L PLL1

5I = H PLL1 Isource

– 1

–0.2

–1 mA

Sink current VCP  VScp/2 PLL2

5I = L PLL1

5I = H PLL1 Isink

0.2

1mA

Leakage current VCP  VScp/2 IL5 nA

1) RMS voltage at 50 ; 2) OSCo is open if an external reference frequency is applied

TELEFUNKEN Semiconductors

U2783B-FS

Preliminary Information

4Rev. A2: 14.03.1995

Serial Programming Bus

Reference and programmable counters can be

programmed by the 3-wire-bus (Clock, Data and Enable).

After setting Enable in high condition the data is transfered

bit by bit during the rising edge of the clock into the shift

low the programmed information is loaded according to the

adressbits into the selected latch. There is no check made

how many clock pulses arrived during enable high. During

powerdown mode the 3-wire-bus remains active and the IC

can be reprogrammed.

Bit Allocation

MSB LSB

Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6Bit

7Bit

8Bit

9Bit

10 Bit

11 Bit

12 Bit

13 Bit

14 Bit

15 Bit

16 Bit

17 Bit

18 Bit

19 Bit

data bits address bits

D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

PLL1

M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S5 S4 S3 S2 S1 PLL1

S0 0 0 1

PLL1

R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 PLL1

R0 0 1 0

PLL2

M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 PLL2

S0 0 1 1

PLL2

R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 PLL2

R0 1 0 0

RF/

2Test 5IP TRI

2TRI

1PS2 PS1 H2P H1P LPB LPA P4 P3 P2 P1 P0 1 0 1

SPD

5I SPD

2SPD

11 1 0

Scaling factors

PGT of PLL1:

S0 ... S5: These bits are setting the swallow counter SS.

TS = S0*20 + S1*21 + ... + S4*24 + S5*25

allowed scalling factors for SS: 0 ... 63, TS < TM

M0 ... M10: These bits are setting the main counter SM.

TM = M0*20 + M1*21 + ... + M9*29 + M10*210

allowed scalling factors for SM: 5 ... 2047

SPGT: Total scalling factor of the programmable counter:

SPGT = (64*SM) + SS Condition: SS < SM

RFT of PLL1 and PLL2:

R0 ... R11: These bits are setting the reference counter SR.

SR = R0*20 + ... + R10*210 + R11*211

allowed scalling factors for SR: 5 ... 4096

RF/2 = 1: SRFT = 2 * SR

RF/2 = 0: SRFT = SR

PGT of PLL2:

S0 ... S4: These bits are setting the swallow counter SS.

TS = S0*20 + S1*21 + ... + S3*23 + S4*24

allowed scalling factors for SS: 0 ... 31, TS < TM

M0 ... M9: These bits are setting the main counter SM.

TM = M0*20 + M1*21 + ... + M8*28 + M9*29

allowed scalling factors for SM: 5 ... 1023

SPGT: Total scalling factor of the programmable counter:

SPGT = (32*SM) + SS Condition: SS < SM

TELEFUNKEN Semiconductors U2783B-FS

Preliminary Information 5

Rev. A2: 14.03.1995

Serial Programming Bus

Control bits:

P0 ... P4: o.c. output ports (1 = high impedance)

LPA, LPB: selection of P2 output or locksignal LPA LPB function of pin 10

0 0 o.c. output P2

0 1 locksignal of synthesizer 2

1 0 locksignal of synthesizer 1

1 1 wiredor locksignal of both synthesizer

H1P, H2P: selection of P1/4 output or hardware power down input of synthesizer 1/2 (0 = Port / 1 = HPD)

5IP: selection of P0 output or high current switching input for the charge pump current of synthesizer 1

(0 = Port / 1 = charge pump 1 current switch input)

PS1, PS2: phase selection of synthesizer 1 and synthesizer 2 (1 = normal / 0 = invers)

PS-PLL1/2 = 1 PS-PLL1/2 = 0

CP1/2 CP1/2

fR > fPIsink Isource

fR < fPIsource Isink

fR = fP0 0

RF/2: divide by 2 prescaler for reference divider (0 = off / 1 = on)

SPD1, SPD2: software power down bit of synthesizer 1/2 (0 = powerdown / 1 = powerup)

5I: software switch for the charge pump current of synthesizer 1 (0 = low current / 1 = high current)

TRI1, TRI2: enables tristate for the charge pump of synthesizer 1/2 (0 = normal / 1 = tristate)

TEST: enables counter testmode (0 = disabled / 1 = enabled)

TEST LPA LPB PS1 PS2 Testsignal

at pin 10

1 1 0 1 x RFT1

1 1 0 0 x PGT1

1 0 1 x 1 RFT2

1 0 1 x 0 PGT2

Preset condition at hard power up (supply voltage switched on):

P0 ... P4 = 1 high impedane

LPA, LPB = 1 common lock signal

H1P, H2P = 1 hardware power down enable

5IP = 1 current switching input synthesizer 1 enabled

PS1, PS2 = 1 normal value for passive loop filter

RF/2 = 0 divide by 2 prescaler for reference divider off

SPD1, SPD2 = 0 software power down active

5I = 1 synthesizer 1 high current charge pump active

TRI1, TRI2 = 0 tristate off

TEST = 0 testmode off

The device is in power up condition when SPD-PLL1/2 = 1 and if H1P/H2P = 1 the hardware power down pins 9/14 are

in high state.

High current of charge pump synthesizer 1 is active when 5I = 1 and if 5IP = 1 the charge pump current control input pin

1 is in high state.

TELEFUNKEN Semiconductors

U2783B-FS

Preliminary Information

6Rev. A2: 14.03.1995

Application Circuit

5I / P0

RF2

HPD1 / PORT1

HPD2 / PORT4

RF1

CRYSTAL OSC.

CLOCK

DATA

ENABLE

LOCK / PORT2 / TEST

47u 10n

10n 18

10n 10n

10n

18 18

1851 10n 47u

10n

5118

10n

VCO1 VCO2

INPUT

94 9621

V VCO

VScp

TELEFUNKEN Semiconductors U2783B-FS

Preliminary Information 7

Rev. A2: 14.03.1995

Timing Diagram Serial Bus

Data

Clock

Enable

MSB LSB

94 8919

Dimensions in mm

SSO-20

We reserve the right to make changes to improve technical design without further notice.

Parameters can vary in different applications. All operating parameters must be validated for each customer

application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application,

the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or

indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use.

TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany

Telephone: 49 (0)7131 67 2831, Fax Number: 49 (0)7131 67 2423