Vishay Siliconix
DG9421, DG9422
Document Number: 70679
S11-1429-Rev. G, 18-Jul-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Precision Low-Voltage, Low-Glitch CMOS Analog Switches
FEATURES
• Halogen-free according to IEC 61249-2-21
Definition
• 2.7 V thru 12 V single supply or
± 2.7 V thru ± 6 V dual supply
• Low on-resistance - RDS(on): 2 at 12 V
• Fast switching - tON: 22 ns
- tOFF: 28 ns
• TTL and low voltage logic
• Low leakage: 10 pA (typ.)
• > 2000 V ESD protection
BENEFITS
• High accuracy
• High speed, low glitch
• Single and dual supply capability
• Low RON in small TSOP package
• Low leakage
• Low power consumption
APPLICATIONS
• Automatic test equipment
• Data acquisition
• XDSL and DSLAM
• PBX systems
• Reed relay replacement
• Audio and video signal routing
DESCRIPTION
Using BiCMOS wafer fabrication technology allows the
DG9421, DG9422 to operate on single and dual supplies.
Designed for optimal performance at single 5 V and dual
± 5 V, the DG9421, DG9422 combine low and flat
on-resistance (3 ), fast speed (tON = 38 ns) and is well
suited for applications where signal switching accuracy, low
noise and low distortion is critical.
The DG9421 and DG9422 respond to opposite control logic
as shown in the Truth Table.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Logic "0" 0.8 V
Logic "1" 2.4 V
Switches Shown for Logic "0" Input
* Pb containing terminations are not RoHS compliant, exemptions may apply
IN
NC
GND
1
2
3
6
5
Top V i ew
V+
COM
V- 4
TSOP-6
Device Marking:
DG9421DV = 4Exxx
IN
NO
GND
1
2
3
6
5
Top V i ew
V+
COM
V- 4
TSOP-6
Device Marking:
DG9422DV = 4Fxxx
TRUTH TABLE
Logic DG9421 DG9422
0ONOFF
1OFFON
ORDERING INFORMATION
Temp. Range Package Part Number
- 40 °C to 85 °C 6/Pin TSOP
DG9421DV-T1
DG9421DV-T1-E3
DG9422DV-T1
DG9422DV-T1-E3
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Document Number: 70679
S11-1429-Rev. G, 18-Jul-11
Vishay Siliconix
DG9421, DG9422
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 7 mW/°C above 25 °C.
ABSOLUTE MAXIMUM RATINGS
Parameter Limit Unit
V+ to V- - 0.3 to 13 V
GND to V- 7
VINa, VS, VD
- 0.3 to (V+ + 0.3)
or 50 mA, whichever occurs first V/mA
Continuous Current (Any Terminal) 50 mA
Peak Current, S or D (Pulsed at 1 ms, 10 % Duty Cycle) 100
Storage Temperature - 65 to 150 °C
Power Dissipation (Packages)b6-Pin TSOPc570 mW
SPECIFICATIONSa (Single Supply 12 V)
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 12 V, V- = 0 V, VIN = 2.4 V, 0.8 VfTemp.b
Limits
- 40 °C to 85°C
Unit Min.dTyp.cMax.d
Analog Switch
Analog Signal RangeaVANALOG Full 0 12 V
Drain-Source
On-Resistance RDS(on) V+ = 10.8 V, V- = 0 V, IS = 5 mA, VD = 2/9 V Room
Full 23
3.4
Switch Off
Leakage Current
IS(off)
VD = 1/11 V, VS = 11/1 V
Room
Full
- 1
- 10
1
10
nA
ID(off) Room
Full
- 1
- 10
1
10
Channel-On
Leakage Current ID(on) VS = VD = 11/1 V Room
Full
- 1
- 10
1
10
Digital Control
Input Current, VIN Low IIL VIN Under Test = 0.8 V Full - 1 0.02 1 µA
Input Current, VIN High IIH VIN Under Test = 2.4 V Full - 1 0.02 1
Dynamic Characteristics
Tur n - O n T i m eetON RL = 300 , CL = 35 pF, VS = 5 V
see figure 2
Room
Full
20 45
49 ns
Turn-Off TimeetOFF Room
Full
25 47
59
Charge InjectioneQVg = 0 V, Rg = 0 , CL = 1 nF Room 43 pC
Off-IsolationeOIRR RL = 50 , CL = 5 pF , f = 1 MHz Room - 60 dB
Source Off CapacitanceeCS(off)
f = 1 MHz
Room 31
pFDrain Off CapacitanceeCD(off) Room 30
Channel On CapacitanceeCD(on) Room 71
Power Supplies
Positive Supply Current I+
VIN = 0 V or 12 V
Room
Full
0.02 1
5
µANegative Supply Current I- Room
Full
- 1
- 5
- 0.002
Ground Current IGND Room
Full
- 1
- 5
- 0.002
Document Number: 70679
S11-1429-Rev. G, 18-Jul-11
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Vishay Siliconix
DG9421, DG9422
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SPECIFICATIONSa (Dual Supply ± 5 V)
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 5 V, V- = - 5 V, VIN = 2.4 V, 0.8 VfTemp.b
Limits
- 40 °C to 85 °C
Unit Min.dTyp.cMax.d
Analog Switch
Analog Signal RangeeVANALOG Full - 5 5 V
Drain-Source
On-Resistance RDS(on) V+ = 5 V, V- = - 5 V
IS = 5 mA, VD = ± 3.5 V
Room
Full
2.2 3.2
3.6
Switch Off
Leakage Currentg
IS(off) V+ = 5.5 V, V- = - 5.5 V
VD = ± 4.5 V, VS = -/+ 4.5 V
Room
Full
- 1
- 10
1
10
nA
ID(off) Room
Full
- 1
- 10
1
10
Channel-On
Leakage CurrentgID(on) V+ = 5.5 V, V- = - 5.5 V
VS = VD = ± 4.5 V
Room
Full
- 1
- 10
1
10
Digital Control
Input Current, VIN LoweIIL VIN Under Test = 0.8 V Full - 1 0.02 1 µA
Input Current, VIN HigheIIH VIN Under Test = 2.4 V Full - 1 0.02 1
Dynamic Characteristics
Tu r n - O n T i m e tON RL = 300 , CL = 35 pF, VS = ± 3.5 V
see figure 2
Room
Full
38 63
68 ns
Turn-Off Time tOFF Room
Full
45 83
97
Charge InjectioneQVg = 0 V, Rg = 0 , CL = 1 nF Room 207 pC
Off-IsolationeOIRR RL = 50 , CL = 5 pF , f = 1 MHz Room - 57 dB
Source Off CapacitanceeCS(off)
f = 1 MHz
Room 32
pFDrain Off CapacitanceeCD(off) Room 31
Channel On CapacitanceeCD(on) Room 71
Power Supplies
Positive Supply CurrenteI+
VIN = 0 V or 5 V
Room
Full
0.03 1
5
µANegative Supply CurrenteI- Room
Full
- 1
- 5
- 0.002
Ground CurrenteIGND Room
Full
- 1
- 5
- 0.002
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Document Number: 70679
S11-1429-Rev. G, 18-Jul-11
Vishay Siliconix
DG9421, DG9422
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SPECIFICATIONSa (Single Supply 5 V)
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 5 V, V- = 0 V, VIN = 2.4 V, 0.8 VfTemp.b
Limits
- 40 °C to 85 °C
Unit Min.dTyp.cMax.d
Analog Switch
Analog Signal RangeeVANALOG Full 0 5 V
Drain-Source
On-Resistance RDS(on)
V+ = 4.5 V, IS = 5 mA,
VD = 1 V, 3.5 V
Room
Full
3.6 6.0
6.6
Dynamic Characteristics
Tur n - O n T i m eetON RL = 300 , CL = 35 pF, VS = 3.5 V,
see figure 2
Room
Hot
43 67
74 ns
Turn-Off TimeetOFF Room
Hot
30 67
80
Charge InjectioneQVg = 0 V, Rg = 0 , CL = 1 nF Room 25 pC
Power Supplies
Positive Supply CurrenteI+
VIN = 0 V or 5 V
Room
Hot
0.02 1
5
µA
Negative Supply CurrenteI- Room
Hot
- 1
- 5
- 0.002
Ground CurrenteIGND Room
Hot
- 1
- 5
- 0.002
Document Number: 70679
S11-1429-Rev. G, 18-Jul-11
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5
Vishay Siliconix
DG9421, DG9422
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. Leakage parameters are guaranteed by worst case test conditions and not subject to test.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONSa (Single Supply 3 V)
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 3 V, V- = 0 V, VIN = 0.4 VfTempb
Limits
- 40 °C to 85 °C
Unit Min.dTyp.cMax.d
Analog Switch
Analog Signal RangeeVANALOG Full 0 3 V
Drain-Source
On-Resistance RDS(on) V+ = 2.7 V, V- = 0 V
IS = 5 mA, VD = 0.5, 2.2 V
Room
Full
7.3 8.8
10.1
Switch Off
Leakage Currentg
IS(off) V+ = 3.3 V, V- = 0 V
VS = 1, 2 V, VD = 2, 1 V
Room
Full
- 1
- 10
1
10
nA
ID(off) Room
Full
- 1
- 10
1
10
Channel-On
Leakage CurrentgID(on) V+ = 3.3 V, V- = 0 V
VD = VS = 1, 2 V
Room
Full
- 1
- 10
1
10
Digital Control
Input Current, VIN LoweIIL VIN Under Test = 0.4 V Full - 1 0.02 1
µA
Input Current, VIN HigheIIH VIN Under Test = 2.4 V Full - 1 0.02 1
Dynamic Characteristics
Tu r n - O n T i m e tON RL = 300 , CL = 35 pF, VS = 1.5 V
see figure 2
Room
Full
90 110
125 ns
Turn-Off Time tOFF Room
Full
32 84
99
Charge InjectioneQVg = 0 V, Rg = 0 , CL = 1 nF Room 31 pC
Off-IsolationeOIRR RL = 50 , CL = 5 pF , f = 1 MHz Room - 60 dB
Source Off CapacitanceeCS(off)
f = 1 MHz
Room 35
pF
Drain Off CapacitanceeCD(off) Room 34
Channel On CapacitanceeCD(on) Room 77
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Document Number: 70679
S11-1429-Rev. G, 18-Jul-11
Vishay Siliconix
DG9421, DG9422
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
RON vs. VCOM and Supply Voltage
RON vs. Analog Voltage and Temperature
Supply Current vs. Input Switching Frequency
0
2
4
6
8
10
02468 1 0
VCOM - Analog Voltage (V)
- On-Resistance (Ω)RON
V+ = 12 V
V+ = 10.8 V
V+ = 5.0 V
V+ = 3.0 V
T = 25 °C
I
S
= 5 mA
12
Drain Voltage (V)
A
B
C
0
2
4
6
8
- 5 - 3 - 1 1 3 5
V± = ± 5 V
I
S
= 5 mA
- On-Resistance (Ω)RON
A = 85 °C
B = 25 °C
C = - 40 °C
Input Switching Frequences (Hz)
10 m
1 m
100 µ
10 µ
1 µ
100 n
10 n
10 100 1K 10K 100K 1M 10M
I+ - Supply Current (A)
RON vs. Analog Voltage and Temperature
Supply Current vs. Temperature
Leakage Current vs. Temperature
V
COM
- Analog Voltage (V)
- On-Resistance (Ω)R
ON
A
B
C
A
B
C
0
2
4
6
8
10
I
S
= 5 mA
V+ = 3.0 V
V+ = 5.0 V
A = 85 °C
B = 25 °C
C = - 40 °C
012345
Temperature (°C)
I+ - Supply Current (pA)
- 60 - 40 - 20 0 20 40 60 80 100
1000
100
10
V+ = ± 5 V
V
IN
= 0 V
- 60 - 40 - 20 0 20 40 60 80 100
100
10
1
V+ = 5 V
V- = 0 V
Leakage Current (pA)
I
( on)
Temperature (°C)
I
(o f f )
Document Number: 70679
S11-1429-Rev. G, 18-Jul-11
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Vishay Siliconix
DG9421, DG9422
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Leakage Current vs. Temperature
Leakage vs. Analog Voltage
Insertion Loss, Off Isolation vs. Frequency
- 60 - 40 - 20 0 20 40 60 80 100
100
10
0.1
V+ = ± 5 V
Leakage Current (pA)
I
( on)
Temperature (°C)
1
I
(o f f )
- 400
- 300
- 200
- 100
0
100
200
300
400
024681012
V
COM
, V
NO
, V
NC
- Analog Voltage (V)
I
NO(off)
/I
NC(off)
I
COM(on)
Leakage Current (pA)
V+ = 12 V
V- = 0 V
I
COM(off)
100K
- 90
1M
- 30
10
- 70
- 50
100M
Frequency (MHz)
- 80
Loss, OIRR (dB)
OIRR
Loss
10M
- 10
0
- 60
- 40
- 20
V+ = 3 V
R
L
= 50 Ω
1G
Leakage vs. Analog Voltage
Switching Time vs. Temperature and
Supply Voltage (DG9421)
Switching Threshold vs. Supply Voltage
- 100
- 60
- 20
20
60
100
VCOM, VNO, VNC - Analog Voltage (V)
I
NO ( o f f )
/I
NC( of f)
I
CO M( on)
Leakage Current (pA)
V+ = 5 V
V- = 0 V
I
CO M ( of f)
01 5234
0.0
0.5
1.0
1.5
2.0
2.5
02 46 8 1 0 1 2
V+ - Supply Voltage (V)
- Switching Threshold (V)VT
14
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Document Number: 70679
S11-1429-Rev. G, 18-Jul-11
Vishay Siliconix
DG9421, DG9422
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
SCHEMATIC DIAGRAM (Typical Channel)
TEST CIRCUITS
Charge Injection vs. Analog Voltage
VCOM - Analog Voltage (V)
Q - Charge Injection (pC)
- 300
- 250
- 200
- 150
- 100
- 50
0
50
100
150
200
250
300
02 4 6 810
12
V+ = 12 V
V+ = 5 V
V+ = 3 V
Charge Injection vs. Analog Voltage
VCOM - Analog Voltage (V)
Q - Charge Injection (pC)
- 300
- 250
- 200
- 150
- 100
- 50
0
50
100
150
200
250
300
- 6 - 4 - 2 0 2 4 6
V = ± 5 V
Figure 1.
Level
Shift/
Drive
VIN
NC/NO
V+
GND
V-
COM
V-
V+
Figure 2. Switching Time
0 V
Logic
Input
Switch
Input*
Switch
Output
50 %
0 V
Switch
Input*
V
S
t
r
< 5 ns
t
f
< 5 ns
90 %
- V
S
t
OFF
t
ON
V
O
90 %
V
O
Note: * Logic input waveform is inverted for switches that
have the opposite logic sense control
C
L
(includes fixture and stray capacitance)
V+
IN
RL
RL + rDS(on)
V
O
= V
S
S D
V-
V
O
GND
C
L
35 pF
V-
R
L
300 Ω
V+
V
S
V
NC/NO
Document Number: 70679
S11-1429-Rev. G, 18-Jul-11
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9
Vishay Siliconix
DG9421, DG9422
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TEST CIRCUITS
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70679.
Figure 3. Charge Injection
CL
10 nF
D
Rg
VO
V+
S
V-
3 V
IN
Vg
GND
OFFONOFF
OFFONOFF
VO
ΔVO
INX
INX
Q = ΔVO x CL
INX dependent on switch configuration Input polarity determined
by sense of switch.
V-
V+
Figure 4. Crosstalk
, 2.4 V
S
1
X
TALK Isolation = 20 log
V
S
V
O
D
2
C = RF bypass
R
L
D
1
S
2
V
S
0 V , 2.4 V
IN
1 50 Ω
V
O
IN
2
R
g
= 50 Ω
V+
GND V-
NC
C
C
V+
V-
0 V
Figure 5. Off Isolation
RL
50 Ω
D
0 V, 2.4 V
V+
Rg = 50 Ω
GND V- C
VS
Off Isolation = 20 log
VS
VO
IN
VO
S
C
C = RF Bypass
V-
V+
Figure 6. Source/Drain Capacitances
D
IN
S
V+
GND V- C
0 V, 2.4 V
Meter
HP4192A
Impedance
Analyzer
or Equivalent
C
V+
V-
Vishay Siliconix
Package Information
Document Number: 71200
18-Dec-06
www.vishay.com
1
1 2 3
Gauge Plane
L
5 4
R
R
C 0.15 M B A
b
C 0.08
0.17 Ref
Seating Plane
-C-
Seating Plane
A
1
A
2 A
-A-
D
-B-
E
1 E
L
2
(L
1
)
c
4x 1
4x 1
e
e1
1 2 3
6 5 4
C 0.15 M B A
b
-B-
E
1 E
e
e1
5-LEAD TSOP 6-LEAD TSOP
TSOP: 5/6−LEAD
JEDEC Part Number: MO-193C
MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A 0.91 - 1.10 0.036 - 0.043
A
1 0.01 - 0.10 0.0004 - 0.004
A
2 0.90 - 1.00 0.035 0.038 0.039
b 0.30 0.32 0.45 0.012 0.013 0.018
c 0.10 0.15 0.20 0.004 0.006 0.008
D 2.95 3.05 3.10 0.116 0.120 0.122
E 2.70 2.85 2.98 0.106 0.112 0.117
E
1 1.55 1.65 1.70 0.061 0.065 0.067
e 0.95 BSC 0.0374 BSC
e
1 1.80 1.90 2.00 0.071 0.075 0.079
L 0.32 - 0.50 0.012 - 0.020
L
1 0.60 Ref 0.024 Ref
L
2 0.25 BSC 0.010 BSC
R 0.10 - - 0.004 - -
0 4 8 0 4 8
1 7 Nom 7 Nom
ECN: C-06593-Rev. I, 18-Dec-06
DWG: 5540
AN823
Vishay Siliconix
Document Number: 71743
27-Feb-04
www.vishay.com
1
Mounting LITTLE FOOTR TSOP-6 Power MOSFETs
Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages. Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFETs. Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What has remained the same is the footprint of the
packages.
The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package. For the TSOP-6 package
outline drawing see http://www.vishay.com/doc?71200 and see
http://www.vishay.com/doc?72610 for the minimum pad footprint.
In converting the footprint to the pad set for a power MOSFET, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.
In the case of the TSOP-6 package, the electrical connections are
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together. For a small signal device or integrated
circuit, typical connections would be made with traces that are
0.020 inches wide. Since the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate. The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance. Also, heat
spreads in a circular fashion from the heat source. In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.
Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package. This pattern shows the starting point for
utilizing the board area available for the heat spreading copper. To
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions. This pattern uses all the available area
underneath the body for this purpose.
FIGURE 1. Recommended Copper Spreading Footprint
0.049
1.25
0.010
0.25
0.014
0.35
0.074
1.875 0.122
3.1
0.026
0.65
0.167
4.25
0.049
1.25
Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components, “thermal” connections from the planar copper to the
pads have not been used. Even if additional planar copper area is
used, there should be no problems in the soldering process. The
actual solder connections are defined by the solder mask
openings. By combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAST, or pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.
Ramp-Up Rate +6_C/Second Maximum
Temperature @ 155 " 15_C120 Seconds Maximum
Temperature Above 180_C70 − 180 Seconds
Maximum Temperature 240 +5/−0_C
Time at Maximum Temperature 20 − 40 Seconds
Ramp-Down Rate +6_C/Second Maximum
FIGURE 2. Solder Reflow Temperature Profile
AN823
Vishay Siliconix
www.vishay.com
2Document Number: 71743
27-Feb-04
255 − 260_C
1X4_C/s (max) 3-6_C/s (max)
10 s (max)
Reflow Zone
Pre-Heating Zone
3_C/s (max)
140 − 170_C
Maximum peak temperature at 240_C is allowed.
FIGURE 3. Solder Reflow Temperature and Time Durations
60-120 s (min)
217_C
60 s (max)
THERMAL PERFORMANCE
A basic measure of a device’s thermal performance is the
junction-to-case thermal resistance, Rqjc, or the
junction-to-foot thermal resistance, Rqjf. This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which the
device is mounted. Table 1 shows the thermal performance
of the TSOP-6.
TABLE 1.
Equivalent Steady State Performance—TSOP-6
Thermal Resistance Rqjf 30_C/W
SYSTEM AND ELECTRICAL IMPACT OF
TSOP-6
In any design, one must take into account the change in
MOSFET rDS(on) with temperature (Figure 4).
0.6
0.8
1.0
1.2
1.4
1.6
−50 −25 0 25 50 75 100 125 150
VGS = 4.5 V
ID = 6.1 A
On-Resistance vs. Junction Temperature
TJ − Junction Temperature (_C)
FIGURE 4. Si3434DV
rDS(on) − On-Resiistance
(Normalized)
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72610
26 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR TSOP-6
0.119
(3.023)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.099
(2.510)
0.064
(1.626)
0.028
(0.699)
0.039
(1.001)
0.020
(0.508)
0.019
(0.493)
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