DATASHEET - FINAL DA14580 Low Power Bluetooth Smart SoC General description 84 kB ROM 8 kB Retention SRAM Power management Integrated Buck/Boost DC-DC converter P0, P1, P2 and P3 ports with 3.3 V tolerance Easy decoupling of only 4 supply pins Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V) battery cells 10-bit ADC for battery voltage measurement Digital controlled oscillators 16 MHz crystal (20 ppm max) and RC oscillator 32 kHz crystal (50 ppm, 500 ppm max) and RCX oscillator General purpose, Capture and Sleep timers Digital interfaces General purpose I/Os: 14 (WLCSP34 package), 24 (QFN40 package), 32 (QFN48 package) 2 UARTs with hardware flow control up to 1 MBd SPI+TM interface I2C bus at 100 kHz, 400 kHz 3-axes capable Quadrature Decoder Analog interfaces 4-channel 10-bit ADC Radio transceiver Fully integrated 2.4 GHz CMOS transceiver Single wire antenna: no RF matching or RX/TX switching required Supply current at VBAT3V: TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC) 0 dBm transmit output power -20 dBm output power in "Near Field Mode" -93 dBm receiver sensitivity Packages: WLCSP 34 pins, 2.436 mm x 2.436 mm QFN 40 pins, 5 mm x 5 mm QFN 48 pins, 6 mm x 6 mm KGD (wafer, dice) The DA14580 integrated circuit has a fully integrated radio transceiver and baseband processor for Bluetooth(R) Smart. It can be used as a standalone application processor or as a data pump in hosted systems. The DA14580 supports a flexible memory architecture for storing Bluetooth profiles and custom application code, which can be updated over the air (OTA). The qualified Bluetooth Smart protocol stack is stored in a dedicated ROM. All software runs on the ARM(R) Cortex(R)-M0 processor via a simple scheduler. The Bluetooth Smart firmware includes the L2CAP service layer protocols, Security Manager (SM), Attribute Protocol (ATT), the Generic Attribute Profile (GATT) and the Generic Access Profile (GAP). All profiles published by the Bluetooth SIG as well as custom profiles are supported. The transceiver interfaces directly to the antenna and is fully compliant with the Bluetooth 4.1 standard. The DA14580 has dedicated hardware for the Link Layer implementation of Bluetooth Smart and interface controllers for enhanced connectivity capabilities. Features System diagram 1 www.dialog-semiconductor.com Low Power Bluetooth Smart SoC Complies with Bluetooth V4.1, ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US) and ARIB STD-T66 (Japan) Processing power 16 MHz 32 bit ARM Cortex-M0 with SWD inter face Dedicated Link Layer Processor AES-128 bit encryption Processor Memories 32 kB One-Time-Programmable (OTP) memory 42 kB System SRAM ________________________________________________________________________________________________ (c) 2014 Dialog Semiconductor DA14580 JANUARY 29, 2015 V3.1 DA14580 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 ARM CORTEXM0 CPU . . . . . . . . . . . . . . . . . . 9 3.2 BLUETOOTH SMART . . . . . . . . . . . . . . . . . . . . 9 3.2.1 BLE Core . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.2 Radio Transceiver . . . . . . . . . . . . . . . . . 10 3.2.3 SmartSnippets 3.3 MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . 11 3.5 POWER MODES. . . . . . . . . . . . . . . . . . . . . . . 12 3.6 INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6.1 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6.2 SPI+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6.3 I2C interface . . . . . . . . . . . . . . . . . . . . . 12 3.6.4 General purpose ADC . . . . . . . . . . . . . . 13 3.6.5 Quadrature decoder. . . . . . . . . . . . . . . . 13 3.6.6 Keyboard controller . . . . . . . . . . . . . . . . 13 3.6.7 Input/output ports . . . . . . . . . . . . . . . . . . 13 3.7 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7.1 General purpose timers . . . . . . . . . . . . . 13 3.7.2 Wake-Up timer . . . . . . . . . . . . . . . . . . . . 14 3.7.3 Watchdog timer . . . . . . . . . . . . . . . . . . . 14 3.8 CLOCK/RESET . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.9 POWER MANAGEMENT . . . . . . . . . . . . . . . . 15 4. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6. Package information . . . . . . . . . . . . . . . . . . . . . . 154 Low Power Bluetooth Smart SoC 6.1 MOISTURE SENSITIVITY LEVEL (MSL) . . . 154 6.2 WLCSP HANDLING . . . . . . . . . . . . . . . . . . . 154 6.3 SOLDERING INFORMATION . . . . . . . . . . . . 154 6.4 PACKAGE OUTLINES . . . . . . . . . . . . . . . . . 155 (c) 2014 Dialog Semiconductor 2 Final - January 29, 2015 v3.1 (c) 2014 Dialog Semiconductor 1. Block diagram 24 April 2012 ARM Cortex M0 XTAL 32.768 kHz DCDC (BUCK/BOOST) XTAL 16 MHz LDO SYS CORE LDO RET RC 16 MHz LDO LDO LDO SYS SYS RF RC 32 kHz RCX POReset BLE Core SWD (JTAG) AES-128 System/ Exchange RAM 42 KB Radio Transceiver LINK LAYER HARDWARE ROM 84 KB Timer 2 3xPWM QUAD DECODER GP ADC I2C FIFO SPI UART2 FIFO UART GPIO MULTIPLEXING Figure 1 DA14580 block diagram DA14580 Low Power Bluetooth Smart SoC Final - January 29, 2015 v3.1 OTPC Timer 0 1xPWM FIFO DMA KEYBOARD CTRL OTP 32 KB SW TIMER WAKE UP TIMER Ret. RAM4 1 KB POWER/CLOCK Management (PMU) Ret. RAM3 2 KB APB bridge Ret. RAM2 3 KB Memory Controller 3 Ret. RAM 2 KB Pinout 2. A Quad Flat Package No Leads (QFN) with 48 pins The DA14580 comes in three packages: 3. A Quad Flat Package No Leads (QFN) with 40 pins 1. A Wafer Level Chip Scale Package (WLCSP) with 34 balls The actual pin/ball assignment is depicted in the following figures: 6 P0 _0 3 P0 _5 P0 _ V P0 _6 XT AL 32 Kp XT AL 32 Km VB AT _R F P0 _7 G P0 _ 4 N D P0 _ 2 G N D P0 _1 R G N VP P D FI O p O FI R ND D N G RS T VB AT 3 G N D CD C VD C 5 G P1 _ P1 _1 0 P1 _ VB AT 1V F H SW D E 4 m 3 2 LK D SW IT C SW _C B IO A 2 XT XT AL AL 16 16 M M m p VD C P1 D C_ _3 R F 1 DA14580 2. RFIOm P3_7 P2_6 P2_5 VDCDC_RF 41 40 39 38 37 P2_7 44 NC P2_8 45 RFIOp VPP 46 42 P2_9 47 43 P2_0 48 Figure 2 WLCSP34 ball assignment XTAL16Mp P0_3 4 33 P1_3 P3_0 5 P0_4 6 P0_5 7 P2_1 8 29 P1_1 P0_6 9 28 VBAT1V P3_1 10 27 P1_0 P0_7 11 26 SWITCH 12 25 P3_5 18 19 20 21 22 23 24 VBAT3V GND RST P2_3 VDCDC P2_4 SWDIO P3_4 (Top View) 17 SW_CLK 30 16 P1_2 31 P2_2 Pin 0: GND plane 32 DA14580 VBAT_RF P3_2 15 34 P3_3 3 14 XTAL16Mm P0_2 XTAL32Kp P3_6 35 13 36 2 XTAL32Km 1 P0_1 Low Power Bluetooth Smart SoC P0_0 Figure 3 QFN48 pin assignment (c) 2014 Dialog Semiconductor 4 Final - January 29, 2015 v3.1 P2_7 RFIOm P2_6 P2_5 VDCDC_RF 34 33 32 31 P2_8 RFIOp VPP 37 35 P2_9 39 38 36 P2_0 40 DA14580 P0_0 1 30 P0_1 2 29 XTAL16Mp P0_2 3 28 P1_3 P0_3 4 NC 5 P0_4 6 P0_5 7 24 P1_1 P2_1 8 23 VBAT1V P0_6 9 22 P1_0 P0_7 10 21 SWITCH 18 19 20 VDCDC P2_4 16 GND 17 15 VBAT3V RST 14 VBAT_RF P2_3 13 SWDIO P2_2 (Top View) 12 SW_CLK 25 11 P1_2 26 XTAL32Kp 27 DA14580 XTAL32Km Pin 0: GND plane XTAL16Mm Figure 4 QFN40 pin assignment Table 1: Ordering information (samples) Part number Package Size (mm) Shipment form Pack quantity DA14580-01UNA WLSCP34 2.436 x 2.436 Mini-reel 50/100/1000 DA14580-01A31 QFN48 6x6 Tray 50 DA14580-01AT1 QFN40 5x5 Tray 50 Table 2: Ordering information (production) Package Size (mm) Shipment form Pack quantity DA14580-01UNA WLSCP34 2.436 x 2.436 Mini-reel 5000 DA14580-01A32 QFN48 6x6 Reel 4000 DA14580-01AT2 QFN40 5x5 Reel 5000 DA14580-01WO4 KGD wafer Contact Dialog Semiconductor sales office DA14580-01WC4 KGD dice Contact Dialog Semiconductor sales office (c) 2014 Dialog Semiconductor 5 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Part number DA14580 Table 3: Pin Description PIN NAME TYPE Drive (mA) Reset state (Note ) DESCRIPTION General Purpose I/Os DIO DIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. P1_0 P1_1 P1_2 P1_3 P1_4/SWCLK P1_5/SW_DIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PU INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. This signal is the JTAG clock by default This signal is the JTAG data I/O by default P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 P2_8 P2_9 DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. NOTE: This port is only available on the QFN40/QFN48 packages. P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 DIO DIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contain state retention mechanism during power down. NOTE: This port is only available on the QFN48 package. SWDIO/P1_5 DIO 4.8 I-PU INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and control communication. Can also be used as a GPIO SW_CLK/ P1_4 DIO 4.8 I-PD INPUT JTAG clock signal. Can also be used as a GPIO Debug interface Clocks XTAL16Mp AI INPUT. Crystal input for the 16 MHz XTAL XTAL16Mm AO OUTPUT. Crystal output for the 16 MHz XTAL XTAL32kp AI INPUT. Crystal input for the 32.768 kHz XTAL XTAL32km AO OUTPUT. Crystal output for the 32.768 kHz XTAL Quadrature decoder QD_CHA_X DI INPUT. Channel A for the X axis. Mapped on Px ports QD_CHB_X DI INPUT. Channel B for the X axis. Mapped on Px ports QD_CHA_Y DI INPUT. Channel A for the Y axis. Mapped on Px ports QD_CHB_Y DI INPUT. Channel B for the Y axis. Mapped on Px ports (c) 2014 Dialog Semiconductor 6 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 DA14580 Table 3: Pin Description Drive (mA) Reset state (Note ) PIN NAME TYPE DESCRIPTION QD_CHA_Z DI INPUT. Channel A for the Z axis. Mapped on Px ports QD_CHB_Z DI INPUT. Channel B for the Z axis. Mapped on Px ports SPI_CLK DO INPUT/OUTPUT. SPI Clock. Mapped on Px ports SPI_DI DI INPUT. SPI Data input. Mapped on Px ports SPI_DO DO OUTPUT. SPI Data output. Mapped on Px ports SPI_EN DI INPUT. SPI Clock enable (active LOW). Mapped on Px ports SPI bus interface I2C bus interface SDA DIO/DIOD INPUT/OUTPUT. I2C bus Data with open drain port. Mapped on Px ports SCL DIO/DIOD INPUT/OUTPUT. I2C bus Clock with open drain port. In open drain mode, SCL is monitored to support bit stretching by a slave. Mapped on Px ports. UART interface UTX DO OUTPUT. UART transmit data. Mapped on Px ports URX DI INPUT. UART receive data. Mapped on Px ports URTS DO OUTPUT. UART Request to Send. Mapped on Px ports UCTS DI INPUT. UART Clear to Send. Mapped on Px ports UTX2 DO OUTPUT. UART 2 transmit data. Mapped on Px ports URX2 DI INPUT. UART 2 receive data. Mapped on Px ports URTS2 DO OUTPUT. UART 2 Request to Send. Mapped on Px ports UCTS2 DI INPUT. UART 2 Clear to Send. Mapped on Px ports ADC[0] AI INPUT. Analog to Digital Converter input 0. Mapped on P0[0] ADC[1] AI INPUT. Analog to Digital Converter input 1. Mapped on P0[1] ADC[2] AI INPUT. Analog to Digital Converter input 2. Mapped on P0[2] ADC[3] AI INPUT. Analog to Digital Converter input 3. Mapped on P0[3] Analog interface Radio transceiver AIO RF input/output. Impedance 50 RFIOm AIO RF ground Miscellaneous RST DI INPUT. Reset signal (active high). Must be connected to GND if not used. VBAT_RF AIO Connect to VBAT3V on the PCB VDCDC_RF AIO Connect to VDCDC on the PCB VPP AI INPUT. This pin is used while OTP programming and testing. OTP programming: VPP = 6.8 V 0.25 V OTP Normal operation: leave VPP floating Power supply VBAT3V AIO (c) 2014 Dialog Semiconductor INPUT/OUTPUT. Battery connection. Used for a single coin battery (3 V). If an alkaline or a NiMH battery (1.5 V) is attached to pin VBAT1V, this is the second output of the DC-DC converter. 7 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC RFIOp DA14580 Table 3: Pin Description PIN NAME TYPE Drive (mA) Reset state (Note ) DESCRIPTION VBAT1V AI INPUT. Battery connection. Used for an alkaline or a NiMh battery (1.5 V). If a single coin battery (3 V) is attached to pin VBAT3V,this pin must be connected to GND. SWITCH AIO INPUT/OUTPUT. Connection for the external DC-DC converter inductor. VDCDC AO GND AIO Output of the DC-DC converter - - Ground Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 8 Final - January 29, 2015 v3.1 System overview the architecture, which the OS can use as a tick timer or as a general timer in other applications without an OS. The DA14580 contains the following internal blocks: 3.1 ARM CORTEXM0 CPU * SuperVisor Call (SVC) instruction with a dedicated SVC exception and PendSV (Pendable SuperVisor service) to support various operations in an embedded OS. The Cortex-M0 processor is a 32-bit Reduced Instruction Set Computing (RISC) processor with a von Neumann architecture (single bus interface). It uses an instruction set called Thumb, which was first supported in the ARM7TDMI processor; however, several newer instructions from the ARMv6 architecture and a few instructions from the Thumb-2 technology are also included. Thumb-2 technology extended the previous Thumb instruction set to allow all operations to be carried out in one CPU state. The instruction set in Thumb-2 includes both 16-bit and 32-bit instructions; most instructions generated by the C compiler use the 16-bit instructions, and the 32-bit instructions are used when the 16-bit version cannot carry out the required operations. This results in high code density and avoids the overhead of switching between two instruction sets. * Architecturally defined sleep modes and instructions to enter sleep. The sleep features allow power consumption to be reduced dramatically. Defining sleep modes as an architectural feature makes porting of software easier because sleep is entered by a specific instruction rather than implementation defined control registers. * Fault handling exception to catch various sources of errors in the system. * Support for 24 interrupts. * Little endian memory support. * Wake up Interrupt Controller (WIC) to allow the processor to be powered down during sleep, while still allowing interrupt sources to wake up the system. In total, the Cortex-M0 processor supports only 56 base instructions, although some instructions can have more than one form. Although the instruction set is small, the Cortex-M0 processor is highly capable because the Thumb instruction set is highly optimized. * Halt mode debug. Allows the processor activity to stop completely so that register values can be accessed and modified. No overhead in code size and stack memory size. Academically, the Cortex-M0 processor is classified as load-store architecture, as it has separate instructions for reading and writing to memory, and instructions for arithmetic or logical operations that use registers. * CoreSight technology. Allows memories and peripherals to be accessed from the debugger without halting the processor. * High performance. Up to 0.9 DMIPS/MHz (Dhrystone 2.1) with fast multiplier. * Four (4) hardware breakpoints and two (2) watch points. * Built-in Nested Vectored Interrupt Controller (NVIC). This makes interrupt configuration and coding of exception handlers easy. When an interrupt request is taken, the corresponding interrupt handler is executed automatically without the need to determine the exception vector in software. * Breakpoint instruction support for an unlimited number of software breakpoints. * Programmer's model similar to the ARM7TDMI processor. Most existing Thumb code for the ARM7TDMI processor can be reused. This also makes it easy for ARM7TDMI users, as there is no need to learn a new instruction set. * Interrupts can have four different programmable priority levels. The NVIC automatically handles nested interrupts. * The design is configured to respond to exceptions (e.g. interrupts) as soon as possible (minimum 16 clock cycles). 3.2 BLUETOOTH SMART * Non maskable interrupt (NMI) input for safety critical systems. The BLE (Bluetooth Low Energy) core is a qualified Bluetooth baseband controller compatible with the Bluetooth Smart specification and it is in charge of packet encoding/decoding and frame scheduling. 3.2.1 BLE Core * Easy to use and C friendly. There are only two modes (Thread mode and Handler mode). The whole application, including exception handlers, can be written in C without any assembler. Features * All device classes support (Broadcaster, Central, Observer, Peripheral) * Built-in System Tick timer for OS support. A 24-bit timer with a dedicated exception type is included in 9 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC * Thumb instruction set. Highly efficient, high code density and able to execute all Thumb instructions from the ARM7TDMI processor. * Supports Serial Wire Debug (SWD) connections. The serial wire debug protocol can handle the same debug features as the JTAG, but it only requires two wires and is already supported by a number of debug solutions from various tools vendors. Features (c) 2014 Dialog Semiconductor DA14580 3. DA14580 * All packet types (Advertising / Data / Control) * Encryption (AES / CCM) * Bit stream processing (CRC, Whitening) * FDMA/TDMA/events formatting and synchronization * Frequency hopping calculation * Operating clock 16 MHz or 8 MHz * Low power modes supporting 32.0 kHz or 32.768 kHz * Supports power down of the baseband during the protocol's idle periods * AHB Slave interface for register file access * AHB Slave interface for Exchange Memory access of CPU via BLE core * AHB Master interface for direct access of BLE core to Exchange Memory space 3.2.2 Radio Transceiver The Radio Transceiver implements the RF part of the Bluetooth Smart protocol. Together with the Bluetooth 4.0 PHY layer, this provides a 93 dB RF link budget for reliable wireless communication. All RF blocks are supplied by on-chip low-drop out-regulators (LDOs). The bias scheme is programmable per block and optimized for minimum power consumption. The Bluetooth LE radio comprises the Receiver, Transmitter, Synthesizer, Rx/Tx combiner block, and Biasing LDOs. Figure 5 SmartSnippets stack Apart from the protocol stack, the Software platform supports a Hardware Abstraction Layer (HAL) which enables easy access to peripheral's features from a programmer's point of view, as presented in the following figure. Features * Single ended RFIO interface, 50 matched * Alignment free operation * -93 dBm receiver sensitivity * 0 dBm transmit output power Low Power Bluetooth Smart SoC * Ultra low power consumption * Fast frequency tuning minimises overhead 3.2.3 SmartSnippets The DA14580 comes complete with Dialog's SmartSnippets Bluetooth Software platform which includes a qualified Bluetooth Smart single-mode stack on chip. Numerous Bluetooth Smart profiles for consumer wellness, sport, fitness, security and proximity applications are supplied as standard, while additional customer profiles can be developed and added as needed. The SmartSnippets software development environment is based on Keil's uVision mature tools and contains example application code for both embedded and hosted modes. (c) 2014 Dialog Semiconductor 10 Final - January 29, 2015 v3.1 DA14580 Application Accelerometer Driver SPI FLASH Driver Sample Drivers Battery Driver CORE Drivers EEPROM I2C Driver GPIO Driver SPI Driver UART Driver ADC Driver Quadrature Timers Figure 6 Hardware abstraction layer 3.4 FUNCTIONAL MODES The DA14580 is optimized for deeply embedded applications such as health monitoring, sports measuring, human interaction devices etc. Customers are able to develop and test their own applications. Upon completion of the development, the application code can be programmed into the OTP. In general, the system has three functional modes of operation: Core drivers are provided for each interface of the DA14580 enabling optimized usage of the hardware's capabilities. These drivers provide an easy-to-use interface towards the hardware engines without having to interfere with the register programming directly. On top of the core drivers, a number of sample drivers is also provided enabling communication with basic Bluetooth Smart application components: accelerometers, FLASH/EEPROM non-volatile memories, etc. A. Development mode: During this phase application code is developed using the ARM Cortex-M0 SW environment. The compiled code is then downloaded into the System RAM or any Retention RAMs by means of SWD (JTAG) or any serial interface (e.g. UART). Address 0x00 is remapped to the physical memory that contains the code and the CPU is configured to reset and execute code from the remapped device. This mode is enabling application development, debugging and on-the-fly testing. 3.3 MEMORIES The following memories are part of the DA14580's internal blocks: ROM. This is a 84 kB ROM containing the Bluetooth Smart protocol stack as well as the boot code sequence. B. Normal mode: After the application is ready and verified, the code can be burned into the OTP. When the system boots/wakes up, the DMA of the OTP controller will automatically copy the program code from the OTP into the system RAM. Next, a SW reset or a jump to the System RAM occurs and code execution is started. Hence, in this mode, the system is autonomous, contains the required SW in OTP and is ready for integration into the final product. System SRAM. This is a 42 kB system SRAM (SysRAM) which is primarily used for mirroring the program code from the OTP when the system wakes/powers up. It also serves as Data RAM for intermediate variables and various data that the protocol requires. Optionally, it can be used as extra memory space for the BLE TX and RX data structures. C. Calibration mode: Between Development and Normal mode, there is an intermediate stage where the chip needs to be calibrated with respect to two important features: Retention RAMs. These are 4 special low leakage SRAM cells (2 kB + 2 kB + 3 kB + 1 kB) used to store various data of the Bluetooth Smart protocol as well as the system's global variables and processor stack when the system goes into Deep Sleep mode. Storage of this data ensures secure and quick configuration of the BLE Core after the system wakes up. Every cell can be powered on or off according to the application needs for retention area when in Deep Sleep mode. (c) 2014 Dialog Semiconductor * Programming of the Bluetooth device address * Programming of the trimming value for the external 16 MHz crystal. This mode of operation applies to the final product and is performed by the customer. During this phase, cer11 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC OTP. This is a 32 kB One-Time Programmable memory array, used to store the application code as well as Bluetooth Smart profiles. It also contains the system configuration and calibration data. by the following: baud rate = (serial clock frequency)/ (divisor). 3.5 POWER MODES There are four different power modes in the DA14580: 3.6.2 SPI+ * Active mode: System is active and operates at full speed. This interface supports a subset of the Serial Peripheral Interface (SPITM). The serial interface can transmit and receive 8, 16 or 32 bits in master/slave mode and transmit 9 bits in master mode. The SPI+ interface has enhanced functionality with bidirectional 2x16-bit word FIFOs. * Sleep mode: No power gating has been programmed, the ARM CPU is idle, waiting for an interrupt. PD_SYS is on. PD_PER and PED_RAD depending on the programmed enabled value. * Extended Sleep mode: All power domains are off except for the PD_AON, the programmed PD_RRx and the PD_SR. Since the SysRAM retains its data, no OTP mirroring is required upon waking up the system. SPI is a trademark of Motorola, Inc. * Deep Sleep mode: All power domains are off except for the PD_AON and the programmed PD_RRx. This mode dissipates the minimum leakage power. However, since the SysRAM has not retained its data, an OTP mirror action is required upon waking up the system. * Clock speeds upto 16 MHz for the SPI controller. Programmable output frequencies of SPI source clock divided by 1, 2, 4, 8 3.6 INTERFACES * Programmable SPI_DO idle level Features * Slave and Master mode * 8 bit, 9 bit, 16 bit or 32 bit operation * SPI clock line speed up to 8 MHz * SPI mode 0, 1, 2, 3 support (clock edge and phase) * Maskable Interrupt generation 3.6.1 UARTs * Bus load reduction by unidirectional writes-only and reads-only modes. The UART is compliant to the industry-standard 16550 and is used for serial communication with a peripheral, modem (data carrier equipment, DCE) or data set. Data is written from a master (CPU) over the APB bus to the UART and it is converted to serial form and transmitted to the destination device. Serial data is also received by the UART and stored for the master (CPU) to read back. Built-in RX/TX FIFOs for continuous SPI bursts. 3.6.3 I2C interface The I2C interface is a programmable control bus that provides support for the communications link between Integrated Circuits in a system. It is a simple two-wire bus with a software-defined protocol for system control, which is used in temperature sensors and voltage level translators to EEPROMs, general-purpose I/O, A/D and D/A converters. There is no DMA support on the UART block since its contains internal FIFOs. Both UARTs support hardware flow control signals (RTS, CTS, DTR, DSR). Features Features * Hardware flow control support (CTS/RTS) * Two-wire I2C serial interface consists of a serial data line (SDA) and a serial clock (SCL) * Shadow registers to reduce software overhead and also include a software programmable reset * Two speeds are supported: * Transmitter Holding Register Empty (THRE) interrupt mode * Fast mode (<= 400 kbit/s) * Standard mode (0 to 100 kbit/s) * IrDA 1.0 SIR mode supporting low power mode. * Clock synchronization * Functionality based on the 16550 industry standard: * 32 deep transmit/receive FIFOs * Programmable character properties, such as number of data bits per character (5-8), optional * Master transmit, Master receive operation * parity bit (with odd or even select) and number of stop bits (1, 1.5 or 2) * 7 or 10-bit combined format transfers * 7 or 10-bit addressing * Bulk transmit mode * Line break generation and detection * Default slave address of 0x055 * Prioritized interrupt identification * Interrupt or polled-mode operation * Programmable serial data baud rate as calculated 12 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC * 16 bytes Transmit and receive FIFOs (c) 2014 Dialog Semiconductor DA14580 tain fields in the OTP should be programmed * Programmable SDA hold time 3.6.6 Keyboard controller The Keyboard controller can be used for debouncing the incoming GPIO signals when implementing a keyboard scanning engine. It generates an interrupt to the CPU (KEYBR_IRQ). 3.6.4 General purpose ADC The DA14580 is equipped with a high-speed ultra low power 10-bit general purpose Analog-to-Digital Converter (GPADC). It can operate in unipolar (single ended) mode as well as in bipolar (differential) mode. The ADC has its own voltage regulator (LDO) of 1.2 V, which represents the full scale reference voltage. DA14580 * Handles Bit and Byte waiting at both bus speeds In parallel, five extra interrupt lines can be triggered by a state change on 32 selectable GPIOs (GPIOx_IRQ). Features * Monitors any of the 32 available GPIOs (12 in the WLCSP package, 22 in the QFN40 and 32 in the QFN48) Features * 10-bit dynamic ADC with 65 ns conversion time * Generates a keyboard interrupt on key press or key release * Maximum sampling rate 3.3 Msample/s * Ultra low power (5 A typical supply current at 100 ksample/s) * Implements debouncing time from 0 upto 63 ms * Supports five separate interrupt generation lines from GPIO toggling * Single-ended as well as differential input with two input scales * Four single-ended or two differential external input channels 3.6.7 Input/output ports * Battery monitoring function The DA14580 has software-configurable I/O pin assignment, organized into ports Port 0, Port1, Port2 and Port 3. Port 2 is only available at the QFN40 package while ports 2 and 3 are available at the QFN48 package. * Chopper function * Offset and zero scale adjust * Common-mode input level adjust Features * Port 0: 8 pins, Port 1: 6 pins (including SW_CLK and SWDIO), Port 2: 10 pins, Port 3: 8 pins 3.6.5 Quadrature decoder This block decodes the pulse trains from a rotary encoder to provide the step and the direction of the movement of an external device. Three axes (X, Y, Z) are supported. * Fully programmable pin assignment * Selectable 25 k pull-up, pull-down resistors per pin * Pull-up voltage either VBAT3V (BUCK mode) or VBAT1V (BOOST mode) configurable per pin The integrated quadrature decoder can automatically decode the signals for the X, Y and Z axes of a HID input device, reporting step count and direction: the channels are expected to provide a pulse train with 90 degrees phase difference; depending on whether the reference channel is leading or lagging, the direction can be determined. * Fixed assignment for analog pin ADC[3:0] This block can be used for waking up the chip as soon as there is any kind of movement from the external device connected to it. 3.7 TIMERS Features The Timer block contains 2 timer modules that are software controlled, programmable and can be used for various tasks. 3.7.1 General purpose timers * Three 16-bit signed counters that provide the step count and direction on each of the axes (X, Y and Z) Timer 0 * Programmable system clock sampling at maximum 16 MHz. * 16-bit general purpose timer * Ability to generate 2 Pulse Width Modulated signals (PWM0 and PWM1, with common programming) * APB interface for control and programming * Programmable source from P0, P1 and P2 ports * Programmable output frequency: 16, 8, 4, 2 MHz or 32 kHz f = -----------------------------------------------------------------------M + 1 + N + 1 * Digital filter on the channel inputs to avoid spikes (c) 2014 Dialog Semiconductor 13 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC * Pins retain their last state when system enters the Extended or Deep Sleep mode. Maskable Watchdog freeze by user program. Note that if the system is not remapped, i.e. SysRAM is at address 0x20000000, then a watchdog fire will trigger the BootROM code to be executed again. * Programmable duty cycle: M+1 = -------------------------------------------- 100 % M + 1 + N + 1 * Separately programmable interrupt timer: 16, 8, 4, 2 MHz or 32 kHz T = ----------------------------------------------------------------------- ON + 1 3.8 CLOCK/RESET Timer 2 3.8.1 Clocks * 14-bit general purpose timer DA14580 Debug state. with N = 0 to (216-1), M = 0 to (216-1) The Digital Controlled Xtal Oscillator (DXCO) is a Pierce configured type of oscillator designed for low power consumption and high stability. There are two such crystal oscillators in the system, one at 16 MHz(XTAL16M) and a second at 32.768 kHz (XTAL32K). The 32.768 kHz oscillator has no trimming capabilities and is used as the clock of the Extended/ Deep Sleep modes. The 16 MHz oscillator can be trimmed. * Ability to generate 3 Pulse Width Modulated signals (PWM2, PWM3 and PWM4) * Input clock frequency: f IN = sys_clk ------------------- with N = 1, 2, 4 or 8 N and sys_clk = 16 MHz or 32 kHz * Programmable output frequency: f IN f IN - f OUT = ------ to ---------------- 2 2 14 - 1 The principle schematic of the two oscillators is shown in Figure 7 below. No external components to the DA14580 are required other than the crystal itself. If the crystal has a case connection, it is advised to connect the case to ground. * Three outputs with Programmable duty cycle from 0 % to 100 % 16 MHz 32.768 kHz XTAL32Km The Wake-up timer can be programmed to wake up the DA14580 from power down mode after a preprogrammed number of GPIO events. XTAL32Kp XTAL16Mp 3.7.2 Wake-Up timer XTAL16Mm * Used for white LED intensity (on/off) control Features * Monitors any GPIO state change 0-22.4 pF * Implements debouncing time from 0 upto 63 ms * Accumulates external events and compares the number to a programmed value clock16MHz * Generates an interrupt to the CPU There are 3 RC oscillators in the DA14580: one providing 16 MHz (RC16M), one providing 32 kHz (RC32K) and one providing a frequency in the range of 10.5 kHz (RCX). The Watchdog timer is an 8-bit timer with sign bit that can be used to detect an unexpected execution sequence caused by a software run-away and can generate a full system reset or a Non-Maskable Interrupt (NMI). Features 3.8.2 Reset * 8 bits down counter with sign bit, clocked with a 10.24 ms clock for a maximum 2.6 s time-out. The DA14580 comprises an RST pad which is active high. It contains an RC filter for spikes suppression with 400 k and 2.8 pF for the resistor and the capacitor respectively. It also contains a 25 k pull-down resistor. This pad should be connected to ground if not needed by the application. The typical latency of the RST pad is in the range of 2 s. * Non-Maskable Interrupt (NMI) or WDOG reset. * Optional automatic WDOG reset if NMI handler fails to update the Watchdog register. * Non-maskable Watchdog freeze of the Cortex-M0 Debug module when the Cortex-M0 is halted in 14 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Figure 7 Crystal oscillator circuits 3.7.3 Watchdog timer (c) 2014 Dialog Semiconductor clock32kHz 3.9 POWER MANAGEMENT The DA14580 has a complete power management function integrated with Buck or Boost DC-DC converter and separate LDOs for the different power domains of the system. 2. LDO OTP: This is the LDO powering the OTP macro cell. This is the reason for using the step-up DC-DC converter when running from an Alkaline battery. 3. LDO SYS: This is the LDO providing the system with the actual VDD power required for the digital part to operate. Note that the Power Block implements seamless switching from the LDO SYS to the LDO RET when the system enters Deep Sleep mode. In the latter case, a low voltage is applied to the PD_AON power domain to further reduce leakage. Features * On-chip LDOs, without external capacitors * Synchronous DC-DC converter which can be configured as either: * Boost (step-up) converter, starting from 0.9 V, when running from an Alkaline/NiMH cell. 4. LDO (various): This a group of LDOs used for the elaborate control of the powering up/down of the Radio, the GP ADC and the XTAL16M oscillator. * Buck (step-down) converter for increased efficiency when running from a Lithium coin-cell or 2 Alkaline batteries down to 2.35 V. analog/RF SWITCH LDO LDO digital retention LDO analog/RF Buck Converter DA14580 Figure 8 Supply overview, Coin-cell application (c) 2014 Dialog Semiconductor 15 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC VBAT1V VBAT3V VBAT_RF The Power Block contains a DC-DC converter which can be configured to operate as a Step-Up or a StepDown converter. The converter provides power to four LDO groups in the system: VDCDC * Use of small external components (2.2 H inductor and 1F capacitor) VDCDC_RF There are two ways of connecting external batteries to the Power Block of the DA14580. They depend on the specific battery cell used and its voltage range. Battery cells are distinguished into Lithium coin cells (2.35 V to 3.3 V) and Alkaline cells (1.0 V to 1.8 V). The connection diagrams are presented in Figure 9 and Figure 8 respectively: * Battery voltage measurement ADC (multiplexed input from general purpose ADC) 2.35 V to 3.3 V Lithium coin-cell DA14580 1. LDO RET: This is the LDO providing power to the Retention domain (PD_AON). It powers the Retention RAMs and the digital part which is always on. DA14580 0.9 V to 2.0 V VBAT1V SWITCH internal supply for boost conv. VBAT3V < 0.9 V Alkaline or NiMH VDCDC on Boost Converter VDCDC_RF LDO LDO digital LDO VBAT_RF analog/RF retention DA14580 Figure 9 Supply overview, Alkaline-cell application The usage of Boost or Buck mode with respect to the provided voltage ranges is illustrated in the following figure which also illustrates the efficiency of the engine assuming a 10 mA constant load. dashed lines. The first one (0 V to 0.9 V) indicates that the DA14580 is not operational when the voltage is below 0.9 V. This is the absolute threshold for the DCDC converter Boost mode. DCDC Efficiency vs Voltage 95% 90% 85% 80% 75% 70% 65% 60% 55% 50% 0 0.5 0.9 1 1.5 Buck Boost 1.8 2 2.35 2.5 3 Note: The system should never be cold booted when the supply voltage is less than 2.5 V. A manual power up with a power supply less than 2.5 V in buck mode might create instability. 3.5 Boost (Vout > 1.4 V) Figure 10 DC-DC efficiency in Buck/Boost mode at various voltage levels The X axis represents the supply voltage. BOOST mode should be used when voltage ranges from 0.9 V to 2.0 V to sustain a decent efficiency over 70 %. From that point on, the power dissipation becomes quite large. BUCK mode can operate correctly with voltages in the range of 2.35 V to 3.3 V. There are two voltage areas in Figure 10 designated by (c) 2014 Dialog Semiconductor 16 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC The second area (1.8 V to 2.2 V) indicates that Deep Sleep mode is not allowed when the DC-DC converter is configured in BUCK mode and the voltage is within this range, because the OTP will not be readable any more. However, this part of the voltage range can be covered by the BOOST mode. Furthermore, when BUCK mode is mandatory, Extended Sleep mode can be activated instead of Deep Sleep mode, thus not using the OTP for the code mirroring but retain the code in SysRAM. Registers This section contains a detailed view of the DA14580 registers. It is organized as follows: An overview table is presented initially, which depicts all register names, addresses and descriptions. A detailed bit level description of each register follows. DA14580 4. The register file of the ARM Cortex-M0 can be found in the following documents, available on the ARM website: Devices Generic User Guide: DUI0497A_cortex_m0_r0p0_generic_ug.pdf Technical Reference Manual: DDI0432C_cortex_m0_r0p0_trm.pdf These documents contain the register descriptions for the Nested Vectored Interrupt Controller (NVIC), the System Control Block (SCB) and the System Timer (SysTick). Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 17 Final - January 29, 2015 v3.1 DA14580 Table 4: Register map Address Port Description 0x40008000 OTPC_MODE_REG Mode register 0x40008004 OTPC_PCTRL_REG Bit-programming control register 0x40008008 OTPC_STAT_REG Status register 0x4000800C OTPC_AHBADR_REG AHB master start address 0x40008010 OTPC_CELADR_REG Macrocell start address 0x40008014 OTPC_NWORDS_REG Number of words 0x40008018 OTPC_FFPRT_REG Ports access to fifo logic 0x4000801C OTPC_FFRD_REG Latest read data from the OTPC_FFPRT_REG 0x40008400 PATCH_VALID_REG Validity Control Register 0x40008404 PATCH_VALID_SET_REG Validity Set Control Register 0x40008408 PATCH_VALID_RESET_REG Validity Reset Control Register 0x40008410 PATCH_ADDR0_REG Patch entry 0: Address field 0x40008414 PATCH_DATA0_REG Patch entry 0: Data field 0x40008418 PATCH_ADDR1_REG Patch entry 1: Address field 0x4000841C PATCH_DATA1_REG Patch entry 1: Data field 0x40008420 PATCH_ADDR2_REG Patch entry 2: Address field 0x40008424 PATCH_DATA2_REG Patch entry 2: Data field 0x40008428 PATCH_ADDR3_REG Patch entry 3: Address field 0x4000842C PATCH_DATA3_REG Patch entry 3: Data field 0x40008430 PATCH_ADDR4_REG Patch entry 4: Address field 0x40008434 PATCH_DATA4_REG Patch entry 4: Data field 0x40008438 PATCH_ADDR5_REG Patch entry 5: Address field 0x4000843C PATCH_DATA5_REG Patch entry 5: Data field 0x40008440 PATCH_ADDR6_REG Patch entry 6: Address field 0x40008444 PATCH_DATA6_REG Patch entry 6: Data field PATCH_ADDR7_REG Patch entry 7: Address field PATCH_DATA7_REG Patch entry 7: Data field 0x50000000 CLK_AMBA_REG HCLK, PCLK, divider and clock gates 0x50000002 CLK_FREQ_TRIM_REG Xtal frequency trimming register 0x50000004 CLK_PER_REG Peripheral divider register 0x50000008 CLK_RADIO_REG Radio PLL control register 0x5000000A CLK_CTRL_REG Clock control register 0x50000010 PMU_CTRL_REG Power Management Unit control register 0x50000012 SYS_CTRL_REG System Control register 0x50000014 SYS_STAT_REG System status register 0x50000016 TRIM_CTRL_REG Control trimming of the XTAL16M 0x50000020 CLK_32K_REG 32 kHz oscillator register 0x50000022 CLK_16M_REG 16 MHz RC-oscillator register 0x50000024 CLK_RCX20K_REG 20 kHz RXC-oscillator control register 0x50000028 BANDGAP_REG Bandgap trimming 0x5000002A ANA_STATUS_REG Status bit of analog (power management) circuits 0x50000100 WKUP_CTRL_REG Control register for the wakeup counter 0x50000102 WKUP_COMPARE_REG Number of events before wakeup interrupt (c) 2014 Dialog Semiconductor 18 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC 0x40008448 0x4000844C DA14580 Table 4: Register map Address Port Description 0x50000104 WKUP_RESET_IRQ_REG Reset wakeup interrupt 0x50000106 WKUP_COUNTER_REG Actual number of events of the wakeup counter 0x50000108 WKUP_RESET_CNTR_REG Reset the event counter 0x5000010A WKUP_SELECT_P0_REG Select which inputs from P0 port can trigger wkup counter 0x5000010C WKUP_SELECT_P1_REG Select which inputs from P1 port can trigger wkup counter 0x5000010E WKUP_SELECT_P2_REG Select which inputs from P2 port can trigger wkup counter 0x50000110 WKUP_SELECT_P3_REG Select which inputs from P3 port can trigger wkup counter 0x50000112 WKUP_POL_P0_REG Select the sensitivity polarity for each P0 input 0x50000114 WKUP_POL_P1_REG Select the sensitivity polarity for each P1 input 0x50000116 WKUP_POL_P2_REG Select the sensitivity polarity for each P2 input WKUP_POL_P3_REG Select the sensitivity polarity for each P3 input QDEC_CTRL_REG Quad Decoder control register 0x50000202 QDEC_XCNT_REG Counter value of the X Axis 0x50000204 QDEC_YCNT_REG Counter value of the Y Axis 0x50000206 QDEC_CLOCKDIV_REG Clock divider register 0x50000208 QDEC_CTRL2_REG Quad Decoder control register 0x5000020A QDEC_ZCNT_REG Z_counter 0x50001000 UART_RBR_THR_DLL_REG Receive Buffer Register 0x50001004 UART_IER_DLH_REG Interrupt Enable Register 0x50001008 UART_IIR_FCR_REG Interrupt Identification Register/FIFO Control Register 0x5000100C UART_LCR_REG Line Control Register 0x50001010 UART_MCR_REG Modem Control Register 0x50001014 UART_LSR_REG Line Status Register 0x50001018 UART_MSR_REG Modem Status Register 0x5000101C UART_SCR_REG Scratchpad Register 0x50001020 UART_LPDLL_REG Low Power Divisor Latch Low 0x50001024 UART_LPDLH_REG Low Power Divisor Latch High 0x50001030 UART_SRBR_STHR0_REG Shadow Receive/Transmit Buffer Register 0x50001034 UART_SRBR_STHR1_REG Shadow Receive/Transmit Buffer Register 0x50001038 UART_SRBR_STHR2_REG Shadow Receive/Transmit Buffer Register 0x5000103C UART_SRBR_STHR3_REG Shadow Receive/Transmit Buffer Register 0x50001040 UART_SRBR_STHR4_REG Shadow Receive/Transmit Buffer Register 0x50001044 UART_SRBR_STHR5_REG Shadow Receive/Transmit Buffer Register 0x50001048 UART_SRBR_STHR6_REG Shadow Receive/Transmit Buffer Register 0x5000104C UART_SRBR_STHR7_REG Shadow Receive/Transmit Buffer Register 0x50001050 UART_SRBR_STHR8_REG Shadow Receive/Transmit Buffer Register 0x50001054 UART_SRBR_STHR9_REG Shadow Receive/Transmit Buffer Register 0x50001058 UART_SRBR_STHR10_REG Shadow Receive/Transmit Buffer Register 0x5000105C UART_SRBR_STHR11_REG Shadow Receive/Transmit Buffer Register 0x50001060 UART_SRBR_STHR12_REG Shadow Receive/Transmit Buffer Register 0x50001064 UART_SRBR_STHR13_REG Shadow Receive/Transmit Buffer Register (c) 2014 Dialog Semiconductor 19 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC 0x50000118 0x50000200 Address Port Description 0x50001068 UART_SRBR_STHR14_REG Shadow Receive/Transmit Buffer Register 0x5000106C UART_SRBR_STHR15_REG Shadow Receive/Transmit Buffer Register 0x5000107C UART_USR_REG UART Status register. 0x50001080 UART_TFL_REG Transmit FIFO Level 0x50001084 UART_RFL_REG Receive FIFO Level. 0x50001088 UART_SRR_REG Software Reset Register. 0x5000108C UART_SRTS_REG Shadow Request to Send 0x50001090 UART_SBCR_REG Shadow Break Control Register 0x50001094 UART_SDMAM_REG Shadow DMA Mode UART_SFE_REG Shadow FIFO Enable UART_SRT_REG Shadow RCVR Trigger 0x500010A0 UART_STET_REG Shadow TX Empty Trigger 0x500010A4 UART_HTX_REG Halt TX 0x500010F4 UART_CPR_REG Component Parameter Register 0x500010F8 UART_UCV_REG Component Version 0x500010FC UART_CTR_REG Component Type Register 0x50001100 UART2_RBR_THR_DLL_REG Receive Buffer Register 0x50001104 UART2_IER_DLH_REG Interrupt Enable Register 0x50001108 UART2_IIR_FCR_REG Interrupt Identification Register/FIFO Control Register 0x5000110C UART2_LCR_REG Line Control Register 0x50001110 UART2_MCR_REG Modem Control Register 0x50001114 UART2_LSR_REG Line Status Register 0x50001118 UART2_MSR_REG Modem Status Register 0x5000111C UART2_SCR_REG Scratchpad Register 0x50001120 UART2_LPDLL_REG Low Power Divisor Latch Low 0x50001124 UART2_LPDLH_REG Low Power Divisor Latch High 0x50001130 UART2_SRBR_STHR0_REG Shadow Receive/Transmit Buffer Register 0x50001134 UART2_SRBR_STHR1_REG Shadow Receive/Transmit Buffer Register 0x50001138 UART2_SRBR_STHR2_REG Shadow Receive/Transmit Buffer Register 0x5000113C UART2_SRBR_STHR3_REG Shadow Receive/Transmit Buffer Register 0x50001140 UART2_SRBR_STHR4_REG Shadow Receive/Transmit Buffer Register 0x50001144 UART2_SRBR_STHR5_REG Shadow Receive/Transmit Buffer Register 0x50001148 UART2_SRBR_STHR6_REG Shadow Receive/Transmit Buffer Register 0x5000114C UART2_SRBR_STHR7_REG Shadow Receive/Transmit Buffer Register 0x50001150 UART2_SRBR_STHR8_REG Shadow Receive/Transmit Buffer Register 0x50001154 UART2_SRBR_STHR9_REG Shadow Receive/Transmit Buffer Register 0x50001158 UART2_SRBR_STHR10_REG Shadow Receive/Transmit Buffer Register 0x5000115C UART2_SRBR_STHR11_REG Shadow Receive/Transmit Buffer Register 0x50001160 UART2_SRBR_STHR12_REG Shadow Receive/Transmit Buffer Register 0x50001164 UART2_SRBR_STHR13_REG Shadow Receive/Transmit Buffer Register 0x50001168 UART2_SRBR_STHR14_REG Shadow Receive/Transmit Buffer Register 0x5000116C UART2_SRBR_STHR15_REG Shadow Receive/Transmit Buffer Register 0x5000117C UART2_USR_REG UART Status register. 0x50001180 UART2_TFL_REG Transmit FIFO Level (c) 2014 Dialog Semiconductor 20 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC 0x50001098 0x5000109C DA14580 Table 4: Register map DA14580 Table 4: Register map Address Port Description 0x50001184 UART2_RFL_REG Receive FIFO Level. 0x50001188 UART2_SRR_REG Software Reset Register. 0x5000118C UART2_SRTS_REG Shadow Request to Send 0x50001190 UART2_SBCR_REG Shadow Break Control Register 0x50001194 UART2_SDMAM_REG Shadow DMA Mode UART2_SFE_REG Shadow FIFO Enable UART2_SRT_REG Shadow RCVR Trigger 0x500011A0 UART2_STET_REG Shadow TX Empty Trigger 0x500011A4 UART2_HTX_REG Halt TX 0x500011F4 UART2_CPR_REG Component Parameter Register 0x500011F8 UART2_UCV_REG Component Version 0x500011FC UART2_CTR_REG Component Type Register 0x50001200 SPI_CTRL_REG SPI control register 0 0x50001202 SPI_RX_TX_REG0 SPI RX/TX register0 0x50001204 SPI_RX_TX_REG1 SPI RX/TX register1 0x50001206 SPI_CLEAR_INT_REG SPI clear interrupt register 0x50001208 SPI_CTRL_REG1 SPI control register 1 0x50001300 I2C_CON_REG I2C Control Register 0x50001304 I2C_TAR_REG I2C Target Address Register 0x50001308 I2C_SAR_REG I2C Slave Address Register 0x50001310 I2C_DATA_CMD_REG I2C Rx/Tx Data Buffer and Command Register 0x50001314 I2C_SS_SCL_HCNT_REG Standard Speed I2C Clock SCL High Count Register 0x50001318 I2C_SS_SCL_LCNT_REG Standard Speed I2C Clock SCL Low Count Register 0x5000131C I2C_FS_SCL_HCNT_REG Fast Speed I2C Clock SCL High Count Register 0x50001320 I2C_FS_SCL_LCNT_REG Fast Speed I2C Clock SCL Low Count Register 0x5000132C I2C_INTR_STAT_REG I2C Interrupt Status Register 0x50001330 I2C_INTR_MASK_REG I2C Interrupt Mask Register 0x50001334 I2C_RAW_INTR_STAT_REG I2C Raw Interrupt Status Register 0x50001338 I2C_RX_TL_REG I2C Receive FIFO Threshold Register 0x5000133C I2C_TX_TL_REG I2C Transmit FIFO Threshold Register 0x50001340 I2C_CLR_INTR_REG Clear Combined and Individual Interrupt Register 0x50001344 I2C_CLR_RX_UNDER_REG Clear RX_UNDER Interrupt Register 0x50001348 I2C_CLR_RX_OVER_REG Clear RX_OVER Interrupt Register 0x5000134C I2C_CLR_TX_OVER_REG Clear TX_OVER Interrupt Register 0x50001350 I2C_CLR_RD_REQ_REG Clear RD_REQ Interrupt Register 0x50001354 I2C_CLR_TX_ABRT_REG Clear TX_ABRT Interrupt Register 0x50001358 I2C_CLR_RX_DONE_REG Clear RX_DONE Interrupt Register 0x5000135C I2C_CLR_ACTIVITY_REG Clear ACTIVITY Interrupt Register 0x50001360 I2C_CLR_STOP_DET_REG Clear STOP_DET Interrupt Register 0x50001364 I2C_CLR_START_DET_REG Clear START_DET Interrupt Register 0x50001368 I2C_CLR_GEN_CALL_REG Clear GEN_CALL Interrupt Register 0x5000136C I2C_ENABLE_REG I2C Enable Register 0x50001370 I2C_STATUS_REG I2C Status Register 0x50001374 I2C_TXFLR_REG I2C Transmit FIFO Level Register (c) 2014 Dialog Semiconductor 21 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC 0x50001198 0x5000119C DA14580 Table 4: Register map Address Port Description 0x50001378 I2C_RXFLR_REG I2C Receive FIFO Level Register 0x5000137C I2C_SDA_HOLD_REG I2C SDA Hold Time Length Register 0x50001380 I2C_TX_ABRT_SOURCE_REG I2C Transmit Abort Source Register 0x50001394 I2C_SDA_SETUP_REG I2C SDA Setup Register 0x50001398 I2C_ACK_GENERAL_CALL_REG I2C ACK General Call Register 0x5000139C I2C_ENABLE_STATUS_REG I2C Enable Status Register 0x500013A0 I2C_IC_FS_SPKLEN_REG I2C SS and FS spike suppression limit Size 0x50001400 GPIO_IRQ0_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ0 0x50001402 GPIO_IRQ1_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ1 0x50001404 GPIO_IRQ2_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ2 0x50001406 GPIO_IRQ3_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ3 0x50001408 GPIO_IRQ4_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ4 0x5000140C GPIO_DEBOUNCE_REG debounce counter value for GPIO inputs 0x5000140E GPIO_RESET_IRQ_REG GPIO interrupt reset register 0x50001410 GPIO_INT_LEVEL_CTRL_REG high or low level select for GPIO interrupts 0x50001412 KBRD_IRQ_IN_SEL0_REG GPIO interrupt selection for KBRD_IRQ for P0 0x50001414 KBRD_IRQ_IN_SEL1_REG GPIO interrupt selection for KBRD_IRQ for P1 and P2 0x50001416 KBRD_IRQ_IN_SEL2_REG GPIO interrupt selection for KBRD_IRQ for P3 0x50001500 GP_ADC_CTRL_REG General Purpose ADC Control Register 0x50001502 GP_ADC_CTRL2_REG General Purpose ADC Second Control Register 0x50001504 GP_ADC_OFFP_REG General Purpose ADC Positive Offset Register 0x50001506 GP_ADC_OFFN_REG General Purpose ADC Negative Offset Register 0x50001508 GP_ADC_CLEAR_INT_REG General Purpose ADC Clear Interrupt Register GP_ADC_RESULT_REG General Purpose ADC Result Register GP_ADC_DELAY_REG General Purpose ADC Delay Register 0x5000150E GP_ADC_DELAY2_REG General Purpose ADC Second Delay Register 0x50001600 CLK_REF_SEL_REG Select clock for oscillator calibration 0x50001602 CLK_REF_CNT_REG Count value for oscillator calibration 0x50001604 CLK_REF_VAL_L_REG XTAL16M reference cycles, lower 16 bits 0x50001606 CLK_REF_VAL_H_REG XTAL16M reference cycles, upper 16 bits 0x50003000 P0_DATA_REG P0 Data input / output register 0x50003002 P0_SET_DATA_REG P0 Set port pins register 0x50003004 P0_RESET_DATA_REG P0 Reset port pins register 0x50003006 P00_MODE_REG P00 Mode Register 0x50003008 P01_MODE_REG P01 Mode Register 0x5000300A P02_MODE_REG P02 Mode Register 0x5000300C P03_MODE_REG P03 Mode Register 0x5000300E P04_MODE_REG P04 Mode Register 0x50003010 P05_MODE_REG P05 Mode Register 0x50003012 P06_MODE_REG P06 Mode Register 0x50003014 P07_MODE_REG P07 Mode Register 0x50003020 P1_DATA_REG P1 Data input / output register 0x50003022 P1_SET_DATA_REG P1 Set port pins register 0x50003024 P1_RESET_DATA_REG P1 Reset port pins register (c) 2014 Dialog Semiconductor 22 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC 0x5000150A 0x5000150C DA14580 Table 4: Register map Address Port Description 0x50003026 P10_MODE_REG P10 Mode Register 0x50003028 P11_MODE_REG P11 Mode Register 0x5000302A P12_MODE_REG P12 Mode Register 0x5000302C P13_MODE_REG P13 Mode Register 0x5000302E P14_MODE_REG P14 Mode Register 0x50003030 P15_MODE_REG P15 Mode Register 0x50003040 P2_DATA_REG P2 Data input / output register 0x50003042 P2_SET_DATA_REG P2 Set port pins register 0x50003044 P2_RESET_DATA_REG P2 Reset port pins register 0x50003046 P20_MODE_REG P20 Mode Register 0x50003048 P21_MODE_REG P21 Mode Register 0x5000304A P22_MODE_REG P22 Mode Register 0x5000304C P23_MODE_REG P23 Mode Register 0x5000304E P24_MODE_REG P24 Mode Register 0x50003050 P25_MODE_REG P25 Mode Register 0x50003052 P26_MODE_REG P26 Mode Register 0x50003054 P27_MODE_REG P27 Mode Register 0x50003056 P28_MODE_REG P28 Mode Register 0x50003058 P29_MODE_REG P29 Mode Register 0x50003070 P01_PADPWR_CTRL_REG Ports 0 and 1 Output Power Control Register 0x50003072 P2_PADPWR_CTRL_REG Port 2 Output Power Control Register 0x50003074 P3_PADPWR_CTRL_REG Port 3 Output Power Control Register 0x50003080 P3_DATA_REG P3 Data input / output register 0x50003082 P3_SET_DATA_REG P3 Set port pins register 0x50003084 P3_RESET_DATA_REG P3 Reset port pins register 0x50003086 P30_MODE_REG P30 Mode Register 0x50003088 P31_MODE_REG P31 Mode Register P32_MODE_REG P32 Mode Register P33_MODE_REG P33 Mode Register 0x5000308E P34_MODE_REG P34 Mode Register 0x50003090 P35_MODE_REG P35 Mode Register 0x50003092 P36_MODE_REG P36 Mode Register 0x50003094 P37_MODE_REG P37 Mode Register 0x50003100 WATCHDOG_REG Watchdog timer register. 0x50003102 WATCHDOG_CTRL_REG Watchdog control register. 0x50003200 CHIP_ID1_REG Chip identification register 1. 0x50003201 CHIP_ID2_REG Chip identification register 2. 0x50003202 CHIP_ID3_REG Chip identification register 3. 0x50003203 CHIP_SWC_REG Software compatibility register. 0x50003204 CHIP_REVISION_REG Chip revision register. 0x50003205 CHIP_CONFIG1_REG Chip configuration register 1. 0x50003206 CHIP_CONFIG2_REG Chip configuration register 2. 0x50003207 CHIP_CONFIG3_REG Chip configuration register 3. 0x5000320A CHIP_TEST1_REG Chip test register 1. (c) 2014 Dialog Semiconductor 23 Low Power Bluetooth Smart SoC 0x5000308A 0x5000308C Final - January 29, 2015 v3.1 DA14580 Table 4: Register map Address Port Description 0x5000320B CHIP_TEST2_REG Chip test register 2. 0x50003300 SET_FREEZE_REG Controls freezing of various timers/counters. 0x50003302 RESET_FREEZE_REG Controls unfreezing of various timers/counters. 0x50003304 DEBUG_REG Various debug information register. 0x50003306 GP_STATUS_REG General purpose system status register. 0x50003308 GP_CONTROL_REG General purpose system control register. 0x50003400 TIMER0_CTRL_REG Timer0 control register 0x50003402 TIMER0_ON_REG Timer0 on control register 0x50003404 TIMER0_RELOAD_M_REG 16 bits reload value for Timer0 0x50003406 TIMER0_RELOAD_N_REG 16 bits reload value for Timer0 0x50003408 PWM2_DUTY_CYCLE Duty Cycle for PWM2 0x5000340A PWM3_DUTY_CYCLE Duty Cycle for PWM3 0x5000340C PWM4_DUTY_CYCLE Duty Cycle for PWM4 0x5000340E TRIPLE_PWM_FREQUENCY Frequency for PWM 2,3 and 4 0x50003410 TRIPLE_PWM_CTRL_REG PWM 2 3 4 Control Table 5: OTPC_MODE_REG (0x40008000) Bit Mode Symbol Description Reset 31:30 - - Reserved 0x0 29:28 R/W OTPC_MODE_PRG_ PORT_MUX Selects the source that is connected to the prg_port port of the controller. 00 - {16'd0, BANDGAP_REG[15:0]} 01 - {RF_RSSI_COMP_CTRL_REG[15:0], 8'd0, RFIO_CTRL1_REG{7:0]} 10 - {3'd0, RF_LNA_CTRL3_REG[4:0], RF_LNA_CTRL2_REG[11:0], RF_LNA_CTRL1_REG[11:0]} 11 - {28'd0, RF_VCO_CTRL_REG[3:0]} 0x0 See OTPC_MODE_PRG_PORT_SEL about the use of the prg_port - - Reserved 0x0 8 R/W OPTC_MODE_PRG_ FAST Defines the timing that will be used for all the programming activities (APROG, MPROG and TWR) 0 - Selects the normal timing 1 - Selects the fast timing 0 7 R/W OTPC_MODE_PRG_ PORT_SEL Selects an alternative data source for the programming of the OTP macrocells, when the controller is configured in APROG mode. 0 - The fifo will be used as the data source. The fifo will be filled with a way defined by the register OTPC_MODE_USE_DMA. The number of words that will be programmed is defined by OTPC_NWORDS. 1 - Only one word will programmed. The value of the word is contained in the prg_port port of the controller. The values of the registers OTPC_MODE_USE_DMA, OTPC_NWORDS and the contents of the FIFO will not be used. 0x0 6 R/W OTPC_MODE_TWO_ CC_ACC Defines the duration of each read from the OTP macrocells. 0 - Reads 16 bits of data every one clock cycle. 1 - Reads 16 bits of data every two clock cycles. 0x0 (c) 2014 Dialog Semiconductor 24 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC 27:9 Bit Mode Symbol Description Reset 5 R/W OTPC_MODE_FIFO_ FLUSH Writing 1, removes any content from the FIFO. This bit returns automatically to 0. 0x0 4 R/W OTPC_MODE_USE_ DMA Selects the use of the dma, when the controller is configured in one of the modes: AREAD or APROG. 0 - DMAis not used. The data should be transfered from/to controller through OTPC_FFPRT_REG 1 - DMA is used. Data transfers from/to controller are performed automatically. The AHB base address should be configured in OTPC_AHBADR_REG before the selection of the mode. If programming of the OTPC_MODE_REG is performed through the serial interface,the OTPC_MODE_USE_DMA will be set to 0 automatically. If the controller is in APROG mode and the OTPC_MODE_PRG_PORT_SEL is enabled, the dma will stay inactive. 0x0 3 - - Reserved 0x0 2:0 R/W OTPC_MODE_MODE Defines the mode of operation of the OTPC controller. The encoding of the modes is as follows: 000 - STBY mode 001 - MREAD mode 010 - MPROG mode 011 - AREAD mode 100 - APROG mode 101 - Test mode. Reserved 110 - Test mode. Reserved 111 - Test mode. Reserved To manually move between modes, always return to STBY mode first. 0x0 DA14580 Table 5: OTPC_MODE_REG (0x40008000) Table 6: OTPC_PCTRL_REG (0x40008004) Mode Symbol Description Reset 31:28 - - Reserved 0x0 27 R/W OTPC_PCTRL_ENU Enables the programming in the upper bank of the OTP. 0 - Programming sequence is not applied in the upper bank. 1 - Programming sequence is applied in the upper bank. 0x0 26 R/W OTPC_PCTRL_BITU Defines the value of the selected bit in the upper bank, after the programming sequence. 0x0 25 R/W OTPC_PCTRL_ENL Enables the programming in the lower bank. 0 - The programming sequence is not applied in the lower bank. 1 -The programming sequence is applied in the lower bank. 0x0 24 R/W OTPC_PCTRL_BITL Defines the value of the selected bit in the lower bank, after the programming sequence. 0x0 23 R/W OTPC_PCTRL_BSEL U Selects between the U1 and U0 byte for the programming sequence in the upper bank. 0 - Program the U0 byte 1 - Program the U1 byte 0x0 22:20 R/W OTPC_PCTRL_BADR U Selects the bit inside the Ux (x=0,1) byte, which will be programmed in the upper bank. 0x0 19 R/W OTPC_PCTRL_BSEL L Selects between the L1 and L0 byte for the programming sequence in the lower bank. 0 - Program the L0 byte 1 - Program the L1 byte 0x0 (c) 2014 Dialog Semiconductor 25 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 18:16 R/W OTPC_PCTRL_BADR L Selects the bit inside the Lx (x=0,1) byte, which will be programmed in the lower bank. 0x0 15:13 - - Reserved 0x0 12:0 R/W OTPC_PCTRL_WAD DR Defines the address of a 32 bits word {U1,L1,U0,L0} in the 0x0 macrocells, where one or two bits will be programmed. There are two macrocell banks, with 8 bits each. Each bank contribute with two memory positions for each 32 bits word. The Ux, Lx represent the bytes of the upper and lower bank respectively. DA14580 Table 6: OTPC_PCTRL_REG (0x40008004) Table 7: OTPC_STAT_REG (0x40008008) Mode Symbol Description Reset 31:29 - - Reserved 0x0 28:16 R OTPC_STAT_NWOR DS Contains the current value of the words to be processed. 0 15 R OTPC_STAT_TERR_ U Indicates the upper bank as the source of a test error. This value is valid when OTPC_STAT_TERROR is valid. 0 - There is no test error in the upper bank 1 - A test error has occured in the upper bank 0x0 14 R OTPC_STAT_TERR_L Indicates the lower bank as the source of a test error. The value is valid when OTPC_STAT_TERROR is valid. 0 - There is no test error in the lower bank 1 - A test error has occured in the lower bank 0x0 13 R OTPC_STAT_PERR_ U Indicates the upper bank as the source of a programming error. The value is valid when OTPC_STAT_PERROR is valid. 0 - There is no programming error in the upper bank 1 - A programming error has occured in the upper bank 0x0 12 R OTPC_STAT_PERR_ L Indicates the lower bank as the source of a programming error. The value is valid when OTPC_STAT_PERROR is valid. 0 - There is no programming error in the lower bank 1 - A programming error has occured in the lower bank 0x0 11:8 R OTPC_STAT_FWORD Indicates the number of words which contained in the fifo of S the controller. 0x0 7:5 - - Reserved 0x0 4 R OTPC_STAT_ARDY Monitors the progress of read or programming operations while in the AREAD or APROG modes. 0 - The controller is busy while reading or programming (AREAD or APROG modes). 1 - The controller is not busy in AREAD or APROG mode. 0x1 3 R OTPC_STAT_TERRO R Indicates the result of a test sequence. Should be checked after the end of a TBLANK, TDEC and TWR mode (OTPC_STAT_TRDY= 1). 0 - The test sequence ends with no error. 1 - The test sequence has failed. 0x0 2 R OTPC_STAT_TRDY Indicates the state of a test mode. Should be used to monitor the progress of the TBLANK, TDEC and TWR modes. 0 - The controller is busy. A test mode is in progress. 1 - There is no active test mode. 0x1 (c) 2014 Dialog Semiconductor 26 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 1 R OTPC_STAT_PERRO R Indicates that an error has occurred during the bit-programming process. 0 - No error during the bit-programming process. 1 - The process of bit-programming failed. When the controller is in MPROG mode, this bit should be checked after the end of the programming process (OTPC_STAT_PRDY= 1). During APROG mode, the value of this field is normal to change periodically. Upon finishing the operation in the APROG mode (OTPC_STAT_ARDY= 1), this field indicates if the programming has failed or ended succesfully. 0x0 0 R OTPC_STAT_PRDY Indicates the state of a bit-programming process. 0 - The controller is busy. A bit-programming is in progress 1 - The logic which performs bit-programming is idle. When the controller is in MPROG mode, this bit should be used to monitor the progress of a programming request. During APROG mode, the value of this field it is normal to changing periodically. 0x1 DA14580 Table 7: OTPC_STAT_REG (0x40008008) Table 8: OTPC_AHBADR_REG (0x4000800C) Bit Mode Symbol Description Reset 31:2 R/W OTPC_AHBADR Tthe AHB address used by the AHB master interface of the controller ( bits [31:2]). 0x0 1:0 - - Reserved 0x0 Table 9: OTPC_CELADR_REG (0x40008010) Bit Mode Symbol Description Reset 31:13 - - Reserved 0x0 12:0 R/W OTPC_CELADR Defines a word address inside the macrocell. Used in modes AREAD and APROG and is automatically updated. 0x0 Table 10: OTPC_NWORDS_REG (0x40008014) Mode Symbol Description Reset 31:13 - - Reserved 0x0 12:0 R/W OTPC_NWORDS The number of words (minus one) for reading/programming during the AREAD/APROG mode. If in APROG mode, and the OTPC_MODE_PRG_PORT_SEL is enabled (=1), this register will not be used and will stay unchanged. During mirroring, this register reflects the current amount of data that will be copied. It keeps its value until be written by the software with a new value. The number of the words that remaining to be processed by the controller is contained in the field OTPC_STAT_NWORDS. 0x0 (c) 2014 Dialog Semiconductor 27 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 31:0 R/W OTPC_FFPRT Provides access to the fifo through an access port. Write this 0x0 register with the corresponding data, when the APROG mode is selected and the DMA is disabled. Read from this register the corresponding data, when the AREAD mode is selected and the DMA is disabled. Check OTPC_STAT_FWORDS register for data/space availability, before accessing the fifo. DA14580 Table 11: OTPC_FFPRT_REG (0x40008018) Table 12: OTPC_FFRD_REG (0x4000801C) Bit Mode Symbol Description Reset 31:0 R OTPC_FFRD Contains the value read from the fifo, after a read of the OTPC_FFPRT_REG register. 0x0 Table 13: PATCH_VALID_REG (0x40008400) Bit Mode Symbol Description Reset 31:8 - - Reserved 0x0 7:0 R/W PATCH_VALID Indicates which patch entry is valid. For example, when bit 0 is high it indicates that entry 0 is valid, i.e. the values of PATCH_ADDR0_REG / PATCH_DATA0_REG, are effective. 0x0 Table 14: PATCH_VALID_SET_REG (0x40008404) Bit Mode Symbol Description Reset 31:8 - - Reserved 0x0 7:0 R/W PATCH_VALID_SET Writing a bit with 1 will set the corresponding bit of PATCH_VALID_REG to 1. Writing a bit with 0 is ignored. Read always as 0. 0x0 Table 15: PATCH_VALID_RESET_REG (0x40008408) Mode Symbol Description Reset 31:8 - - Reserved 0x0 7:0 R/W PATCH_VALID_RESE T Writing a bit with 1 will clear the corresponding bit of PATCH_VALID_REG to 0. Writing a bit with zero is ignored. Read always as 0. 0x0 Table 16: PATCH_ADDR0_REG (0x40008410) Bit Mode Symbol Description Reset 31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as "0". Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block. 0x0 (c) 2014 Dialog Semiconductor 28 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG 0x0 DA14580 Table 17: PATCH_DATA0_REG (0x40008414) Table 18: PATCH_ADDR1_REG (0x40008418) Bit Mode Symbol Description Reset 31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as "0". Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block. 0x0 Table 19: PATCH_DATA1_REG (0x4000841C) Bit Mode Symbol Description Reset 31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG 0x0 Table 20: PATCH_ADDR2_REG (0x40008420) Bit Mode Symbol Description Reset 31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as "0". Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block. 0x0 Table 21: PATCH_DATA2_REG (0x40008424) Mode Symbol Description Reset 31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG 0x0 Table 22: PATCH_ADDR3_REG (0x40008428) Bit Mode Symbol Description Reset 31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as "0". Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block. 0x0 (c) 2014 Dialog Semiconductor 29 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG 0x0 DA14580 Table 23: PATCH_DATA3_REG (0x4000842C) Table 24: PATCH_ADDR4_REG (0x40008430) Bit Mode Symbol Description Reset 31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as "0". Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block. 0x0 Table 25: PATCH_DATA4_REG (0x40008434) Bit Mode Symbol Description Reset 31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG 0x0 Table 26: PATCH_ADDR5_REG (0x40008438) Bit Mode Symbol Description Reset 31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as "0". Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block. 0x0 Table 27: PATCH_DATA5_REG (0x4000843C) Mode Symbol Description Reset 31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG 0x0 Table 28: PATCH_ADDR6_REG (0x40008440) Bit Mode Symbol Description Reset 31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as "0". Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block. 0x0 (c) 2014 Dialog Semiconductor 30 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG 0x0 DA14580 Table 29: PATCH_DATA6_REG (0x40008444) Table 30: PATCH_ADDR7_REG (0x40008448) Bit Mode Symbol Description Reset 31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as "0". Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block. 0x0 Table 31: PATCH_DATA7_REG (0x4000844C) Bit Mode Symbol Description Reset 31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG 0x0 Table 32: CLK_AMBA_REG (0x50000000) Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 R/W OTP_ENABLE Clock enable for OTP controller 0x0 6 - - Reserved 0x0 5:4 R/W PCLK_DIV APB interface clock (PCLK). Divider is cascaded with HCLK_DIV. PCLK is HCLK divided by: 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 0x2 3:2 - - Reserved 0x0 1:0 R/W HCLK_DIV AHB interface and microprocessor clock (HCLK). HCLK is source clock divided by: 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 0x2 Table 33: CLK_FREQ_TRIM_REG (0x50000002) Bit Mode Symbol Description Reset 15:11 - - Reserved 0x0 10:8 R/W COARSE_ADJ Xtal frequency course trimming register. 0x0: lowest frequency 0x7: highest frequencyIncrement or decrement the binary value with 1. Wait approximately 200 us to allow the adjustment to settle. 0x0 (c) 2014 Dialog Semiconductor 31 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 7:0 R/W FINE_ADJ Xtal frequency fine trimming register. 0x00: lowest frequency 0xFF: highest frequency 0x0 DA14580 Table 33: CLK_FREQ_TRIM_REG (0x50000002) Table 34: CLK_PER_REG (0x50000004) Bit Mode Symbol Description Reset 15 R/W QUAD_ENABLE Enable the Quadrature clock 0x0 14:13 - - Reserved 0x0 11 R/W SPI_ENABLE Enable SPI clock 0x0 10 - - Reserved 0x0 9:8 R/W SPI_DIV Division factor for SPI 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 0x0 7 R/W UART1_ENABLE Enable UART1 clock 0x0 6 R/W UART2_ENABLE Enable UART2 clock 0x0 5 R/W I2C_ENABLE Enable I2C clock 0x0 4 R/W WAKEUPCT_ENABLE Enable Wakeup CaptureTimer clock 0x0 3 R/W TMR_ENABLE Enable TIMER0 and TIMER2 clock 0x0 2 - - Reserved 0x0 1:0 R/W TMR_DIV Division factor for TIMER0 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 0x0 Table 35: CLK_RADIO_REG (0x50000008) Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 R/W BLE_ENABLE Enable the BLE core clocks 0x0 6 R/W BLE_LP_RESET Reset for the BLE LP timer 0x1 5:4 R/W BLE_DIV Division factor for BLE core blocks 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 The programmed frequency should not be lower than 8 MHz and not faster than the programmed CPU clock frequency. Refer also to BLE_CNTL2_REG[BLE_CLK_SEL]. 0x0 3 R/W RFCU_ENABLE Enable the RF control Unit clock 0x0 2 - - Reserved 0x0 1:0 R/W RFCU_DIV Division factor for RF Control Unit 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 The programmed frequency must be exactly 8 MHz. 0x0 (c) 2014 Dialog Semiconductor 32 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 R RUNNING_AT_XTAL1 6M Indicates that the XTAL16M clock is used as clock, and may not be switched off 0x1 6 R RUNNING_AT_RC16 M Indicates that the RC16M clock is used as clock 0x0 5 R RUNNING_AT_32K Indicates that either the RC32k or XTAL32k is being used as clock 0x0 4 - - Reserved 0x0 3 R/W XTAL16M_SPIKE_FLT Disable spikefilter in digital clock _DISABLE 0x0 2 R/W XTAL16M_DISABLE Setting this bit instantaneously disables the 16 MHz crystal oscillator. Also, after sleep/wakeup cycle, the oscillator will not be enabled. This bit may not be set to '1'when "RUNNING_AT_XTAL16M is '1' to prevent deadlock. After resetting this bit, wait for XTAL16_SETTLED or XTAL16_TRIM_READY to become '1' before switching to XTAL16 clock source. 0x0 1:0 R/W SYS_CLK_SEL Selects the clock source. 0x0: XTAL16M (check the XTAL16_SETTLED and XTAL16_TRIM_READY bits!!) 0x1: RC16M 0x2/0x3: either RC32k or XTAL32k is used 0x0 DA14580 Table 36: CLK_CTRL_REG (0x5000000A) Table 37: PMU_CTRL_REG (0x50000010) Mode Symbol Description Reset 15:12 - - Reserved 0x0 11:8 R/W RETENTION_MODE Select the retainability of the 4 retention RAM macros. '1' is retainable, '0' is power gated. (3) is RETRAM4 (2) is RETRAM3 (1) is RETRAM2 (0) is RETRAM1 0x0 7 R/W FORCE_BOOST Force the DCDC into boost mode at next wakeup. Setting this bit reduces the deepsleep current. FORCE_BOOST has highest priority. When either FORCE_BOOST or FORCE_BUCK have been written, these bits cannot be changed. 0x0 6 R/W FORCE_BUCK Force the DCDC into buck mode at next wakeup. Setting this bit reduces the deepsleep current. FORCE_BOOST has highest priority. When either FORCE_BOOST or FORCE_BUCK have been written, these bits cannot be changed. 0x0 5:4 R/W OTP_COPY_DIV Sets the HCLK division during OTP mirroring 0x0 2 R/W RADIO_SLEEP Put the digital part of the radio in powerdown 0x1 1 R/W PERIPH_SLEEP Put all peripherals (I2C, UART, SPI, ADC) in powerdown 0x1 0 R/W RESET_ON_WAKEU P Perform a Hardware Reset after waking up. Booter will be started. 0x0 (c) 2014 Dialog Semiconductor 33 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 15 W SW_RESET Writing a '1' to this bit will reset the device, except for: SYS_CTRL_REG CLK_FREQ_TRIM_REG ... 0x0 9 R/W TIMEOUT_DISABLE Disables timeout in Power statemachine. By default, the statemachine continues if after 2 ms the blocks are not started up. This can be read back from ANA_STATUS_REG. 0x0 8 - - Reserved 0x0 7 R/W DEBUGGER_ENABL E Enable the debugger. This bit is set by the booter according to the OTP header. If not set, the SWDIO and SW_CLK can be used as gpio ports. 0x0 6 R/W OTPC_RESET_REQ Reset request for the OTP controller. 0x0 5 R/W PAD_LATCH_EN Latches the control signals of the pads for state retention in powerdown mode. 0: Control signals are retained 1: Latch is transparant, pad can be recontrolled 0x1 4 R/W OTP_COPY Enables OTP to SysRAM copy action after waking up PD_SYS 0x0 3 R/W CLK32_SOURCE Sets the clock source of the 32 kHz clock 0 = RC-oscillator 1 = 32 kHz crystal oscillator 0x0 2 R/W RET_SYSRAM Sets the development phase mode. The PD_SYS is not actually power gated (SysRAM is retained). No copy action to SysRAM is done when the system wakes up. For emulating startup time, the OTP_COPY bit still needs to be set. 0x0 1:0 R/W REMAP_ADR0 Controls which memory is located at address 0x0000 for exe- 0x0 cution. 0x0: ROM 0x1: OTP 0x2: SysRAM 0x3: RetRAM Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 R XTAL16_SETTLED Indicates that XTAL16 has had > 2 ms of settle time 0x0 6 R XTAL16_TRIM_READ Y Indicates that XTAL trimming mechanism is ready, i.e. the trimming equals CLK_FREQ_TRIM_REG. 0x1 5 R DBG_IS_UP Indicates that PD_DBG is functional 0x0 4 R DBG_IS_DOWN Indicates that PD_DBG is in power down 0x1 3 R PER_IS_UP Indicates that PD_PER is functional 0x0 2 R PER_IS_DOWN Indicates that PD_PER is in power down 0x1 1 R RAD_IS_UP Indicates that PD_RAD is functional 0x0 0 R RAD_IS_DOWN Indicates that PD_RAD is in power down 0x1 (c) 2014 Dialog Semiconductor 34 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Table 39: SYS_STAT_REG (0x50000014) DA14580 Table 38: SYS_CTRL_REG (0x50000012) Bit Mode Symbol Description Reset 7:4 R/W TRIM_TIME Defines the delay between XTAL16M enable and applying the CLK_FREQ_TRIM_REG in steps of 250 us. 0x0: apply directly 0x1: wait between 0 and 250 us 0x2: wait between 250 us and 500 us etc. (Note 1) 0xA 3:0 R/W SETTLE_TIME Defines the delay between applying CLK_FREQ_TRIM_REG and XTAL16_SETTLED in steps of 250 us. 0x0: XTAL16_SETTLED is set direcly 0x1: wait between 0 and 250 us 0x2: wait between 250 us and 500 us etc. 0x2 Note 1: DA14580 Table 40: TRIM_CTRL_REG (0x50000016) The period duration of 250 us is derived by dividing the RC16M clock signal by 4000. Consequently, the period duration may vary over temperature. Table 41: CLK_32K_REG (0x50000020) Mode Symbol Description Reset 15:13 - - Reserved 0x0 12 R/W XTAL32K_DISABLE_ AMPREG Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator. Set this bit to '1' for an external clock applied at XTAL32Kp. Keep this bit '0' with a crystal between XTAL32Kp and XTAL32Km. 0x0 11:8 R/W RC32K_TRIM Controls the frequency of the RC32K oscillator. 0x0: lowest frequency 0x7: default 0xF: highest frequency 0x7 7 R/W RC32K_ENABLE Enables the 32 kHz RC oscillator 0x1 6:3 R/W XTAL32K_CUR Bias current for the 32kHz XTAL oscillator. 0x0: minimum 0x3: default 0xF: maximum For each application there is an optimal setting for which the startup behaviour is optimal. 0x3 2:1 R/W XTAL32K_RBIAS Setting for the bias resistor of the 32 kHz XTAL oscillator. 0x0: maximum 0x3: minimum Prefered setting will be provided by Dialog. 0x2 0 R/W XTAL32K_ENABLE Enables the 32 kHz XTAL oscillator 0x0 Table 42: CLK_16M_REG (0x50000022) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9 R/W XTAL16_NOISE_FILT _ENABLE Enables noise flter in 16 MHz crystal oscillator 0x0 8 R/W XTAL16_BIAS_SH_E NABLE Enables Ibias sample/hold function in 16 MHz crystal oscillator. This bit should be set when the system wake up and reset before entering deep or extended sleep mode. 0x0 (c) 2014 Dialog Semiconductor 35 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 7:5 R/W XTAL16_CUR_SET Bias current for the 16 MHz XTAL oscillator. 0x0: minimum 0x7: maximum 0x5 4:1 R/W RC16M_TRIM Controls the frequency of the RC16M oscillator. 0x0: lowest frequency 0xF: highest frequency 0x0 0 R/W RC16M_ENABLE Enables the 16 MHz RC oscillator 0x0 DA14580 Table 42: CLK_16M_REG (0x50000022) Table 43: CLK_RCX20K_REG (0x50000024) Bit Mode Symbol Description Reset 12 R/W RCX20K_SELECT Selects RCX oscillator. 0 : RC32K oscillator 1: RCX oscillator 0 11 R/W RCX20K_ENABLE Enable the RCX oscillator 0 10 R/W RCX20K_LOWF Extra low frequency 0 9:8 R/W RCX20K_BIAS Bias control 1 7:4 R/W RCX20K_NTC Temperature control 7 3:0 R/W RCX20K_TRIM Controls the frequency of the RCX oscillator. 0x0: lowest frequency 0x7: default 0xF: highest frequency 8 Table 44: BANDGAP_REG (0x50000028) Bit Mode Symbol Description Reset 15 - - Reserved 0x0 14 R/W BGR_LOWPOWER Test-mode, do not use. It disables the bandgap core (voltages will continue for some time, but will slowely drift away) 0x0 13:10 R/W LDO_RET_TRIM (Note 2) 0x0 9:5 R/W BGR_ITRIM Current trimming for bias 0x0 4:0 R/W BGR_TRIM Trim register for bandgap 0x0 0xF is the lowest voltage, but is too low for reliable startup at high temperature in combination with extended sleep. 0xA is 100 mV higher and considered to be the lowest value which is safe to use. 0x0 or 0x1 is again 100 mV higher and 0x0 is the reset value. 0x4 is the maximum voltage. Table 45: ANA_STATUS_REG (0x5000002A) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9 R BOOST_SELECTED Indicates that DCDC is in boost mode 0x0 8 - - Reserved 0x0 7 R BANDGAP_OK Indicates that BANDGAP is OK 0x1 6 R BOOST_VBAT_OK Indicates that VBAT is above threshold while in BOOST converter mode. 0x0 5 R LDO_ANA_OK Indicates that LDO_ANA is in regulation. This LDO is used for the general-purpose ADC only 0x0 4 R LDO_VDD_OK Indicates that LDO_VDD is in regulation 0x1 3 R LDO_OTP_OK Indicates that LDO_OTP is in regulation 0x0 (c) 2014 Dialog Semiconductor 36 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Note 2: Bit Mode Symbol Description Reset 2 R VDCDC_OK Indicates that VDCDC is above threshold. 0x0 1 R VBAT1V_OK Indicates that VBAT1V is above threshold. 0x0 0 R VBAT1V_AVAILABLE Indicates that VBAT1V is available. 0x0 DA14580 Table 45: ANA_STATUS_REG (0x5000002A) Table 46: WKUP_CTRL_REG (0x50000100) Bit Mode Symbol Description Reset 15:14 - - Reserved 0x0 7 R/W WKUP_ENABLE_IRQ 0: no interrupt will be enabled 1: if the event counter reaches the value set by WKUP_COMPARE_REG an IRQ will be generated 0x0 6 R/W WKUP_SFT_KEYHIT 0: no effect 1: emulate key hit. The event counter will increment by 1 (after debouncing if enabled). First make this bit 0 before any new key hit can be sensed. 0x0 5:0 R/W WKUP_DEB_VALUE Keyboard debounce time (N*1 ms with N = 1 to 63). 0x0: no debouncing 0x1 to 0x3F: 1 ms to 63 ms debounce time 0x0 Table 47: WKUP_COMPARE_REG (0x50000102) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W COMPARE The number of events that have to be counted before the wakeup interrupt will be given 0x0 Table 48: WKUP_RESET_IRQ_REG (0x50000104) Bit Mode Symbol Description Reset 15:0 W WKUP_IRQ_RST writing any value to this register will reset the interrupt. reading always returns 0. 0x0 Table 49: WKUP_COUNTER_REG (0x50000106) Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R EVENT_VALUE This value represents the number of events that have been counted so far. It will be reset by resetting the interrupt. 0x0 Table 50: WKUP_RESET_CNTR_REG (0x50000108) Bit Mode Symbol Description Reset 15:0 W WKUP_CNTR_RST writing any value to this register will reset the event counter 0x0 Table 51: WKUP_SELECT_P0_REG (0x5000010A) Bit Mode Symbol Description Reset 7:0 R/W WKUP_SELECT_P0 0: input P0x is not enabled for wakeup event counter 1: input P0x is enabled for wakeup event counter 0x0 (c) 2014 Dialog Semiconductor 37 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 5:0 R/W WKUP_SELECT_P1 0: input P1x is not enabled for wakeup event counter 1: input P1x is enabled for wakeup event counter 0x0 DA14580 Table 52: WKUP_SELECT_P1_REG (0x5000010C) Table 53: WKUP_SELECT_P2_REG (0x5000010E) Bit Mode Symbol Description Reset 9:0 R/W WKUP_SELECT_P2 0: input P2x is not enabled for wakeup event counter 1: input P2x is enabled for wakeup event counter 0x0 Table 54: WKUP_SELECT_P3_REG (0x50000110) Bit Mode Symbol Description Reset 7:0 R/W WKUP_SELECT_P3 0: input P3x is not enabled for wakeup event counter 1: input P3x is enabled for wakeup event counter 0x0 Table 55: WKUP_POL_P0_REG (0x50000112) Bit Mode Symbol Description Reset 7:0 R/W WKUP_POL_P0 0: enabled input P0x will increment the event counter if that input goes high 1: enabled input P0x will increment the event counter if that input goes low 0x0 Table 56: WKUP_POL_P1_REG (0x50000114) Bit Mode Symbol Description Reset 5:0 R/W WKUP_POL_P1 0: enabled input P1x will increment the event counter if that input goes high 1: enabled input P1x will increment the event counter if that input goes low 0x0 Table 57: WKUP_POL_P2_REG (0x50000116) Mode Symbol Description Reset 9:0 R/W WKUP_POL_P2 0: enabled input P2x will increment the event counter if that input goes high 1: enabled input P2x will increment the event counter if that input goes low 0x0 Table 58: WKUP_POL_P3_REG (0x50000118) Bit Mode Symbol Description Reset 7:0 R/W WKUP_POL_P3 0: enabled input P3x will increment the event counter if that input goes high 1: enabled input P3x will increment the event counter if that input goes low 0x0 Table 59: QDEC_CTRL_REG (0x50000200) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 38 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 9:3 R/W QD_IRQ_THRES The number of events on either counter (X or Y) that need to be reached before an interrupt is generated. If 0 is written, then threshold is considered to be 1. 0x2 2 R QD_IRQ_STATUS Interrupt Status. If 1 an interrupt has occured. 0x0 1 R/W QD_IRQ_CLR Writing 1 to this bit clears the interrupt. This bit is autocleared 0x0 0 R/W QD_IRQ_MASK 0: interrupt is masked 1: interrupt is enabled 0x0 DA14580 Table 59: QDEC_CTRL_REG (0x50000200) Table 60: QDEC_XCNT_REG (0x50000202) Bit Mode Symbol Description Reset 15:0 R X_COUNTER Contains a signed value of the events. Zero when channel is disabled 0x0 Table 61: QDEC_YCNT_REG (0x50000204) Bit Mode Symbol Description Reset 15:0 R Y_COUNTER Contains a signed value of the events. Zero when channel is disabled 0x0 Table 62: QDEC_CLOCKDIV_REG (0x50000206) Bit Mode Symbol Description Reset 9:0 R/W CLOCK_DIVIDER Contains the number of the input clock cycles minus one, that are required to generate one logic clock cycle. 0x0 Table 63: QDEC_CTRL2_REG (0x50000208) Mode Symbol Description Reset 15:12 - - Reserved 0 11:8 R/W CHZ_PORT_SEL Defines which GPIOs are mapped on Channel Z 0: none 1: P0[0] -> CHZ_A, P0[1] -> CHZ_B 2: P0[2] -> CHZ_A, P0[3] -> CHZ_B 3: P0[4] -> CHZ_A, P0[5] -> CHZ_B 4: P0[6] -> CHZ_A, P0[7] -> CHZ_B 5: P1[0] -> CHZ_A, P1[1] -> CHZ_B 6: P1[2] -> CHZ_A, P1[3] -> CHZ_B 7: P2[3] -> CHZ_A, P2[4] -> CHZ_B 8: P2[5] -> CHZ_A, P2[6] -> CHZ_B 9: P2[7] -> CHZ_A, P2[8] -> CHZ_B 10: P2[9] -> CHZ_A, P2[0] -> CHZ_B 11..15: None 0 (c) 2014 Dialog Semiconductor 39 Low Power Bluetooth Smart SoC Bit Final - January 29, 2015 v3.1 Bit Mode Symbol Description Reset 7:4 R/W CHY_PORT_SEL Defines which GPIOs are mapped on Channel Y 0: none 1: P0[0] -> CHY_A, P0[1] -> CHY_B 2: P0[2] -> CHY_A, P0[3] -> CHY_B 3: P0[4] -> CHY_A, P0[5] -> CHY_B 4: P0[6] -> CHY_A, P0[7] -> CHY_B 5: P1[0] -> CHY_A, P1[1] -> CHY_B 6: P1[2] -> CHY_A, P1[3] -> CHY_B 7: P2[3] -> CHY_A, P2[4] -> CHY_B 8: P2[5] -> CHY_A, P2[6] -> CHY_B 9: P2[7] -> CHY_A, P2[8] -> CHY_B 10: P2[9] -> CHY_A, P2[0] -> CHY_B 11..15: None 0 3:0 R/W CHX_PORT_SEL Defines which GPIOs are mapped on Channel X 0: none 1: P0[0] -> CHX_A, P0[1] -> CHX_B 2: P0[2] -> CHX_A, P0[3] -> CHX_B 3: P0[4] -> CHX_A, P0[5] -> CHX_B 4: P0[6] -> CHX_A, P0[7] -> CHX_B 5: P1[0] -> CHX_A, P1[1] -> CHX_B 6: P1[2] -> CHX_A, P1[3] -> CHX_B 7: P2[3] -> CHX_A, P2[4] -> CHX_B 8: P2[5] -> CHX_A, P2[6] -> CHX_B 9: P2[7] -> CHX_A, P2[8] -> CHX_B 10: P2[9] -> CHX_A, P2[0] -> CHX_B 11..15: None 0 DA14580 Table 63: QDEC_CTRL2_REG (0x50000208) Table 64: QDEC_ZCNT_REG (0x5000020A) Bit Mode Symbol Description Reset 15:0 R Z_COUNTER Contains a signed value of the events. Zero when channel is disabled 0 Table 65: UART_RBR_THR_DLL_REG (0x50001000) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 40 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W RBR_THR_DLL Receive Buffer Register: This register contains the data byte 0x0 received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Transmit Holding Register: This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Divisor Latch (Low): This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor) Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. Reset Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 R/W PTIME_DLH7 Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[7] of the 8 bit DLH register. 0x0 6:4 - - Reserved 0x0 3 R/W EDSSI_DLH3 Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[3] of the 8 bit DLH register 0x0 2 R/W ELSI_DHL2 Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[2] of the 8 bit DLH register. 0x0 (c) 2014 Dialog Semiconductor 41 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Table 66: UART_IER_DLH_REG (0x50001004) DA14580 Table 65: UART_RBR_THR_DLL_REG (0x50001000) Bit Mode Symbol Description 1 R/W ETBEI_DLH1 Interrupt Enable Register: ETBEI, Enable Transmit Holding 0x0 Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[1] of the 8 bit DLH register. Reset 0 R/W ERBFI_DLH0 Interrupt Enable Register: ERBFI, Enable Received Data 0x0 Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled Divisor Latch (High): Bit[0] of the 8 bit DLH register. DA14580 Table 66: UART_IER_DLH_REG (0x50001004) Table 67: UART_IIR_FCR_REG (0x50001008) Mode Symbol Description Reset 15:0 R/W IIR_FCR Interrupt Identification Register, reading this register; FIFO Control Register, writing to this register. Interrupt Identification Register: Bits[7:6], FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disabled. 00 = disabled. 11 = enabled. Bits[3:0], Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status. 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. Bits[7:6], RCVR Trigger (or RT):. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full Bits[5:4], TX Empty Trigger (or TET): This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/ 2 full Bit[3], DMA Mode (or DMAM): This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 Bit[2], XMIT FIFO Reset (or XFIFOR): This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. Bit[1], RCVR FIFO Reset (or RFIFOR): This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. Bit[0], FIFO Enable (or FIFOE): This enables/ disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFO's will be reset. 0x0 (c) 2014 Dialog Semiconductor 42 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 R/W UART_DLAB Divisor Latch Access Bit. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. 0x0 6 R/W UART_BC Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. 0x0 5 - - Reserved 0x0 4 R/W UART_EPS Even Parity Select. 0x0 This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. 3 R/W UART_PEN Parity Enable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled 2 R/W UART_STOP Number of stop bits. 0x0 This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit 1:0 R/W UART_DLS Data Length Select. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits 0x0 Bit Mode Symbol Description Reset 15:7 - - Reserved 0x0 43 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC 0x0 Table 69: UART_MCR_REG (0x50001010) (c) 2014 Dialog Semiconductor DA14580 Table 68: UART_LCR_REG (0x5000100C) Mode Symbol Description Reset 6 R/W UART_SIRE SIR Mode Enable. This is used to enable/disable the IrDA SIR Mode features as described in "IrDA 1.0 SIR Protocol" on page 53. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled 0x0 5 R/W UART_AFCE Auto Flow Control Enable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, hardware Auto Flow Control is enabled via CTS and RTS. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled 0x0 4 R/W UART_LB LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line. 0x0 3 R/W UART_OUT2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. 0x0 2 R/W UART_OUT1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. 0x0 (c) 2014 Dialog Semiconductor 44 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit DA14580 Table 69: UART_MCR_REG (0x50001010) Bit Mode Symbol Description Reset 1 R/W UART_RTS Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto Flow Control is disabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high. When Auto Flow Control is enabled (MCR[5] set to one) and FIFOs are enabled (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive (high) while the value of this location is internally looped back to an input. 0x0 0 - - Reserved 0x0 DA14580 Table 69: UART_MCR_REG (0x50001010) Table 70: UART_LSR_REG (0x50001014) Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 R UART_RFE Receiver FIFO Error bit. This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. 0x0 6 R UART_TEMT Transmitter Empty bit. If FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. 0x1 5 R UART_THRE Transmit Holding Register Empty bit. If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. 0x1 (c) 2014 Dialog Semiconductor 45 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Mode Symbol Description Reset 4 R UART_B1 Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. 0x0 3 R UART_FE Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. 0x0 2 R UART_PE Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. 0x0 (c) 2014 Dialog Semiconductor 46 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit DA14580 Table 70: UART_LSR_REG (0x50001014) Bit Mode Symbol Description Reset 1 R UART_OE Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. 0x0 0 R UART_DR Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. 0x0 DA14580 Table 70: UART_LSR_REG (0x50001014) Table 71: UART_MSR_REG (0x50001018) Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 R UART_DCD Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). 0x0 6 R UART_R1 Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). 0x0 5 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 47 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Mode Symbol Description Reset 4 R UART_CTS Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the UART Ctrl. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS). 0x0 3 R UART_DDCD Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. 0x0 2 R UART_TERI Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. 0x0 1 - - Reserved 0x0 0 R UART_DCTS Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on cts_n since last read of MSR 1 = change on cts_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. 0x0 Table 72: UART_SCR_REG (0x5000101C) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W UART_SCRATCH_PA D This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl. 0x0 Table 73: UART_LPDLL_REG (0x50001020) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 48 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit DA14580 Table 71: UART_MSR_REG (0x50001018) Bit Mode Symbol Description Reset 7:0 R/W UART_LPDLL This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may be accessed only when the DLAB bit (LCR[7]) is set. The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest UART Ctrl clock should be allowed to pass before transmitting or receiving data. 0x0 DA14580 Table 73: UART_LPDLL_REG (0x50001020) Table 74: UART_LPDLH_REG (0x50001024) Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W UART_LPDLH This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may be accessed only when the DLAB bit (LCR[7]) is set. The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest UART Ctrl clock should be allowed to pass before transmitting or receiving data. 0x0 Table 75: UART_SRBR_STHR0_REG (0x50001030) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 49 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 75: UART_SRBR_STHR0_REG (0x50001030) Table 76: UART_SRBR_STHR1_REG (0x50001034) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 50 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 76: UART_SRBR_STHR1_REG (0x50001034) Table 77: UART_SRBR_STHR2_REG (0x50001038) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 51 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 77: UART_SRBR_STHR2_REG (0x50001038) Table 78: UART_SRBR_STHR3_REG (0x5000103C) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 52 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 78: UART_SRBR_STHR3_REG (0x5000103C) Table 79: UART_SRBR_STHR4_REG (0x50001040) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 53 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 79: UART_SRBR_STHR4_REG (0x50001040) Table 80: UART_SRBR_STHR5_REG (0x50001044) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 54 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 80: UART_SRBR_STHR5_REG (0x50001044) Table 81: UART_SRBR_STHR6_REG (0x50001048) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 55 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 81: UART_SRBR_STHR6_REG (0x50001048) Table 82: UART_SRBR_STHR7_REG (0x5000104C) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 56 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 82: UART_SRBR_STHR7_REG (0x5000104C) Table 83: UART_SRBR_STHR8_REG (0x50001050) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 57 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 83: UART_SRBR_STHR8_REG (0x50001050) Table 84: UART_SRBR_STHR9_REG (0x50001054) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 58 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 84: UART_SRBR_STHR9_REG (0x50001054) Table 85: UART_SRBR_STHR10_REG (0x50001058) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 59 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 85: UART_SRBR_STHR10_REG (0x50001058) Table 86: UART_SRBR_STHR11_REG (0x5000105C) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 60 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 86: UART_SRBR_STHR11_REG (0x5000105C) Table 87: UART_SRBR_STHR12_REG (0x50001060) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 61 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 87: UART_SRBR_STHR12_REG (0x50001060) Table 88: UART_SRBR_STHR13_REG (0x50001064) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 62 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 88: UART_SRBR_STHR13_REG (0x50001064) Table 89: UART_SRBR_STHR14_REG (0x50001068) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 63 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 89: UART_SRBR_STHR14_REG (0x50001068) Table 90: UART_SRBR_STHR15_REG (0x5000106C) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 64 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 90: UART_SRBR_STHR15_REG (0x5000106C) Table 91: UART_USR_REG (0x5000107C) Mode Symbol Description Reset 15:5 - - Reserved 0x0 4 R UART_RFF Receive FIFO Full. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. 0x0 3 R UART_RFNE Receive FIFO Not Empty. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. 0x0 2 R UART_TFE Transmit FIFO Empty. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. 0x1 (c) 2014 Dialog Semiconductor 65 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 1 R UART_TFNF Transmit FIFO Not Full. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. 0x1 0 - - Reserved 0x0 DA14580 Table 91: UART_USR_REG (0x5000107C) Table 92: UART_TFL_REG (0x50001080) Bit Mode Symbol Description Reset 15:0 R UART_TRANSMIT_FI FO_LEVEL Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. 0x0 Table 93: UART_RFL_REG (0x50001084) Bit Mode Symbol Description Reset 15:0 R UART_RECEIVE_FIF O_LEVEL Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. 0x0 Table 94: UART_SRR_REG (0x50001088) Mode Symbol Description Reset 15:3 - - Reserved 0x0 2 W UART_XFR XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 0x0 1 W UART_RFR RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 0x0 0 W UART_UR UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. 0x0 Table 95: UART_SRTS_REG (0x5000108C) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 66 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 0 R/W UART_SHADOW_RE QUEST_TO_SEND Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to perform a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART Ctrl is ready to exchange data. When Auto Flow Control is disabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. When Auto Flow Control is enabled (MCR[5] = 1) and FIFOs are enabled (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. 0x0 DA14580 Table 95: UART_SRTS_REG (0x5000108C) Table 96: UART_SBCR_REG (0x50001090) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R/W UART_SHADOW_BR EAK_CONTROL Shadow Break Control Bit. 0x0 This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. Table 97: UART_SDMAM_REG (0x50001094) Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R/W UART_SHADOW_DM A_MODE Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 0x0 Table 98: UART_SFE_REG (0x50001098) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 67 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 0 R/W UART_SHADOW_FIF O_ENABLE Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. 0x0 DA14580 Table 98: UART_SFE_REG (0x50001098) Table 99: UART_SRT_REG (0x5000109C) Bit Mode Symbol Description Reset 15:2 - - Reserved 0x0 1:0 R/W UART_SHADOW_RC VR_TRIGGER Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO A1/4 full 10 = FIFO A1/2 full 11 = FIFO 2 less than full 0x0 Table 100: UART_STET_REG (0x500010A0) Mode Symbol Description Reset 15:2 - - Reserved 0x0 1:0 R/W UART_SHADOW_TX _EMPTY_TRIGGER Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO A1/4 full 11 = FIFO A1/2 full 0x0 Table 101: UART_HTX_REG (0x500010A4) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 68 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 0 R/W UART_HALT_TX This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. 0x0 DA14580 Table 101: UART_HTX_REG (0x500010A4) Table 102: UART_CPR_REG (0x500010F4) Bit Mode Symbol Description Reset 15:0 R CPR Component Parameter Register 0x0 Table 103: UART_UCV_REG (0x500010F8) Bit Mode Symbol Description Reset 15:0 R UCV Component Version 0x333038 2A Table 104: UART_CTR_REG (0x500010FC) Bit Mode Symbol Description Reset 15:0 R CTR Component Type Register 0x445701 10 Table 105: UART2_RBR_THR_DLL_REG (0x50001100) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 69 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W RBR_THR_DLL Receive Buffer Register: This register contains the data byte 0x0 received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Transmit Holding Register: This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Divisor Latch (Low): This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor) Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. Reset Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 R/W PTIME_DLH7 Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[7] of the 8 bit DLH register. 0x0 6:4 - - Reserved 0x0 3 R/W EDSSI_DLH3 Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[3] of the 8 bit DLH register 0x0 2 R/W ELSI_DHL2 Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[2] of the 8 bit DLH register. 0x0 (c) 2014 Dialog Semiconductor 70 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Table 106: UART2_IER_DLH_REG (0x50001104) DA14580 Table 105: UART2_RBR_THR_DLL_REG (0x50001100) Bit Mode Symbol Description 1 R/W ETBEI_DLH1 Interrupt Enable Register: ETBEI, Enable Transmit Holding 0x0 Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[1] of the 8 bit DLH register. Reset 0 R/W ERBFI_DLH0 Interrupt Enable Register: ERBFI, Enable Received Data 0x0 Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled Divisor Latch (High): Bit[0] of the 8 bit DLH register. DA14580 Table 106: UART2_IER_DLH_REG (0x50001104) Table 107: UART2_IIR_FCR_REG (0x50001108) Mode Symbol Description Reset 15:0 R/W IIR_FCR Interrupt Identification Register, reading this register; FIFO Control Register, writing to this register. Interrupt Identification Register: Bits[7:6], FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disabled. 00 = disabled. 11 = enabled. Bits[3:0], Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status. 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. Bits[7:6], RCVR Trigger (or RT):. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full Bits[5:4], TX Empty Trigger (or TET): This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/ 2 full Bit[3], DMA Mode (or DMAM): This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 Bit[2], XMIT FIFO Reset (or XFIFOR): This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. Bit[1], RCVR FIFO Reset (or RFIFOR): This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. Bit[0], FIFO Enable (or FIFOE): This enables/ disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFO's will be reset. 0x0 (c) 2014 Dialog Semiconductor 71 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 R/W UART_DLAB Divisor Latch Access Bit. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. 0x0 6 R/W UART_BC Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. 0x0 5 - - Reserved 0x0 4 R/W UART_EPS Even Parity Select. 0x0 This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. 3 R/W UART_PEN Parity Enable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled 2 R/W UART_STOP Number of stop bits. 0x0 This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit 1:0 R/W UART_DLS Data Length Select. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits 0x0 Bit Mode Symbol Description Reset 15:7 - - Reserved 0x0 72 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC 0x0 Table 109: UART2_MCR_REG (0x50001110) (c) 2014 Dialog Semiconductor DA14580 Table 108: UART2_LCR_REG (0x5000110C) Mode Symbol Description Reset 6 R/W UART_SIRE SIR Mode Enable. This is used to enable/disable the IrDA SIR Mode features as described in "IrDA 1.0 SIR Protocol" on page 53. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled 0x0 5 R/W UART_AFCE Auto Flow Control Enable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, hardware Auto Flow Control is enabled via CTS and RTS. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled 0x0 4 R/W UART_LB LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line. 0x0 3 R/W UART_OUT2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. 0x0 2 R/W UART_OUT1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. 0x0 (c) 2014 Dialog Semiconductor 73 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit DA14580 Table 109: UART2_MCR_REG (0x50001110) Bit Mode Symbol Description Reset 1 R/W UART_RTS Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto Flow Control is disabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high. When Auto Flow Control is enabled (MCR[5] set to one) and FIFOs are enabled (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive (high) while the value of this location is internally looped back to an input. 0x0 0 - - Reserved 0x0 DA14580 Table 109: UART2_MCR_REG (0x50001110) Table 110: UART2_LSR_REG (0x50001114) Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 R UART_RFE Receiver FIFO Error bit. This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. 0x0 6 R UART_TEMT Transmitter Empty bit. If FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. 0x1 5 R UART_THRE Transmit Holding Register Empty bit. If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. 0x1 (c) 2014 Dialog Semiconductor 74 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Mode Symbol Description Reset 4 R UART_B1 Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. 0x0 3 R UART_FE Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. 0x0 2 R UART_PE Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. 0x0 (c) 2014 Dialog Semiconductor 75 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit DA14580 Table 110: UART2_LSR_REG (0x50001114) Bit Mode Symbol Description Reset 1 R UART_OE Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. 0x0 0 R UART_DR Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. 0x0 DA14580 Table 110: UART2_LSR_REG (0x50001114) Table 111: UART2_MSR_REG (0x50001118) Mode Symbol Description Reset 15:8 - - Reserved 0x0 7 R UART_DCD Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). 0x0 6 R UART_R1 Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). 0x0 5 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 76 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Mode Symbol Description Reset 4 R UART_CTS Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the UART Ctrl. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS). 0x0 3 R UART_DDCD Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. 0x0 2 R UART_TERI Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. 0x0 1 - - Reserved 0x0 0 R UART_DCTS Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on cts_n since last read of MSR 1 = change on cts_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. 0x0 Table 112: UART2_SCR_REG (0x5000111C) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W UART_SCRATCH_PA D This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl. 0x0 Table 113: UART2_LPDLL_REG (0x50001120) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 77 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit DA14580 Table 111: UART2_MSR_REG (0x50001118) Bit Mode Symbol Description Reset 7:0 R/W UART_LPDLL This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may be accessed only when the DLAB bit (LCR[7]) is set. The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest UART Ctrl clock should be allowed to pass before transmitting or receiving data. 0x0 DA14580 Table 113: UART2_LPDLL_REG (0x50001120) Table 114: UART2_LPDLH_REG (0x50001124) Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W UART_LPDLH This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may be accessed only when the DLAB bit (LCR[7]) is set. The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest UART Ctrl clock should be allowed to pass before transmitting or receiving data. 0x0 Table 115: UART2_SRBR_STHR0_REG (0x50001130) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 78 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 115: UART2_SRBR_STHR0_REG (0x50001130) Table 116: UART2_SRBR_STHR1_REG (0x50001134) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 79 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 116: UART2_SRBR_STHR1_REG (0x50001134) Table 117: UART2_SRBR_STHR2_REG (0x50001138) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 80 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 117: UART2_SRBR_STHR2_REG (0x50001138) Table 118: UART2_SRBR_STHR3_REG (0x5000113C) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 81 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 118: UART2_SRBR_STHR3_REG (0x5000113C) Table 119: UART2_SRBR_STHR4_REG (0x50001140) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 82 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 119: UART2_SRBR_STHR4_REG (0x50001140) Table 120: UART2_SRBR_STHR5_REG (0x50001144) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 83 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 120: UART2_SRBR_STHR5_REG (0x50001144) Table 121: UART2_SRBR_STHR6_REG (0x50001148) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 84 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 121: UART2_SRBR_STHR6_REG (0x50001148) Table 122: UART2_SRBR_STHR7_REG (0x5000114C) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 85 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 122: UART2_SRBR_STHR7_REG (0x5000114C) Table 123: UART2_SRBR_STHR8_REG (0x50001150) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 86 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 123: UART2_SRBR_STHR8_REG (0x50001150) Table 124: UART2_SRBR_STHR9_REG (0x50001154) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 87 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 124: UART2_SRBR_STHR9_REG (0x50001154) Table 125: UART2_SRBR_STHR10_REG (0x50001158) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 88 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 125: UART2_SRBR_STHR10_REG (0x50001158) Table 126: UART2_SRBR_STHR11_REG (0x5000115C) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 89 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 126: UART2_SRBR_STHR11_REG (0x5000115C) Table 127: UART2_SRBR_STHR12_REG (0x50001160) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 90 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 127: UART2_SRBR_STHR12_REG (0x50001160) Table 128: UART2_SRBR_STHR13_REG (0x50001164) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 91 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 128: UART2_SRBR_STHR13_REG (0x50001164) Table 129: UART2_SRBR_STHR14_REG (0x50001168) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 92 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 129: UART2_SRBR_STHR14_REG (0x50001168) Table 130: UART2_SRBR_STHR15_REG (0x5000116C) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 93 Final - January 29, 2015 v3.1 Bit Mode Symbol Description 7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register 0x0 for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Reset DA14580 Table 130: UART2_SRBR_STHR15_REG (0x5000116C) Table 131: UART2_USR_REG (0x5000117C) Mode Symbol Description Reset 15:5 - - Reserved 0x0 4 R UART_RFF Receive FIFO Full. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. 0x0 3 R UART_RFNE Receive FIFO Not Empty. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. 0x0 2 R UART_TFE Transmit FIFO Empty. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. 0x1 (c) 2014 Dialog Semiconductor 94 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 1 R UART_TFNF Transmit FIFO Not Full. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. 0x1 0 - - Reserved 0x0 DA14580 Table 131: UART2_USR_REG (0x5000117C) Table 132: UART2_TFL_REG (0x50001180) Bit Mode Symbol Description Reset 15:0 R UART_TRANSMIT_FI FO_LEVEL Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. 0x0 Table 133: UART2_RFL_REG (0x50001184) Bit Mode Symbol Description Reset 15:0 R UART_RECEIVE_FIF O_LEVEL Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. 0x0 Table 134: UART2_SRR_REG (0x50001188) Mode Symbol Description Reset 15:3 - - Reserved 0x0 2 W UART_XFR XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 0x0 1 W UART_RFR RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 0x0 0 W UART_UR UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. 0x0 Table 135: UART2_SRTS_REG (0x5000118C) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 95 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 0 R/W UART_SHADOW_RE QUEST_TO_SEND Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to perform a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART Ctrl is ready to exchange data. When Auto Flow Control is disabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. When Auto Flow Control is enabled (MCR[5] = 1) and FIFOs are enabled (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. 0x0 DA14580 Table 135: UART2_SRTS_REG (0x5000118C) Table 136: UART2_SBCR_REG (0x50001190) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R/W UART_SHADOW_BR EAK_CONTROL Shadow Break Control Bit. 0x0 This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. Table 137: UART2_SDMAM_REG (0x50001194) Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R/W UART_SHADOW_DM A_MODE Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 0x0 Table 138: UART2_SFE_REG (0x50001198) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 96 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 0 R/W UART_SHADOW_FIF O_ENABLE Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. 0x0 DA14580 Table 138: UART2_SFE_REG (0x50001198) Table 139: UART2_SRT_REG (0x5000119C) Bit Mode Symbol Description Reset 15:2 - - Reserved 0x0 1:0 R/W UART_SHADOW_RC VR_TRIGGER Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO A1/4 full 10 = FIFO A1/2 full 11 = FIFO 2 less than full 0x0 Table 140: UART2_STET_REG (0x500011A0) Mode Symbol Description Reset 15:2 - - Reserved 0x0 1:0 R/W UART_SHADOW_TX _EMPTY_TRIGGER Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO A1/4 full 11 = FIFO A1/2 full 0x0 Table 141: UART2_HTX_REG (0x500011A4) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 97 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 0 R/W UART_HALT_TX This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. 0x0 DA14580 Table 141: UART2_HTX_REG (0x500011A4) Table 142: UART2_CPR_REG (0x500011F4) Bit Mode Symbol Description Reset 15:0 R CPR Component Parameter Register 0x0 Table 143: UART2_UCV_REG (0x500011F8) Bit Mode Symbol Description Reset 15:0 R UCV Component Version 0x333038 2A Table 144: UART2_CTR_REG (0x500011FC) Bit Mode Symbol Description Reset 15:0 R CTR Component Type Register 0x445701 10 Table 145: SPI_CTRL_REG (0x50001200) Mode Symbol Description Reset 15 R/W SPI_EN_CTRL 0 = SPI_EN pin disabled in slave mode. Pin SPI_EN is don't care. 1 = SPI_EN pin enabled in slave mode. 0x0 14 R/W SPI_MINT 0 = Disable SPI_INT_BIT to ICU 1 = Enable SPI_INT_BIT to ICU. Note that the SPI_INT interrupt is shared with AD_INT interrupt 0x0 13 R SPI_INT_BIT 0 = RX Register or FIFO is empty. 1 = SPI interrupt. Data has been transmitted and receivedMust be reset by SW by writing to SPI_CLEAR_INT_REG. 0x0 12 R SPI_DI Returns the actual value of pin SPI_DIN (delayed with two internal SPI clock cycles) 0x0 11 R SPI_TXH 0 = TX-FIFO is not full, data can be written. 1 = TX-FIFO is full, data can not be written. 0x0 10 R/W SPI_FORCE_DO 0 = normal operation 1 = Force SPIDO output level to value of SPI_DO. 0x0 9 R/W SPI_RST 0 = normal operation 1 = Reset SPI. Same function as SPI_ON except that internal clock remain active. 0x0 8:7 R/W SPI_WORD 00 = 8 bits mode, only SPI_RX_TX_REG0 used 01 = 16 bit mode, only SPI_RX_TX_REG0 used 10 = 32 bits mode, SPI_RX_TX_REG0 & SPI_RX_TX_REG1 used 11 = 9 bits mode. Only valid in master mode. 0x0 (c) 2014 Dialog Semiconductor 98 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 6 R/W SPI_SMN Master/slave mode 0 = Master, 1 = Slave(SPI1 only) 0x0 5 R/W SPI_DO Pin SPI_DO output level when SPI is idle or when SPI_FORCE_DO=1 0x0 4:3 R/W SPI_CLK Select SPI_CLK clock frequency in master mode:00 = (XTAL) / (CLK_PER_REG *8) 01 = (XTAL) / (CLK_PER_REG *4) 10 = (XTAL) / (CLK_PER_REG *2) 11 = (XTAL) / (CLK_PER_REG *14) 0x0 2 R/W SPI_POL Select SPI_CLK polarity. 0 = SPI_CLK is initially low. 1 = SPI_CLK is initially high. 0x0 1 R/W SPI_PHA Select SPI_CLK phase. See functional timing diagrams in SPI chapter 0x0 0 R/W SPI_ON 0 = SPI Module switched off (power saving). Everything is reset except SPI_CTRL_REG0 and SPI_CTRL_REG1. When this bit is cleared the SPI will remain active in master mode until the shift register and holding register are both empty. 1 = SPI Module switched on. Should only be set after all control bits have their desired values. So two writes are needed! 0x0 DA14580 Table 145: SPI_CTRL_REG (0x50001200) Table 146: SPI_RX_TX_REG0 (0x50001202) Bit Mode Symbol Description Reset 15:0 R0/W SPI_DATA0 Write: SPI_TX_REG0 output register 0 (TX-FIFO) Read: SPI_RX_REG0 input register 0 (RX-FIFO) In 8 or 9 bits mode bits 15 to 8 are not used, they contain old data. 0x0 Table 147: SPI_RX_TX_REG1 (0x50001204) Mode Symbol Description Reset 15:0 R0/W SPI_DATA1 Write: SPI_TX_REG1 output register 1 (MSB's of TX-FIFO) Read: SPI_RX_REG1 input register 1 (MSB's of RX-FIFO) In 8 or 9 or 16 bits mode bits this register is not used. 0x0 Table 148: SPI_CLEAR_INT_REG (0x50001206) Bit Mode Symbol Description Reset 15:0 R0/W SPI_CLEAR_INT Writing any value to this register will clear the SPI_CTRL_REG[SPI_INT_BIT] Reading returns 0. 0x0 Table 149: SPI_CTRL_REG1 (0x50001208) Bit Mode Symbol Description Reset 15:5 - - Reserved 0x0 4 R/W SPI_9BIT_VAL Determines the value of the first bit in 9 bits SPI mode. 0x0 (c) 2014 Dialog Semiconductor 99 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 3 R SPI_BUSY 0 = The SPI is not busy with a transfer. This means that either no TX-data is available or that the transfers have been suspended due to a full RX-FIFO. The SPIx_CTRL_REG0[SPI_INT_BIT] can be used to distinguish between these situations. 1 = The SPI is busy with a transfer. 0x0 2 R/W SPI_PRIORITY 0 = The SPI has low priority, the DMA request signals are reset after the corresponding acknowledge. 1 = The SPI has high priority, DMA request signals remain active until the FIFOS are filled/emptied, so the DMA holds the AHB bus. 0x0 1:0 R/W SPI_FIFO_MODE 0: TX-FIFO and RX-FIFO used (Bidirectional mode). 1: RX-FIFO used (Read Only Mode) TX-FIFO single depth, no flow control 2: TX-FIFO used (Write Only Mode), RX-FIFO single depth, no flow control 3: No FIFOs used (backwards compatible mode) 0x3 DA14580 Table 149: SPI_CTRL_REG1 (0x50001208) Table 150: I2C_CON_REG (0x50001300) Mode Symbol Description Reset 15:7 - - Reserved 0x0 6 R/W I2C_SLAVE_DISABLE Slave enabled or disabled after reset is applied, which means software does not have to configure the slave. 0=slave is enabled 1=slave is disabled Software should ensure that if this bit is written with '0', then bit 0 should also be written with a '0'. 0x1 5 R/W I2C_RESTART_EN Determines whether RESTART conditions may be sent when acting as a master 0= disable 1=enable 0x1 4 R/W I2C_10BITADDR_MA STER Controls whether the controller starts its transfers in 7- or 10bit addressing mode when acting as a master. 0= 7-bit addressing 1= 10-bit addressing 0x1 3 R/W I2C_10BITADDR_SLA VE When acting as a slave, this bit controls whether the controller responds to 7- or 10-bit addresses. 0= 7-bit addressing 1= 10-bit addressing 0x1 2:1 R/W I2C_SPEED These bits control at which speed the controller operates. 1= standard mode (100 kbit/s) 2= fast mode (400 kbit/s) 0x2 0 R/W I2C_MASTER_MODE This bit controls whether the controller master is enabled. 0= master disabled 1= master enabled Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. 0x1 Table 151: I2C_TAR_REG (0x50001304) Bit Mode Symbol Description Reset 15:12 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 100 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description 11 R/W SPECIAL This bit indicates whether software performs a General Call or 0x0 START BYTE command. 0: ignore bit 10 GC_OR_START and use IC_TAR normally 1: perform special I2C command as specified in GC_OR_START bit Reset 10 R/W GC_OR_START If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a 0x0 General Call or START byte command is to be performed by the controller. 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The controller remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. 1: START BYTE 9:0 R/W IC_TAR This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. Note: If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave 0x55 DA14580 Table 151: I2C_TAR_REG (0x50001304) Table 152: I2C_SAR_REG (0x50001308) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:0 R/W IC_SAR The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. 0x55 Table 153: I2C_DATA_CMD_REG (0x50001310) Mode Symbol Description Reset 15:9 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 101 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description 8 R/W CMD This bit controls whether a read or a write is performed. This 0x0 bit does not control the direction when the I2C Ctrl acts as a slave. It controls only the direction when it acts as a master. 1 = Read 0 = Write When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a "don't care" because writes to this register are not required. In slave-transmitter mode, a "0" indicates that CPU data is to be transmitted and as DAT or IC_DATA_CMD[7:0]. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the I2C_RAW_INTR_STAT_REG), unless bit 11 (SPECIAL) in the I2C_TAR register has been cleared. If a "1" is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. NOTE: It is possible that while attempting a master I2C read transfer on the controller, a RD_REQ interrupt may have occurred simultaneously due to a remote I2C master addressing the controller. In this type of scenario, it ignores the I2C_DATA_CMD write, generates a TX_ABRT interrupt, and waits to service the RD_REQ interrupt Reset 7:0 R/W DAT This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the controller. However, when you read this register, these bits return the value of data received on the controller's interface. DA14580 Table 153: I2C_DATA_CMD_REG (0x50001310) 0x0 Table 154: I2C_SS_SCL_HCNT_REG (0x50001314) Mode Symbol Description 15:0 R/W IC_SS_SCL_HCNT This register must be set before any I2C bus transaction can 0x48 take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. NOTE: This register must not be programmed to a value higher than 65525, because the controller uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. (c) 2014 Dialog Semiconductor Reset 102 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 15:0 R/W IC_SS_SCL_LCNT This register must be set before any I2C bus transaction can 0x4F take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. DA14580 Table 155: I2C_SS_SCL_LCNT_REG (0x50001318) Table 156: I2C_FS_SCL_HCNT_REG (0x5000131C) Bit Mode Symbol Description Reset 15:0 R/W IC_FS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast speed. It is used in highspeed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. 0x8 Table 157: I2C_FS_SCL_LCNT_REG (0x50001320) Mode Symbol Description Reset 15:0 R/W IC_FS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low-period count for fast speed. It is used in highspeed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the controller. The lower byte must be programmed first. Then the upper byte is programmed. 0x17 Table 158: I2C_INTR_STAT_REG (0x5000132C) Bit Mode Symbol Description Reset 15:12 - - Reserved 0x0 11 R R_GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. The controller stores the received data in the Rx buffer. 0x0 10 R R_START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 0x0 9 R R_STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 0x0 (c) 2014 Dialog Semiconductor 103 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Mode Symbol Description Reset 8 R R_ACTIVITY This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 0x0 7 R R_RX_DONE When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 0x0 6 R R_TX_ABRT This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a "transmit abort". When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 0x0 5 R R_RD_REQ This bit is set to 1 when the controller is acting as a slave and 0x0 another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register 4 R R_TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0. 0x0 3 R R_TX_OVER Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared 0x0 2 R R_RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 0x0 (c) 2014 Dialog Semiconductor 104 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit DA14580 Table 158: I2C_INTR_STAT_REG (0x5000132C) Bit Mode Symbol Description Reset 1 R R_RX_OVER Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0x0 0 R R_RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0x0 DA14580 Table 158: I2C_INTR_STAT_REG (0x5000132C) Table 159: I2C_INTR_MASK_REG (0x50001330) Mode Symbol Description Reset 15:12 - - Reserved 0x0 11 R/W M_GEN_CALL These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 10 R/W M_START_DET These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x0 9 R/W M_STOP_DET These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x0 8 R/W M_ACTIVITY These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x0 7 R/W M_RX_DONE These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 6 R/W M_TX_ABRT These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 5 R/W M_RD_REQ These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 4 R/W M_TX_EMPTY These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 3 R/W M_TX_OVER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 2 R/W M_RX_FULL These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 1 R/W M_RX_OVER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 0 R/W M_RX_UNDER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0x1 Table 160: I2C_RAW_INTR_STAT_REG (0x50001334) Bit Mode Symbol Description Reset 15:12 - - Reserved 0x0 11 R GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. I2C Ctrl stores the received data in the Rx buffer. 0x0 (c) 2014 Dialog Semiconductor 105 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Mode Symbol Description Reset 10 R START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 0x0 9 R STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 0x0 8 R ACTIVITY This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 0x0 7 R RX_DONE When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 0x0 6 R TX_ABRT This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a "transmit abort". When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 0x0 5 R RD_REQ This bit is set to 1 when I2C Ctrl is acting as a slave and 0x0 another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register 4 R TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0. 0x0 3 R TX_OVER Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared 0x0 (c) 2014 Dialog Semiconductor 106 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit DA14580 Table 160: I2C_RAW_INTR_STAT_REG (0x50001334) Bit Mode Symbol Description Reset 2 R RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 0x0 1 R RX_OVER Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0x0 0 R RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0x0 DA14580 Table 160: I2C_RAW_INTR_STAT_REG (0x50001334) Table 161: I2C_RX_TL_REG (0x50001338) Bit Mode Symbol Description Reset 15:5 - - Reserved 0x0 4:0 R/W RX_TL Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 31 sets the threshold for 32 entries. 0x0 Table 162: I2C_TX_TL_REG (0x5000133C) Mode Symbol Description Reset 15:5 - - Reserved 0x0 4:0 R/W RX_TL Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 31 sets the threshold for 32 entries.. 0x0 Table 163: I2C_CLR_INTR_REG (0x50001340) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 107 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 0 R CLR_INTR Read this register to clear the combined interrupt, all individual interrupts, and the I2C_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing I2C_TX_ABRT_SOURCE 0x0 DA14580 Table 163: I2C_CLR_INTR_REG (0x50001340) Table 164: I2C_CLR_RX_UNDER_REG (0x50001344) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R CLR_RX_UNDER Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register. 0x0 Table 165: I2C_CLR_RX_OVER_REG (0x50001348) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R CLR_RX_OVER Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register. 0x0 Table 166: I2C_CLR_TX_OVER_REG (0x5000134C) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register. 0x0 Table 167: I2C_CLR_RD_REQ_REG (0x50001350) Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register. 0x0 Table 168: I2C_CLR_TX_ABRT_REG (0x50001354) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R CLR_TX_ABRT Read this register to clear the TX_ABRT interrupt (bit 6) of the 0x0 IC_RAW_INTR_STAT register, and the I2C_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. (c) 2014 Dialog Semiconductor 108 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register. 0x0 DA14580 Table 169: I2C_CLR_RX_DONE_REG (0x50001358) Table 170: I2C_CLR_ACTIVITY_REG (0x5000135C) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register 0x0 Table 171: I2C_CLR_STOP_DET_REG (0x50001360) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. 0x0 Table 172: I2C_CLR_START_DET_REG (0x50001364) Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R CLR_START_DET Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. 0x0 Table 173: I2C_CLR_GEN_CALL_REG (0x50001368) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R CLR_GEN_CALL Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register. 0x0 Table 174: I2C_ENABLE_REG (0x5000136C) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 109 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 0 R/W CTRL_ENABLE Controls whether the controller is enabled. 0: Disables the controller (TX and RX FIFOs are held in an erased state) 1: Enables the controller Software can disable the controller while it is active. However, it is important that care be taken to ensure that the controller is disabled properly. When the controller is disabled, the following occurs: * The TX FIFO and RX FIFO get flushed. * Status bits in the IC_INTR_STAT register are still active until the controller goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer. There is a two ic_clk delay when enabling or disabling the controller 0x0 DA14580 Table 174: I2C_ENABLE_REG (0x5000136C) Table 175: I2C_STATUS_REG (0x50001370) Mode Symbol Description Reset 15:7 - - Reserved 0x0 6 R SLV_ACTIVITY Slave FSM Activity Status. When the Slave Finite State 0x0 Machine (FSM) is not in the IDLE state, this bit is set. 0: Slave FSM is in IDLE state so the Slave part of the controller is not Active 1: Slave FSM is not in IDLE state so the Slave part of the controller is Active 5 R MST_ACTIVITY Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Master FSM is in IDLE state so the Master part of the controller is not Active 1: Master FSM is not in IDLE state so the Master part of the controller is Active 0x0 4 R RFF Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0: Receive FIFO is not full 1: Receive FIFO is full 0x0 3 R RFNE Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. 0: Receive FIFO is empty 1: Receive FIFO is not empty 0x0 2 R TFE Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0: Transmit FIFO is not empty 1: Transmit FIFO is empty 0x1 1 R TFNF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0: Transmit FIFO is full 1: Transmit FIFO is not full 0x1 (c) 2014 Dialog Semiconductor 110 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 0 R I2C_ACTIVITY I2C Activity Status. 0x0 DA14580 Table 175: I2C_STATUS_REG (0x50001370) Table 176: I2C_TXFLR_REG (0x50001374) Bit Mode Symbol Description Reset 15:6 - - Reserved 0x0 5:0 R TXFLR Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Size is constrained by the TXFLR value 0x0 Table 177: I2C_RXFLR_REG (0x50001378) Bit Mode Symbol Description Reset 15:6 - - Reserved 0x0 5:0 R RXFLR Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Size is constrained by the RXFLR value 0x0 Table 178: I2C_SDA_HOLD_REG (0x5000137C) Bit Mode Symbol Description Reset 15:0 R/W IC_SDA_HOLD SDA Hold time 0x1 Table 179: I2C_TX_ABRT_SOURCE_REG (0x50001380) Mode Symbol Description Reset 15 R ABRT_SLVRD_INTX 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register 0x0 14 R ABRT_SLV_ARBLOS T 1: Slave lost the bus while transmitting data to a remote master. I2C_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never "owns" the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then the controller no longer own the bus. 0x0 13 R ABRT_SLVFLUSH_TX 1: Slave has received a read command and some data exists FIFO in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. 0x0 12 R ARB_LOST 1: Master has lost arbitration, or if I2C_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Note: I2C can be both master and slave at the same time. 0x0 11 R ABRT_MASTER_DIS 1: User tries to initiate a Master operation with the Master mode disabled. 0x0 10 R ABRT_10B_RD_NOR STRT 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) 0x0 = 0) and the master sends a read command in 10-bit addressing mode. (c) 2014 Dialog Semiconductor 111 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 9 R ABRT_SBYTE_NORS TRT To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (I2C_CON[5]=1), the SPECIAL bit must be cleared (I2C_TAR[11]), or the GC_OR_START bit must be cleared (I2C_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets re-asserted. 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to send a START Byte. 0x0 8 R ABRT_HS_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode 0x0 7 R ABRT_SBYTE_ACKD ET 1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). 0x0 6 R ABRT_HS_ACKDET 1: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). 0x0 5 R ABRT_GCALL_READ 1: the controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). 0x0 4 R ABRT_GCALL_NOAC K 1: the controller in master mode sent a General Call and no slave on the bus acknowledged the General Call. 0x0 3 R ABRT_TXDATA_NOA CK 1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). 0x0 2 R ABRT_10ADDR2_NO ACK 1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave. 0x0 1 R ABRT_10ADDR1_NO ACK 1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. 0x0 0 R ABRT_7B_ADDR_NO ACK 1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. 0x0 Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W SDA_SETUP SDA Setup. This register controls the amount of time delay (number of I2C clock periods) between the rising edge of SCL and SDA changing by holding SCL low when I2C block services a read request while operating as a slave-transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. It is recommended that if the required delay is 1000ns, then for an I2C frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11.Writes to this register succeed only when IC_ENABLE[0] = 0. 0x64 (c) 2014 Dialog Semiconductor 112 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Table 180: I2C_SDA_SETUP_REG (0x50001394) DA14580 Table 179: I2C_TX_ABRT_SOURCE_REG (0x50001380) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R/W ACK_GEN_CALL ACK General Call. When set to 1, I2C Ctrl responds with a ACK (by asserting ic_data_oe) when it receives a General Call. When set to 0, the controller does not generate General Call interrupts. 0x0 DA14580 Table 181: I2C_ACK_GENERAL_CALL_REG (0x50001398) Table 182: I2C_ENABLE_STATUS_REG (0x5000139C) Mode Symbol Description Reset 15:3 - - Reserved 0x0 2 R SLV_RX_DATA_LOST Slave Received Data Lost. This bit indicates if a SlaveReceiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting of IC_ENABLE from 1 to 0. When read as 1, the controller is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit is also set to 1. When read as 0, the controller is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. 0x0 1 R SLV_DISABLED_WHI LE_BUSY Slave Disabled While Busy (Transmit, Receive). This bit indi- 0x0 cates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) I2C Ctrl is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, the controller is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C Ctrl (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as 0, the controller is deemed to have been disabled when there is master activity, or when the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. (c) 2014 Dialog Semiconductor 113 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description 0 R IC_EN ic_en Status. This bit always reflects the value driven on the 0x0 output port ic_en. When read as 1, the controller is deemed to be in an enabled state. When read as 0, the controller is deemed completely inactive. NOTE: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset DA14580 Table 182: I2C_ENABLE_STATUS_REG (0x5000139C) Table 183: I2C_IC_FS_SPKLEN_REG (0x500013A0) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W IC_FS_SPKLEN This register must be set before any I2C bus transaction can 0x1 take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 2; hardware prevents values less than this being written, and if attempted results in 2 being set. Table 184: GPIO_IRQ0_IN_SEL_REG (0x50001400) Bit Mode Symbol Description Reset 15:6 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 114 Final - January 29, 2015 v3.1 Bit Mode Symbol Description Reset 5:0 R/W KBRD_IRQ0_SEL input selection that can generate a GPIO interrupt 0: no input selected 1: P0[0] is selected 2: P0[1] is selected 3: P0[2] is selected 4: P0[3] is selected 5: P0[4] is selected 6: P0[5] is selected 7: P0[6] is selected 8: P0[7] is selected 9: P1[0] is selected 10: P1[1] is selected 11: P1[2] is selected 12: P1[3] is selected 13: P1[4] is selected 14: P1[5] is selected 15: P2[0] is selected 16: P2[1] is selected 17: P2[2] is selected 18: P2[3] is selected 19: P2[4] is selected 20: P2[5] is selected 21: P2[6] is selected 22: P2[7] is selected 23: P2[8] is selected 24: P2[9] is selected 25: P3[0] is selected 26: P3[1] is selected 27: P3[2] is selected 28: P3[3] is selected 29: P3[4] is selected 30: P3[5] is selected 31: P3[6] is selected 32: P3[7] is selected all others: no input selected 0x0 DA14580 Table 184: GPIO_IRQ0_IN_SEL_REG (0x50001400) Table 185: GPIO_IRQ1_IN_SEL_REG (0x50001402) Mode Symbol Description Reset 15:5 - - Reserved 0x0 5:0 R/W KBRD_IRQ1_SEL see KBRD_IRQ0_SEL 0x0 Table 186: GPIO_IRQ2_IN_SEL_REG (0x50001404) Bit Mode Symbol Description Reset 15:5 - - Reserved 0x0 5:0 R/W KBRD_IRQ2_SEL see KBRD_IRQ0_SEL 0x0 Table 187: GPIO_IRQ3_IN_SEL_REG (0x50001406) Bit Mode Symbol Description Reset 15:5 - - Reserved 0x0 5:0 R/W KBRD_IRQ3_SEL see KBRD_IRQ0_SEL 0x0 (c) 2014 Dialog Semiconductor 115 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 15:5 - - Reserved 0x0 5:0 R/W KBRD_IRQ4_SEL see KBRD_IRQ0_SEL 0x0 DA14580 Table 188: GPIO_IRQ4_IN_SEL_REG (0x50001408) Table 189: GPIO_DEBOUNCE_REG (0x5000140C) Bit Mode Symbol Description Reset 15:14 - - Reserved 0x0 13 R/W DEB_ENABLE_KBRD enables the debounce counter for the KBRD interface 0x0 12 R/W DEB_ENABLE4 enables the debounce counter for GPIO IRQ4 0x0 11 R/W DEB_ENABLE3 enables the debounce counter for GPIO IRQ3 0x0 10 R/W DEB_ENABLE2 enables the debounce counter for GPIO IRQ2 0x0 9 R/W DEB_ENABLE1 enables the debounce counter for GPIO IRQ1 0x0 8 R/W DEB_ENABLE0 enables the debounce counter for GPIO IRQ0 0x0 7:6 - - Reserved 0x0 5:0 R/W DEB_VALUE Keyboard debounce time if enabled. Generate KEYB_INT after specified time. Debounce time: N*1 ms. N =0..63 0x0 Table 190: GPIO_RESET_IRQ_REG (0x5000140E) Mode Symbol Description Reset 15:6 - - Reserved 0x0 5 R0/W RESET_KBRD_IRQ writing a 1 to this bit will reset the KBRD IRQ. Reading returns 0. 0x0 4 R0/W RESET_GPIO4_IRQ writing a 1 to this bit will reset the GPIO4 IRQ. Reading returns 0. 0x0 3 R0/W RESET_GPIO3_IRQ writing a 1 to this bit will reset the GPIO3 IRQ. Reading returns 0. 0x0 2 R0/W RESET_GPIO2_IRQ writing a 1 to this bit will reset the GPIO2 IRQ. Reading returns 0. 0x0 1 R0/W RESET_GPIO1_IRQ writing a 1 to this bit will reset the GPIO1 IRQ. Reading returns 0. 0x0 0 R0/W RESET_GPIO0_IRQ writing a 1 to this bit will reset the GPIO0 IRQ. Reading returns 0. 0x0 Table 191: GPIO_INT_LEVEL_CTRL_REG (0x50001410) Bit Mode Symbol Description Reset 15:14 - - Reserved 0x0 12 R/W EDGE_LEVELN4 see EDGE_LEVELn0, but for GPIO IRQ4 0x0 11 R/W EDGE_LEVELN3 see EDGE_LEVELn0, but for GPIO IRQ3 0x0 10 R/W EDGE_LEVELN2 see EDGE_LEVELn0, but for GPIO IRQ2 0x0 9 R/W EDGE_LEVELN1 see EDGE_LEVELn0, but for GPIO IRQ1 0x0 8 R/W EDGE_LEVELN0 0: do not wait for key release after interrupt was reset for GPIO IRQ0, so a new interrupt can be initiated immediately 1: wait for key release after interrupt was reset for IRQ0 0x0 7:6 - - Reserved 0x0 4 R/W INPUT_LEVEL4 see INPUT_LEVEL0, but for GPIO IRQ4 0x0 (c) 2014 Dialog Semiconductor 116 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 3 R/W INPUT_LEVEL3 see INPUT_LEVEL0, but for GPIO IRQ3 0x0 2 R/W INPUT_LEVEL2 see INPUT_LEVEL0, but for GPIO IRQ2 0x0 1 R/W INPUT_LEVEL1 see INPUT_LEVEL0, but for GPIO IRQ1 0x0 0 R/W INPUT_LEVEL0 0 = selected input will generate GPIO IRQ0 if that input is high. 1 = selected input will generate GPIO IRQ0 if that input is low. 0x0 DA14580 Table 191: GPIO_INT_LEVEL_CTRL_REG (0x50001410) Table 192: KBRD_IRQ_IN_SEL0_REG (0x50001412) Bit Mode Symbol Description Reset 15 R/W KBRD_REL 0 = No interrupt on key release 1 = Interrupt also on key release (also debouncing if enabled) 0x0 14 R/W KBRD_LEVEL 0 = enabled input will generate KBRD IRQ if that input is high. 0x0 1 = enabled input will generate KBRD IRQ if that input is low. 13:8 R/W KEY_REPEAT While key is pressed, automatically generate repeating KEYB_INT after specified time unequal to 0. Repeat time: N*1 ms. N =1..63, N=0 disables the timer. 0x0 7 R/W KBRD_P07_EN enable P0[7] for the keyboard interrupt 0x0 6 R/W KBRD_P06_EN enable P0[6] for the keyboard interrupt 0x0 5 R/W KBRD_P05_EN enable P0[5] for the keyboard interrupt 0x0 4 R/W KBRD_P04_EN enable P0[4] for the keyboard interrupt 0x0 3 R/W KBRD_P03_EN enable P0[3] for the keyboard interrupt 0x0 2 R/W KBRD_P02_EN enable P0[2] for the keyboard interrupt 0x0 1 R/W KBRD_P01_EN enable P0[1] for the keyboard interrupt 0x0 0 R/W KBRD_P00_EN enable P0[0] for the keyboard interrupt 0x0 Table 193: KBRD_IRQ_IN_SEL1_REG (0x50001414) Mode Symbol Description Reset 15 R/W KBRD_P15_EN enable P1[5] for the keyboard interrupt 0x0 14 R/W KBRD_P14_EN enable P1[4] for the keyboard interrupt 0x0 13 R/W KBRD_P13_EN enable P1[3] for the keyboard interrupt 0x0 12 R/W KBRD_P12_EN enable P1[2] for the keyboard interrupt 0x0 11 R/W KBRD_P11_EN enable P1[1] for the keyboard interrupt 0x0 10 R/W KBRD_P10_EN enable P1[0] for the keyboard interrupt 0x0 9 R/W KBRD_P29_EN enable P2[9] for the keyboard interrupt 0x0 8 R/W KBRD_P28_EN enable P2[8] for the keyboard interrupt 0x0 7 R/W KBRD_P27_EN enable P2[7] for the keyboard interrupt 0x0 6 R/W KBRD_P26_EN enable P2[6] for the keyboard interrupt 0x0 5 R/W KBRD_P25_EN enable P2[5] for the keyboard interrupt 0x0 4 R/W KBRD_P24_EN enable P2[4] for the keyboard interrupt 0x0 3 R/W KBRD_P23_EN enable P2[3] for the keyboard interrupt 0x0 2 R/W KBRD_P22_EN enable P2[2] for the keyboard interrupt 0x0 1 R/W KBRD_P21_EN enable P2[1] for the keyboard interrupt 0x0 0 R/W KBRD_P20_EN enable P2[0] for the keyboard interrupt 0x0 (c) 2014 Dialog Semiconductor 117 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 7 R/W KBRD_P37_EN enable P3[7] for the keyboard interrupt 0x0 6 R/W KBRD_P36_EN enable P3[6] for the keyboard interrupt 0x0 5 R/W KBRD_P35_EN enable P3[5] for the keyboard interrupt 0x0 4 R/W KBRD_P34_EN enable P3[4] for the keyboard interrupt 0x0 3 R/W KBRD_P33_EN enable P3[3] for the keyboard interrupt 0x0 2 R/W KBRD_P32_EN enable P3[2] for the keyboard interrupt 0x0 1 R/W KBRD_P31_EN enable P3[1] for the keyboard interrupt 0x0 0 R/W KBRD_P30_EN enable P3[0] for the keyboard interrupt 0x0 DA14580 Table 194: KBRD_IRQ_IN_SEL2_REG (0x50001416) Table 195: GP_ADC_CTRL_REG (0x50001500) Mode Symbol 15 R/W GP_ADC_LDO_ZERO Forces LDO-output to 0V. 0x0 14 R/W GP_ADC_LDO_EN Turns on LDO. 0x0 13 R/W GP_ADC_CHOP Takes two samples with opposite GP_ADC_SIGN to cancel the internal offset voltage of the ADC; Highly recommended for DC-measurements. 0x0 12 R/W GP_ADC_MUTE Takes sample at mid-scale (to dertermine the internal offset and/or noise of the ADC with regards to VDD_REF which is also sampled by the ADC). 0x0 11 R/W GP_ADC_SE 0 = Differential mode 1 = Single ended mode 0x0 10 R/W GP_ADC_SIGN 0 = Default 1 = Conversion with opposite sign at input and output to cancel out the internal offset of the ADC and low-frequency 0x0 9:6 R/W GP_ADC_SEL ADC input selection which must be set before the GP_ADC_START bit is enabled. If GP_ADC_SE = 1 (single ended mode): 0000 = P0[0] 0001 = P0[1] 0010 = P0[2] 0011 = P0[3] 0100 = AVS 0101 = VDD_REF 0110 = VDD_RTT 0111 = VBAT3V 1000 = VDCDC 1001 = VBAT1V All other combinations are reserved. If GP_ADC_SE = 0 (differential mode): 0000 = P0[0] vs P0[1] All other combinations are P0[2] vs P0[3]. 0x0 5 R/W GP_ADC_MINT 0 = Disable (mask) GP_ADC_INT. 1 = Enable GP_ADC_INT to ICU. 0x0 4 R GP_ADC_INT 1 = AD conversion ready and has generated an interrupt. Must be cleared by writing any value to GP_ADC_CLEAR_INT_REG. 0x0 3 R/W GP_ADC_CLK_SEL 0 = Internal high-speed ADC clock used. 1 = Digital clock used. 0x0 2 - GP_ADC_TEST Reserved, keep 0. 0x0 (c) 2014 Dialog Semiconductor Description Reset 118 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 1 R/W GP_ADC_START 0 = ADC conversion ready. 1 = If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set. 0x0 0 R/W GP_ADC_EN 0 = ADC is disabled and in reset. 1 = ADC is enabled and sampling of input is started. 0x0 DA14580 Table 195: GP_ADC_CTRL_REG (0x50001500) Table 196: GP_ADC_CTRL2_REG (0x50001502) Bit Mode Symbol Description Reset 15:4 - - Reserved 0x0 3 R/W GP_ADC_I20U Adds 20uA constant load current at the ADC LDO to minimize ripple on the reference voltage of the ADC. 0x0 2 R/W GP_ADC_IDYN Enables dynamic load current at the ADC LDO to minimize ripple on the reference voltage of the ADC. 0x0 1 R/W GP_ADC_ATTN3X 0 = Input voltages up to 1.2V allowed. 0x0 1 = Input voltages up to 3.6V allowed by enabling 3x attenuator. 0 R/W GP_ADC_DELAY_EN Enables delay function for several signals. This is not autocleared. Toggle this bit before every sampling to enable succesive conversions. 0x0 Table 197: GP_ADC_OFFP_REG (0x50001504) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:0 R/W GP_ADC_OFFP Offset adjust of 'positive' array of ADC-network (effective if "GP_ADC_SE=0", or "GP_ADC_SE=1 AND GP_ADC_SIGN=0") 0x200 Table 198: GP_ADC_OFFN_REG (0x50001506) Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:0 R/W GP_ADC_OFFN Offset adjust of 'negative' array of ADC-network (effective if "GP_ADC_SE=0", or "GP_ADC_SE=1 AND GP_ADC_SIGN=1") 0x200 Table 199: GP_ADC_CLEAR_INT_REG (0x50001508) Bit Mode Symbol Description Reset 15:0 R0/W GP_ADC_CLR_INT Writing any value to this register will clear the ADC_INT inter- 0x0 rupt. Reading returns 0. Table 200: GP_ADC_RESULT_REG (0x5000150A) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:0 R GP_ADC_VAL Returns the 10 bits linear value of the last AD conversion. 0x0 (c) 2014 Dialog Semiconductor 119 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W DEL_LDO_EN Defines the delay before the LDO enable 0x0 (GP_ADC_LDO_EN). Reset value is 0 s since the LDO enable should be the first thing to be programmed in the sequence of bringing the GP ADC up. DA14580 Table 201: GP_ADC_DELAY_REG (0x5000150C) Table 202: GP_ADC_DELAY2_REG (0x5000150E) Bit Mode Symbol Description Reset 15:8 R/W DEL_ADC_START Defines the delay for the GP_ADC_START bit. Reset value is 17 s which is the recommended value to wait before starting the GP ADC. This is the third and last step of bringing up the GP ADC 0x88 7:0 R/W DEL_ADC_EN Defines the delay for the GP_ADC_EN bit. Reset value is 16 s which is the recommended value to wait after enabling the LDO. This is the second step in bringing up the GP ADC. 0x80 Table 203: CLK_REF_SEL_REG (0x50001600) Bit Mode Symbol Description Reset 15:3 - - Reserved 0x0 2 R/W REF_CAL_START Writing a '1' starts a calibration. This bit is cleared when calibration is finished, and CLK_REF_VAL is ready. 0x0 1:0 R/W REF_CLK_SEL Select clock input for calibration: 0x0 : RC32KHz oscillator 0x0 0x1 : RC16MHz oscillator 0x2 : XTAL32KHz oscillator 0x3 : RCX32KHz oscillator Table 204: CLK_REF_CNT_REG (0x50001602) Mode Symbol Description Reset 15:0 R/W REF_CNT_VAL Indicates the calibration time, with a decrement counter to 1. 0x0 Table 205: CLK_REF_VAL_L_REG (0x50001604) Bit Mode Symbol Description Reset 15:0 R XTAL_CNT_VAL Returns the lower 16 bits of XTAL16 clock cycles during the calibration time, defined with REF_CNT_VAL 0x0 Table 206: CLK_REF_VAL_H_REG (0x50001606) Bit Mode Symbol Description Reset 15:0 R XTAL_CNT_VAL Returns the upper 16 bits of XTAL16 clock cycles during the calibration time, defined with REF_CNT_VAL 0x0 (c) 2014 Dialog Semiconductor 120 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W P0_DATA Set P0 output register when written; Returns the value of P0 port when read 0x0 DA14580 Table 207: P0_DATA_REG (0x50003000) Table 208: P0_SET_DATA_REG (0x50003002) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W P0_SET Writing a 1 to P0[y] sets P0[y] to 1. Writing 0 is discarded; Reading returns 0 0x0 Table 209: P0_RESET_DATA_REG (0x50003004) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W P0_RESET Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded; Reading returns 0 0x0 Table 210: P00_MODE_REG (0x50003006) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 121 Final - January 29, 2015 v3.1 Bit Mode Symbol Description Reset 4:0 R/W PID Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1. 0x0 DA14580 Table 210: P00_MODE_REG (0x50003006) Table 211: P01_MODE_REG (0x50003008) Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 122 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 4:0 R/W PID Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1. 0x0 DA14580 Table 211: P01_MODE_REG (0x50003008) Table 212: P02_MODE_REG (0x5000300A) Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 123 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 4:0 R/W PID Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1. 0x0 DA14580 Table 212: P02_MODE_REG (0x5000300A) Table 213: P03_MODE_REG (0x5000300C) Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 124 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 4:0 R/W PID Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1. 0x0 DA14580 Table 213: P03_MODE_REG (0x5000300C) Table 214: P04_MODE_REG (0x5000300E) Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 125 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 4:0 R/W PID Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1. 0x0 DA14580 Table 214: P04_MODE_REG (0x5000300E) Table 215: P05_MODE_REG (0x50003010) Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 126 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 4:0 R/W PID Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1. 0x0 DA14580 Table 215: P05_MODE_REG (0x50003010) Table 216: P06_MODE_REG (0x50003012) Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 127 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 4:0 R/W PID Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1. 0x0 DA14580 Table 216: P06_MODE_REG (0x50003012) Table 217: P07_MODE_REG (0x50003014) Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 128 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 4:0 R/W PID Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1. 0x0 DA14580 Table 217: P07_MODE_REG (0x50003014) Table 218: P1_DATA_REG (0x50003020) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W P1_DATA Set P1 output register when written; Returns the value of P1 port when read 0x0 Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W P1_SET Writing a 1 to P1[y] sets P1[y] to 1. Writing 0 is discarded; Reading returns 0 0x0 Table 220: P1_RESET_DATA_REG (0x50003024) Bit Mode Symbol Description Reset 15:8 - - Reserved 0x0 7:0 R/W P1_RESET Writing a 1 to P1[y] sets P1[y] to 0. Writing 0 is discarded; Reading returns 0 0x0 (c) 2014 Dialog Semiconductor 129 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Table 219: P1_SET_DATA_REG (0x50003022) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up) 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 DA14580 Table 221: P10_MODE_REG (0x50003026) Table 222: P11_MODE_REG (0x50003028) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up) 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 Table 223: P12_MODE_REG (0x5000302A) Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up) 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 Table 224: P13_MODE_REG (0x5000302C) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up) 0x2 7:5 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 130 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 DA14580 Table 224: P13_MODE_REG (0x5000302C) Table 225: P14_MODE_REG (0x5000302E) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up) 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 Table 226: P15_MODE_REG (0x50003030) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up) 0x1 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 Table 227: P2_DATA_REG (0x50003040) Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:0 R/W P2_DATA Set P2 output register when written; Returns the value of P2 port when read 0x0 Table 228: P2_SET_DATA_REG (0x50003042) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:0 R/W P2_SET Writing a 1 to P2[y] sets P2[y] to 1. Writing 0 is discarded; Reading returns 0 0x0 Table 229: P2_RESET_DATA_REG (0x50003044) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:0 R/W P2_RESET Writing a 1 to P2[y] sets P2[y] to 0. Writing 0 is discarded; Reading returns 0 0x0 (c) 2014 Dialog Semiconductor 131 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 DA14580 Table 230: P20_MODE_REG (0x50003046) Table 231: P21_MODE_REG (0x50003048) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 Table 232: P22_MODE_REG (0x5000304A) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 Table 234: P24_MODE_REG (0x5000304E) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 132 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Table 233: P23_MODE_REG (0x5000304C) Bit Mode Symbol Description Reset 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 DA14580 Table 234: P24_MODE_REG (0x5000304E) Table 235: P25_MODE_REG (0x50003050) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 Table 236: P26_MODE_REG (0x50003052) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 Table 237: P27_MODE_REG (0x50003054) Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 Table 238: P28_MODE_REG (0x50003056) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 133 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 DA14580 Table 238: P28_MODE_REG (0x50003056) Table 239: P29_MODE_REG (0x50003058) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care 0x2 7:5 - - Reserved 0x0 4:0 R/W PID See P0x_MODE_REG[PID] 0x0 Table 240: P01_PADPWR_CTRL_REG (0x50003070) Bit Mode Symbol Description Reset 15:12 - - Reserved 0x0 13:8 R/W P1_OUT_CTRL 1 = P1_x port output is powered by 1V rail 0 = P1_x port output is powered by 3V rail bit 8 controls the power of P1[0], bit 13 controls the power of P1[5] (Note 3) 0x0 7:0 R/W P0_OUT_CTRL 1 = P0_x port output is powered by 1V rail 0 = P0_x port output is powered by 3V rail bit 0 controls the power of P0[0], bit 7 controls the power of P0[7] (Note 4) 0x0 For buck mode the output must be powered by the 3V rail, for boost mode by the 1V rail. Note 4: For buck mode the output must be powered by the 3V rail, for boost mode by the 1V rail. Table 241: P2_PADPWR_CTRL_REG (0x50003072) Bit Mode Symbol Description Reset 15:10 - - Reserved 0x0 9:0 R/W P2_OUT_CTRL 1 = P2_x port output is powered by 1V rail 0 = P2_x port output is powered by 3V rail bit 0 controls the power of P2[0], bit 9 controls the power of P2[9], (Note 5) 0x0 Note 5: For buck mode the output must be powered by the 3V rail, for boost mode by the 1V rail. Table 242: P3_PADPWR_CTRL_REG (0x50003074) Bit Mode Symbol Description Reset 15:8 - - Reserved 0 (c) 2014 Dialog Semiconductor 134 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Note 3: Bit Mode Symbol Description Reset 7:0 R/W P3_OUT_CTRL 1 = P3_x port output is powered by 1V rail 0 = P3_x port output is powered by 3V rail bit 0 controls the power of P3[0], bit 7 controls the power of P3[7], (Note 6) 0 Note 6: DA14580 Table 242: P3_PADPWR_CTRL_REG (0x50003074) For buck mode the output must be powered by the 3V rail, for boost mode by the 1V rail. Table 243: P3_DATA_REG (0x50003080) Bit Mode Symbol Description Reset 15:8 - - Reserved 0 7:0 R/W P3_DATA Set P3 output register when written; Returns the value of P3 port when read 0 Table 244: P3_SET_DATA_REG (0x50003082) Bit Mode Symbol Description Reset 15:8 - - Reserved 0 7:0 R0/W P3_SET Writing a 1 to P3[y] sets P3[y] to 1. Writing 0 is discarded; Reading returns 0 0 Table 245: P3_RESET_DATA_REG (0x50003084) Bit Mode Symbol Description Reset 15:8 - - Reserved 0 7:0 R0/W P3_RESET Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded; Reading returns 0 0 Table 246: P30_MODE_REG (0x50003086) Mode Symbol Description Reset 15:10 - - Reserved 0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 2 7:5 - - Reserved 0 4:0 R/W PID See P0x_MODE_REG[PID] 0 Table 247: P31_MODE_REG (0x50003088) Bit Mode Symbol Description Reset 15:10 - - Reserved 0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 2 7:5 - - Reserved 0 4:0 R/W PID See P0x_MODE_REG[PID] 0 (c) 2014 Dialog Semiconductor 135 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 15:10 - - Reserved 0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 2 7:5 - - Reserved 0 4:0 R/W PID See P0x_MODE_REG[PID] 0 DA14580 Table 248: P32_MODE_REG (0x5000308A) Table 249: P33_MODE_REG (0x5000308C) Bit Mode Symbol Description Reset 15:10 - - Reserved 0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 2 7:5 - - Reserved 0 4:0 R/W PID See P0x_MODE_REG[PID] 0 Table 250: P34_MODE_REG (0x5000308E) Bit Mode Symbol Description Reset 15:10 - - Reserved 0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 2 7:5 - - Reserved 0 4:0 R/W PID See P0x_MODE_REG[PID] 0 Bit Mode Symbol Description Reset 15:10 - - Reserved 0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 2 7:5 - - Reserved 0 4:0 R/W PID See P0x_MODE_REG[PID] 0 Table 252: P36_MODE_REG (0x50003092) Bit Mode Symbol Description Reset 15:10 - - Reserved 0 (c) 2014 Dialog Semiconductor 136 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Table 251: P35_MODE_REG (0x50003090) Bit Mode Symbol Description Reset 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 2 7:5 - - Reserved 0 4:0 R/W PID See P0x_MODE_REG[PID] 0 DA14580 Table 252: P36_MODE_REG (0x50003092) Table 253: P37_MODE_REG (0x50003094) Bit Mode Symbol Description Reset 15:10 - - Reserved 0 9:8 R/W PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 2 7:5 - - Reserved 0 4:0 R/W PID See P0x_MODE_REG[PID] 0 Table 254: WATCHDOG_REG (0x50003100) Mode Symbol Description Reset 15:9 R0/W WDOG_WEN 0000.000 = Write enable for Watchdog timer else Write disable. This filter prevents unintentional presetting the watchdog with a SW run-away. 0x0 8 R/W WDOG_VAL_NEG 0 = Watchdog timer value is positive. 1 = Watchdog timer value is negative. 0x0 7:0 R/W WDOG_VAL Write: Watchdog timer reload value. Note that all bits 15-9 must be 0 to reload this register. Read: Actual Watchdog timer value. Decremented by 1 every 10.24 msec. Bit 8 indicates a negative counter value. 2, 1, 0, 1FF16, 1FE16 etc. An NMI or WDOG (SYS) reset is generated under the following conditions: If WATCHDOG_CTRL_REG[NMI_RST] = 0 then If WDOG_VAL = 0 -> NMI (Non Maskable Interrupt) if WDOG_VAL = 1F016 -> WDOG reset -> reload FF16 If WATCHDOG_CTRL_REG[NMI_RST] = 1 then if WDOG_VAL <= 0 -> WDOG reset -> reload FF16 0xFF Table 255: WATCHDOG_CTRL_REG (0x50003102) Bit Mode Symbol Description Reset 15:14 - - Reserved 0x0 (c) 2014 Dialog Semiconductor 137 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 0 R/W NMI_RST 0 = Watchdog timer generates NMI at value 0, and WDOG (SYS) reset at <=-16. Timer can be frozen /resumed using SET_FREEZE_REG[FRZ_WDOG]/ RESET_FREEZE_REG[FRZ_WDOG]. 0x0 DA14580 Table 255: WATCHDOG_CTRL_REG (0x50003102) 1 = Watchdog timer generates a WDOG (SYS) reset at value 0 and can not be frozen by Software. Note that this bit can only be set to 1 by SW and only be reset with a WDOG (SYS) reset or SW reset. The watchdog is always frozen when the Cortex-M0 is halted in DEBUG State. Table 256: CHIP_ID1_REG (0x50003200) Bit Mode Symbol Description Reset 7:0 R CHIP_ID1 First character of device type "580" in ASCII. 0x35 Table 257: CHIP_ID2_REG (0x50003201) Bit Mode Symbol Description Reset 7:0 R CHIP_ID2 Second character of device type "580" in ASCII. 0x38 Table 258: CHIP_ID3_REG (0x50003202) Bit Mode Symbol Description Reset 7:0 R CHIP_ID3 Third character of device type "580" in ASCII. 0x30 Table 259: CHIP_SWC_REG (0x50003203) Mode Symbol Description Reset 7:4 - - Reserved 0x0 3:0 R CHIP_SWC SoftWare Compatibility code. Integer (default = 0) which is incremented if a silicon change has impact on the CPU Firmware. Can be used by software developers to write silicon revision dependent code. 0x0 Table 260: CHIP_REVISION_REG (0x50003204) Bit Mode Symbol Description Reset 7:0 R REVISION_ID Chip version, corresponds with type number in ASCII. 0x41 = 'A', 0x42 = 'B' 0x41 Table 261: CHIP_CONFIG1_REG (0x50003205) Bit Mode Symbol Description Reset 7:0 R CHIP_CONFIG1 First character of Chip Configuration "0M2" in ASCII. 0x30 (c) 2014 Dialog Semiconductor 138 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 7:0 R CHIP_CONFIG2 Second character of Chip Configuration "0M2" in ASCII. 0x4D DA14580 Table 262: CHIP_CONFIG2_REG (0x50003206) Table 263: CHIP_CONFIG3_REG (0x50003207) Bit Mode Symbol Description Reset 7:0 R CHIP_CONFIG3 Third character of Chip Configuration "0M2" in ASCII. 0x32 Table 264: CHIP_TEST1_REG (0x5000320A) Bit Mode Symbol Description Reset 7:0 - - Reserved 0x0 Table 265: CHIP_TEST2_REG (0x5000320B) Bit Mode Symbol Description Reset 7:0 - - Reserved 0x20 Table 266: SET_FREEZE_REG (0x50003300) Bit Mode Symbol Description Reset 15:4 - - Reserved 0x0 3 R/W FRZ_WDOG If '1', the watchdog timer is frozen, '0' is discarded. WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow the freeze function. 0x0 2 R/W FRZ_BLETIM If '1', the BLE master clock is frozen, '0' is discarded. 0x0 1 R/W FRZ_SWTIM If '1', the SW Timer (TIMER0) is frozen, '0' is discarded. 0x0 0 R/W FRZ_WKUPTIM If '1', the Wake Up Timer is frozen, '0' is discarded. 0x0 Table 267: RESET_FREEZE_REG (0x50003302) Mode Symbol Description Reset 15:4 - - Reserved 0x0 3 R/W FRZ_WDOG If '1', the watchdog timer continues, '0' is discarded. 0x0 2 R/W FRZ_BLETIM If '1', the the BLE master clock continues, '0' is discarded. 0x0 1 R/W FRZ_SWTIM If '1', the SW Timer (TIMER0) continues, '0' is discarded. 0x0 0 R/W FRZ_WKUPTIM If '1', the Wake Up Timer continues, '0' is discarded. 0x0 Table 268: DEBUG_REG (0x50003304) Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R/W DEBUGS_FREEZE_E N Default '1', freezing of the on-chip timers is enabled when the Cortex-M0 is halted in DEBUG State. If '0', freezing of the on-chip timers is depending on FREEZE_REG when the Cortex-M0 is halted in DEBUG State except the watchdog timer. The watchdog timer is always frozen when the Cortex-M0 is halted in DEBUG State. 0x1 (c) 2014 Dialog Semiconductor 139 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Bit Mode Symbol Description Reset 15:1 - - Reserved 0x0 0 R/W CAL_PHASE If '1', it designates that the chip is in Calibration Phase i.e. the OTP has been initially programmed but no Calibration has occured. 0x0 DA14580 Table 269: GP_STATUS_REG (0x50003306) Table 270: GP_CONTROL_REG (0x50003308) Bit Mode Symbol Description Reset 15:6 - - Reserved 0 5:1 R/W EM_MAP Select the mapping of the Exchange memory pages. 0: EM size 0 kB, SysRAM size 42 kB 1: EM size 2 kB, SysRAM size 48 kB 2: EM size 3 kB, SysRAM size 47 kB 3: EM size 4 kB, SysRAM size 46 kB 4: EM size 5 kB, SysRAM size 45 kB 5: EM size 6 kB, SysRAM size 44 kB 6: EM size 7 kB, SysRAM size 43 kB 7: EM size 8 kB, SysRAM size 42 kB 8: Reserved 9: EM size 4 kB, SysRAM size 40 kB 10: EM size 5 kB, SysRAM size 40 kB 11: EM size 6 kB, SysRAM size 40 kB 12: EM size 7 kB, SysRAM size 40 kB 13: EM size 8 kB, SysRAM size 40 kB 14: EM size 9 kB, SysRAM size 40 kB 15: EM size 10 kB, SysRAM size 40 kB 16: Reserved 17: EM size 6 kB, SysRAM size 38 kB 18: EM size 7 kB, SysRAM size 38 kB 19: EM size 8 kB, SysRAM size 38 kB 20: EM size 9 kB, SysRAM size 38 kB 21: EM size 10 kB, SysRAM size 38 kB 22: EM size 11 kB, SysRAM size 38 kB 23: EM size 12 kB, SysRAM size 38 kB other: Reserved. 0x1 0 R/W BLE_WAKEUP_REQ If '1', the BLE wakes up. 0x0 Bit Mode Symbol Description Reset 15:4 - - Reserved 0x0 3 R/W PWM_MODE 0 = PWM signals are '1' during high time. 1 = PWM signals send out the (fast) clock divided by 2 during high time. So it will be in the range of 1 to 8 MHz. 0x0 2 R/W TIM0_CLK_DIV 1 = Timer0 uses selected clock frequency as is. 0 = Timer0 uses selected clock frequency divided by 10. Note that this applies only to the ON-counter. 0x0 1 R/W TIM0_CLK_SEL 1 = Timer0 uses 16, 8, 4 or 2 MHz (fast) clock frequency. 0 = Timer0 uses 32 kHz (slow) clock frequency. 0x0 0 R/W TIM0_CTRL 0 = Timer0 is off and in reset state. 1 = Timer0 is running. 0x0 (c) 2014 Dialog Semiconductor 140 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Table 271: TIMER0_CTRL_REG (0x50003400) Bit Mode Symbol Description Reset 15:0 R0/W TIM0_ON Timer0 On reload value: If read the actual counter value ON_CNTer is returned 0x0 DA14580 Table 272: TIMER0_ON_REG (0x50003402) Table 273: TIMER0_RELOAD_M_REG (0x50003404) Bit Mode Symbol Description Reset 15:0 R0/W TIM0_M Timer0 'high' reload valueIf read the actual counter value T0_CNTer is returned 0x0 Table 274: TIMER0_RELOAD_N_REG (0x50003406) Bit Mode Symbol Description Reset 15:0 R0/W TIM0_N Timer0 'low' reload value: If read the actual counter value T0_CNTer is returned 0x0 Table 275: PWM2_DUTY_CYCLE (0x50003408) Bit Mode Symbol Description Reset 13:0 R/W DUTY_CYCLE duty cycle for PWM 0x0 Table 276: PWM3_DUTY_CYCLE (0x5000340A) Bit Mode Symbol Description Reset 13:0 R/W DUTY_CYCLE duty cycle for PWM 0x0 Table 277: PWM4_DUTY_CYCLE (0x5000340C) Bit Mode Symbol Description Reset 13:0 R/W DUTY_CYCLE duty cycle for PWM 0x0 Table 278: TRIPLE_PWM_FREQUENCY (0x5000340E) Mode Symbol Description Reset 13:0 R/W FREQ Freq for PWM 2 3 4 0x0 Table 279: TRIPLE_PWM_CTRL_REG (0x50003410) Bit Mode Symbol Description Reset 2 R/W HW_PAUSE_EN '1' = HW can pause PWM 2,3,4 0x1 1 R/W SW_PAUSE_EN '1' = PWM 2 3 4 is paused 0x0 0 R/W TRIPLE_PWM_ENAB LE '1' = PWM 2 3 4 is enabled 0x0 (c) 2014 Dialog Semiconductor 141 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Bit Specifications All MIN/MAX specification limits are guaranteed by design, production testing and/or statistical characterisation. Typical values are based on characterisation results at default measurement conditions and are informative only. Default measurement conditions (unless otherwise specified): VBAT(VBAT3V) = 3.0 V (buck mode), VBAT(VBAT1V) = 1.2 V (boost mode), TA = 25 C. All radio measurements are performed with standard RF measurement equipment providing a source/load impedance of 50 . DA14580 5. The specifications in the following tables are valid for the reference circuits shown in Figure 11 (Boost mode) and Figure 12 (Buck mode). 9%$79 933 73 9%$7 9GFGF 6:&/. 73 %7 9$$$ / X+ & 6:',2 73 & & ' ' ( ( ( ' & % ( ( 9%$7B5) 9%$79 $ 933 & $ 9'&'&B5) 3B 6:B&/. ' % 6:',2 % & X) & X) X) 3B 9GFGF 9'&'& 9%$79 & X) 9%$7 $17 ) 3B & X) 3B 3B 5),2S 3B 5),2P 8 3B 3B $ $ '$ 3B ;7$/0S 3B ;7$/0P % $ < 0+] 3B 3B ;7$/.S ) < N+] *1' ) % *1' *1' & *1' $ ' ) *1' ;7$/.P *1' 567 ' ( ) 73 *1' 9%$7 ) 73 6:,7&+ 9%$7 (c) 2014 Dialog Semiconductor 142 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Figure 11 Alkaline battery cell powered system diagram (Boost mode) 73 *1' 73 933 73 9%$7 9GFGF DA14580 9%$7 9%$7 9GFGF / 6:&/. 73 ' ' ( ( ( ' & % ) 9%$7B5) 6:,7&+ ( 9%$79 $ 933 & $ 9'&'&B5) 9'&'& 9%$79 ) ) 3B 3B 3B 5),2S 3B 5),2P 8 3B 3B %7 9&RLQ & X) '$ 3B ;7$/0S 3B ;7$/0P $ $ % < 0+] $ 3B 3B ;7$/.S ) ) < N +] *1' 237,21$/ % *1' *1' & *1' $ ' ) *1' ;7$/.P *1' 567 ' ( $17 9%$7 & 3B & X) & 3B 6:B&/. ' % 6:',2 % X+ & X) ( & X) 6:',2 73 Figure 12 Lithium coin cell powered system diagram (Buck mode) Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 143 Final - January 29, 2015 v3.1 Parameter Description VPIN(LIM)(defaul limiting voltage on a pin t) Conditions Min Max Unit Voltage between pin and GND (Note 7) -0.1 Typ min{3.6, VBAT_RF +0.2} V -50 150 C 100 ms storage temperature tR(SUP) supply rise time Power supply rise time VBAT(LIM)(VBA T1V) limiting battery supply voltage Supply voltage on VBAT1V in a boost converter application (VBAT3V is second output of boost-converter in this case) (Note 7) -0.1 3.6 V VBAT(LIM)(VBA T3V) limiting battery supply voltage Supply voltage on VBAT3V and VBAT_RF in a buck-converter application, pin VBAT1V is connected to ground (Note 7) -0.1 3.6 V VPIN(LIM)(1V2) limiting voltage on a pin XTAL32Km, XTAL16Mp, XTAL16Mm (Note 7) -0.2 min(1.2,V BAT_RF+ 0.2) V VPIN(LIM)(VDC DC_RF) limiting voltage on the VDCDC_RF pin Supply voltage on VDCDC_RF (Note 7) -0.2 min(2,VBA T_RF+0.2 ) V VPIN(LIM)(XTAL 32Kp) limiting voltage on a pin XTAL32Kp -0.2 min(1.5,V BAT_RF+ 0.2) V VESD(HBM)(WL CSP34) electrostatic discharge voltage (Human Body Model) 2000 V VESD(HBM)(QF N40) electrostatic discharge voltage (Human Body Model) 4000 V VESD(HBM)(QF N48) electrostatic discharge voltage (Human Body Model) 4000 V VESD(MM)(WLC SP34) electrostatic discharge voltage (Machine Model) 200 V VESD(MM)(QFN 40) electrostatic discharge voltage (Machine Model) 200 V VESD(MM)(QFN 48) electrostatic discharge voltage (Machine Model) 200 V VESD(CDM)(WL CSP34) electrostatic discharge voltage (Charged Device Model) 500 V VESD(CDM)(QF N40) electrostatic discharge voltage (Charged Device Model) 1000 V VESD(CDM)(QF N48) electrostatic discharge voltage (Charged Device Model) 1000 V (c) 2014 Dialog Semiconductor 144 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC TSTG DA14580 Table 280: Absolute maximum ratings The device should not be exposed for prolonged periods of time to voltages between the Recommended Operating Conditions and the Absolute Maximum Ratings range. Table 281: Recommended operating conditions Parameter Description Conditions Min Typ Max Unit VPP programming voltage Supply voltage on pin VPP during OTP programming; TJ 50 C 6.6 6.7 6.8 V VBAT(VBAT1V) battery supply voltage Supply voltage on VBAT1V in a boost converter application (VBAT3V is second output of boost-converter in this case) 0.9 3.3 V VBAT(VBAT3V) battery supply voltage Supply voltage on VBAT3V and VBAT_RF in a buck-converter application, pin VBAT1V is connected to ground 3.3 V VPIN(default) voltage on a pin Voltage between pin and GND 0 min(3.3,V BAT_RF+ 0.2) V VPIN(1V2) voltage on a pin XTAL32Km, XTAL16Mp, XTAL16Mm 0 1.2 V VPIN(VDCDC_ RF) voltage on a pin Supply voltage on VDCDC_RF 0 2 V TA ambient temperature -40 85 C Note 8: 2.35 (Note 8) DA14580 Note 7: Cold boot should not be performed if voltage is less than 2.5 V because of possible corruption during OTP data mirroring. Trim values programmed in the OTP as well as the application image, should be copied into RAM while VBAT3V >= 2.5 V. Table 282: DC characteristics Parameter Description Conditions Min Typ Max Unit Boost configuration in deep-sleep with 1 kB retention RAM active, running from RC32K oscillator at lowest frequency 0.48 A IBAT(DP_SLP)_ battery supply current BOOST_2kB Boost configuration in deep-sleep with 2 kB retention RAM active, running from XTAL32K oscillator 0.55 A IBAT(DP_SLP)_ battery supply current BOOST_8kB Typical boost-application in deep-sleep with 8 kB retention RAM active, running from XTAL32K oscillator 0.7 IBAT(EXT_SLP) battery supply current _BOOST_43K B Typical boost-application in extended-sleep mode with 42 kB (SysRAM) and 1 kB (RetRAM) retained 1.37 (c) 2014 Dialog Semiconductor 145 2 A A Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC IBAT(DP_SLP)_ battery supply current BOOST_1kB Parameter Typ Max Unit IBAT(EXT_SLP) battery supply current _BOOST_50kB Description Conditions Typical boost-application in extended-sleep mode with 42 kB (SysRAM) and 8 kB (RetRAM) retained Min 1.5 3 A IBAT(DP_SLP)_ battery supply current BUCK_1kB Buck configuration in deep-sleep with 1 kB retention RAM active, running from RC32K oscillator at lowest frequency 0.4 A IBAT(DP_SLP)_ battery supply current BUCK_2kB Buck configuration in deep-sleep with 2 kB retention RAM active, running from XTAL32K oscillator 0.45 A IBAT(DP_SLP)_ battery supply current BUCK_8kB Typical buck-application in deep-sleep with 8 kB retention RAM active, running from XTAL32K oscillator 0.6 IBAT(EXT_SLP) battery supply current _BUCK_43KB Typical buck-application in extended-sleep mode with 42 kB (SysRAM) and 1 kB (RetRAM) retained 1.2 IBAT(EXT_SLP) battery supply current _BUCK_50kB Typical buck-application in extended-sleep mode with 42 kB (SysRAM) and 8 kB (RetRAM) retained 1.4 3 A IBAT(ACT_RX) _BOOST battery supply current Typical application with boost converter and receiver active 13.4 16 mA IBAT(ACT_TX)_ battery supply current BOOST Typical application with boost converter and transmitter active 12.4 15 mA IBAT(ACT_RX) _BUCK battery supply current Typical application with buck converter and receiver active 5.1 6 mA IBAT(ACT_TX)_ battery supply current BUCK Typical application with buck converter and transmitter active 4.8 6 mA Typ Max Unit 2 A A Description Conditions tSTA(BOOST) startup time Boost-mode; time from deep-sleep to software start. Typical application, running from retention RAM on 16 MHz RC oscillator (c) 2014 Dialog Semiconductor Min 146 1.2 (Note 9) ms Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Table 283: Timing characteristics Parameter DA14580 Table 282: DC characteristics Parameter Description Conditions tSTA(BUCK) startup time Buck-mode; time from deep-sleep to software start. Typical application, running from retention RAM on 16 MHz RC oscillator Note 9: Min Typ Max 1 (Note 9) Unit ms DA14580 Table 283: Timing characteristics Worst-case value under Normal Operating Conditions. Table 284: 16 MHz Crystal Oscillator: Recommended operating conditions Parameter Description Conditions Min fXTAL(16M) crystal oscillator frequency ESR(16M) equivalent series resistance CL(16M) load capacitance C0(16M) shunt capacitance fXTAL(16M) crystal frequency tolerance After optional trimming; including aging and temperature drift (Note 10) fX- crystal frequency tolerance Typ Max 16 Unit MHz 100 12 pF 5 pF -20 20 ppm Untrimmed; including aging and temperature drift (Note 11) -40 40 ppm PDRV(MAX)(16M maximum drive power ) (Note 12) 100 VCLK(EXT)(16M) external clock voltage Only in case of an external reference clock on XTAL16Mp (XTAL16Mm floating or connected to mid-level 0.6 V) N(EXTERNAL)16M fC = 50 kHz in case of an external reference clock TAL(16M)UNT phase noise No external capacitors are required 10 1 W 1.2 V -130 dBc/ Hz Note 11: Maximum allowed frequency tolerance for compensation by the internal varicap trimming mechanism. Note 12: Select a crystal which can handle a drive-level equal or more than this specification Table 285: 16 MHz Crystal Oscillator: Timing characteristics Parameter Description Conditions tSTA(XTAL)(16M) crystal oscillator startup time (c) 2014 Dialog Semiconductor 147 Min Typ Max Unit 0.5 2 3 ms Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Note 10: Using the internal varicaps a wide range of crystals can be trimmed to the required tolerance. Parameter Description Conditions Min Typ Max Unit VCLK(EXT)(32K) external clock voltage peak-peak voltage of external clock at XTAL32Kp, pin XTAL32Km floating. note: XTAL32Kp is internally AC coupled 0.1 0.2 1.5 V fXTAL(32k) crystal oscillator frequency frequency range for an external clock (for a crystal, use either 32.000 kHz or 32.768 kHz) 10 32.768 100 kHz ESR(32k) equivalent series resistance 100 k CL(32k) load capacitance 7 9 pF C0(32k) shunt capacitance 1 2 pF fXTAL(32k) crystal frequency tolerance (including aging) 250 ppm PDRV(MAX)(32k) maximum drive power no external capacitors are required for a 6 pF or 7 pF crystal Timing accuracy is dominated by crystal accuracy. A much smaller value is preferred (Note 13) 6 -250 DA14580 Table 286: 32 kHz Crystal Oscillator: Recommended operating conditions W 0.1 Note 13: Select a crystal that can handle a drive-level of at least this specification. Table 287: 32 kHz Crystal Oscillator: Timing characteristics Parameter Description Conditions Min tSTA(XTAL)(32k) crystal oscillator startup time Typical application, time until 1000 clocks are detected (Note 14) Typ Max 0.4 Unit s Note 14: This parameter is very much dependent on crystal parameters Parameter Description L effective inductance COUT(VDCDC) effective load capacitance COUT(VBAT3V) effective load capacitance Conditions Min Typ Max Unit 1.5 2.2 3 H VDCDC and VDDCRF combined (Note 15) 0.5 1 10 F VBATRF and VBAT3V combined are the second output of the boostconverter (Note 15) 0.5 1 10 F Min Typ Max Unit Note 15: A low value will result in lowest power consumption, keep this value at 1 uF or 2 uF. Table 289: DC-DC converter: DC characteristics Parameter Description Conditions VO(BUCK) output voltage default settings (c) 2014 Dialog Semiconductor 148 1.41 V Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Table 288: DC-DC converter: Recommended operating conditions Parameter Description Conditions VO(BOOST) output voltage default settings, VDCDC Min CONV_MAX(BU CK) Typ Max Unit 1.41 V maximum conversion efficiency 86 % CONV_MAX(BO OST) maximum conversion efficiency 80 % VO/ VI(BUCK) line regulation 2.35 V VBAT3V 3.3 V -2 0.7 2 %/V VO/ VI(BOOST) line regulation 0.9 V VBAT1V 1.2 V (Note 16) -2 1 4 %/V VO/IL(BUCK) load regulation VBAT3V = 2.5 V -0.2 -0.02 0.2 %/mA VO/ IL(BOOST) load regulation VBAT1V = 1.2 V -0.2 -0.07 0.2 %/mA VRPL(BUCK) ripple voltage buck mode; RMS ripple voltage 5 mV VRPL(BOOST) ripple voltage VBAT1V 1.2 V, boost mode; RMS ripple voltage (Note 16) 8 mV DA14580 Table 289: DC-DC converter: DC characteristics Note 16: When VBAT1V > VDCDC_nominal, VDCDC will follow VBAT1V. Table 290: Digital Input/Output: DC characteristics Parameter Description VIH HIGH level input voltage VIL LOW level input voltage VIH(RST) HIGH level input voltage RST pin VIL(RST) LOW level input voltage RST pin VOH(VBAT1V) HIGH level output voltage Iout = -250 A, VBAT3V = 2.35 V, VBAT1V = 0.9 V 0.72 V VOH(VBAT3V) HIGH level output voltage Iout = -4.8 mA, VBAT3V = 2.35 V, VBAT1V = 0 V 1.88 V VOL(VBAT1V) LOW level output voltage Iout = 250 A, VBAT3V = 2.35 V, VBAT1V = 0.9 V 0.18 V VOL(VBAT3V) LOW level output voltage Iout = 4.8 mA, VBAT3V = 2.35 V, VBAT1V = 0 V 0.47 V IIH HIGH level input current Vin = VBAT3V = 2.5 V -1 1 A IIL LOW level input current Vin = VSS = 0 V -1 1 A IIH(PD) HIGH level input current Vin = VBAT3V = 2.5 V 50 150 A IIL(PU) LOW level input current Vin = VSS = 0 V -150 -50 A IIH(RST) HIGH level input current RST pin, V(RST) = 1.2 V 25 75 A Min Typ Max 0.84 V 0.36 0.84 V V 0.36 149 Unit V Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor Conditions Parameter Description NBIT(ADC) number of bits (resolution) Conditions Min Typ Max 10 Unit bit DA14580 Table 291: General purpose ADC: Recommended operating conditions Table 292: General purpose ADC: DC characteristics Parameter Description Conditions Min Typ Max Unit VI(ZS) zero-scale input voltage single-ended, calibrated at zero input -2.5 0 2.5 mV VI(FS) full-scale input voltage single-ended, calibrated at zero input 1150 1180 1250 mV VI(FSN) negative full-scale input voltage differential, calibrated at zero input -1180 mV VI(FSP) positive full-scale input voltage differential, calibrated at zero input 1180 mV INL integral non-linearity -2 2 LSB DNL differential non-linearity -2 2 LSB Typ Max Unit 0.25 0.4 s Typ Max Unit Table 293: General purpose ADC: Timing characteristics Parameter Description Conditions Min tCONV(ADC) conversion time Excluding initial settling time of the LDO and the 3x-attenuation (if used): LDO settling time is 20 s (max), 3x-attenuation settling time = 1 s (max) Using internal ADC-clock (~200 MHz) Table 294: Radio: DC characteristics Description Conditions Min IBAT(RF)RX battery supply current receive mode; radio receiver and synthesizer active; DCDC converter assumed ideal; TA = 25 C (Note 17) 3.7 4.3 mA IBAT(RF)TX battery supply current transmit mode; radio transmitter and synthesizer active; DCDC converter assumed ideal; TA = 25 C (Note 17) 3.4 4 mA Note 17: The DCDC-converter efficiency is assumed to be 100 % to enable benchmarking of the radio currents at battery supply domain (VBAT3V = 3 V). (c) 2014 Dialog Semiconductor 150 Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC Parameter Parameter Description Conditions PSENS(CLEAN) sensitivity level DC-DC converter enabled; Dirty Transmitter disabled; TA = 25 C; PER = 30.8 % (Note 18) PSENS sensitivity level Normal Operating Conditions; DC-DC converter enabled; TA = 25 C; PER = 30.8 % (Note 18) PI(max) input power level DC-DC converter disabled; TA = 25 C; PER 30.8 % (Note 18) 10 PINT(IMD) intermodulation distortion interferer power level worst case interferer level @ f1, f2 with 2f1-f2 = f0, |f1-f2| = n MHz and n = 3,4,5; PWANTED = -64 dBm @ f0; PER = 30.8 %; TA = 25 C (Note 20) -35 CIR(0) carrier to interferer ratio n = 0; interferer @ f1 = f0 + n*1 MHz; TA = 25 C (Note 21) 7 21 dB CIR(1) carrier to interferer ratio n = 1; interferer @ f1 = f0 + n*1 MHz; TA = 25 C (Note 21) -3 15 dB CIR(P2) carrier to interferer ratio n = +2 (image frequency); interferer @ f1 = f0 + n*1 MHz; TA = 25 C (Note 21) -20 -9 dB CIR(M2) carrier to interferer ratio n = -2; interferer @ f1 = f0 + n*1 MHz; TA = 25 C (Note 21) -30 -17 dB CIR(P3) carrier to interferer ratio n = +3 (image frequency + 1 MHz); interferer @ f1 = f0 + n*1 MHz; TA = 25 C (Note 21) -30 -15 dB CIR(M3) carrier to interferer ratio n = -3; interferer @ f1 = f0 + n*1 MHz; TA = 25 C (Note 21) -35 -27 dB PBL(I) blocker power level 30 MHz fBL 2000 MHz; PWANTED = -67 dBm; TA = 25 C (Note 22) -5 dBm PBL(II) blocker power level 2003 MHz fBL 2399 MHz; PWANTED = -67 dBm; TA = 25 C (Note 22) -15 dBm 151 Typ Max Unit -93 dBm -92.5 dBm dBm -31 dBm Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor Min DA14580 Table 295: Radio: AC characteristics Parameter Description Conditions Min PBL(III) blocker power level 2484 MHz fBL 2997 MHz; PWANTED = -67 dBm; TA = 25 C (Note 22) -15 CIR(4) carrier to interferer ratio |n| >= 4 (any other BLE channel); interferer @ f1 = f0 + n*1 MHz; TA = 25 C (Note 21) PBL(IV) blocker power level 3000 MHz fBL 12.75 GHz; PWANTED = -67 dBm; TA = 25 C (Note 22) -5 PRSSI(min) RSSI power level absolute power level for RXRSSI[7:0] = 0; TA = 25 C (Note 23) -115 -112 PRSSI(max) RSSI power level upper limit of monotonous range; TA = 25 C -26 -19 LACC(RSSI)BO OST level accuracy tolerance of 5 % to 95 % confidence interval of PRF: when RXRSSI[7:0] = X, 50 < X < 175; burst mode 1500 packets; TA = 25 C; DC-DC converter in BOOST mode 0 3 dB LACC(RSSI)BU CK level accuracy tolerance of 5 % to 95 % confidence interval of PRF: when RXRSSI[7:0] = X, 50 < X < 175; burst mode 1500 packets; TA = 25 C; DC-DC converter in BUCK mode 0 2 dB LRES(RSSI) level resolution gradient of monotonous range for RXRSSI[7:0] = X, 50 < X < 175; burst mode 1500 packets; TA = 25C 0.474 0.485 dB/ LSB ACP(2M) adjacent channel power level fOFFSET = 2 MHz; TA = 25C (Note 24) -53 -50 dBm ACP(2M)(EOC) adjacent channel power level fOFFSET = 2 MHz; -40C TA +85C (Note 24) -53 -47 dBm ACP(3M) fOFFSET 3 MHz; TA = 25C (Note 24) -57 -55 dBm fOFFSET 3 MHz; -40C TA +85C (Note 24) -57 -47 dBm ACP(3M)(EOC) adjacent channel power level (c) 2014 Dialog Semiconductor 152 Unit dBm -37 0.46 Max -27 dB dBm -109 dBm dBm Final - January 29, 2015 v3.1 Low Power Bluetooth Smart SoC adjacent channel power level Typ DA14580 Table 295: Radio: AC characteristics Parameter Description Conditions PO output power level VDD = 3 V; maximum gain; TA = 25 C Min Typ Max Unit -2 -1 0 dBm PO(HD2) output power level (second harmonic) VDD = 3 V; maximum gain; TA = 25 C -54 -40 dBm PO(HD3) output power level (third harmonic) VDD = 3 V; maximum gain; TA = 25 C -56 -40 dBm PO(HD4) output power level (fourth harmonic) VDD = 3 V; maximum gain; TA = 25 C -70 -40 dBm PO(HD5) output power level (fifth harmonic) VDD = 3 V; maximum gain; TA = 25 C -70 -40 dBm PO(NFM) output power level in 'Near Field Mode' VDD = 3 V; maximum gain; TA = 25 C (Note 25) -20 -15 dBm -25 DA14580 Table 295: Radio: AC characteristics Note 18: Measured according to Bluetooth(R) Low Energy Test Specification RF-PHY.TS/4.0.1, section 6.4.1. Note 19: Measured according to Bluetooth(R) Low Energy Test Specification RF-PHY.TS/4.0.1, section 6.4.2. Note 20: Measured according to Bluetooth(R) Core Technical Specification document, version 4.0, volume 6, section 4.4. Published value is for n = IXIT = 4 . IXIT = 5 gives the same results, IXIT = 3 gives results that are 5 dB lower. Note 21: Measured according to Bluetooth(R) Core Technical Specification document, version 4.0, volume 6, section 4.2. Note 22: Measured according to Bluetooth(R) Core Technical Specification document, version 4.0, volume 6, section 4.3. Due to limitations of the measurement equipment, levels of -5 dBm should be interpreted as > -5 dBm. Note 23: PRF = PRSSI(min) + LRES(RSSI) x RXRSSI[7:0] LACC(RSSI). Thanks to constant gain biasing of RF part in the receiver, the RSSI can be used to estimate absolute power levels, rather than mere level changes. Even across the full temperature range the variation is limited. Note 24: Measured according to Bluetooth(R) Low Energy Test Specification RF-PHY.TS/4.0.1, section 6.2.3. Note 25: To activate the "Near Field Mode", program address 0x50002418 with the value 0x0030. Table 296: Stable low frequency RCX Oscillator: Timing characteristics Parameter Description Conditions fRC(RCX) RCX oscillator frequency default setting, buck mode only fRC(RCX) RCX oscillator frequency drift buck mode only (Note 26) Min Typ Max Unit 5 10 40 kHz 500 ppm -500 Note 26: Maximum recommended connection interval (including slave latency) for the RCX usage is 2 s. Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 153 Final - January 29, 2015 v3.1 DA14580 6. Package information 6.1 MOISTURE SENSITIVITY LEVEL (MSL) The MSL is an indicator for the maximum allowable time period (floor life time) in which a moisture sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a maximum temperature of 30 C and a maximum relative humidity of 60 % RH. before the solder reflow process. WLCSP packages are qualified for MSL 1. QFN packages are qualified for MSL 3. MSL Level Floor Life Time MSL 3 168 hours MSL 1 Unlimited at 30C/85%RH 6.2 WLCSP HANDLING Manual handling of WLCSP packages should be reduced to the absolute minimum. In cases where it is still necessary, a vacuum pick-up tool should be used. In extreme cases plastic tweezers could be used, but metal tweezers are not acceptable, since contact may easily damage the silicon chip. Removal will cause damage to the solder balls and therefore a removed sample cannot be reused. WLCSP is sensitive to visible and infrared light. Precautions should be taken to properly shield the chip in the final product. 6.3 SOLDERING INFORMATION Refer to the JEDEC standard J-STD-020 for relevant soldering information. This document can be downloaded from http:// www.jedec.org Low Power Bluetooth Smart SoC (c) 2014 Dialog Semiconductor 154 Final - January 29, 2015 v3.1 DA14580 6.4 PACKAGE OUTLINES Low Power Bluetooth Smart SoC Figure 13 QFN48 Package Outline Drawing (c) 2014 Dialog Semiconductor 155 Final - January 29, 2015 v3.1 DA14580 Low Power Bluetooth Smart SoC Figure 14 QFN40 Package Outline Drawing (c) 2014 Dialog Semiconductor 156 Final - January 29, 2015 v3.1 DA14580 Low Power Bluetooth Smart SoC Figure 15 WLCSP34 Package Outline Drawing (c) 2014 Dialog Semiconductor 157 Final - January 29, 2015 v3.1 Version Datasheet status Product status Definition 1.<n> Target Development This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. 2.<n> Preliminary Qualification This datasheet contains the specifications and preliminary characterisation data for products in pre-production. Specifications may be changed at any time without notice in order to improve the design. 3.<n> Final Production This datasheet contains the final specifications for products in volume production. The specifications may be changed at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via Customer Product Notifications. 4.<n> Obsolete Archived This datasheet contains the specifications for discontinued products. The information is provided for reference only. DA14580 Status definitions Disclaimer Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information. 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