General Description
The MAX5894 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for high-
performance wideband, single-carrier transmit applica-
tions. The device integrates a selectable 2x/4x/8x
interpolating filter, a digital quadrature modulator, and
dual 14-bit, high-speed DACs on a single integrated cir-
cuit. At 30MHz output frequency and 500Msps update
rate, the in-band SFDR is 86dBc while consuming 1.1W.
The device also delivers 73dB ACLR for two-carrier
WCDMA at a 61.44MHz output frequency.
The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease
reconstruction filter requirements and enhance the
passband dynamic performance. Individual offset and
gain programmability allow the user to calibrate out local
oscillator (LO) feedthrough and sideband suppression
errors generated by analog quadrature modulators.
The MAX5894 features a fIM/4 digital image-reject mod-
ulator. This modulator generates a quadrature-modulat-
ed IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
frequency-translated with image pairs at fIM/2 or fIM/4.
The MAX5894 features a standard 1.8V CMOS, 3.3V tol-
erant data input bus for easy interface. A 3.3V SPI™ port
is provided for mode configuration. The programmable
modes include the selection of 2x/4x/8x interpolating fil-
ters, fIM/2, fIM/4 or no digital quadrature modulation with
image rejection, channel gain and offset adjustment, and
offset binary or two’s complement data interface.
Pin-compatible 12- and 16-bit devices are also available.
Refer to the MAX5893 data sheet for the 12-bit version
and the MAX5895 data sheet for the 16-bit version.
Applications
Base Stations: 3G UMTS, CDMA, and GSM
Broadband Wireless Transmitters
Broadband Cable Infrastructure
Instrumentation and Automatic Test Equipment (ATE)
Analog Quadrature Modulation Architectures
Features
o74dB ACLR at fOUT = 61.44MHz (Single-Carrier
WCDMA)
oMeets 3G UMTS, cdma2000®, GSM Spectral Masks
(fOUT = 122MHz)
oNoise Spectral Density = -154dBFS/Hz at
fOUT = 16MHz
o91dBc SFDR at Low-IF Frequency (10MHz)
o88dBc SFDR at High-IF Frequency (50MHz)
oLow Power: 886mW (fCLK = 250MHz)
oUser Programmable
Selectable 2x, 4x, or 8x Interpolating Filters
< 0.01dB Passband Ripple
> 99dB Stopband Rejection
Selectable Real or Complex Modulator Operation
Selectable Modulator LO Frequency: OFF, fIM/2
or fIM/4
Selectable Output Filter: Lowpass or Highpass
Channel Gain and Offset Adjustment
oEV Kit Available (Order the MAX5894 EV Kit)
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
________________________________________________________________
Maxim Integrated Products
1
PART RESOLUTION
(BITS)
DAC UPDATE
RATE (Msps)
INPUT
LOGIC
MAX5893 12 500 CMOS
MAX5894 14 500 CMOS
MAX5895 16 500 CMOS
MAX5898 16 500 LVDS
PART TEMP RANGE PIN-PACKAGE
MAX5894EGK-D -40°C to +85°C 68 QFN-EP*
MAX5894EGK+D -40°C to +85°C 68 QFN-EP*
Selector Guide
Ordering Information
DATA SYNCH
AND DEMUX
DAC
DATA
PORT A
DATA
PORT B
DATACLK
OUTI
OUTQ
MODULATOR
2x
INTERPOLATING
FILTERS
1x/2x/4x
INTERPOLATING
FILTERS
DAC
Simplified Diagram
19-3631; Rev 2; 10/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Pin Configuration appears at end of data sheet.
SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of Telecommunications
Industry Association.
D = Dry pack.
*
EP = Exposed pad.
+
Denotes a lead-free/RoHS-compliant package.
EVALUATION KIT
AVAILABLE
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port
mode, 50Ωdouble-terminated outputs, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C, unless otherwise noted.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DVDD1.8, AVDD1.8 to GND, DACREF ..................-0.3V to +2.16V
AVDD3.3, AVCLK, DVDD3.3 to GND, DACREF........-0.3V to +3.9V
DATACLK, A0–A13, B0–B11,
SELIQ/B13, DATACLK/B12, CS, RESET, SCLK,
DIN and DOUT to GND, DACREF ...-0.3V to (DVDD3.3 + 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AVCLK + 0.3V)
REFIO, FSADJ to GND, DACREF ........-0.3V to (AVDD3.3 + 0.3V)
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF..................-1V to (AVDD3.3 + 0.3V)
DOUT, DATACLK, DATACLK/B12 Continuous Current........8mA
Continuous Power Dissipation (TA= +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C)
(Note 1) ...................................................................3333.3mW
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Thermal Resistance θJC (Note 1)....................................0.8°C/W
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution 14 Bits
Differential Nonlinearity DNL ±0.5 LSB
Integral Nonlinearity INL ±1.0 LSB
Offset Error OS -0.025 0.003 +0.025 %FS
Offset Drift ±0.03 ppm/°C
Full-Scale Gain Error GEFS -4 -0.6 +4 %FS
Gain-Error Drift ±110 ppm/°C
Full-Scale Output Current IOUTFS 220mA
Output Compliance -0.5 +1.1 V
Output Resistance ROUT 1MΩ
Output Capacitance COUT 5pF
DYNAMIC PERFORMANCE
Maximum Clock Frequency fCLK 500 MHz
Minimum Clock Frequency fCLK 1 MHz
Maximum DAC Update Rate fDAC fDAC = fCLK or fDAC = fCLK/2 500 Msps
Minimum DAC Update Rate fDAC fDAC = fCLK or fDAC = fCLK/2 1 Msps
Maximum Input Data Rate fDATA 125 MWps
No interpolation -154
2x interpolation -154
fDATACLK = 125MHz,
fOUT = 16MHz, fOFFSET
= 10MHz, -12dBFS 4x interpolation -154
Noise Spectral Density
fDATACLK = 125MHz,
fOUT = 16MHz, fOFFSET
= 10MHz, 0dBFS
4x interpolation -151
dBFS/
Hz
Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed pad area.
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port
mode, 50Ωdouble-terminated outputs, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
fOUT = 10MHz 91
fOUT = 30MHz 85
fDATACLK = 125MHz,
interpolation off, 0dBFS
fOUT = 50MHz 73
fOUT = 10MHz 77 89
fOUT = 30MHz 86
fDATACLK = 125MHz,
2x interpolation, 0dBFS fOUT = 50MHz 85
fOUT = 10MHz 91
fOUT = 30MHz 86
In-Band SFDR
(DC to fDATA/2) SFDR
fDATACLK = 125MHz,
4x interpolation, 0dBFS fOUT = 50MHz 88
dBc
No interpolation -102
2x interpolation -102
fDATACLK = 125MHz,
fOUT1 = 9MHz, fOUT2 =
10MHz, -6.1dBFS 4x interpolation -102
2x interpolation,
fIM/4 complex
modulation
-73
fDATA = 125MHz, fOUT1
= 79MHz, fOUT2 =
80MHz, -6.1dBFS 4x interpolation,
fIM/4 complex
modulation
-75
fDATACLK = 62.5MHz,
fOUT1 = 9MHz, fOUT2 =
10MHz, -6.1dBFS
8x interpolation -99
fDATACLK = 62.5MHz,
fOUT1 = 69MHz, fOUT2
= 70MHz, -6.1dBFS
8x interpolation,
fIM/4 complex
modulation
-70
Two-Tone IMD TTIMD
fDATACLK = 62.5MHz,
fOUT1 = 179MHz, fOUT2
= 180MHz, -6.1dBFS
8x, highpass
interpolation,
fIM/4 complex
modulation
-63
dBc
Four-Tone IMD FTIMD
fDATACLK = 125MHz, fOUT spaced 1MHz
apart from 32MHz, -12dBFS, 2x
interpolation
-95 dBc
4x interpolation 78
fDATACLK = 61.44MHz,
fOUT = baseband 8x interpolation 78
fDATACLK =
122.88MHz, fOUT =
61.44MHz
2x interpolation,
fIM/4 complex
modulation
74
ACLR for WCDMA
(Note 3) ACLR
fDATACLK =
122.88MHz, fOUT =
122.88MHz
4x interpolation,
fIM/4 complex
modulation
69
dB
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port
mode, 50Ωdouble-terminated outputs, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Propagation Delay tPD 1x interpolation (Note 4) 2.9 ns
Output Rise Time tRISE 10% to 90% (Note 5) 0.75 ns
Output Fall Time tFALL 10% to 90% (Note 5) 1 ns
Output Settling Time To 0.5% (Note 5) 11 ns
Output Bandwidth -1dB bandwidth (Note 6) 240 MHz
Passband Width Ripple < -0.01dB 0.4 x
fDATA
0.604 x fDATA, 2x interpolation 100
0.604 x fDATA, 4x interpolation 100
Stopband Rejection
0.604 x fDATA, 8x interpolation 100
dB
1x interpolation 22
2x interpolation 70
4x interpolation 146
Data Latency
8x interpolation 311
Clock
Cycles
DAC INTERCHANNEL MATCHING
Gain Match ∆Gain fOUT = DC - 80MHz, IOUTFS = 20mA ±0.1 dB
Gain-Match Tempco ∆Gain/°C IOUTFS = 20mA ±0.02 ppm/°C
Phase Match ∆Phase fOUT = 60MHz, IOUTFS = 20mA ±0.13 Deg
Phase-Match Tempco ∆Phase/°C fOUT = 60MHz, IOUTFS = 20mA ±0.006 Deg/°C
DC Gain Match IOUTFS = 20mA -0.25 0.04 +0.25 dB
Channel-to-Channel Crosstalk fOUT = 50MHz, fDAC = 250MHz, 0dBFS -90 dB
REFERENCE
Reference Input Range 0.125 1.250 V
Reference Output Voltage VREFIO Internal reference 1.14 1.20 1.27 V
Reference Input Resistance RREFIO 10 kΩ
Reference Voltage Drift ±50 ppm/°C
CMOS LOGIC INPUT/OUTPUT (A13–A0, SELIQ/B13, DATACLK/B12, B11–B0, DATACLK)
Input High Voltage VIH 0.7 x
DVDD1.8 V
Input Low Voltage VIL 0.3 x
DVDD1.8 V
Input Current IIN -20 ±1 +20 µA
Input Capacitance CIN 3pF
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage VOH 200µA load 0.8 x
DVDD3.3 V
Output Low Voltage VOL 200µA load 0.2 x
DVDD3.3 V
Output Leakage Current Three-state 1 µA
Rise/Fall Time CLOAD = 10pF, 20% to 80% 1.6 ns
CLOCK INPUT (CLKP, CLKN)
Sine-wave input > 1.5
Differential Input Voltage Swing VDIFF Square-wave input > 0.5 VP-P
Differential Input Slew Rate > 100 V/µs
Common-Mode Voltage VCOM AC-coupled AVCLK/2 V
Input Resistance RCLK 5kΩ
Input Capacitance CCLK 3pF
Minimum Clock Duty Cycle 45 %
Maximum Clock Duty Cycle 55 %
CLKP/CLKN, DATACLK TIMING (Figure 4) (Notes 7, 8)
CLK to DATACLK Delay tDDATACLK output mode, CLOAD = 10pF 6.2 ns
Capturing rising edge 1.0
Data Hold Time, DATACLK
Input/Output (Pin 14) tDH Capturing falling edge 2.1 ns
Capturing rising edge 0.4
Data Setup Time, DATACLK
Input/Output (Pin 14) tDS Capturing falling edge -0.7 ns
Capturing rising edge 1.0
Data Hold Time, DATACLK/B10
Input/Output (Pin 27) tDH Capturing falling edge 2.3 ns
Capturing rising edge 0.2
Data Setup Time, DATACLK/B10
Input/Output (Pin 27) tDS Capturing falling edge -0.4 ns
SERIAL-PORT INTERFACE TIMING (Figure 3) (Note 7)
SCLK Frequency fSCLK 10 MHz
CS Setup Time tSS 2.5 ns
Input Hold Time tSDH 0ns
Input Setup Time tSDS 4.5 ns
Data Valid Duration tSDV 6.5 16.5 ns
ELECTRICAL CHARACTERISTICS (continued)
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port
mode, 50Ωdouble-terminated outputs, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C, unless otherwise noted.) (Note 2)
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
6 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
Digital Supply Voltage DVDD1.8 1.71 1.8 1.89 V
Digital I/O Supply Voltage DVDD3.3 3.0 3.3 3.6 V
Clock Supply Voltage AVCLK 3.135 3.3 3.465 V
AVDD3.3 3.135 3.3 3.465
Analog Supply Voltage AVDD1.8 1.71 1.8 1.89 V
IAVDD3.3 fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz 110 130
Analog Supply Current
IAVDD1.8 fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz 27 32
mA
Digital Supply Current IDVDD1.8 fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz 225 250 mA
Digital I/O Supply Current IDVDD3.3 fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz 21 32 mA
Clock Supply Current IAVCLK fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz 35mA
Total Power Dissipation PTOTAL fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz 886 mW
AVDD3.3 450
AVDD1.8 1
DVDD1.8 10
DVDD3.3 100
Power-Down Current
All I/O are static high or
low, bit 2 to bit 4 of
address 00h are set high
AVCLK 1
µA
AVDD3.3 Power-Supply Rejection
Ratio PSRRA(Note 9) 0.05 %FS/V
ELECTRICAL CHARACTERISTICS (continued)
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, dual-port
mode, 50Ωdouble-terminated outputs, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C, unless otherwise noted.) (Note 2)
Note 2: All limit specifications are 100% tested at TA≥+25°C. Specifications at TA< +25°C are guaranteed by design and characterization.
Note 3: 3.84MHz bandwidth, single carrier.
Note 4: Excludes data latency.
Note 5: Measured single-ended into a 50Ωload.
Note 6: Excludes sin(x)/x rolloff.
Note 7: Guaranteed by design and characterization.
Note 8: Setup and hold time specifications characterized with 3.3V CMOS logic levels.
Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
_______________________________________________________________________________________
7
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 2x INTERPOLATION
MAX5894 toc01
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
40302010
20
40
60
80
100
120
0
050
-0.1dBFS
-6dBFS
-12dBFS
SPURS MEASURED BETWEEN
0MHz AND 62.5MHz
0UT-OF-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 2x INTERPOLATION
MAX5894 toc02
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
40302010
100
0
050
10
20
30
40
50
60
70
80
90
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
-0.1dBFS
-6dBFS
-12dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 2x INTERPOLATION
MAX5894 toc03
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
102.592.582.572.5
10
20
30
40
50
60
70
80
90
0
62.5 112.5
-6dBFS
-12dBFS
-0.1dBFS
-0.1dBFS
UPPER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATION
MAX5894 toc04
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
40302010
20
40
60
80
100
120
0
050
-0.1dBFS
-6dBFS
-12dBFS
SPURS MEASURED BETWEEN
0MHz AND 62.5MHz
OUT-OF-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATION
MAX5894 toc05
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
40302010
10
20
30
40
50
60
70
80
90
0
050
SPURS MEASURED BETWEEN
62.5MHz AND 250MHz
-6dBFS
-0.1dBFS
-12dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATION
MAX5894 toc06
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
1151059585
90
0
75 125
10
20
30
40
50
60
70
80
LOWER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
-0.1dBFS
-6dBFS
-12dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATION
MAX5894 toc07
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
165155145135
10
20
30
40
50
60
70
80
90
0
125 175
UPPER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
125MHz AND 187.5MHz
-0.1dBFS
-12dBFS
-6dBFS
TWO-TONE IMD vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 2x INTERPOLATION
MAX5894 toc08
CENTER FREQUENCY (MHz)
TWO-TONE IMD (dBc)
100755025
-100
-80
-60
-40
-20
0
-120
0
1MHz CARRIER SPACING
COMPLEX MODULATION FOR
OUTPUT FREQUENCIES
GREATER THAN 50MHz
-12dBFS
-6dBFS
-6dBFS
-9dBFS
TWO-TONE IMD vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATION
MAX5894 toc09
CENTER FREQUENCY (MHz)
TWO-TONE IMD (dBc)
1601301007040
-100
-60
-20
-80
-40
0
-120
10
1MHz CARRIER SPACING
COMPLEX MODULATION FOR
OUTPUT FREQUENCIES
GREATER THAN 50MHz
-12dBFS
-6dBFS
-9dBFS
Typical Operating Characteristics
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, output is transformer-coupled to
50Ωload, TA= +25°C, unless otherwise noted.)
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
8 _______________________________________________________________________________________
GAIN MISMATCH vs. TEMPERATURE
fDATA = 125Mwps, 2x INTERPOLATION
MAX5894 toc10
TEMPERATURE (°C)
GAIN MISMATCH (dB)
603510-15
0.025
0.050
0.075
0.100
0
-40 85
fOUT = 22.7MHz
AOUT = -6dBFS
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5894 toc11
DIGITAL INPUT CODE
DNL (LSB)
12,28881924096
-0.50
-0.25
-0.75
0.25
0.50
0
0.75
1.00
-1.00
0 16,38
4
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5894 toc12
DIGITAL INPUT CODE
INL (LSB)
12,28881924096
-0.5
1.0
-1.5
0
1.5
-1.0
0.5
2.0
-2.0
0 16,384
SUPPLY CURRENT vs. DAC UPDATE RATE
2x INTERPOLATION, fOUT = 5MHz
MAX5894 toc13
fDAC (MHz)
SUPPLY CURRENT (mA)
250200150
50
100
150
200
250
300
350
400
450
500
0
100 300
1.8V TOTAL
3.3V TOTAL
SUPPLY CURRENT vs. DAC UPDATE RATE
4x INTERPOLATION, fOUT = 5MHz
MAX5894 toc14
fDAC (MHz)
SUPPLY CURRENT (mA)
400300200
50
100
150
200
250
300
350
400
450
500
0
100 500
1.8V TOTAL
3.3V TOTAL
SUPPLY CURRENT vs. DAC UPDATE RATE
8x INTERPOLATION, fOUT = 5MHz
MAX5894 toc15
fDAC (MHz)
SUPPLY CURRENT (mA)
400300200
50
100
150
200
250
300
350
400
450
500
0
100 500
1.8V TOTAL
3.3V TOTAL
Typical Operating Characteristics (continued)
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, output is transformer-coupled to
50Ωload, TA= +25°C, unless otherwise noted.)
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
_______________________________________________________________________________________
9
TWO-CARRIER WCDMA ACLR SPECTRAL PLOT
fDATA = 61.44Mwps, 8x INTERPOLATION
MAX5894 toc19
fCENTER = 61.44MHz
SPAN = 30.5MHz
ACLR2 = 75dB
OUTPUT POWER (dBm)
ACLR1 = 74dB
ACLR1 = 73dB
ACLR2 = 74dB
CARRIER = -14dBm
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
WCDMA ACLR SPECTRAL PLOT
fDATA = 122.88Mwps, 4x INTERPOLATION
MAX5894 toc20
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
fCENTER = 122.88MHz
SPAN = 25.5MHz
ACLR2 = 70dB
OUTPUT POWER (dBm)
ACLR1 = 67dB
ACLR1 = 67dB
ACLR2 = 69dB
CARRIER = -14dBm
TWO-CARRIER WCDMA ACLR SPECTRAL PLOT
fDATA = 122.88Mwps, 4x INTERPOLATION
MAX5894 toc21
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
fCENTER = 122.88MHz
SPAN = 30.5MHz
ACLR2 = 68dB
OUTPUT POWER (dBm)
ACLR1 = 65dB
ACLR1 = 65dB
ACLR2 = 67dB
CARRIER = -17dBm
Typical Operating Characteristics (continued)
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, output is transformer-coupled to
50Ωload, TA= +25°C, unless otherwise noted.)
WCDMA ACLR vs. OUTPUT FREQUENCY
fDATA = 122.88Mwps, 4x INTERPOLATION
MAX5894 toc16
fCENTER (MHz)
ACLR (dB)
1208040
50
60
70
80
90
100
40
0 160
TWO-CARRIER
ADJACENT CHANNEL
ONE-CARRIER
ADJACENT CHANNEL
TWO-CARRIER
ALTERNATE CHANNEL
ONE-CARRIER
ALTERNATE CHANNEL
WCDMA ACLR vs. OUTPUT FREQUENCY
fDATA = 76.8Mwps, 4x INTERPOLATION
MAX5894 toc17
fCENTER (MHz)
ACLR (dB)
8040
50
60
70
80
90
100
40
0
ONE-CARRIER
ALTERNATE CHANNEL
ONE-CARRIER
ADJACENT CHANNEL
TWO-CARRIER
ALTERNATE CHANNEL
TWO-CARRIER
ADJACENT
CHANNEL
MAX5894 toc18
WCDMA ACLR SPECTRAL PLOT
fDATA = 61.44Mwps, 8x INTERPOLATION
fCENTER = 61.44MHz
SPAN = 25.5MHz
ACLR2 = 78dB
OUTPUT POWER (dBm)
ACLR1 = 76dB
ACLR1 = 75dB
ACLR2 = 77dB
CARRIER = -11dBm
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 CLKP Noninverting Differential Clock Input. Internally biased to AVCLK/2.
2 CLKN Inverting Differential Clock Input. Internally biased to AVCLK/2.
3, 4, 5, 24, 25,
42, 43 N.C. Internally Connected. Do not connect.
6, 21, 30, 37 DVDD1.8 Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a
0.1µF capacitor as close to the pin as possible.
7–12, 15–20,
22, 23 A13–A0
A-Port Data Inputs.
Dual-port mode:
I-channel data input. Data is latched on the rising/falling edge (programmable) of the DATACLK.
Single-port mode:
I-channel and Q-channel data input, with SELIQ.
13, 44 DVDD3.3 CMOS I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass each pin to ground with a
0.1µF capacitor as close to the pin as possible.
14 DATACLK Programmable Data Clock Input/Output. See the DATACLK Modes section for details.
26 SELIQ/B13
Select I-/Q-Channel Input or B-Port MSB Input.
Single-port mode:
If SELIQ = LOW, data is latched into Q-channel on the rising/falling edge (programmable) of
the DATACLK.
If SELIQ = HIGH, data is latched into I-channel on the rising/falling edge (programmable) of the
DATACLK.
Dual-port mode:
Q-channel MSB input.
27 DATACLK/B12
Alternate DATACLK Input/Output or B-Port Bit 12 Input.
Single-port mode:
See the DATACLK Modes section for details.
Dual-port mode:
Q-channel bit 12 input.
If unused connect to GND.
28, 29, 31–36,
38–41 B11–B0
B-Port Data Bits 11–0.
Dual-port mode:
Q-channel inputs. Data is latched on the rising/falling (programmable) edge of the DATACLK.
Single-port mode:
Connect to GND.
45 DOUT Serial-Port Data Output
46 DIN Serial-Port Data Input
47 SCLK Serial-Port Clock Input. Data on DIN is latched on the rising edge of SCLK.
48 CS Serial-Port Interface Select. Drive CS low to enable serial-port interface.
49 RESET Reset Input. Set RESET low during power-up.
50 REFIO Reference Input/Output. Bypass to ground with a 1µF capacitor as close to the pin as possible.
51 DACREF
C ur r ent- S et Resi stor Retur n P ath. For a 20m A ful l - scal e outp ut cur r ent, connect a 2kΩ r esi stor b etw een
FS AD J and D AC RE F. Inter nal l y connected to GN D . D O NO T U SE A S A N EXT ER N A L G R O U N D
C O N N EC T IO N .
52 FSADJ Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2kΩ resistor between FSADJ and DACREF.
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 11
Pin Description (continued)
Functional Diagram
PIN NAME FUNCTION
53, 67 AVDD1.8 Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with
a 0.1µF capacitor as close to the pin as possible.
54, 56, 59, 61,
64, 66 GND Ground
55, 60, 65 AVDD3.3 Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a
0.1µF capacitor as close to the pin as possible.
57 OUTQN Inverting Differential DAC Current Output for Q-Channel
58 OUTQP Noninverting Differential DAC Current Output for Q-Channel
62 OUTIN Inverting Differential DAC Current Output for I-Channel
63 OUTIP Noninverting Differential DAC Current Output for I-Channel
68 AVCLK Clock Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass to ground with a 0.1µF
capacitor as close to the pin as possible.
— EP Exposed Pad. Must be connected to GND through a low-impedance path.
IDAC
OUTIP
OUTIN
QDAC
OUTQP
OUTQN
SELIQ
A0–A13
B0–B13
DATACLK
SERIAL INTERFACE
CONTROL REGISTERS
REFERENCE
MODULATOR
CLOCK BUFFERS
AND DIVIDERS
CLKPCLKN
RESET
fCLK
fDAC
fDAC
DATA SYNCH
AND DEMUX
MUX
Q
I
Q
I
2x
INTERPOLATING
FILTER
2x
INTERPOLATING
FILTER
2x
INTERPOLATING
FILTER
2x
INTERPOLATING
FILTER
2x
INTERPOLATING
FILTER
2x
INTERPOLATING
FILTER
MUX
MUX MUX
DIGITAL
OFFSET
ADJUST
DIGITAL
OFFSET
ADJUST
DIGITAL
GAIN
ADJUST
/2/2
DOUT DIN CS SCLK DACREF FSADJ REFIO
∑
∑∑
fIM/2, fIM/4
∑
DIGITAL
GAIN
ADJUST
/2/2
MAX5894
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
12 ______________________________________________________________________________________
Detailed Description
The MAX5894 dual, 500Msps, high-speed, 14-bit, cur-
rent-output DAC provides superior performance in
communication systems requiring low-distortion ana-
log-signal reconstruction. The MAX5894 combines two
DAC cores with 8x/4x/2x/1x programmable digital inter-
polation filters, a digital quadrature modulator, an SPI-
compatible serial interface for programming the device,
and an on-chip 1.20V reference. The full-scale output
current range is programmable from 2mA to 20mA to
optimize power dissipation and gain control.
Each channel contains three selectable interpolating fil-
ters making the MAX5894 capable of 1x, 2x, 4x, or 8x
interpolation, which allows for low input data rates and
high DAC update rates. When operating in 8x interpola-
tion mode, the interpolator increases the DAC conver-
sion rate by a factor of eight, providing an eight-fold
increase in separation between the reconstructed
waveform spectrum and its first image. The MAX5894
accepts either two’s complement or offset binary input
data format and can operate from either a single- or
dual-port input bus.
The MAX5894 includes modulation modes at fIM/2 and
fIM/4, where fIM is the data rate at the input of the modu-
lator. If 2x interpolation is used, this data rate is 2x the
input data rate. If 4x or 8x interpolation is used, this data
rate is 4x the input data rate. Table 1 summarizes the
modulator operating data rates for dual-port mode.
The power-down modes can be used to turn off each
DAC’s output current or the entire digital section.
Programming both DACs into power-down simultane-
ously automatically powers down the digital interpolator
filters. Note the SPI section is always active.
The analog and digital sections of the MAX5894 have
separate power-supply inputs (AVDD3.3, AVDD1.8,
AVCLK, DVDD3.3, and DVDD1.8), which minimize noise
coupling from one supply to the other. AVDD1.8 and
DVDD1.8 operate from a typical 1.8V supply, and all
other supply inputs operate from a typical 3.3V supply.
Serial Interface
The SPI-compatible serial interface programs the
MAX5894 registers. The serial interface consists of the
CS, DIN, SCLK, and DOUT. Data is shifted into DIN on
the rising edge of the SCLK when CS is low. When CS
is high, data presented at DIN is ignored and DOUT is
in high-impedance mode. Note: CS must transition
high after each read/write operation. DOUT is the
serial data output for reading registers to facilitate easy
debugging during development. DIN and DOUT can
be connected together to form a 3-wire serial interface
bus or remain separate and form a 4-wire SPI bus.
The serial interface supports two-byte transfer in a
communication cycle. The first byte is a control byte
written to the MAX5894 only. The second byte is a data
byte and can be written to or read from the MAX5894.
Table 1. Quadrature Modulator Operating Data Rates (fIM is the Data Rate at the Input of
the Modulator) for Dual-Port Mode
INTERPOLATION RATE MODULATION MODE (fLO)MODULATION FREQUENCY
RELATIVE TO fDAC
MODULATION FREQUENCY
RELATIVE TO fDATA
fIM/2 fDAC/2 fDATA/2
1x fIM/4 fDAC/4 fDATA/4
fIM/2 fDAC/2 fDATA
2x fIM/4 fDAC/4 fDATA/2
fIM/2 fDAC/2 2 x fDATA
4x fIM/4 fDAC/4 fDATA
fIM/2 fDAC/4 2 x fDATA
8x fIM/4 fDAC/8 fDATA
When writing to the MAX5894, data is shifted into DIN;
data is shifted out of DOUT in a read operation. Bits 0 to
3 of the control byte are the address bits. These bits set
the address of the register to be written to or read from.
Bits 4 to 6 of the control byte must always be set to 0.
Bit 7 is a read/write bit: 0 for write operation and 1 for
read operation. The most significant bit (MSB) is shifted
in first in default mode. If the serial port is set to LSB-first
mode, both the control byte and data byte are shifted LSB
in first. Figures 1 and 2 show the SPI serial-interface oper-
ation in the default write and read mode, respectively.
Figure 3 is a timing diagram for the SPI serial interface.
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 13
Figure 1. SPI Serial-Interface Write Cycle, MSB-First Mode
CS
SCLK
DIN
DOUT
10003210
HIGH
IMPEDANCE
IGNORED
ADDRESS DATA
READ CYCLE N - 1
DATA N - 2
10003210
HIGH
IMPEDANCE
IGNORED
ADDRESS DATA
READ CYCLE N
DATA N - 1
10003210
HIGH
IMPEDANCE
IGNORED
ADDRESS DATA
READ CYCLE N + 1
DATA N
0 0 0 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CS
SCLK
DIN
DOUT HIGH IMPEDANCE
Figure 2. SPI Serial-Interface Read Cycle, MSB-First Mode
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
14 ______________________________________________________________________________________
tSS
SCLK
DIN
tSDS tSDH
CS
tSDV
DOUT
Figure 3. SPI Serial-Interface Timing Diagram
MAX5894
Programming Registers
Programming its registers with the SPI serial interface
sets the MAX5894 operation modes. Table 2 shows all
of the registers. The following are descriptions of each
register.
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 15
ADD BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h Unused 0 = MSB first
1 = LSB first
Software Reset
0 = Normal
1 = Reset all
registers
Interpolator
Power-Down
0 = Normal
1 = Power-down
IDAC Power-
Down
0 = Normal
1 = Power-down
QDAC Power-
Down
0 = Normal
1 = Power-down
Unused
01h
Interpolation Rate
(Bit 7, Bit 6)
00 = No interpolation
01 = 2x interpolation
10 = 4x interpolation
11 = 8x interpolation
Third
Interpolation
Filter
Configuration
0 = Lowpass
1 = Highpass
Modulation Mode
(Bit 4, Bit 3)
00 = Modulation off
01 = fIM/2
10 = fIM/4
11 = fIM/4
Mixer Modulation
Mode
0 = Complex
1 = Real
Modulation
Sign
0 = e-jω
1 = e-jω
Unused
02h
0 = Two’s
complement
input data
1 = Offset
binary input
data
0 = Single
port (A),
interleaved
I/Q
1 = Dual port
I/Q input
0 = Clock output
on DATACLK
1 = Clock output
on D ATAC LK/B12
0 = Input data
latched on
rising clock
edge
1 = Input data
latched on falling
clock edge
0 = Data clock
input enabled
1 = Data clock
output enabled
Data
Synchronizer
0 = Enabled
1 = Disabled
Unused
03h Unused
04h 8-Bit IDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
05h Unused 4-Bit IDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
06h 10-Bit IDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 06h register are the MSB bits. Bit 1 and bit 0 are the LSB
bits in 07h register. Default: 000h
07h
IDAC IOFFSET
Direction
0 = Current on
OUTIN
1 = Current on
OUTIP
Unused
IDAC Offset
Adjustment
Bit 1
(see 06h
register)
IDAC Offset
Adjustment
Bit 0
(see 06h
register)
08h 8-Bit QDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
09h Unused 4-Bit QDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
0Ah 10-Bit QDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 0Ah register are the MSB bits. Bit 1 and bit 0 are the
LSB bits in 0Bh register. Default: 000h
0Bh
QDAC
IOFFSET
Direction
0 = Current on
OUTQN
1 = Current on
OUTQP
Unused
QDAC Offset
Adjustment
Bit 1
(see 0Ah
register)
QDAC Offset
Adjustment
Bit 0
(see 0Ah
register)
0Ch Reserved, do not write to these bits.
0Dh Reserved, do not write to these bits.
0Eh Reserved, do not write to these bits.
Table 2. MAX5894 Programmable Registers
Conditions in bold are default states after reset.
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
16 ______________________________________________________________________________________
Address 00h
Bit 6 Logic 0 (default) causes the serial port to use
MSB first address/data format. When set to a
logic 1, the serial port uses LSB first address/
data format.
Bit 5 When set to a logic 1, all registers reset to
their default state (this bit included).
Bit 4 Logic 1 stops the clock to the digital interpo-
lators. DAC outputs hold last value prior to
interpolator power-down.
Bit 3 IDAC power-down mode. A logic 1 to this bit
powers down the IDAC.
Bit 2 QDAC power-down mode. A logic 1 to this bit
powers down the QDAC.
Note: If both bit 2 and bit 3 are 1, the MAX5894 is in
full-power-down mode, leaving only the serial interface
active.
Address 01h
Bits 7, 6 Configure the interpolation filters according
to the following table:
00 1x (no interpolation)
01 2x
10 4x
11 8x (default)
Bit 5 Logic 0 configures FIR3 as a lowpass digital
filter (default). A logic 1 configures FIR3 as a
highpass digital filter.
Bits 4, 3 Configure the modulation frequency accord-
ing to the following table:
00 No modulation
01 fIM/2 modulation
10 fIM/4 modulation (default)
11 fIM/4 modulation
where fIM is the data rate at the input of the
modulator.
Bit 2 Configures the modulation mode for either
real or complex (image reject) modulation.
Logic 1 sets the modulator to the real mode
(default). Complex modulation is only avail-
able for fIM/4 modulation.
Bit 1 Quadrature modulator sign inversion. With I-
channel data leading Q-channel data by 90°,
logic 0 sets the complex modulation to be
e-jw (default), cancelling the upper image
when used with an external quadrature mod-
ulator. A logic 1 sets the complex modulation
to be e+jw, cancelling the lower image when
used with an external quadrature modulator.
Address 02h
Bit 7 Logic 0 (default) configures the data port for
two’s complement. A logic 1 configures the
data ports for offset binary.
Bit 6 Logic 0 (default) configures the data bus for
single-port, interleaved I/Q data. I and Q data
enter through one 14-bit bus. Logic 1 config-
ures the data bus for dual-port I/Q data. I and
Q data enter on separate buses.
Bit 5 Logic 0 (default) configures the data clock
for pin 14. A logic 1 configures the data clock
for pin 27 (DATACLK/B12).
Bit 4 Logic 0 (default) sets the internal latches to
latch the data on the rising edge of DATACLK.
A logic 1 sets the internal latches to latch the
data on the falling edge of DATACLK.
Bit 3 Logic 0 (default) configures the DATACLK
pin (pin 14 or pin 27) to be an input. A logic 1
configures the DATACLK pin to be an output.
Bit 2 Logic 0 (default) enables the data synchro-
nizer circuitry. A logic 1 disables the data
synchronizer circuitry.
Address 03h
Bits 7–0 Unused.
Address 04h
Bits 7–0 These 8 bits define the binary number for
fine-gain adjustment of the IDAC full-scale
current (see the
Gain Adjustment
section). Bit
7 is the MSB. Default is all zeros.
Address 05h
Bits 3–0 These four bits define the binary number for
the coarse-gain adjustment of the IDAC full-
scale current (see the
Gain Adjustment
sec-
tion). Bit 3 is the MSB. Default is all ones.
Address 06h, Bits 7–0; Address 07h, Bit 1 and Bit 0
These 10 bits represent a binary number that
defines the magnitude of the offset added to
the IDAC output (see the
Offset Adjustment
section). Default is all zeros.
Address 07h
Bit 7 Logic 0 (default) adds the 10 bits offset cur-
rent to OUTIN. A logic 1 adds the 10 bits off-
set current to OUTIP.
Address 08h
Bits 7–0 These eight bits define the binary number for
fine-gain adjustment of the QDAC full-scale
current (see the
Gain Adjustment
section). Bit
7 is the MSB. Default is all zeros.
Address 09h
Bits 3–0 These four bits define the binary number for
the coarse-gain adjustment of the QDAC full-
scale current (see the
Gain Adjustment
sec-
tion). Bit 3 is the MSB. Default is all ones.
Address 0Ah, Bits 7–0; Address 0Bh, Bit 1 and Bit 0
These 10 bits represent a binary number that
defines the magnitude of the offset added to
the QDAC output (see the
Offset Adjustment
section). Default is all zeros.
Address 0Bh
Bit 7 Logic 0 (default) adds the 10 bits offset to
OUTQN. A logic 1 adds the 10 bits offset to
OUTQP.
Offset Adjustment
Offset adjustment is achieved by adding a digital code to
the DAC inputs. The code OFFSET (see equation below),
as stored in the relevant control registers, has a range
from 0 to 1023 and a sign bit. The applied DAC offset is
stored in the register, providing an offset adjustment
range of ±1023 LSB codes. The resolution is 1 LSB.
Gain Adjustment
Gain adustment is peformed by varying the full-scale
current according to the following formula:
where IREF is the reference current (see the
Reference
Input/Output
section). COARSE is the register content
of registers 05h and 09h for the I- and Q-channel,
respectively. FINE is the register content of register 04h
and 08h for the I- and Q-channel, respectively. The
range of coarse is from 0 to 15, with 15 being the
default. The range for FINE is from 0 to 255 with 0
being the default. The gain can be adjusted in steps of
approximately 0.01dB.
Single-Port/Dual-Port Data-Input Modes
The MAX5894 is capable of capturing data in single-
port and dual-port modes (selected through bit 6,
address 02h). In single-port mode, the data for both
DAC channels is latched on the A port (A13–A0).
The channel for the input data is determined by the
state of the SELIQ/B13 (pin 26) bit. When SELIQ is set
to logic-high, the input data is presented to the
I-channel, when set to logic-low, the input data is
presented to the Q-channel. The unused B-port inputs
(DATACLK/B12, B11–B0) should be grounded when
running in single-port mode.
Dual-port mode, as the name implies, requires that
each channel receives its data from a separate data
bus. SELIQ/B13 and DATACLK/B12 revert to data bit
inputs for the Q-channel in dual-port mode.
The MAX5894 control registers can be programmed to
allow either signed or unsigned binary format (bit 7,
address 02h) data in either single-port or dual-port
mode. Table 3 shows the corresponding DAC output
levels when using signed or unsigned data modes.
Data Synchronization Modes
Data synchronization circuitry is provided to allow oper-
ation with an input data clock. The data clock must be
frequency locked to the DAC clock (fDAC), but can
have arbitrary phase with respect to the DAC clock.
The synchronization circuitry allows for phase jitter on
the input data clock of up to ±1 data clock cycles.
Synchronization is initially established when the reset
pin is asynchronously deasserted and the input data
clock has been running for at least four clock cycles.
Subsequently, the MAX5894 monitors the phase rela-
IICOARSE IFINE
OUTFS REF REF
=×
⎛
⎝
⎜⎞
⎠
⎟+
⎛
⎝
⎜⎞
⎠
⎟×
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢⎤
⎦
⎥⎛
⎝
⎜⎞
⎠
⎟
−
3
4
1
16
3
32 256
1024
24
IOFFSET I
OFFSET OUTFS
=×
214
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 17
DIGITAL INPUT CODE
OFFSET
BINARY
(UNSIGNED)
TWO'S
COMPLEMENT
(SIGNED)
OUT_P OUT_N
00 0000 0000 0000 10 0000 0000 0000 0 IOUTFS
01 1111 1111 1111 00 0000 0000 0000 IOUTFS/2 IOUTFS/2
11 1111 1111 1111 01 1111 1111 1111 IOUTFS 0
Table 3. DAC Output Code Table
MAX5894
tionship and detects if the phase drifts more than ±1
data clock cycle. If this occurs, the synchronizer auto-
matically re-establishes synchronization. However, dur-
ing the resynchronization phase, up to 8 data words
may be lost or repeated.
Bit 2 of register 02h disables or enables (default) the
automatic data clock phase detection. Disabling the
data synchronization circuitry requires the data clock
and the DAC clock phase to be locked.
DATACLK Modes
The MAX5894 has a main DATACLK available at
pin 14. An alternate DATACLK is available at pin 27
(DATACLK/B12) when configured in single-port data
input mode (bit 5, address 02h). The DATACLK can be
configured to accept an input clock signal for latching
the input data, or to source a clock signal that can drive
up to 10pF load while latching the input data (bit 3,
address 02h). If DATACLK is configured as an output, it
is frequency divided from the CLKP/CLKN input,
depending on the operating mode, see Table 4.
The MAX5894 can be configured to latch the input
data on either the rising edge or falling edge of the
DATACLK signal (bit 4, address 02h). Figure 4 shows
the timing requirements between the DATACLK signal
and the input-data bus with latching on the rising edge.
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
18 ______________________________________________________________________________________
INPUT
MODE
INTERPOLATION
RATE fDATA:fCLK fDAC:fCLK
1x 1:1 1:2
2x 1:1 1:1
4x 1:2 1:1
Single
Port
8x 1:4 1:1
1x 1:1 1:1
2x 1:2 1:1
4x 1:4 1:1
Dual Port
8x 1:8 1:1
Table 4. Clock Frequency Ratios in
Various Modes
Figure 4. Data-Input Timing Diagram
tDtDS
tCLK
CLKP–CLKN
DATACLK
A0–A13/B0–B13
tDH
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 19
Interpolating Filter
The MAX5894 features three cascaded FIR half-band
filters. The interpolating filters are enabled or disabled
in combinations to support 1x (no interpolation), 2x, 4x,
or 8x interpolation. Bits 7 and 6 of register 01h set the
interpolation rate (see Table 2). The last interpolation fil-
ter is located after the modulator. In the 8x interpolation
mode, the last filter (FIR3) can be configured as low-
pass or highpass (bit 5, address 01h) to select the
lower or upper sideband from the modulation output.
The frequency responses of these three filters are plot-
ted in Figures 5–8.
Figure 5. Interpolation Filter Frequency Response, 2x
Interpolation Mode
0 0.1 0.2 0.3 0.4
-0.0004
-0.0002
0
PASSBAND DETAIL
0
0 0.4 0.6 0.8
fOUT - NORMALIZED TO INPUT DATA RATE
1.0 1.2 1.4 1.6 1.8 2.0
-20
-40
-60
-80
-100
GAIN (dBFS)
-120
0.2
00.1 0.2 0.3 0.4
-0.0004
-0.0002
0
PASSBAND DETAIL
Figure 6. Interpolation Filter Frequency Response, 4x
Interpolation Mode
0
0 1.0 1.5 2.0
fOUT - NORMALIZED TO INPUT DATA RATE
2.5 3.0 3.5 4.0
-20
-40
-60
-80
-100
GAIN (dBFS)
-120
0.5
00.1 0.2 0.3 0.4
-0.0004
-0.0002
0
PASSBAND DETAIL
Figure 7. Interpolation Filter Frequency Response, 8x
Interpolation Mode (FIR3 Lowpass Mode)
0
0234
fOUT - NORMALIZED TO INPUT DATA RATE
5678
-20
-40
-60
-80
-100
GAIN (dBFS)
-120
1
00.1 0.2 0.3 0.4
-0.0004
-0.0002
0
PASSBAND DETAIL
Figure 8. Interpolation Filter Frequency Response, 8x
Interpolation Mode (FIR3 Highpass Mode)
0
0234
fOUT - NORMALIZED TO INPUT DATA RATE
5678
-20
-40
-60
-80
-100
GAIN (dBFS)
-120
1
3.6 3.8 4.0 4.2 4.4
-0.0004
-0.0002
0
PASSBAND DETAIL
MAX5894
The programmable interpolation filters multiply the
MAX5894 input data rate by a factor of 2x, 4x, or 8x to
separate the reconstructed waveform spectrum and the
DAC image. The original spectral images, appearing at
around multiples of the input data rate, are attenuated
by the internal digital filters. This feature provides three
benefits:
1) Image separation reduces complexity of analog
reconstruction filters.
2) Lower input data rates eliminate board-level high-
speed data transmission.
3) Sin(x)/x rolloff is reduced over the effective bandwidth.
Figure 9 illustrates a practical example of the benefits
when using the MAX5894 in 2x, 4x, and 8x interpolation
modes with the third filter configured as a lowpass filter.
With no interpolation filter, the first image signal appears
in the second Nyquist zone between fS/2 and fS. The first
interpolating filter removes this image. In fact, all of the
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
20 ______________________________________________________________________________________
Figure 9. Spectral Representation of Interpolating Filter Responses (Output Frequencies are Relative to the Data Input Frequency, fS)
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
FILTER
RESPONSE
FILTER
RESPONSE
FILTER
RESPONSE
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
INPUT
SPECTRUM
AND THIRD
FILTER
RESPONSE
OUTPUT
SPECTRUM
OF THE
THIRD
FILTER
2x INTERPOLATION
4x INTERPOLATION
8x INTERPOLATION
NO INTERPOLATION
SIGNAL IMAGE
SIGNAL IMAGE
SIGNAL IMAGE
SIGNAL
SIGNAL
SIGNAL
IMAGE
IMAGE
IMAGE
images at odd numbers of fSare filtered. At the output of
the first filter, the images are at 2fS, 4fS, etc. This signal is
then passed to the second interpolating filter, which is
similar to the first filter and removes the images at 2fS, 6fS,
10fS, etc. Finally, the third filter removes images at 4fS,
12fS, 20fS, etc. Figures 10, 11, and 12 similarly illustrate
the spectral responses when using the interpolating filters
combined with the digital modulator.
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 21
Figure 10. Spectral Representation of 4x Interpolation Filter with fIM/4 Modulation (Output Frequencies are Relative to the Data Input
Frequency, fS)
FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND
LOWER
SIDEBAND
UPPER
SIDEBAND
fS2fS3fS4fS
fS2fS3fS4fS
fS2fS3fS4fS
fS2fS3fS4fS
fS2fS3fS4fS
FILTER
RESPONSE
FILTER
RESPONSE
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
OUTPUT
SPECTRUM
OF THE
MODULATOR
2x INTERPOLATION
4x INTERPOLATION
NO INTERPOLATION
SIGNAL IMAGE
SIGNAL IMAGE
SIGNAL IMAGE
SIGNAL
SIGNAL
IMAGE
IMAGE
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
22 ______________________________________________________________________________________
Figure 11. Spectral Representation of 8x Interpolation Filter with fIM/4 Modulation and Lowpass Mode Enabled (Output Frequencies
are Relative to the Data Input Frequency, fS)
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
FILTER
RESPONSE
FILTER
RESPONSE
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
OUTPUT
SPECTRUM
OF THE
MODULATOR
OUTPUT
SPECTRUM
OF THE
THIRD
FILTER
2x INTERPOLATION
4x INTERPOLATION
8x INTERPOLATION
NO INTERPOLATION
SIGNAL IMAGE
SIGNAL IMAGE
SIGNAL IMAGE
SIGNAL
SIGNAL
IMAGE
IMAGE
IMAGE
IMAGE
fS2fS3fS4fS5fS6fS7fS8fS
FILTER RESPONSE
INPUT
SPECTRUM
AND THIRD
FILTER
RESPONSE
SIGNAL
FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND
LOWER
SIDEBAND
UPPER
SIDEBAND
SIGNAL
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 23
Figure 12. Spectral Representation of 8x Interpolation Filter with fIM/4 Modulation and Highpass Mode Enabled (Output Frequencies
are Relative to the Data Input Frequency, fS)
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
fS2fS3fS4fS5fS6fS7fS8fS
FILTER
RESPONSE
FILTER
RESPONSE
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
OUTPUT
SPECTRUM
OF THE
MODULATOR
OUTPUT
SPECTRUM
OF THE
THIRD
FILTER
2x INTERPOLATION
4x INTERPOLATION
8x INTERPOLATION
NO INTERPOLATION
SIGNAL IMAGE
SIGNAL IMAGE
SIGNAL IMAGE
SIGNAL
SIGNAL
IMAGE
IMAGE
IMAGE
IMAGE
fS2fS3fS4fS5fS6fS7fS8fS
FILTER
RESPONSE
INPUT
SPECTRUM
AND THIRD
FILTER
RESPONSE
SIGNAL
FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND
LOWER
SIDEBAND
UPPER
SIDEBAND
SIGNAL
MAX5894
Digital Modulator
The MAX5894 features digital modulation at frequencies
of fIM/2 and fIM/4, where fIM is the data rate at the input
to the modulator. fIM equals fDAC in 1x, 2x, and 4x inter-
polation modes. In 8x interpolation mode, fIM equals
fDAC/2. The output rate of the modulator is always the
same as the input data rate to the modulator.
In complex modulation mode, data from the second
interpolation filter is frequency mixed with the on-chip
in-phase and quadrature (I/Q) local oscillator (LO).
Complex modulation provides the benefit of image
sideband rejection when combined with an external
quadrature modulator commonly found in wireless
communication systems.
In the fLO = fIM/4 mode, real or complex modulation can
be used. The modulator multiplies successive input data
samples by the sequence [1, 0, -1, 0] for a cos(ωt). The
modulator modulates the input signal up to fIM/4, creat-
ing upper and lower images around fIM/4. The quadra-
ture LO sin(ωt) is realized by delaying the cos(ωt)
sequence by one clock cycle. Using complex modula-
tion, complex IF is generated. The complex IF combined
with an external quadrature modulator provides image
rejection. The sign of the LO can be changed to allow
the user to select whether the upper or the lower image
should be rejected (bit 1 of register 01h).
When fIM/2 is chosen as the LO frequency, the input
signal is multiplied by [-1, 1] on both channels. This pro-
duces images around fIM/2. The complex image-reject
modulation mode is not available for this LO frequency.
The outputs of the modulator can be expressed as:
in complex modulation, e+jwt
in complex modulation, e-jwt
where ω= 2 x πx fLO.
For real modulation, the outputs of the modulator can
be expressed as:
If more than one MAX5894 is used, their LO phases
can be synchronized by simultaneously releasing
RESET. This sets the MAX5894 to its predefined initial
phase.
Device Reset
The MAX5894 can be reset by holding the RESET pin
low for 10ns. This will program the control registers to
their default values in Table 2. During power-on, RESET
must be held low until all power supplies have stabi-
lized. Alternatively, programming bit 5 of address 00h
to a logic-high also resets the MAX5894 after power-up.
It At t
Qt At t
()
=
()
×
()
()
=
()
×
()
cos
cos
ω
ω
It At t Bt t
Qt At t Bt t
()
=
()
×
()
+
()
×
()
()
=
()
×
()
+
()
×
()
cos sin
sin cos
ωω
ωω
It At t Bt t
Qt At t Bt t
()
=
()
×
() ()
×
()
()
=
()
×
()
+
()
×
()
− cos sin
sin cos
ωω
ωω
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
24 ______________________________________________________________________________________
Figure 13. (a) Modulator in Complex Modulation Mode; (b) Modulator in Real Modulation Mode
sin(ωt)
sin(ωt)
cos(ωt)
cos(ωt)
I-CHANNEL
INPUT DATA
TO
FIR3
(a)
Q-CHANNEL
INPUT DATA
I-CHANNEL
OUTPUT DATA
Q-CHANNEL
OUTPUT DATA
(b)
∑
∑
sin(ωt)
sin(ωt)
cos(ωt)
cos(ωt)
I-CHANNEL
INPUT DATA
TO
FIR3
Q-CHANNEL
INPUT DATA
I-CHANNEL
OUTPUT DATA
Q-CHANNEL
OUTPUT DATA
∑
∑
Power-Down Mode
The MAX5894 features three power-saving modes.
Each DAC can be individually powered down through
bits 2 and 3 of address 00h. The interpolation filters can
also be powered down through bit 4 of address 00h,
preserving the output level of each DAC (the DACs
remain powered). Powering down both DACs automati-
cally puts the MAX5894 into full power-down, including
the interpolation filters.
Applications Information
Frequency Planning
System designers need to take the DAC into account
during frequency planning for high-performance appli-
cations. Proper frequency planning can ensure that
optimal system performance is achieved. The
MAX5894 is designed to deliver excellent dynamic per-
formance across wide bandwidths, as required for
communication systems. As with all DACs, some com-
binations of output frequency and update rate produce
better performance than others.
Harmonics are often folded down into the band of inter-
est. Specifically, if the DAC outputs a frequency close
to fS/N, the Mth harmonic of the output signal will be
aliased down to:
Thus, if N ≈(M + 1), the Mth harmonic will be close to
the output frequency. SFDR performance of a current-
steering DAC is often dominated by 3rd-order harmonic
distortion. If this is a concern, placing the output signal
at a different frequency other than fS/4 should be con-
sidered.
Common to interpolating DACs are images near the
divided clocks. In a DAC configured for 4x interpolation,
this applies to images around fS/4 and fS/2. In a DAC
configured for 8x interpolation, this applies to images
around fS/8, fS/4, and fS/2. Most of these images are
not part of the in-band (0 to fDATA/2) SFDR specifica-
tion, though they are a consideration for out-of-band
(fDATA/2 - fDAC/2) SFDR and may depend on the rela-
tionship of the DATACLK to DAC update clock (see the
Data Clock
section). When specifying the output recon-
struction filter for other than baseband signals, these
images should not be ignored.
Data Clock
The MAX5894 features synchronizers that allow for arbi-
trary phase alignment between DATACLK and
CLKP/CLKN. The DATACLK causes internal switching in
the MAX5894 and the phase between DATACLK (input
mode) to CLKP/CLKN influences the images at
DATACLK. Optimum image rejection is achieved when
DATACLK transitions are aligned with the falling edge of
CLKP. Figure 14 shows the image level near DATACLK
as a function of the DATACLK (input mode) to
CLKP/CLKN phase at 500Msps, 4x interpolation for a
10MHz, -6dBFS output signal.
Clock Interface
The MAX5894 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AVCLK) to
achieve optimum jitter performance. It uses an ultra-low
jitter clock to achieve the required noise density. Clock
jitter must be less than 0.5psRMS to meet the specified
noise density. For that reason, the CLKP/CLKN input
source must be designed carefully. The differential
clock (CLKN and CLKP) input can be driven from a sin-
gle-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended opera-
tion, drive CLKP with a low noise source and bypass
CLKN to GND with a 0.1µF capacitor.
The CLKP and CLKN pins are internally biased to
AVCLK/2. This allows the user to AC-couple clock
ff Mf f NM
N
S OUT S
=×=
⎡
⎣
⎢⎤
⎦
⎥
−−
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 25
Figure 14. Effect of CLKP/CLKN to DATACLK Phase on fS/4
Images
fS/4 IMAGES vs. CLKP/CLKN to DATACLK DELAY
fDATA = 125Mwps, 4x INTERPOLATION
CLKP/CLKN DELAY (ns)
IMAGE LEVEL (dBc)
642
-100
-90
-80
-70
-60
-50
-110
08
fS/4 - fOUT
fOUT = 10MHz
AOUT = -6dBFS
fS/4 + fOUT
MAX5894
sources directly to the device without external resistors
to define the DC level. The input resistance of CLKP
and CLKN is 5kΩ.
A convenient way to apply a differential signal is with a
balun transformer as shown in Figure 15. Alternatively,
these inputs may be driven from a CMOS-compatible
clock source, however it is recommended to use
sine-wave or AC-coupled differential ECL/PECL drive for
best dynamic performance.
Output Interface (OUTI, OUTQ)
The MAX5894 outputs complementary currents (OUTIP,
OUTIN, OUTQP, and OUTQN) that can be utilized in a
differential configuration. Load resistors convert these
two output currents into a differential output voltage.
The differential output between OUTIP (OUTQP) and
OUTIN (OUTQN) can be converted to a single-ended
output using a transformer or a differential amplifier.
Figure 16 shows a typical transformer-based applica-
tion circuit for generation of IF output signals. In this
configuration, the MAX5894 operates in differential
mode, which reduces even-order harmonics, and
increases the available output power. Pay close atten-
tion to the transformer core saturation characteristics
when selecting a transformer. Transformer core satura-
tion can introduce strong second harmonic distortion,
especially at low output frequencies and high signal
amplitudes. It is recommended to connect the trans-
former center tap to ground.
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
26 ______________________________________________________________________________________
Figure 15. Single-Ended-to-Differential Clock Conversion Using
a Balun Transformer
SINGLE-ENDED
IINPUT
1:1 RATIO
MINI-CIRCUITS
ADTL1-12 24.9Ω
24.9Ω
CLKP
CLKN
100nF
100nF
MAX5894
Figure 16. Differential-to-Single-Ended Conversion Using Wideband RF Transformers
MAX5894
OUTQP
OUTQN
QDAC
14 1:1
1:1
50Ω
100Ω
50Ω
VQOUT, SINGLE-ENDED
OUTIP
OUTIN
IDAC
14 1:1
1:1
50Ω
100Ω
50Ω
VIOUT, SINGLE-ENDED
If a transformer is not used, the outputs must have a
resistive termination to ground. Figure 17 shows the
MAX5894 output configured for differential DC-coupled
mode. The DC-coupled configuration can be used to
eliminate waveform distortion due to highpass filter
effects. Applications include communication systems
employing analog quadrature upconverters and requir-
ing a high-speed DAC for baseband I/Q synthesis.
If a single-ended DC-coupled unipolar output is desir-
able, OUTIP (OUTQP) should be selected as the out-
put, and connect OUTIN (OUTQN) to ground. Using the
MAX5894 output single-ended is not recommended
because it introduces additional noise and distortion.
The distortion performance of the DAC also depends
on the load impedance. The MAX5894 is optimized for
a 50Ωdouble termination. It can be used with a trans-
former output as shown in Figure 16 or just one 25Ω
resistor from each output to ground and one 50Ωresis-
tor between the outputs (Figure 17). Higher output ter-
mination resistors can be used, as long as each output
voltage does not exceed +1V with respect to GND, but
at the cost of degraded distortion performance and
increased output noise voltage.
Reference Input/Output
The MAX5894 supports operation with the on-chip 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, low-
impedance reference source, and as the output if the
DAC is operating with the internal reference.
For stable operation with the internal reference, REFIO
should be decoupled to GND with a 1µF capacitor.
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 27
Figure 17. The DC-Coupled Differential Output Configuration
MAX5894
OUTQP
OUTQN
QDAC
14
25Ω
50Ω
25Ω
OUTIP
OUTIN
IDAC
14
25Ω
50Ω
25Ω
MAX5894
REFIO must be buffered with an external amplifier, if heavy
loading is required, due to its 10kΩoutput resistance.
Alternatively, apply a temperature-stable external refer-
ence to REFIO (Figure 18). The internal reference is over-
driven by the external reference. For improved accuracy
and drift performance, choose a fixed output voltage ref-
erence such as the MAX6520 bandgap reference.
The MAX5894’s reference circuit (Figure 19) employs a
control amplifier, designed to regulate the full-scale cur-
rent IOUT for the differential current outputs of the DAC.
The output current can be calculated as:
IOUTFS = 32 x IREF x 16383/16384
where IREF is the reference output current (IREF = VREFIO/
RSET). Located between FSADJ and DACREF, RSET is the
reference resistor, which determines the amplifier’s output
current for the DAC. Use Table 5 for a matrix of different
IOUTFS and RSET selections.
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
28 ______________________________________________________________________________________
Figure 18. Typical External Reference Circuit
1.2V
REFERENCE
CURRENT-
SOURCE
ARRAY DAC
REFIO
EXTERNAL
1.25V
REFERENCE
RSET
FSADJ
IREF
10kΩ
DACREF
1µF
MAX5894
1.2V
REFERENCE
CURRENT-
SOURCE
ARRAY DAC
REFIO
FSADJ
IREF
10kΩ
DACREF
1µF
MAX5894
RSET
FULL-SCALE
CURRENT
REFERENCE
CURRENT RSET (kΩ) OUTPUT VOLTAGE
IOUTFS (mA) IREF (µA) CALCULATED 1% EIA STD VIOUTP/N* (mVP-P)
2 62.50 19.2 19.1 100
5 156.26 7.68 7.5 250
10 312.50 3.84 3.83 500
15 468.75 2.56 2.55 750
20 625.00 1.92 1.91 1000
Figure 19. MAX5894 Internal Reference Architecture
Table 5. IOUTFS and RSET Selection Matrix Based on a Typical 1.20V Reference Voltage
*
Terminated into a 50
Ω
load.
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 29
Power Supplies, Bypassing,
Decoupling, and Layout
Grounding and power-supply decoupling strongly influ-
ence the MAX5894 performance. Unwanted digital
crosstalk can couple through the input, reference,
power-supply, and ground connections, which can
affect dynamic specifications like signal-to-noise ratio
or spurious-free dynamic range. In addition, electro-
magnetic interference (EMI) can either couple into or
be generated by the MAX5894. Observe the grounding
and power-supply decoupling guidelines for high-
speed, high-frequency applications. Follow the power-
supply and filter configuration guidelines to achieve
optimum dynamic performance.
Using a multilayer PCB with separate ground and
power-supply planes, run high-speed signals on lines
directly above the ground plane. Since the MAX5894
has separate analog and digital sections, the PCB
should include separate analog and digital ground sec-
tions with only one point connecting the three planes at
the exposed pad under the MAX5894. Run digital sig-
nals above the digital ground plane and analog/clock
signals above the analog/clock ground plane. Keep
digital signals as far away from sensitive analog inputs,
reference lines, and clock inputs as practical. Use a
symmetric design of clock input and the analog output
lines to minimize 2nd-order harmonic distortion compo-
nents, thus optimizing the dynamic performance of the
DAC. Keep digital signal paths short and run lengths
matched to avoid propagation delay and data skew
mismatches.
The MAX5894 requires five separate power-supply
inputs for the analog (AVDD1.8 and AVDD3.3), digital
(DVDD1.8 and DVDD3.3), and clock (AVCLK) circuitry.
Decouple each voltage supply pin with a separate
0.1µF capacitor as close to the device as possible and
with the shortest possible connection to the appropriate
ground plane. Minimize the analog and digital load
capacitances for optimized operation. Decouple all
power-supply voltages at the point they enter the PCB
with tantalum or electrolytic capacitors. Ferrite beads
with additional decoupling capacitors forming a pi-net-
work could also improve performance.
The exposed pad MUST be soldered to the ground.
Use multiple vias, an array of at least 4 x 4 vias, directly
under the EP to provide a low thermal and electrical
impedance path for the IC.
Static Performance Parameter
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified.
For a DAC, the deviations are measured at every indi-
vidual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full-scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Dynamic Performance
Parameter Definitions
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the specified accuracy.
Noise Spectral Density
The DAC output noise is the sum of the quantization
noise and thermal noise. Noise spectral density is the
noise power in 1Hz bandwidth, specified in dBFS/Hz.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog output (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
maximum SNR can be derived from the DAC’s resolu-
tion (N bits):
SNRdB = 6.02dB x N + 1.76dB
MAX5894
However, noise sources such as thermal noise, refer-
ence noise, clock jitter, etc., affect the ideal reading.
Therefore, SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spec-
tral components minus the fundamental, the first four
harmonics, and the DC offset.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the carrier
frequency (maximum signal components) to the RMS
value of their next largest distortion component. SFDR
is usually measured in dBc and with respect to the car-
rier frequency amplitude or in dBFS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or
to Nyquist.
Two-/Four-Tone Intermodulation
Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or
dBFS) of the worst 3rd-order (or higher) IMD products
to either output tone.
Adjacent Channel Leakage
Power Ratio (ACLR)
Commonly used in combination with WCDMA (wide-
band code-division multiple-access), ACLR reflects the
leakage power ratio in dB between the measured pow-
ers within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
30 ______________________________________________________________________________________
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 31
Pin Configuration
5859606162 5455565763
38
39
40
41
42
43
44
45
46
47
A9
A3
OUTIP
QFN
TOP VIEW
OUTIN
GND
AVDD3.3
GND
OUTQP
OUTQN
GND
AVDD3.3
GND
5253
AVDD1.8
DACREF
A4
DVDD1.8
A2
A0
A1
N.C.
N.C.
DATACLK/B12
SELIQ/B13
B10
B11
B9
DVDD1.8
B8
SCLK
DIN
DOUT
DVDD3.3
N.C.
N.C.
B0
B1
B2
B3
35
36
37 DVDD1.8
B4
B5
A10
A11
A12
A13
DVDD1.8
A6
A7
DATACLK
DVDD3.3
A8
N.C.
N.C.
N.C.
CLKN
48 CS
CLKP
64
GND
656667
AVDD1.8
GND
AVDD3.3
68
AVCLK
2322212019 2726252418 2928 323130
B7
B6
3433
49
50 REFIO
RESET
51
FSADJ
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
A5 17
MAX5894
EXPOSED PAD
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
68 QFN-EP G6800-4 21-0122
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
MAX5894
14-Bit, 500Msps, Interpolating and Modulating
Dual DAC with CMOS Inputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 — Initial release —
1 4/07 — —
2 10/08 Add note to setup and hold specifications. 5, 6
