M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Based on 32Mx16 DDR2 SDRAM Features * JEDEC Standard 240-pin Dual In-Line Memory Module * Address and control signals are fully synchronous to positive * 32Mx64 DDR2 Unbuffered DIMM based on 32Mx16 DDR2 clock edge SDRAM * Programmable Operation: - Device CAS Latency: 3, 4, 5 * Performance: - Burst Type: Sequential or Interleave PC2-3200 PC2-4200 PC2-5300 Speed Sort * DIMM CAS Latency f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency 5A 37B 3C 3 4 5 200 266 333 - Burst Length: 4, 8 Unit - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes MHz 5 3.7 3 ns 400 533 667 MHz * Automatic and controlled precharge commands * 13/10/1 Addressing (row/column/bank) * Intended for 200 MHz, 266MHz, and 333MHz applications * 7.8s Max. Average Periodic Refresh Interval * Inputs and outputs are SSTL-18 compatible * Serial Presence Detect * VDD = VDDQ = 1.8Volt 0.1 * Gold contacts * SDRAMs have 4 internal banks for concurrent operation * SDRAMs in 84-ball FBGA Package * Differential clock inputs * Data is read or written on both clock edges * Bi-directional data strobe with one clock cycle preamble and one-half clock post-amble Description M1U25664TUH4A0F & M1Y25664TUH4A0F are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as a one-rank 64Mx64 high-speed memory array. Modules use four 32Mx16 DDR2 SDRAMs in FBGA packages. These DIMMs manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 200 MHz (266MHz and 333MHz) clock speeds and achieves high-speed data transfer rates of up to 400 MHz (533MHz and 667MHz). Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. Ordering Information Part Number Speed Organization Leads Power Note M1U25664TUH4A0F-5A 200MHz (5ns @ CL = 3) DDR2-400 PC2-3200 M1Y25664TUH4A0F-5A Green M1U25664TUH4A0F-37B 266MHz (3.7ns @ CL = 4) DDR2-533 PC2-4200 M1Y25664TUH4A0F-37B 32Mx64 Gold 1.8V Green M1U25664TUH4A0F-3C 333MHz (3ns @ CL = 5) DDR2-667 M1Y25664TUH4A0F-3C REV 1.1 03/2005 PC2-5300 Green 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Pin Description CK0, CK0 CKE0, CKE1 Differential Clock Inputs DQ0-DQ63 Clock Enable CB0-CB7 RAS Row Address Strobe CAS Column Address Strobe WE Write Enable DQS0-DQS17 CS0, CS1 Chip Selects VDD A0-A9, A11-A13 A10/AP BA0, BA1 RESET ODT0, ODT1 NC REV 1.1 03/2005 DQS0-DQS8 Data input/output ECC Check Bit Data Input/Output Bidirectional data strobes DM0-DM8/DQS9-17 Input Data Mask/High Data Strobes Address Inputs VREF Column Address Input/Auto-precharge VDDSPD Differential data strobes Power (1.8V) Ref. Voltage for SSTL_18 inputs Serial EEPROM positive power supply SDRAM Bank Address Inputs VSS Reset pin SCL Serial Presence Detect Clock Input Active termination control lines SDA Serial Presence Detect Data input/output No Connect SA0-2 Ground Serial Presence Detect Address Inputs 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Pinout Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 VREF 42 NC 82 VSS 123 DQ5 164 NC 204 VSS 2 VSS 43 NC 83 DQS4 124 VSS 165 NC 205 DQ38 3 DQ0 44 VSS 84 DQS4 125 DM0, DQS9 166 VSS 206 DQ39 4 DQ1 45 NC 85 VSS 126 DQS9 167 NC 207 VSS 5 VSS 46 NC 86 DQ34 127 VSS 168 NC 208 DQ44 6 DQS0 47 VSS 87 DQ35 128 DQ6 169 VSS 209 DQ45 7 DQS0 48 NC 88 VSS 129 DQ7 170 VDDQ 210 VSS 8 VSS 49 NC 89 DQ40 130 VSS 171 CKE1 211 DM5 9 DQ2 50 VSS 90 DQ41 131 DQ12 172 VDD 212 NC 10 DQ3 51 VDDQ 91 VSS 132 DQ13 173 NC 213 VSS 11 VSS 52 CKE0 92 DQS5 133 VSS 174 NC 214 DQ46 12 DQ8 53 VDD 93 DQS5 134 DM1, DQS10 175 VDDQ 215 DQ47 13 DQ9 54 NC 94 VSS 135 DQS10 176 A12 216 VSS 14 VSS 55 NC 95 DQ42 136 VSS 177 A9 217 DQ52 15 DQS1 56 VDDQ 96 DQ43 137 CK1 178 VDD 218 DQ53 16 DQS1 57 A11 97 VSS 138 CK1 179 A8 219 VSS 17 VSS 58 A7 98 DQ48 139 VSS 180 A6 220 CK2 18 NC 59 VDD 99 DQ49 140 DQ14 181 VDDQ 221 CK2 19 NC 60 A5 100 VSS 141 DQ15 182 A3 222 VSS 20 VSS 61 A4 101 SA2 142 VSS 183 A1 223 DM6 21 DQ10 62 VDDQ 102 NC 143 DQ20 184 VDD 224 NC 22 DQ11 63 A2 103 VSS 144 DQ21 225 VSS 23 VSS 64 VDD 104 DQS6 145 VSS 185 CK0 226 DQ54 24 DQ16 105 DQS6 146 DM2 186 CK0 227 DQ55 25 DQ17 65 VSS 106 VSS 147 NC 187 VDD 228 VSS 26 VSS 66 VSS 107 DQ50 148 VSS 188 A0 229 DQ60 27 DQS2 67 VDD 108 DQ51 149 DQ22 189 VDD 230 DQ61 28 DQS2 68 NC 109 VSS 150 DQ23 190 BA1 231 VSS 29 VSS 69 VDD 110 DQ56 151 VSS 191 VDDQ 232 DM7 30 DQ18 70 A10/AP 111 DQ57 152 DQ28 192 RAS 233 NC 31 DQ19 71 BA0 112 VSS 153 DQ29 193 CS0 234 VSS 32 VSS 72 VDDQ 113 DQS7 154 VSS 194 VDDQ 235 DQ62 33 DQ24 73 WE 114 DQS7 155 DM3 195 ODT0 236 DQ63 34 DQ25 74 CAS 115 VSS 156 NC 196 A13 237 VSS KEY KEY 35 VSS 75 VDDQ 116 DQ58 157 VSS 197 VDD 238 VDDSPD 36 DQS3 76 CS1 117 DQ59 158 DQ30 198 VSS 239 SA0 37 DQS3 77 ODT1 118 VSS 159 DQ31 199 DQ36 240 SA1 38 VSS 78 VDDQ 119 SDA 160 VSS 200 DQ37 39 DQ26 79 VSS 120 SCL 161 NC 201 VSS 40 DQ27 80 DQ32 121 VSS 162 NC 202 DM4 41 VSS 81 DQ33 122 DQ4 163 VSS 203 NC REV 1.1 03/2005 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Input/Output Functional Description Symbol Type Polarity Function CK0, CK1, CK2 (SSTL) The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. CK0, CK1, CK2 (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. CS0, CS1 (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE (SSTL) Active Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. VREF Supply Reference voltage for SSTL-18 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. A0 - A9 A10/AP A11 - A13 (SSTL) - DQ0 - DQ63 CB0 - CB7 (SSTL) Active High VDD, VSS Supply DQS0 - DQS8 DQS0 - DQS8 (SSTL) DM0 - DM8 Input On-Die Termination control signals Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM configurations. Power and ground for the DDR SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. VDDSPD REV 1.1 03/2005 Supply Serial EEPROM positive power supply. 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) CS0 LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS CS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS D1 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 BA0-BA1 A0-A12 CS DQS4 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS6 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQS CS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS D3 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 D2 BA0-BA1 : SDRAMs D0-D3 A0-A12 : SDRAMs D0-D3 RAS : SDRAMs D0-D3 CAS CAS : SDRAMs D0-D3 VDDSPD VDD/VDDQ VREF VSS VDDID WE : SDRAMs D0-D3 CKE0 CKE : SDRAMs D0-D3 ODT0 ODT : SDRAMs D0-D3 Notes : 03/2005 D0 RAS WE REV 1.1 LDQS CS LDQS DQS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/CS relationships are maintained as shown. 3. DQ/DQS/DQS resistors are 22 Ohms +/- 5% 4. BAx, Ax, RAS, CAS, WE resistors are 5.1 Ohms +/- 5% 5. Address and control resistors are 22 Ohms +/- 5% SPD D0-D3 D0-D3 D0-D3 Serial PD SCL WP A0 A1 A2 SA0 SA1 SA2 SDA 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 32Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 32Mx16, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Serial PD Data Entry (Hexadecimal) SPD Entry Value Byte Description DDR2 -400 (-5A) DDR2 -533 (-37B) DDR2 -667 (-3C) DDR2 -400 (-5A) DDR2 -533 (-37B) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly DDR2-SDRAM 08 13 0D 4 Number of Column Addresses on Assembly 5 Number of DIMM Bank, Package, and Height 10 0A 1 rank, Height=30mm 6 Data Width of this Assembly 60 X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Device Cycle Time at CL=5 10 DDR2 SDRAM Device Access Time from Clock at CL=5 5ns 3.75ns 3ns 50 3D 30 0.5ns 0.45ns 60 50 45 DIMM Configuration Type Non - ECC 00 12 Refresh Rate/Type 7.8s/self 82 13 Primary DDR2 SDRAM Width X16 10 14 Error Checking DDR2 SDRAM Device Width 15 Reserved 16 17 N/A 00 Undefined 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 19 Reserved 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 24 Maximum Data Access Time (tac) from Clock at CL=4 DDR2 -667 (-3C) 0.6ns 11 3/4/5 38 Undefined 00 Regular UDIMM (133/35mm) 02 Normal DIMM 00 Support weak driver 01 01 13 5ns 3.75ns 3.75ns 50 3D 3D 0.6ns 0.5ns 0.5ns 60 50 50 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time (tac) from Clock at CL=3 0.6ns 5ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 10ns 28 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 50 45ns 2D 256MB 40 30 Minimum RAS Pulse Width (tRAS) 31 Module Bank Density 32 Address and Command Setup Time Before Clock (tIS) 0.35ns 0.25ns 0.2ns 35 25 20 33 Address and Command Hold Time After Clock (tIH) 0.475ns 0.375ns 0.325ns 47 37 32 34 Data Input Setup Time Before Clock (tDS) 0.15ns 0.1ns 0.05ns 15 10 05 35 Data Input Hold Time After Clock (tDH) 0.275ns 0.225ns 0.175ns 27 22 17 36 Write Recovery Time (tWR) 15ns Internal Write to Read Command delay (tWTR) 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Memory Analysis Probe Characteristics Undefined 00 40 Extension of Byte 41 tRC and Byte 42 tRFC The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 41 Minimum Core Cycle Time (tRC) 60ns 3C 03/2005 7.5ns 3C 37 REV 1.1 10ns Note 7.5ns 28 1E 1E 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 32Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 32Mx16, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte Description DDR2 -400 (-5A) DDR2 -533 (-37B) DDR2 -667 (-3C) Serial PD Data Entry (Hexadecimal) DDR2 -400 (-5A) DDR2 -533 (-37B) 105ns 69 8ns 80 DDR2 -667 (-3C) 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) 0.35ns 0.3ns 0.25ns 23 1E 19 45 Read Data Hold Skew Factor (tQHS) 0.45ns 0.4ns 0.35ns 2D 28 23 46 PLL Relock Time N/A 00 47-xx IDD in SPD Undefined 00 xx-61 Reserved Undefined 00 62 SPD Reversion 63 Checksum for byte 0-62 Checksum data 64-71 Manufacture's JEDEC ID Code NANYA 7F7F7F0B00000000 N/A 00 Undefined 00 72 1.0 Module Manufacturing Location 73-255 Reserved REV 1.1 03/2005 Note 10 05 81 51 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Absolute Maximum Ratings Symbol VIN, VOUT Parameter Voltage on I/O pins relative to VSS Rating Units -0.5 to VDDQ+0.5 V VIN Voltage on Input relative to VSS -0.5 to +2.3 V VDD Voltage on VDD supply relative to VSS -0.5 to +2.3 V VDDQ Voltage on VDDQ supply relative to VSS -0.5 to +2.3 V 0 to +70 C -55 to +100 C TA TSTG Operating Temperature (Ambient) Storage Temperature (Plastic) Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. REV 1.1 03/2005 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM DC Electrical Characteristics and Operating Conditions (TA = 0 C ~ 70 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) Symbol Min Max Units Notes Supply Voltage 1.7 1.9 V 1 I/O Supply Voltage 1.7 1.9 V 1 0 0 V I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 VDD VDDQ VSS, VSSQ VREF Parameter Supply Voltage, I/O Supply Voltage Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value REV 1.1 03/2005 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TA = 0 C ~ 70 C; VDDQ = VDD = 1.8V 0.1V (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) Symbol PC2-3200 PC2-4200 PC2-5300 (-5A) (-37B) (-3C) Parameter/Condition Unit Notes TBD mA 1, 2 360 TBD mA 1, 2 20 20 TBD mA 1, 2 Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 140 170 TBD mA 1, 2 I DD3P Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 55 70 TBD mA 1, 2 I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 145 170 TBD mA 1, 2 I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 350 400 TBD mA 1, 2 I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 370 450 TBD mA 1, 2 I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 490 520 TBD mA 1, 2, 4 I DD6 Self-Refresh Current: CKE 0.2V 18 18 TBD mA 1, 2 I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 850 900 TBD mA 1, 2 I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 290 330 I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 310 I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) I DD2N Note: 1. I DD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ns. 3. Enables on-chip refresh and address counters. 4. Current at 7.8s is time-averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8s. REV 1.1 03/2005 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TA = 0 C ~ 70 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol tAC tDQSCK -5A Parameter -37B -3C Unit Min. Max. Min. Max. Min. Max. DQ output access time from CK/CK -0.6 +0.6 -0.5 +0.5 -0.45 +0.45 ns DQS output access time from CK/CK -0.5 +0.5 -0.45 +0.45 -0.4 +0.4 ns tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCK Clock cycle time tCK tCH or tCL tCH or tCL tCH or tCL tCK CL=3 5 8 3.75 8 3 8 ns CL=4, 5 5 8 3.75 8 3 8 ns tDH DQ and DM input hold time 0.275 0.225 0.175 ns tDS DQ and DM input setup time 0.15 0.1 0.1 ns tIPW Input pulse width 0.6 0.6 0.6 ns tDIPW DQ and DM input pulse width (each input) 0.35 0.35 0.35 ns tHZ Data-out high-impedance time from CK/CK tAC (max) tAC ns tLZ Data-out low-impedance time from CK/CK tAC (max) tAC ns tAC (max) 2tAC (min) tAC (max) 2 tAC (min) tDQSQ DQS-DQ skew (DQS & associated DQ signals) 0.35 0.3 0.24 ns tQHS Data hold Skew Factor 0.45 0.4 0.34 ns tQH Data output hold time from DQS tDQSS tHP tQHS tHP tQHS -0.25 DQS input low (high) pulse width (write cycle) 0.35 0.35 0.35 tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 0.2 0.2 tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 0.2 0.2 tCK tMRD Mode register set command cycle time tWPST Write postamble 0.4 Write preamble 0.35 0.35 0.35 tCK 0.475 0.375 0.275 ns tWPRE tIH tIS Address and control input hold time 2 -0.25 +0.25 2 0.6 0.4 -0.25 tCK Write command to 1st DQS latching transition tDQSL,(H) +0.25 tHP tQHS +0.25 2 0.6 tCK 0.6 Address and control input setup time 0.35 Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 0.4 0.6 0.4 0.6 tCK tRAS Active to Precharge command 45 120,000 40 120,000 45 120,000 ns tRRD Active bank A to Active bank B command 7.5 7.5 7.5 ns tCCD CAS to CAS 2 2 2 tCK 03/2005 0.2 tCK tRPRE REV 1.1 0.25 0.4 tCK ns 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TA = 0 C ~ 70 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol -5A Parameter Min. tWR Write recovery time tDAL Auto precharge write recovery + precharge time tWTR tRTP tXSNR Exit self refresh to a Non-read command tXSRD Exit self refresh to a Read command -37B Max. Min. -3C Max. Min. Unit Max. 15 15 15 ns tWR+tRP tWR+tRP tWR+tRP tCK Internal write to read command delay 10 7.5 7.5 tCK Internal read to precharge command delay 7.5 7.5 7.5 ns tRFC+10 tRFC +10 tRFC +10 ns 200 200 200 tCK Exit precharge power down to any Non- read command 2 2 2 tCK tXARD Exit active power down to read command 2 2 2 tCK tXARDS Exit active power down to read command tXP 6-AL 6-AL 7-AL tCK tCKE CKE minimum pulse width 3 3 3 tCK tAOND ODT turn-on delay 2 2 ODT turn-on tAC (min) tAC (max) tAONPD ODT turn-on (Power down mode) tAC (min) +2 2tCK + tAC (max) +1 tAOFD ODT turn-off delay tAON +1 2.5 ODT turn-off tAC (min) tAOFPD ODT turn-off (Power down mode) tAC (min)+2 2.5tCK + tAC (max) +1 tANPD ODT to power down entry latency 3 tAXPD ODT power down exit latency 8 tOIT OCD drive mode output delay 0 tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tRCD tAC (min) tAC (min) +2 2tCK + tAC (max) +1 +1 2.5 tAC (max) +0.6 tAOF 2 tAC (max) tAC (min) tAC (min)+2 2.5tCK + tAC (max) +1 tAC (min) +2 2tCK + tAC (max) +1 +0.7 tCK tCK tAC (min) ns tAC (min)+2 2.5tCK + tAC (max) +1 ns tCK 8 12 tCK tAC (max) +0.6 3 8 0 tAC (min) 2.5 tAC (max) +0.6 3 12 tCK tAC (max) 0 tCK 12 ns tIS + tCK + tIH tIS + tCK + tIH tIS + tCK + tIH ns Active to Read or Write delay 15 15 12 ns tRP Precharge command period 15 tREFI Average Periodic Refresh Interval REV 1.1 03/2005 15 7.8 12 7.8 ns 7.8 s 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) FRONT 133.35 5.250 131.35 5.171 Detail B 17.80 0.700 Detail A 2.5 0.098 3.0 0.118 10.0 0.394 30.00 1.180 (2X) 4.00 0.157 128.95 5.077 BACK SIDE 3.81 0.125 max. (Front) Detail B 3.80 0.15 4.00 0.157 Detail A 1.50 0.059 0.8 Width 0.031 1.27 0.050 1.00 Pitch 0.039 Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) REV 1.1 03/2005 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1U25664TUH4A0F / M1Y25664TUH4A0F (Green) 256MB: 32M x 64 Unbuffered DDR2 SDRAM DIMM Revision Log Rev Date 0.1 08/2004 Preliminary Release 1.0 01/2005 Added Idd values 1.1 03/2005 Added DDR2-667 spec. REV 1.1 03/2005 Modification 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.