M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 1
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
240pin Unbuffered DDR2 SDRAM MODULE
Based on 32Mx16 DDR 2 SDRAM
Features
• JEDEC Standard 240-pin Dual In-Line Memory Module
• 32Mx64 DDR2 Unbuffered DIMM based on 32Mx16 DDR2
SDRAM
• Performance:
PC2-3200 PC2-4200 PC2-5300
Speed Sort 5A 37B 3C
DIMM CAS Latency* 3 4 5
Unit
f CK Clock Frequency 200 266 333 MHz
t CK Clock Cycle 5 3.7 3 ns
f DQ DQ Burst Frequency 400 533 667 MHz
• Intended for 200 MHz, 266MHz, and 333MHz applications
• Inputs and outputs are SSTL-18 compatible
• VDD = VDDQ = 1.8Volt ± 0.1
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• Bi-directional data strobe with one clock cycle preamble and
one-half clock post-amble
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- Device CAS Latency: 3, 4, 5
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/10/1 Addressing (row/column/bank)
• 7.8µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 84-ball FBGA Package
Description
M1U25664TUH4A0F & M1Y25664TUH4A0F are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line
Memory Module (UDIMM), organized as a one-rank 64Mx64 high-speed memory arra y. Modules use four 32Mx16 DDR2 SDRAMs in
FBGA packages. These DIMMs manufactured using raw cards developed for broad industry use as reference designs. The use of these
common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 200 MHz (266MHz and 333MHz) clock speeds and achieves high-speed
data transfer rates of up to 400 MHz (533MHz and 667MHz). Prior to any access operation, the device CAS latency and burst type/
length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode
register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number Speed Organization Leads Power Note
M1U25664TUH4A0F-5A
M1Y25664TUH4A0F-5A 200MHz (5ns @ CL = 3) DDR2-400 PC2-3200 Green
M1U25664TUH4A0F-37B
M1Y25664TUH4A0F-37B 266MHz (3.7ns @ CL = 4) DDR2-533 PC2-4200 Green
M1U25664TUH4A0F-3C
M1Y25664TUH4A0F-3C 333MHz (3ns @ CL = 5) DDR2-667 PC2-5300
32Mx64 Gold 1.8V
Green
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 2
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Pin Description
CK0, CK0 Differential Clock Inputs DQ0-DQ63 Data input/output
CKE0, CKE1 Clock Enable CB0-CB7 ECC Check Bit Data Input/Output
RAS Row Address Strobe DQS0-DQS8 Bidirectional data strobes
CAS Column Address Strobe DM0-DM8/DQS9-17 Input Data Mask/High Data Strobes
WE Write Enable DQS0-DQS17 Differential data strobes
CS0, CS1 Chip Selects VDD Power (1.8V)
A0-A9, A11-A13 Address Inputs VREF Ref. Voltage for SSTL_18 inputs
A10/AP Column Address Input/Auto-precharge VDDSPD Serial EEPROM positive power supply
BA0, BA1 SDRAM Bank Address Inputs VSS Ground
RESET Reset pin SCL Serial Presence Detect Clock Input
ODT0, ODT1 Active termination control lines SDA Serial Presence Detect Data input/output
NC No Connect SA0-2 Serial Presence Detect Address Inputs
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 3
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Pinout
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1 VREF 42 NC 82 VSS 123 DQ5 164 NC 204 VSS
2 VSS 43 NC 83
DQS4 124 VSS 165 NC 205 DQ38
3 DQ0 44 VSS 84 DQS4 125 DM0, DQS9 166 VSS 206 DQ39
4 DQ1 45 NC 85 VSS 126 DQS9 167 NC 207 VSS
5 VSS 46 NC 86 DQ34 127 VSS 168 NC 208 DQ44
6 DQS0 47 VSS 87 DQ35 128 DQ6 169 VSS 209 DQ45
7 DQS0 48 NC 88 VSS 129 DQ7 170 VDDQ 210 VSS
8 VSS 49 NC 89 DQ40 130 VSS 171 CKE1 211 DM5
9 DQ2 50 VSS 90 DQ41 131 DQ12 172 VDD 212 NC
10 DQ3 51 VDDQ 91 VSS 132 DQ13 173 NC 213 VSS
11 VSS 52 CKE0 92
DQS5 133 VSS 174 NC 214 DQ46
12 DQ8 53 VDD 93 DQS5 134 DM1, DQS10 175 VDDQ 215 DQ47
13 DQ9 54 NC 94 VSS 135 DQS10 176 A12 216 VSS
14 VSS 55 NC 95 DQ42 136 VSS 177 A9 217 DQ52
15 DQS1 56 VDDQ 96 DQ43 137 CK1 178 VDD 218 DQ53
16 DQS1 57 A11 97 VSS 138 CK1 179 A8 219 VSS
17 VSS 58 A7 98 DQ48 139 VSS 180 A6 220 CK2
18 NC 59 VDD 99 DQ49 140 DQ14 181 VDDQ 221 CK2
19 NC 60 A5 100 VSS 141 DQ15 182 A3 222 VSS
20 VSS 61 A4 101 SA2 142 VSS 183 A1 223 DM6
21 DQ10 62 VDDQ 102 NC 143 DQ20 184 VDD 224 NC
22 DQ11 63 A2 103 VSS 144 DQ21 KEY 225 VSS
23 VSS 64 VDD 104
DQS6 145 VSS 185 CK0 226 DQ54
24 DQ16 KEY 105 DQS6 146 DM2 186 CK0 227 DQ55
25 DQ17 65 VSS 106 VSS 147 NC 187 VDD 228 VSS
26 VSS 66 VSS 107 DQ50 148 VSS 188 A0 229 DQ60
27 DQS2 67 VDD 108 DQ51 149 DQ22 189 VDD 230 DQ61
28 DQS2 68 NC 109 VSS 150 DQ23 190 BA1 231 VSS
29 VSS 69 VDD 110 DQ56 151 VSS 191 VDDQ 232 DM7
30 DQ18 70 A10/AP 111 DQ57 152 DQ28 192 RAS 233 NC
31 DQ19 71 BA0 112 VSS 153 DQ29 193 CS0 234 VSS
32 VSS 72 VDDQ 113
DQS7 154 VSS 194 VDDQ 235 DQ62
33 DQ24 73 WE 114 DQS7 155 DM3 195 ODT0 236 DQ63
34 DQ25 74 CAS 115 VSS 156 NC 196 A13 237 VSS
35 VSS 75 VDDQ 116 DQ58 157 VSS 197 VDD 238 VDDSPD
36 DQS3 76 CS1 117 DQ59 158 DQ30 198 VSS 239 SA0
37 DQS3 77 ODT1 118 VSS 159 DQ31 199 DQ36 240 SA1
38 VSS 78 VDDQ 119 SDA 160 VSS 200 DQ37
39 DQ26 79 VSS 120 SCL 161 NC 201 VSS
40 DQ27 80 DQ32 121 VSS 162 NC 202 DM4
41 VSS 81 DQ33 122 DQ4 163 VSS 203 NC
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 4
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Input/Output Functional Description
Symbol Type Polarity Function
CK0, CK1, CK2 (SSTL) Positive
Edge
The positive line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the
rising edge of their associated clocks.
CK0, CK1, CK2 (SSTL) Negative
Edge The negative line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL.
CKE0, CKE1 (SSTL) Active
High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
CS0, CS1 (SSTL) Active
Low
Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
RAS, CAS, WE (SSTL) Active
Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the
operation to be executed by the SDRAM.
VREF Supply Reference voltage for SSTL-18 inputs
VDDQ Supply
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
ODT0, ODT1 Input Active
High On-Die Termination control signals
BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active.
A0 - A9
A10/AP
A11 - A13 (SSTL) -
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address
(CA0-CA10) when sampled at the rising clock edge. In addition to the column address,
AP is used to invoke Autoprecharge operation at the end of the Bur st Read or Write
cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be
precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
DQ0 – DQ63
CB0 – CB7 (SSTL) Active
High Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM
configurations.
VDD, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic
DQS0 – DQS8
DQS0 – DQS8 (SSTL)
Negative
and
Positive
Edge
Data strobe for input and output data
DM0 – DM8 Input Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits
CB0-CB7, and is not used on x64 modules.
SA0 – SA2 -
Address inputs. Connected to either VDD or VSS on the system board to configure the
Serial Presence Detect EEPROM address.
SDA -
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to VDD to act as a pull-up.
SCL -
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pull-up.
VDDSPD Supply Serial EEPROM positive power supply.
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 5
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Functional Block Diagram
(256MB, 1 Rank, 32Mx16 DDR2 SDRAMs)
CS0
Serial PD
A0 A2A1
SCL
WP SDA
SA0 SA2SA1
V
DDSPD
V
SS
SPD
D0-D3
D0-D3
D0-D3
V
DD
/V
DDQ
V
REF
V
DDID
DM0
DQ0
DQ1
DQ2
DQ7
DQ4
DQ6
DQ5
DQ3
DQ8
DQ9
DQ10
DQ15
DQ12
DQ14
DQ13
DQ11
DQS0
DM1
DQS1
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
LDM
CS
D0
I/O 8
I/O 9
I/O 14
I/O 13
I/O 12
I/O 11
I/O 10
I/O 15
UDM
UDQS
LDQS
LDQS
UDQSDQS1
DQS0
DM3
DQS3
DM2
DQS2
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
LDM
CS
D1
I/O 8
I/O 9
I/O 14
I/O 13
I/O 12
I/O 11
I/O 10
I/O 15
UDM
UDQS
LDQS
DQ16
DQ17
DQ18
DQ23
DQ20
DQ22
DQ21
DQ19
DQ24
DQ25
DQ26
DQ31
DQ28
DQ30
DQ29
DQ27
DQS2
UDQS
LDQS
DQS3
DM4
DQS4
DQ32
DQ33
DQ34
DQ39
DQ36
DQ38
DQ37
DQ35
DQ40
DQ41
DQ42
DQ47
DQ44
DQ46
DQ45
DQ43
DQS5
DM5
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
LDM
CS
D2
I/O 8
I/O 9
I/O 14
I/O 13
I/O 12
I/O 11
I/O 10
I/O 15
UDM
UDQS
LDQS
LDQSDQS4
UDQS
DQS5
I/O 0
I/O 1
I/O 6
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
LDM
CS
D3
I/O 8
I/O 9
I/O 14
I/O 13
I/O 12
I/O 11
I/O 10
I/O 15
UDM
UDQS
LDQS
DQ48
DQ49
DQ50
DQ55
DQ52
DQ54
DQ53
DQ51
DQ56
DQ57
DQ58
DQ63
DQ60
DQ62
DQ61
DQ59
DQS6
DM6
DQS7
DM7
LDQS
UDQS
DQS7
DQS6
BA0-BA1
A0-A12
RAS
CAS
CKE0
ODT0
WE
A0-A12 : SDRAMs D0-D3
BA0-BA1 : SDRAMs D0-D3
RAS : SDRAMs D0-D3
CKE : SDRAMs D0-D3
CAS : SDRAMs D0-D3
ODT : SDRAMs D0-D3
WE : SDRAMs D0-D3
Notes : 1. DQ-to-I/O wiring may be changed wi thin a byte.
2. DQ/DQS/DM/CKE/CS relationships are maintained as shown.
3. DQ/DQS/DQS resistors are 22 Ohms +/- 5%
4. BAx, Ax, RAS, CAS, WE resistors are 5.1 Ohms +/- 5%
5. Address and control resistors are 22 Ohms +/- 5%
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 6
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect -- Part 1 of 2
32Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 32Mx16, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD
SPD Entry Value Serial PD Data Entry
(Hexadecimal) Note
Byte Description
DDR2
-400
(-5A)
DDR2
-533
(-37B)
DDR2
-667
(-3C)
DDR2
-400
(-5A)
DDR2
-533
(-37B)
DDR2
-667
(-3C)
0 Number of Serial PD Bytes Written during Production 128 80
1 Total Number of Bytes in Serial PD device 256 08
2 Fundamental Memory Type DDR2-SDRAM 08
3 Number of Row Addresses on Assembly 13 0D
4 Number of Column Addresses on Assembly 10 0A
5 Number of DIMM Bank, Package, and Height 1 rank, Height=30mm 60
6 Data Width of this Assembly X64 40
7 Reserved Undefined 00
8 Voltage Interface Level of this Assembly SSTL_1.8V 05
9 DDR2 SDRAM Device Cycle Time at CL=5 5ns 3.75ns 3ns 50 3D 30
10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.6ns 0.5ns 0.45ns 60 50 45
11 DIMM Configuration Type Non - ECC 00
12 Refresh Rate/Type 7.8µs/self 82
13 Primary DDR2 SDRAM Width X16 10
14 Error Checking DDR2 SDRAM Device Width N/A 00
15 Reserved Undefined 00
16 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C
17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04
18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 3/4/5 38
19 Reserved Undefined 00
20 DDR2 SDRAM DIMM Type Information Regular UDIMM (133/35mm) 02
21 DDR2 SDRAM Module Attributes: Normal DIMM 00
22 DDR2 SDRAM Device Attributes: General Support weak driver 01 01 13
23 Minimum Clock Cycle at CL=4 5ns 3.75ns 3.75ns 50 3D 3D
24 Maximum Data Access Time (tac) from Clock at CL=4 0.6ns 0.5ns 0.5ns 60 50 50
25 Minimum Clock Cycle Time at CL=3 5ns 50
26 Maximum Data Access Time (tac) from Clock at CL=3 0.6ns 60
27 Minimum Row Precharge Time (tRP) 15ns 3C
28 Minimum Row Active to Row Active delay (tRRD) 10ns 28
29 Minimum RAS to CAS delay (tRCD) 15ns 3C
30 Minimum RAS Pulse Width (tRAS) 45ns 2D
31 Module Bank Density 256MB 40
32 Address and Command Setup Time Before Clock (tIS) 0.35ns 0.25ns 0.2ns 35 25 20
33 Address and Command Hold Time After Clock (tIH) 0.475ns 0.375ns 0.325ns 47 37 32
34 Data Input Setup Time Before Clock (tDS) 0.15ns 0.1ns 0.05ns 15 10 05
35 Data Input Hold Time After Clock (tDH) 0.275ns 0.225ns 0.175ns 27 22 17
36 Write Recovery Time (tWR) 15ns 3C
37 Internal Write to Read Command delay (tWTR) 10ns 7.5ns 7.5ns 28 1E 1E
38 Internal Read to Precharge delay (tRTP) 7.5ns 1E
39 Memory Analysis Probe Characteristics Undefined 00
40 Extension of Byte 41 tRC and Byte 42 tRFC The number below a decimal
point of tRC and tRFC are 0, tRFC
is less than 256ns 00
41 Minimum Core Cycle Time (tRC) 60ns 3C
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 7
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect -- Part 2 of 2
32Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 32Mx16, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD
SPD Entry Value Serial PD Data Entry
(Hexadecimal)
Byte Description DDR2
-400
(-5A)
DDR2
-533
(-37B)
DDR2
-667
(-3C)
DDR2
-400
(-5A)
DDR2
-533
(-37B)
DDR2
-667
(-3C)
Note
42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69
43 Maximum Clock Cycle Time (tCK) 8ns 80
44 Max. DQS-DQ Skew Factor (tDQS) 0.35ns 0.3ns 0.25ns 23 1E 19
45 Read Data Hold Skew Factor (tQHS) 0.45ns 0.4ns 0.35ns 2D 28 23
46 PLL Relock Time N/A 00
47-xx IDD in SPD Undefined 00
xx-61 Reserved Undefined 00
62 SPD Reversion 1.0 10
63 Checksum for byte 0-62 Checksum data 05 81 51
64-71 Manufacture’s JEDEC ID Code NANYA 7F7F7F0B00000000
72 Module Manufacturing Location N/A 00
73-255 Reserved Undefined 00
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 8
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Absolute Maximum Ratings
Symbol Parameter Rating Units
VIN, VOUT Voltage on I/O pins relative to VSS -0.5 to VDDQ+0.5 V
VIN Voltage on Input relative to VSS -0.5 to +2.3 V
VDD Voltage on VDD supply relative to VSS -0.5 to +2.3 V
VDDQ Voltage on VDDQ supply relative to VSS -0.5 to +2.3 V
TA Operating Temperature (Ambient) 0 to +70 °C
TSTG Storage Temperature (Plastic) -55 to +100 °C
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 9
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DC Electrical Characteristics and Operating Conditions
(TA = 0 °C ~ 70 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics)
Symbol Parameter Min Max Units Notes
VDD Supply Voltage 1.7 1.9 V 1
VDDQ I/O Supply Voltage 1.7 1.9 V 1
VSS, VSSQ Supply Voltage, I/O Supply Voltage 0 0 V
VREF I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2
VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V 1
VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1
Note:
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed 2% of the DC value
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 10
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
TA = 0 °C ~ 70 °C; VDDQ = VDD = 1.8V ± 0.1V (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs)
Symbol Parameter/Condition PC2-3200
(-5A) PC2-4200
(-37B) PC2-5300
(-3C) Unit Notes
I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK
(MIN); DQ, DM, and DQS inputs changing t wice per clock cycle; address
and control inputs changing once per clock cycle 290 330 TBD mA 1, 2
I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; t RC = tRC
(MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs
changing once per clock cycle 310 360 TBD mA 1, 2
I DD2P Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE ≤ VIL (MAX); tCK = tCK (MIN) 20 20 TBD mA 1, 2
I DD2N Idle Standby Current: CS ≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK =
tCK (MIN); address and control inputs changing once per clock cycle 140 170 TBD mA 1, 2
I DD3P Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ VIL (MAX); tCK = tCK (MIN) 55 70 TBD mA 1, 2
I DD3N
Active Standby Current: one bank; active/precharge; CS ≥ VIH (MIN); CKE ≥
VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle; address and control inputs changing once per clock
cycle
145 170 TBD mA 1, 2
I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 350 400 TBD mA 1, 2
I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs
changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 370 450 TBD mA 1, 2
I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 490 520 TBD mA 1, 2, 4
I DD6 Self-Refresh Current: CKE ≤ 0.2V 18 18 TBD mA 1, 2
I DD7 Operating Current: four bank; four bank interleaving with BL = 4, ad dress
and control inputs randomly changing; 50% of data changing at every
transfer; tRC = tRC (min); IOUT = 0mA. 850 900 TBD mA 1, 2
Note:
1. I
DD specifications are tested after the device is properly initialized.
2. Input slew rate = 1V/ns.
3. Enables on-chip refresh and address counters.
4. Current at 7.8µs is time-averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8µs.
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 11
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(TA = 0 °C ~ 70 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics) (Part 1 of 2)
-5A -37B -3C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tAC DQ out put access time from CK/CK -0.6 +0.6 -0.5 +0.5 -0.45 +0.45 ns
tDQSCK DQS output access time from CK/CK -0.5 +0.5 -0.45 +0.45 -0.4 +0.4 ns
tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tCL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tHP Minimum half clk period for any given cycle;
defined by clk high (tCH) or clk low (tCL) time
tCH
or
tCL tCH
or
tCL tCH
or
tCL t
CK
tCK CL=3 5 8 3.75 8 3 8 ns
tCK Clock cycle time CL=4, 5 5 8 3.75 8 3 8 ns
tDH DQ and DM input hold time 0.275 0.225 0.175 ns
tDS DQ and DM input setup time 0.15 0.1 0.1 ns
tIPW Input pulse width 0.6 0.6 0.6 ns
tDIPW DQ and DM input pulse width (each input) 0.35 0.35 0.35 ns
tHZ Data-out high-impedance time from CK/CK t
AC (max) t
AC (max) t
AC ns
tLZ Data-out low-impedance time from CK/CK 2tAC
(min) tAC (max) 2 tAC
(min) tAC (max) t
AC ns
tDQSQ DQS-DQ skew (DQS & associated DQ signals) 0.35 0.3 0.24 ns
tQHS Data hold Skew Factor 0.45 0.4 0.34 ns
tQH Data output hold time from DQS tHP -
tQHS tHP -
tQHS tHP -
tQHS t
CK
tDQSS Write command to 1st DQS latching transition -0.25 +0.25 -0.25 +0.25 -0.25 +0.25 tCK
tDQSL,(H) DQS input low (high) pulse width
(write cycle) 0.35 0.35 0.35 tCK
tDSS DQS falling edge to CK setup time
(write cycle) 0.2 0.2 0.2 tCK
tDSH DQS falling edge hold time from CK
(write cycle) 0.2 0.2 0.2 tCK
tMRD Mode register set command cycle time 2 2 2 tCK
tWPST Write postamble 0.4 0.6 0.4 0.6 0.4 0.6 tCK
tWPRE Write preamble 0.35 0.35 0.35 tCK
tIH Address and control input hold time
0.475 0.375 0.275 ns
tIS Address and control input setup time 0.35 0.25 0.2 ns
tRPRE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tCK
tRPST Read postamble 0.4 0.6 0.4 0.6 0.4 0.6 tCK
tRAS Active to Precharge command 45 120,000 40 120,000 45 120,000 ns
tRRD Active bank A to Active bank B command 7.5 7.5 7.5 ns
tCCD CAS to CAS 2 2 2 tCK
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 12
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(TA = 0 °C ~ 70 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics) (Part 2 of 2)
-5A -37B -3C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWR Write recovery time 15 15 15 ns
tDAL Auto precharge write recovery + precharge time tWR+tRP t
WR+tRP t
WR+tRP t
CK
tWTR Internal write to read command delay 10 7.5 7.5 tCK
tRTP Internal read to precharge command delay 7.5 7.5 7.5 ns
tXSNR Exit self refresh to a Non-read command tRFC+10 tRFC +10 tRFC +10 ns
tXSRD Exit self refresh to a Read command 200 200 200 tCK
tXP Exit precharge power down to any Non- read
command 2 2 2 tCK
tXARD Exit active power down to read command 2 2 2 tCK
tXARDS Exit active power down to read command 6-AL 6-AL 7-AL tCK
tCKE CKE minimum pulse width 3 3 3 tCK
tAOND ODT turn-on delay 2 2 2 tCK
tAON ODT turn-on tAC (min) tAC (max)
+1 tAC (min) tAC (max)
+1 tAC (min) tAC (max)
+0.7 tCK
tAONPD ODT turn-on (Power down mode) tAC (min)
+2 2tCK + tAC
(max) +1 tAC (min)
+2 2tCK + tAC
(max) +1 tAC (min)
+2 2tCK + tAC
(max) +1 tCK
tAOFD ODT turn-off delay 2.5 2.5 2.5 tCK
tAOF ODT turn-off tAC (min) tAC (max)
+0.6 tAC (min) tAC (max)
+0.6 tAC (min) tAC (max)
+0.6 ns
tAOFPD ODT turn-off (Power down mode) tAC
(min)+2
2.5tCK +
tAC
(max) +1
tAC
(min)+2
2.5tCK +
tAC
(max) +1
tAC
(min)+2
2.5tCK +
tAC
(max) +1 ns
tANPD ODT to power down entry latency 3 3 3 tCK
tAXPD ODT po wer down exit latency 8 8 8 tCK
tOIT OCD drive mode output delay 0 12 0 12 0 12 ns
tDelay Minimum time clocks remains ON after CKE
asynchronously drops Low tIS + tCK +
tIH tIS + tCK +
tIH tIS + tCK +
tIH ns
tRCD Active to Read or Write delay 15 15 12 ns
tRP Precharge command period 15 15 12 ns
tREFI Average Periodic Refresh Interval 7.8 7.8 7.8 µs
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 13
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Package Dimensions
(256MB, 1 Rank, 32Mx16 DDR2 SDRAMs)
FRONT
1.50
Detail A
0.039
Detail B
0.8 Width
BACK
0.059
3.80
0.15
0.157
4.00
0.031
1.00 Pitch
Detail A Detail B
0.098
Θ
2.5
10.0
0.394
133.35
131.35
128.95
5.250
5.171
5.077
17.80
3.0
0.118
0.700
30.00
1.180
(2X) 4.00
0.157
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated.
Units: Millimeters ( Inches)
SIDE
3.81
(Front)
1.27
0.125 max.
0.050
M1U25664TUH4A0F / M1Y25664TUH4A0F (Green)
256MB: 32M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1 14
03/2005 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Revision Log
Rev Date Modification
0.1 08/2004 Preliminary Release
1.0 01/2005 Added Idd values
1.1 03/2005 Added DDR2-667 spec.
