8K x 8 Registered PROM
CY7C265
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-04012 Rev. *A Revised October 9, 2002
65
Features
• CMOS for optimum speed/power
• High speed (Commercial)
—15 ns address set-up
—12 ns clock to output
• Low power
—660 mW (Commercial)
• On-chip edge-triggered registers
—Ideal for pipelined microprogrammed systems
• EPROM technology
—100% programmable
—Reprogrammable (CY7C265W)
•5V ±10% VCC, commercial and military
•Capable of withstanding >2001V static discharge
•Slim 28-pin, 300-mil plastic or hermetic DIP
Functional Description
The CY7C265 is a 8192 x 8 registered PROM. It is organized
as 8,192 words by 8 bits wide, and has a pipeline output
register. In addition, the device features a programmable
initial ize byte that may b e loaded into th e pipeli ne regist er with
the initialize signal. The programmable initialize byte is the
8,193rd byte in the P ROM an d its value is progra mm ed at th e
time of use.
Packaged in 28 pins, the PROM has 13 address signals (A0
through A12), 8 data ou t sign als (O 0 through O7), E/I (enable
or initialize), and CLOCK.
CLOCK functions as a pipeline clock, loading the contents of
the addressed memory location into the pipeline register on
each rising edge. The data will appear on the outputs if they
are enabled. One pin on the CY7C265 is programmed to
perform either the enable or the initialize function.
If the as ynchrono us enabl e (E) is being us ed, the ou tputs may
be disabled at any time by switching the enable to a logic
HIGH, and may be returned to the a ctive state by switching the
enable to a logic LOW.
If the synchro nous ena ble (ES) is bei ng us ed, the outpu t s will
go to the O FF or high-i mpedance st ate upon the next posi tive
clock edge after the synchronous enable input is switched to
a HIGH level. If the synchronous enable pin is switched to a
logic L OW, the s ub se que nt p os iti ve cloc k e dge wil l return the
output to the acti ve sta te. Follow ing a pos itive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
LOW-to-HIGH transition of the clock. This unique feature al-
lows the CY7C265 decoders and sense amplifiers to access
the next l ocation while previously address ed data remains sta-
ble on the outputs.
If the E/I pin i s used fo r INIT (asy nchron ous), then th e out put s
are permanently enabled. The initialize function is useful
during power-up and time-out sequences, and can facilitate
implementation of other sophisticated functions such as a
built-in “jump start” address. When activated, the initialize
control input causes the contents of a user programmed
8193rd 8-bit word to be loaded into the on-chip register. Each
bit is programmable and the initialize function can be used to
load any desired combination of 1’s and 0’s into the register.
In the unprogrammed state, activating INIT will generate a
register clear (all outputs LOW). If all the bits of the initialize
word are programmed to be a 1, activating INIT performs a
register pres et (all outpu ts HIGH).
Applying a LOW to the INIT input causes an immediate load
of the programmed initialize word into the pipeline register and
onto the outputs. The INIT LOW disables clock and must
return HIGH to enable clock independent of all other inputs,
including the clock.
CY7C265
Document #: 38-04012 Rev. *A Page 2 of 11
F
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ...............................................–0.5V to +7.0V
DC Input Voltage............................................–3.0V to +7.0V
DC Program Voltage.....................................................13.0V
UV Exposure ................................................7258 Wsec/cm2
Static Discharge Voltage..... ...... ................. ..... ...........>200 1V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Logic Block Diagram
Pin
Configurations
Top View
LCC/PLCC (Opaque Only)
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
Top View
DIP/Flatpack
15
7C265
A7
A6
A5
A4
A3
A2
GND
CLK
A1
A0
O0
O1
O2
GND
VCC
A8
A9
A10
A11
A12
E/ES,I
GND
GND
O7
O6
O4
O5
O3
O7
O6
O5
O4
O3
O2
O1
O0
A12
A11
A10
A9
A8
A7
A6
A5
COLUMN
MULTIPLEXER
A4
A3
A2
A1
PROGRAMMABLE
MULTIPLEXER
ADDRESS
DECODER
PROGRAMMABLE
ARRAY
8-BIT
EDGE-
TRIGGERED
REGISTER
CLK
INIT/E/ES
CLK
PROGRAMMABLE
INITIALIZE WORD
D
C
O28
4
5
6
7
8
9
10
321 27
13 14 15 16 17
26
25
24
23
22
21
20
11 12 19
O018
A0
A1
A3
A2
A10
GND
A11
A12
GND
O7
GND
CLK E/ES,I
A4A5A6A7VCC A8A9
O1O2GND O 3O4O5O6
A5
A0
ROW
ADDRESS
COLUMN
ADDRESS
Selection Guides
7C265-15 7C265-25 7C265-40 7C265-50 Unit
Minimum Address Set-Up Time 15 25 40 50 ns
Maximum Clock to Output 12 15 20 25 ns
Maximu m Operating Curre nt Com’l120 120 100 mA
Mil 120 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ±10%
Military[1] –55°C to +125°C 5V ±10%
Notes:
1. TA is the “instant on” case temperature.
CY7C265
Document #: 38-04012 Rev. *A Page 3 of 11
Electrical Characteristi cs Ov er the Op erating Ran ge [2]
7C265-15, 25 7C265-40 7C265-50
Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 V
VCC = Min., IOH = –4.0 mA 2.4 2.4
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA Com’l0.4 V
VCC = Min., IOL = 12.0 mA 0.4 0.4
VCC = Min., IOL = 6.0 mA Mil 0.4
VCC = Min., IOL = 8.0 mA 0.4
VIH Input HIGH Voltage 2.0 2.0 2.0 V
VIL Input LOW Voltage 0.8 0.8 0.8 V
IIX Input Load Current GND < VIN < VCC –10 +10 –10 +10 –10 +10 µA
IOZ Output Leakage Current GND < VOUT < VCC,
Output Disabled –40 +40 –40 +40 –40 +40 µA
IOS[3] Output Short Circuit Current VCC = Max., VOUT = GND 90 90 90 mA
ICC VCC Operating Supply
Current VCC = Max., IOUT = 0 mA Com’l120 100 mA
Mil 120
VPP Programming Supply Voltage 12 13 12 13 12 13 V
IPP Programming Supply Current 50 50 50 mA
VIHP Input HIGH Programming
Voltage 3.0 3.0 3.0 V
VILP Input LOW Programming
Voltage 0.4 0.4 0.4 V
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 10 pF
COUT Output Capacitance 10 pF
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
4. See Introduction to CMOS PROMs in this Data Book for general information on testing.
CY7C265
Document #: 38-04012 Rev. *A Page 4 of 11
AC Test Loads and Waveforms
R2 333Ω
(403ΩMIL)
3.0V
5V
OUTPUT
R1500
(658ΩMIL)
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤5ns ≤5ns
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
(a) NormalLoad (b) High Z Load
OUTPUT RTH 200Ω
5V
OUTPUT 5V
OUTPUT
R1 250Ω
30 pF
INCLUDING
JIG AND
SCOPE
5pF
INCLUDING
JIG AND
SCOPE
(c)NormalLoad (d) High Z Load
OUTPUT 2.0V
RTH 100Ω
R1 250Ω
R1500Ω
(658ΩMIL)
R2333Ω
(403ΩMIL)
R2 167ΩR2 167Ω
250ΩMIL
Equivalent to: THÉ VENIN EQUIVALENT
Equivalent to: THÉ VENIN EQUIVALENT
Test Load for -15 through -25 speeds
Test Load for -40 through -50 speeds
Switching Characteristics Over the Operating Range[2, 4]
7C265-15 7C265-25 7C265-40 7C265-50
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
tAS Address Set-Up to Clock 15 25 40 50 ns
tHA Address Hold from Clock 0 0 0 0 ns
tCO Clock to Output Valid 12 15 20 25 ns
tPWC Clock Puls e Width 12 15 15 20 ns
tSES ES Set-Up to Clock
(Sync. E nab le On ly ) 12 15 15 15 ns
tHES ES Hold from Clock 5 5 5 5 ns
tDI INIT to Output Valid 15 18 25 35 ns
tRI INIT Recovery to Clock 12 15 20 25 ns
tPWI INIT Pulse Width 12 15 25 35 ns
tCOS Output Valid from Clock
(Sync. Mode) 12 15 20 25 ns
tHZC Output Inactive from Clock
(Sync. Mode) 12 15 20 25 ns
tDOE Output Valid from E LOW
(Async. Mode) 12 15 20 25 ns
tHZE Output Inactive from E HIGH
(Async. Mode) 12 15 20 25 ns
CY7C265
Document #: 38-04012 Rev. *A Page 5 of 11
Erasure Characteri stics
W ave lengths of lig ht less than 400 0 angstroms begi n to erase
the 7C265 in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM
is exposed to sunlight or fluorescent lighting for extended
periods of time.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 angstroms for a minimum dose (UV
intensity • exposure time) of 25 Wsec/cm2. For an ultraviolet
lamp with a 12 mW/cm2 power rati ng the exposure time woul d
be approximately 45 minutes. The 7C265 needs to be within
one inch of the lam p durin g erasu re. Perman ent damage ma y
result if th e PR OM is exp os ed to hig h-in ten si ty U V lig ht for an
extende d period of time . 7258 W sec/cm2 is the rec ommended
maximum dosage.
Control Byte
00 Asynchronous output enable (default condition)
01 Synchronous output enable
02 Asynchronous initialize
Programming Modes
The 7C2 65 offers a li mited sel ec tion of pro gra mm ed a r ch itec -
tures. Programming these features should be done with a
single 10-ms-wide pulse in place of the intelligent algorithm,
mainly because these features are verified operationally, not
with the VFY pin. Architecture programming is implemented by
applying the supervoltage to two additional pins during
programm ing. In programming the 7C265 architec ture, VPP is
applied to pins 3, 9, and 22. The choice of a particular mode
depends on the states of the other pins during programming,
so it is import a nt that the co nditio n of the other pi ns be met as
set forth in the mode t able. The considera tions th at apply with
respect to power-up and power-down during intelligent
programming also apply during architecture programming.
Once the supervoltages have been established and the
correct logic states exist on the other device pins,
programming may begin. Programming is accomplished by
pulling PGM from HIGH to LOW and then back to HIGH with
a pulse width equal to 10 ms.
Switching Waveform
tHZC
tPWC
tHES
VALID DATA
tCOS tCO
tPWI
tDI
ADDRESS
CLOCK
SYNCHRONOUS
ENABLE
(PROGRAMMABLE)
ASYNCHRONOUS INIT
(PROGRAMMABLE)
OUTPUT
ASYNCHRONOUS
ENABLE
tHZE
tSES
tAH
tAS
tDOE
tRI
Bit Map Data
Programmer Address (Hex.) RAM Data
Decimal Hex Contents
0
.
.
8191
8192
8193
0
.
.
1FFF
2000
2001
Data
.
.
Data
INIT Byte
Control Byte
CY7C265
Document #: 38-04012 Rev. *A Page 6 of 11
Programming Informati on
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end o f this section. Programming algorithm s can
be obtained from any Cypress representative.
Table 1. Mode Selection
Pin Function
Read or Output Disable A12 A11 A10–A7A6A5A4–A3A2
Mode Other A12 A11 A10–A7A6A5A4–A3A2
Asynchro nou s Enab le Re ad A12 A11 A10–A7A6A5A4–A3A2
Synchronous Enab le Read A12 A11 A10–A7A6A5A4–A3A2
Asynchro nou s Init ializati on Read A12 A11 A10–A7A6A5A4–A3A2
Program Memory A12 A11 A10–A7A6A5A4–A3A2
Program Verify A12 A11 A10–A7A6A5A4–A3A2
Pro gram Inhibi t A12 A11 A10–A7A6A5A4–A3A2
Program Synchronous Enable VIHP VIHP A10–A7VIHP VPP A4–A3VIHP
Program Initialize VILP VIHP A10–A7VIHP VPP A4–A3VILP
Program Initial Byte A12 VILP A10 – A7VIHP VPP A4–A3VILP
Pin Function
Read or Output Disable A1A0GND CLK GND E, I O7–O0
Mode Other A1A0PGM CLK VFY VPP D7–D0
Asynchro nou s Enab le Re ad A1A0GND VIL GND VIL O7–O0
Synchronous Enab le Read A1A0GND VIL/VIH GND VIL O7–O0
Asynchro nou s Init ializati on Read A1A0GND VIL GND VIL O7–O0
Program Memory A1A0VILP VILP VIHP VPP D7–D0
Program Verify A1A0VIHP VILP VILP VPP O7–O0
Pro gram Inhibi t A1A0VIHP VILP VIHP VPP High Z
Program Synchronous Enable VPP VILP VILP VILP VIHP VPP D7–D0
Program Initialize VPP VILP VILP VILP VIHP VPP D7–D0
Program Initial Byte VPP VIHP VILP VILP VIHP VPP D7–D0
Figure 1. Programming Pinout
1
2
3
4
5
6
7
8
9
10
11
12 16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
A7
A6
A5
A4
A3
A2
PGM
CLK
A1
A0
D0
D1
D2
GND
VCC
A8
A9
A10
A11
A12
VPP
NA
VFY
D7
D6
D4
D5
D3
15
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1112 19
A5
V
CC
GND A6
A7
D3
D1
D018
D4
D5
A0
A1
A3
A2
A8
D7
PGM
CLK
D2
A10
VPP
VFY
A12
NA
D6
A11
A9
A4
LCC/PLCC (Opaque Only)DIP/Flatpack
CY7C265
Document #: 38-04012 Rev. *A Page 7 of 11
Typical DC and AC Characteristics
1.4
1.6
1.0
0.8
4.0 4.5 5.0 5.5 6.0
1.6
1.4
1.2
1.0
0.8
–55 25 125
–55 25 125
1.2
1.1
NORMALIZED ACCESS T IM E
60
40
30
20
10
0.0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.6
1.2
150
175
125
75
50
25
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
100
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.0
0.9
0.8
NORMALIZED I
CC
NORMALIZED I
CC
ICC
ICC
VCC = 5.0V
TA= 25°C
0.6
0
30
25
20
15
10
5
0 200 400 600 800
DELTA t (ns)
CO
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
01000
VCC =4.5V
TA= 25°C
AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)
TA=25°C
f=MAX.
50
35
1.00
1.05
0.95
0.85
0.80
0.75
025 5075
100
0.70
0.90
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
CLOCK PERIOD (ns)
NORMALIZED I
CC
VCC = 5.5V
TA= 25°C
CY7C265
Document #: 38-04012 Rev. *A Page 8 of 11
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Ordering Information
Speed
(ns) ICC
(mA) Ordering Code Package
Name Package Type Operating
Range
15 120 CY7C265-15JC J64 28-Le ad Plas ti c Lead ed Chip Carri er Commercial
CY7C265-15WC W22 28-Lead (300-Mil) Windowed CerDIP
25 120 CY7C265-25PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C265-25WC W22 28-Lead (300-Mil) Windowed CerDIP
40 100 CY7C265-40PC P21 28-Lead (300-Mil) Molded DIP Commercial
50 120 CY7C265-50DMB D22 28-Le ad (300 -Mi l) CerDIP Military
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tAS 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tCO 7, 8, 9, 10, 11
tPW 7, 8, 9, 10, 11
tSES 7, 8, 9, 10, 11
tHES 7, 8, 9, 10, 11
tCOS 7, 8, 9, 10, 11
CY7C265
Document #: 38-04012 Rev. *A Page 9 of 11
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032-**
28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
CY7C265
Document #: 38-04012 Rev. *A Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
51-85014-*B
28-Lead (300-Mil) Molded DIP P21
28-Lead
(300-Mil)
Windowed CerDIP W22
MIL-STD-1835 D-15 Conf ig. A
51-80087-**
CY7C265
Document #: 38-04012 Rev. *A Page 11 of 11
Document History Page
Document Title: CY7C265 8K x 8 Registered PROM
Document Numbe r: 38-040 12
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 114139 03/18/02 DSG Change from Spec number: 38-00084 to 38-04012
*A 118896 10/09/02 GBI Update orde ring information
