85411 Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer Data Sheet GENERAL DESCRIPTION FEATURES The 85411 is a low skew, high performance 1-to-2 Differentialto-LVDS Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels.The 85411 is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 85411 ideal for those clock distribution applications demanding well defined performance and repeatability. * Two differential LVDS outputs * One differential CLK, nCLK clock input * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 650MHz * Translates any single ended input signal to LVDS levels with resistor bias on nCLK input * Output skew: 20ps (maximum) * Part-to-part skew: 250ps (maximum) * Additive phase jitter, RMS: 0.05ps (typical) * Propagation delay: 2.5 ns (maximum) * 3.3V operating supply * 0C to 70C ambient operating temperature * Available in lead free (RoHS 6) package BLOCK DIAGRAM CLK Pullup nCLK Pulldown PIN ASSIGNMENT Q0 nQ0 Q0 nQ0 Q1 nQ1 Q1 nQ1 1 2 3 4 8 7 6 5 VDD CLK nCLK GND 85411 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View (c)2016 Integrated Device Technology, Inc 1 Revision C January 20, 2016 85411 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 Q0, nQ0 Output 3, 4 Q1, nQ1 Output Differential output pair. LVDS interface levels. 5 GND Power Power supply ground. 6 nCLK Input Pulldown Inverting differential clock input. 7 CLK Input 8 VDD Power Differential output pair. LVDS interface levels. Pullup Non-inverting differential clock input. Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance RPULLUP RPULLDOWN Test Conditions Minimum Typical Maximum Units 4 pF Input Pullup Resistor 51 k Input Pulldown Resistor 51 k (c)2016 Integrated Device Technology, Inc 2 Revision C January 20, 2016 85411 Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 112.7C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V10%, TA = 0C TO 70C Symbol Parameter VDD Positive Supply Voltage Test Conditions IDD Power Supply Current Minimum Typical Maximum Units 2.97 3.3 3.63 V 50 mA Maximum Units TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V10%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 VDD - 0.85 V Units CLK VDD = VIN = 3.63V 5 A nCLK VDD = VIN = 3.63V 150 A CLK VDD = 3.63, VIN = 0V nCLK VDD = 3.63V, VIN = 0V -150 A -5 A NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. TABLE 3C. LVDS DC CHARACTERISTICS, VDD = 3.3V10%, TA = 0C TO 70C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change IOFF Power Off Leakage IOSD IOS Minimum Typical Maximum 247 325 454 mV 0 50 mV 1.325 1.45 1.575 V 5 50 mV -20 1 +20 A Differential Output Short Circuit Current -3.5 -5 mA Output Short Circuit Current -3.5 -5 mA (c)2016 Integrated Device Technology, Inc Test Conditions 3 Revision C January 20, 2016 85411 Data Sheet TABLE 4. AC CHARACTERISTICS, VDD = 3.3V10% TA = 0C TO 70C Symbol Parameter fMAX Output Frequency t PD Propagation Delay; NOTE 1 tsk(o) tsk(pp) tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units 650 MHz 2.5 ns Output Skew; NOTE 2, 4 20 ps Part-to-Part Skew; NOTE 3, 4 250 ps 1.5 (12kHz to 20MHz) 20% to 80% @ 50MHz 0.05 150 ps 350 ps > 500MHz 47 53 % 500MHz 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at 650MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. (c)2016 Integrated Device Technology, Inc 4 Revision C January 20, 2016 85411 Data Sheet ADDITIVE PHASE JITTER (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels 0 -10 -20 Input/Output Additive Phase Jitter @ 200MHz (12kHz to 20MHz) -30 = 0.05ps typical -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M 500M OFFSET FROM CARRIER FREQUENCY (HZ) This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. (c)2016 Integrated Device Technology, Inc 5 Revision C January 20, 2016 85411 Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART-TO-PART SKEW OUTPUT SKEW PROPAGATION DELAY OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD DIFFERENTIAL OUTPUT VOLTAGE SETUP (c)2016 Integrated Device Technology, Inc 6 Revision C January 20, 2016 85411 Data Sheet PARAMETER MEASUREMENT INFORMATION, CONTINUED OFFSET VOLTAGE SETUP POWER OFF LEAKAGE SETUP OUTPUT SHORT CIRCUIT CURRENT SETUP DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT SETUP (c)2016 Integrated Device Technology, Inc 7 Revision C January 20, 2016 85411 Data Sheet APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/ R1 = 0.609. Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVDS All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. (c)2016 Integrated Device Technology, Inc 8 Revision C January 20, 2016 85411 Data Sheet DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for IDT HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY IDT HIPERCLOCKS LVHSTL DRIVER FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE (c)2016 Integrated Device Technology, Inc 9 Revision C January 20, 2016 85411 Data Sheet LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. FIGURE 3. TYPICAL LVDS DRIVER TERMINATION (c)2016 Integrated Device Technology, Inc 10 Revision C January 20, 2016 85411 Data Sheet POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 85411. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 85411 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results. * Power (core)MAX = VDD_MAX * IDD_MAX = 3.63V * 50mA = 181.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.182W * 103.3C/W = 88.8C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (multi-layer). TABLE 5. THERMAL RESISTANCE JA FOR 8-LEAD SOIC, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3C/W 112.7C/W 128.5C/W 103.3C/W 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. (c)2016 Integrated Device Technology, Inc 11 Revision C January 20, 2016 85411 Data Sheet RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3C/W 112.7C/W 128.5C/W 103.3C/W 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 85411 is: 636 PACKAGE OUTLINE & DIMENSIONS PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Reference Document: JEDEC Publication 95, MS-012 (c)2016 Integrated Device Technology, Inc 12 Revision C January 20, 2016 85411 Data Sheet TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 85411AMLF 85411ALF 8 lead "Lead Free" SOIC Tray 0C to +70C 85411AMLFT 85411ALF 8 lead "Lead Free" SOIC Tape and Reel 0C to +70C (c)2016 Integrated Device Technology, Inc 13 Revision C January 20, 2016 85411 Data Sheet REVISION HISTORY SHEET Rev Table Page B T4 1 4 5 Features - added Additive Phase Jitter bullet. AC Characteristics table - added tjit row. Added Additive Phase Jitter Application Note 6/9/04 B T7 12 Ordering Information Table - added Lead Free Part Number. 6/16/04 9/19/06 8 11 Changed VDD from 5% to 10% throughout datasheet. LVDS DC Characteristics Table - changed VOD range from 200mV min./360mV max. to 247mV min./454mV max. Changed VOD from 40mV max. to 50mV max. Changed VOS from 1.125mV min./1.375mV max. to 1.325mV min./1.575mV max. Changed VOS from 25mV max. to 50mV max. Added Recommendations for Unused Output Pins. Added Power Considerations. Ordering Information Table - corrected lead-free marking. 1/17/07 LVDS DC Characteristics Table - deleted VOH & VOL rows. 1/20/09 Removed ICS from part numbers where needed. General Description - Deleted the ICS chip and removed HiPerClockS. Features - removed reference to leaded part numbers. Ordering Information - removed quantity for tape and reel. Deleted LF note below the table. Updated header and footer. 1/20/16 T3C 3 C C T8 14 C T3C 3 C T8 1 1 13 Description of Change (c)2016 Integrated Device Technology, Inc 14 Date Revision C January 20, 2016 85411 Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. 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