85411AMLFT - INTEGRATED DEVICE TECHNOLOGY

Low Skew, 1-to-2 Differential-to-LVDS

Fanout Buffer 85411

Data Sheet

GENERAL DESCRIPTION

The 85411 is a low skew, high performance 1-to-2 Differential-

to-LVDS Fanout Buffer and a member of the family of High

Performance Clock Solutions from IDT. The CLK, nCLK pair

can accept most standard differential input levels.The 85411 is

characterized to operate from a 3.3V power supply. Guaranteed

output and part-to-part skew characteristics make the 85411 ideal

for those clock distribution applications demanding well deﬁ ned

performance and repeatability.

FEATURES

• Two differential LVDS outputs

• One differential CLK, nCLK clock input

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum output frequency: 650MHz

• Translates any single ended input signal to

LVDS levels with resistor bias on nCLK input

• Output skew: 20ps (maximum)

• Part-to-part skew: 250ps (maximum)

• Additive phase jitter, RMS: 0.05ps (typical)

• Propagation delay: 2.5 ns (maximum)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Available in lead free (RoHS 6) package

BLOCK DIAGRAM PIN ASSIGNMENT

85411

8-Lead SOIC

3.90mm x 4.90mm x 1.37mm package body

M Package

Top View

nQ0

nQ1

VDD

CLK

nCLK

GND

nQ0

nQ1

CLK

nCLK Pulldown

Pullup

85411 Data Sheet

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

Number Name Type Description

1, 2 Q0, nQ0 Output Differential output pair. LVDS interface levels.

3, 4 Q1, nQ1 Output Differential output pair. LVDS interface levels.

5 GND Power Power supply ground.

6 nCLK Input Pulldown Inverting differential clock input.

7 CLK Input Pullup Non-inverting differential clock input.

DD Power Positive supply pin.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4 pF

RPULLUP Input Pullup Resistor 51 kΩ

RPULLDOWN Input Pulldown Resistor 51 kΩ

85411 Data Sheet

TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±10%, TA = 0°C TO 70°C

TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±10%, TA = 0°C TO 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Positive Supply Voltage 2.97 3.3 3.63 V

IDD Power Supply Current 50 mA

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress speciﬁ cations only. Functional

operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

TABLE 3C. LVDS DC CHARACTERISTICS, VDD = 3.3V±10%, TA = 0°C TO 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOD Differential Output Voltage 247 325 454 mV

Δ VOD VOD Magnitude Change 0 50 mV

VOS Offset Voltage 1.325 1.45 1.575 V

Δ VOS VOS Magnitude Change 5 50 mV

IOFF Power Off Leakage -20 ±1 +20 µA

IOSD Differential Output Short Circuit Current -3.5 -5 mA

IOS Output Short Circuit Current -3.5 -5 mA

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI -0.5V to VDD + 0.5V

Outputs, IO

Continuous Current 10mA

Surge Current 15mA

Package Thermal Impedance, θ

JA 112.7°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

IIH Input High Current CLK VDD = VIN = 3.63V 5 µA

nCLK VDD = VIN = 3.63V 150 µA

IIL Input Low Current CLK VDD = 3.63, VIN = 0V -150 µA

nCLK VDD = 3.63V, VIN = 0V -5 µA

VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V

VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 VDD - 0.85 V

NOTE 1: VIL should not be less than -0.3V.

NOTE 2: Common mode voltage is deﬁ ned as VIH.

85411 Data Sheet

TABLE 4. AC CHARACTERISTICS, VDD = 3.3V±10% TA = 0°C TO 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 650 MHz

tPD Propagation Delay; NOTE 1 1.5 2.5 ns

tsk(o) Output Skew; NOTE 2, 4 20 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 ps

tjit Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section (12kHz to 20MHz) 0.05 ps

tR / tFOutput Rise/Fall Time 20% to 80% @ 50MHz 150 350 ps

odc Output Duty Cycle > 500MHz 47 53 %

≤ 500MHz 48 52 %

NOTE: Electrical parameters are guaranteed over the speciﬁ ed ambient operating temperature range, which is established

when the device is mounted in a test socket with maintained transverse airﬂ ow greater than 500 lfpm. The device will meet

speciﬁ cations after thermal equilibrium has been reached under these conditions.

All parameters measured at ƒ ≤ 650MHz unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Deﬁ ned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Deﬁ ned as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 4: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

85411 Data Sheet

ADDITIVE PHASE JITTER

Input/Output Additive Phase Jit-

ter @ 200MHz (12kHz to 20MHz)

= 0.05ps typical

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190 100 1k 10k 100k 1M 10M 100M 500M

The spectral purity in a band at a speciﬁ c offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the speciﬁ ed plot in many applications. Phase

noise is deﬁ ned as the ratio of the noise power present in a 1Hz

band at a speciﬁ ed offset from the fundamental frequency to the

power value of the fundamental. This ratio is expressed in decibels

As with most timing speciﬁ cations, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

ﬂ oor of the equipment is higher than the noise ﬂ oor of the device.

(dBm) or a ratio of the power in the 1Hz band to the power in the

fundamental. When the required offset is speciﬁ ed, the phase noise

is called a dBc value, which simply means dBm at a speciﬁ ed offset

from the fundamental. By investigating jitter in the frequency domain,

we get a better understanding of its effects on the desired application

over the entire time record of the signal. It is mathematically possible

to calculate an expected bit error rate given a phase noise plot.

This is illustrated above. The device meets the noise ﬂ oor of what

is shown, but can actually be lower. The phase noise is dependent

on the input source and measurement equipment.

OFFSET FROM CARRIER FREQUENCY (HZ)

SSB PHASE NOISE dBc/HZ

85411 Data Sheet

PARAMETER MEASUREMENT INFORMATION

DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT

PART-TO-PART SKEW

PROPAGATION DELAY OUTPUT RISE/FALL TIME

OUTPUT SKEW

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD DIFFERENTIAL OUTPUT VO LTAGE SETUP

85411 Data Sheet

POWER OFF LEAKAGE SETUP

OFFSET VOLTAGE SETUP

OUTPUT SHORT CIRCUIT CURRENT SETUP DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT SETUP

PARAMETER MEASUREMENT INFORMATION, CONTINUED

85411 Data Sheet

APPLICATION INFORMATION

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input clock

swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/

R1 = 0.609.

RECOMMENDATIONS FOR UNUSED OUTPUT PINS

OUTPUTS:

LVDS

All unused LVDS output pairs can be either left ﬂ oating or

terminated with 100Ω across. If they are left ﬂ oating, there

should be no trace attached.

85411 Data Sheet

FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

3.3V

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

125

Zo = 50 Ohm

3.3V

125

LVPECL

3.3V

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both signals must meet the VPP and

VCMR input requirements. Figures 2A to 2E show interface examples

for the HiPerClockS CLK/nCLK input driven by the most common

driver types. The input interfaces suggested here are examples only.

FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

IDT HIPERCLOCKS LVHSTL DRIVER

Please consult with the vendor of the driver component to conﬁ rm

the driver termination requirements. For example in Figure 2A, the

input termination applies for IDT HiPerClockS LVHSTL drivers. If

you are using an LVHSTL driver from another vendor, use their

termination recommendation.

1.8V

Input

LVHSTL Driver

ICS

HiPerClockS

LVHSTL

3.3V

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER WITH AC COUPLE

Zo = 50 Ohm

125

HiPerClockS

CLK

nCLK

3.3V

100 - 200

3.3V

100 - 200

Input

R5,R6 locate near the driver pin.

Zo = 50 Ohm

125

LVPECL C1

Zo = 50 Ohm

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiv er

CLK

nCLK

3.3V

85411 Data Sheet

LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 3. In a 100Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100Ω across near

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate

the unused outputs.

FIGURE 3. TYPICAL LVDS DRIVER TERMINATION

85411 Data Sheet

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the 85411.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 85411 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results.

• Power (core)MAX = VDD_MAX * IDD_MAX = 3.63V * 50mA = 181.5mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

A = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a

moderate air ﬂ ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.182W * 103.3°C/W = 88.8°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air ﬂ ow, and the

type of board (multi-layer).

TABLE 5. THERMAL RESISTANCE θJA FOR 8-LEAD SOIC, FORCED CONVECTION

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

85411 Data Sheet

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for 85411 is: 636

TABLE 6. θ

JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC TABLE 7. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MS-012

SYMBOL Millimeters

MINIMUN MAXIMUM

A 1.35 1.75

A1 0.10 0.25

B 0.33 0.51

C 0.19 0.25

D 4.80 5.00

E 3.80 4.00

e 1.27 BASIC

H 5.80 6.20

h 0.25 0.50

L 0.40 1.27

α0° 8°

PACKAGE OUTLINE & DIMENSIONS

85411 Data Sheet

Part/Order Number Marking Package Shipping Packaging Temperature

85411AMLF 85411ALF 8 lead “Lead Free” SOIC Tray 0°C to +70°C

85411AMLFT 85411ALF 8 lead “Lead Free” SOIC Tape and Reel 0°C to +70°C

TABLE 8. ORDERING INFORMATION

85411 Data Sheet

REVISION HISTORY SHEET

Rev Table Page Description of Change Date

BT4

Features - added Additive Phase Jitter bullet.

AC Characteristics table - added tjit row.

Added Additive Phase Jitter Application Note

6/9/04

B T7 12 Ordering Information Table - added Lead Free Part Number. 6/16/04

T3C 3

Changed VDD from ±5% to ±10% throughout datasheet.

LVDS DC Characteristics Table - changed VOD range from

200mV min./360mV max. to 247mV min./454mV max.

Changed ΔVOD from 40mV max. to 50mV max.

Changed VOS from 1.125mV min./1.375mV max. to 1.325mV min./1.575mV max.

Changed ΔVOS from 25mV max. to 50mV max.

Added Recommendations for Unused Output Pins.

Added Power Considerations.

9/19/06

C T8 14 Ordering Information Table - corrected lead-free marking. 1/17/07

C T3C 3 LVDS DC Characteristics Table - deleted VOH & VOL rows. 1/20/09

CT8

Removed ICS from part numbers where needed.

General Description - Deleted the ICS chip and removed HiPerClockS.

Features - removed reference to leaded part numbers.

Ordering Information - removed quantity for tape and reel. Deleted LF note below

the table.

Updated header and footer.

1/20/16

85411 Data Sheet

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or speciﬁ cations described herein at any time, without notice, at IDT's sole discretion. Performance speciﬁ cations and

operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided

without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe-

ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect-

ed to signiﬁ cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or

their respective third party owners.

For datasheet type deﬁ nitions and a glossary of common terms, visit www.idt.com/go/glossary.

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