© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 1
1Publication Order Number:
74HC132/D
74HC132
Quad 2−Input NAND Gate
with Schmitt−Trigger Inputs
High−Performance Silicon−Gate CMOS
The 74HC132 is identical in pinout to the LS132. The device inputs
are compatible with standard CMOS outputs; with pull−up resistors,
they are compatible with LSTTL outputs.
The HC132 can be used to enhance noise immunity or to square up
slowly changing waveforms.
Features
•Output Drive Capability: 10 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2.0 to 6.0 V
•Low Input Current: 1.0 mA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance with the Requirements as Defined by JEDEC
Standard No. 7A
•ESD Performance: HBM > 2000 V; Machine Model > 200 V
•Chip Complexity: 72 FETs or 18 Equivalent Gates
•These are Pb−Free Devices
Figure 1. Pin Assignment
11
12
13
14
8
9
105
4
3
2
1
7
6
B3
Y4
A4
B4
VCC
Y3
A3
A2
Y1
B1
A1
GND
Y2
B2
MARKING
DIAGRAMS
HC132 = Device Code
A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
G or G= Pb−Free Package
SOIC−14
D SUFFIX
CASE 751A
HC132G
AWLYWW
TSSOP−14
DT SUFFIX
CASE 948G
HC
132
ALYW G
G
1
14
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
Inputs Output
ABY
LLH
LHH
HLH
HHL
FUNCTION TABLE
1
14
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(Note: Microdot may be in either location)
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2
Figure 2. Logic Diagram
A1
B1
Y1
3
2
1
PIN 14 = VCC
PIN 7 = GND
Y = AB
A2
B2
Y2
6
5
4
A3
B3
Y3
8
10
9
A4
B4
Y4
11
13
12
ORDERING INFORMATION
Device Package Shipping†
74HC132DR2G SOIC−14
(Pb−Free) 2500 / Tape & Reel
74HC132DTR2G TSSOP−14* 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
74HC132
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC Positive DC Supply Voltage 0.5 to 7.0 V
VIN Digital Input Voltage 0.5 to 7.0 V
VOUT DC Output Voltage Output in 3−State
High or Low State
0.5 to 7.0
0.5 to VCC 0.5
V
IIK Input Diode Current 20 mA
IOK Output Diode Current 20 mA
IOUT DC Output Current, per Pin 25 mA
ICC DC Supply Current, VCC and GND Pins 75 mA
IGND DC Ground Current per Ground Pin 75 mA
TSTG Storage Temperature Range 65 to 150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds 260 _C
TJJunction Temperature Under Bias 150 _C
qJA Thermal Resistance 14−SOIC
14−TSSOP
125
170
_C/W
PDPower Dissipation in Still Air at 85_C SOIC
TSSOP
500
450
mW
MSL Moisture Sensitivity Level 1
FRFlammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
VESD ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
2000
200
V
ILatchup Latchup Performance Above VCC and Below GND at 85_C (Note 3) 300 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to EIA/JESD78.
4. For high frequency or heavy load considerations, see Chapter 2the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types 55 125 _C
tr, tfInput Rise and Fall Time (Figure 3) −No Limit
(Note 5)
ns
5. When VIN 0.5 VCC, ICC >> quiescent current.
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions (V) *55_C to 25_C85_C125_CUnit
VT+max Maximum Positive−Going
Input Threshold Voltage
(Figure 5)
VOUT = 0.1 V
|IOUT| 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VT+min Minimum Positive−Going
Input Threshold Voltage
(Figure 5)
VOUT = 0.1 V
|IOUT| 20 mA
2.0
4.5
6.0
1.0
2.3
3.0
0.95
2.25
2.95
0.95
2.25
2.95
V
VT–max Maximum Negative−Going
Input Threshold Voltage
(Figure 5)
VOUT = VCC – 0.1 V
|IOUT| 20 mA
2.0
4.5
6.0
0.9
2.0
2.6
0.95
2.05
2.65
0.95
2.05
2.65
V
VT–min Minimum Negative−Going
Input Threshold Voltage
(Figure 5)
VOUT = VCC – 0.1 V
|IOUT| 20 mA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VHmax
(Note 7)
Maximum Hysteresis
Voltage
(Figure 5)
VOUT = 0.1 V or VCC – 0.1 V
|IOUT| 20 mA
2.0
4.5
6.0
1.2
2.25
3.0
1.2
2.25
3.0
1.2
2.25
3.0
V
VHmin
(Note 7)
Minimum Hysteresis
Voltage
(Figure 5)
VOUT = 0.1 V or VCC – 0.1 V
|IOUT| 20 mA
2.0
4.5
6.0
0.2
0.4
0.5
0.2
0.4
0.5
0.2
0.4
0.5
V
VOH Minimum High−Level
Output Voltage
VIN VT−min or VT+max
|IOUT| 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN −VT−min or VT+max
|IOUT| 4.0 mA
|IOUT| 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL Maximum Low−Level
Output Voltage
VIN ≥ VT+max
|IOUT| 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN ≥ VT+max |IOUT| 4.0 mA
|IOUT| 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN Maximum Input Leakage
Current
VIN = VCC or GND 6.0 0.1 1.0 1.0 mA
ICC Maximum Quiescent
Supply Current
(per Package)
VIN = VCC or GND
IOUT = 0 mA
6.0 2.0 20 40 mA
7. VHmin (VT+min) (VT−max); VHmax = (VT+max) (VT−min).
8. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
74HC132
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5
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
VCC Guaranteed Limit
Symbol Parameter (V) *55_C to 25_C85_C125_CUnit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 3 and 4)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 3 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin Maximum Input Capacitance — 10 10 10 pF
9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (per Gate) (Note 10) 24 pF
10.Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Figure 3. Switching Waveforms
tr
VCC
GND
90%
50%
10%
90%
50%
10%
INPUT
A OR B
Y
tPHL tPLH
tTHL tTLH *Includes all probe and jig capacitance
Figure 4. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
tf
74HC132
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6
Figure 5. Typical Input Threshold, VT+, VT− Versus Power Supply Voltage
Figure 6. Typical Schmitt−Trigger Applications
4
3
2
1
23456
VCC, POWER SUPPLY VOLTAGE (VOLTS)
VHtyp
VHtyp = (VT+ typ) − (VT− typ)
(a)A SCHMITT TRIGGER SQUARES UP INPUTS
(a)WITH SLOW RISE AND FALL TIMES
(b)A SCHMITT TRIGGER OFFERS MAXIMUM
NOISE IMMUNITY
VIN
VOUT
VH
VCC
VT+
VT−
GND
VOH
VOL
VIN
VH
VOUT
VCC
VT+
VT−
GND
VOH
VOL
VCC
VIN
VOUT
VT
, TYPICAL INPUT THRESHOLD VOLTAGE
(VOLTS)
74HC132
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7
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
7X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
74HC132
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8
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇ
ÇÇÇ
ÇÇÇ
SECTION N−N
DETAIL E
JJ1
K
K1
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
14X REFK
N
N
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
74HC132
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9
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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USA/Canada
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Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
74HC132/D
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