STM-4/STM-1/E4 3.3 V Multifunction Transmitter and Receiver GD16591A/GD16592A an Intel company General Description Features The GD16591A and GD16592A is a front-end transmitter/receiver chip set designed for multiple line interfaces: u STM-4 / OC-12 u STM-1 / OC-3 u PDH E4 This chip set is designed to interconnect the high speed line interface to standard CMOS ASICs providing low speed data interface. The GD16591A and GD16592A devices are designed for use in both electrical and optical line interface modules. The devices support line speeds of: u 140/155 Mbit/s NRZ mode for E4/ OC-3/STM-1 for an optical line interface. u 280/311 Mbit/s for E4/OC-3/STM-1 in CMI mode for electrical line interface, where en-/decoding is made at the system site. u 622 Mbit/s NRZ mode line speed for OC-12/STM-4 operation. The on-chip VCO and PLL blocks for clock generation eliminate the need for an external high-speed clock signal. General l l l The low-speed interface I/Os are LVTTL-level, and the high-speed I/Os are differential LVPECL levels (The LIA input is usable as LVPECL input). System (local) Loop-back and Line (remote) Loop-back functions offer simplified manufacturing and field testing. Low power consumption is achieved by the 3.3 V single power supply and by omitting all circuitry, which can easily be implemented in the low speed system ASIC, thus reducing the overall power consumption. l l l The devices are housed in 48 pin EDQUAD TQFPa plastic packages. GD16591A MUX/ Retiming PLL CMOS System ASIC Data 70/78 Mbit/s 17/19 Mbit/s The GD16592A comprises a Limiting Input Amplifier (LIA), Clock & Data Recovery, and a configurable DeMUX circuit. The LIA offers a differential input sensitivity of 10 mV peak to peak for the highspeed serial input. A Lock Detect output monitors the PLL locked onto the received serial data. 140/155 Mbit/s (optical) 280/311 Mbit/s (electrical) 622 Mbit/s (STM-4 opt.) Clock The chip set offers seven line and system speed mode: 622 Mbit/s 78 Mbit/s, 8 bit 311 Mbit/s 78 Mbit/s, 4 bit 155 Mbit/s 78 Mbit/s, 2 bit 155 Mbit/s 19 Mbit/s, 8 bit 280 Mbit/s 70 Mbit/s, 4 bit 140 Mbit/s 70 Mbit/s, 2 bit 140 Mbit/s 17 Mbit/s, 8 bit Four phase selectable clock to data timing at parallel interface. Selectable reference clock input frequencies: 17.408/19.44MHz, 34.816/ 38.88MHz, and 69.632/77.76MHz. Loop Back for System & Line test modes. l 48 pin EDQUAD TQFPa packages. l Single supply: 3.1 ... 3.6 V. l 8:1 / 4:1 / 2:1 MUX. l Differential transmitted clock output. l LVPECL data outputs. l System / Line Loop Back l Data 70/78 Mbit/s 17/19 Mbit/s Jitter performance exceeds the recommendations of ITU-T and Bellcore. GD16591A (Transmitter) Line Interface 2 / 4 / 8 bit Low jitter on-chip VCO and PLL. Optional forward/counter clocking scheme. Power dissipation, typ.: 350 mW Line Interface 2 / 4 / 8 bit 140/155 Mbit/s (optical) 280/311 Mbit/s (electrical) 622 Mbit/s (STM-4 opt.) Clock GD16592A (Receiver) l GD16592A DeMUX/ CDR with PLL 1:8 / 1:4 / 1:2 DeMUX. Data Sheet Rev.: 14 Functional Details General The Transmitter and Receiver functional blocks are split up into two devices in order to reduce cross talk and pin count per device. The telecommunication system (line speed group) is choosen by the select pin (SELPDH): u For SDH/SONET (622/311/155 Mbit/s) set SELPDH High. u For PDH (280/140 Mbit/s) set SELPDH Low. The devices can operate in different line and system speed modes; selected by DSEL1, DSEL2 and SELPDH, see Table 1. The bit order on the low speed parallel interface is defined with bit 0 as the first bit transferred (ID0 for the transmitter and OD0 for the receiver). The bit rate per connection can be kept at 78(70) Mbit/s regardless of the line speed. In addition a separate low speed 1:8 mode support the transmission of 155(140) Mbit/s serial to 19(17) Mbit/s, 8 bit parallel. All data pins are used. Both devices have a selectable clock divider for the system reference clock, which allows the circuits to be driven from either 19 (17), 38(35), or 78(70) MHz reference, independantly of the line and system speed. The reference clock frequency is selected by RSEL1, RSEL2, and SELPDH, see table 2. Connecting the differential Line Loop Signals and Clocks (LLxxx) between GD16591A and GD16592A allows clock recovered loop-back of the received line signal, when LLB on both devices is low. Connecting the differential System Loop Signals (SLSxx) between GD16591A and GD16592A allows system loop-back, when SLB on both devices is low. Both circuits comprise fully integrated PLL functions for re-timing data at the transmit site, and for clock and data recovery at the receive site. The optimal values depends on the actual application. The suggested values in Figures 1 and 2 are optimized for best jitter transfer at the evaluation board. The loop filter values should be optimized for the actual application. VCTL VCTL VCC VCC 1.5kW 1mF VCCA VCCA 15W 1mF OUCHP OUCHP Figure 1. Loop Filter for the Transmitter, GD16591A. Figure 2. Loop Filter for the Receiver, GD16592A. SELPDH DSEL1 DSEL2 Line Speed System Speed Used Bits 0 0 0 0 0 0 1 1 0 1 0 1 140 Mbit/s 140 Mbit/s 280 Mbit/s --- 70 Mbit/s 17 Mbit/s 70 Mbit/s --- 0&1 0...7 0...3 --- 1 1 1 1 0 0 1 1 0 1 0 1 155 Mbit/s 155 Mbit/s 311 Mbit/s 622 Mbit/s 78 Mbit/s 19 Mbit/s 78 Mbit/s 78 Mbit/s 0&1 0...7 0...3 0...7 Table 1. Line and system speed mode selection. SELPDH RSEL1 RSEL2 Ref. Clock 0 0 0 0 1 1 0/1 0 1 69.632 MHz 34.816 MHz 17.408 MHz 1 1 1 0 1 1 0/1 0 1 77.76 MHz 38.88 MHz 19.44 MHz Table 2. Reference clock frequency selection. A passive loop filter (consisting of a resistor and a capacitor) is used for both devices. The external loop filter connecting OUCHP to VCTL is shown in Figure 1 (for the transmitter GD16591A) and Figure 2 (for the receiver GD16592A). The loop filter values are optimized at the evaluation board GD90591/592. Data Sheet Rev.: 14 GD16591A/GD16592A Page 2 of 16 The Transmitter - GD16591A Forward Clocking Co-directional timing for input data is provided. The phase can with the select pins PSEL1-2 be set to 0/ 90/ 180/ 270 difference between data input sampling and reference clock (CKR0/CKR1). When forward clocking, the frequency of the reference clock must be identical to the input data bit rate. I.e. for 78(70) Mbit/s use 78(70) MHz reference clock, and for 19(17) Mbit/s use 19(17) MHz reference clock. Refer to AC Characteristics on page 12. SLB LLB LLSIN LLCIN LLSIP LLCIP PSEL2 PSEL1 DSEL1 By the select signal (CSEL) two different reference clock inputs can be selected (CKR0/CKR1). This allows for line timing in normal operation with a selection of a separate reference when the received line input data is flawed. Thus, allowing forwarding alarm status in the event of a loss of received data. DSEL2 The schematic block diagram of GD16591A is shown in Figure 3. SLSOP SLSON ID0 SOP MUX ID7 SON LD SELPDH VCO VCTL Phase Adjust Clock Gen. COP 0 /90 180o/270o o SELTCK o CON CKOUT Divide by 1/2/4 RSEL1 RSEL2 VCC VCCA V CKR0 R CKR1 PFC U U D D GND GNDA CSEL Counter Clocking In addition, contra directional timing is provided. The phase between input and CKOUT is adjustable with (0/90/180/ 270). Refer to AC Characteristics on page 12. CKOUT is kept synchronous to the reference clock by the Phase Frequency Comparator (PFC). OUCHP Figure 3. The GD16591A Multifunction Transmitter. Output LVPECL The serial data output (SOP/SON) are accompanied by a serial clock output (COP/CON). See timing data on page 12. SLSOP/SLSON is enabled when SLB is low. When SLB is high (e.g. by internal pull-up resistor) SLSOP = 0 and SLSON = 1; thus avoiding noise injection at normal operation. LVPECL 100nF Outputs 180W The outputs from the multiplexer is fed to differential LVPECL output stages. See Figures 4 and 5 for output temination. Input 100nF 180W 50W 0V (GND) 50W 2V (VCC -1.3V) Figure 4. LVPECL Output Termination, AC-coupled. Output Input LVPECL LVPECL 50W 50W 1.3V (VCC -2V) Figure 5. LVPECL Output Termination, DC-coupled. Data Sheet Rev.: 14 GD16591A/GD16592A Page 3 of 16 The Receiver - GD16592A Bang-Bang Phase Detector As a result of the continuous monitoring lock-detect circuit the VCO frequency never deviates more than 500 ppm (2000 ppm) from the reference clock before the PLL is considered to be 'Out of Lock'. Hence the acquisition time is predictable and short and the output clock CKOUT is always kept within the LLCON PSEL2 PSEL1 DSEL2 DSEL1 SLB Once the VCO is inside the lock-range the lock-detection circuit switches the Bang-Bang phase detector into the PLL in order to lock to the data signal. This mode is called CDR mode. The binary output of either the PFC or the Bang-Bang phase detector (depending of the mode of the lock-detection circuit) is fed to a charge pump capable of sinking or sourcing current or tristating. The output of the charge pump is filtered through the loop filter and controls the tuning-voltage of the VCO. LLCOP The PFC is used to ensure predictable lock up conditions for the GD16592A by locking the VCO to an external reference clock source. It is only used during acquisition and pulls the VCO into the lock range where the Bang-Bang phase detector is capable of acquiring lock to incoming data. The PFC is made with digital set/reset cells giving it a true phase and frequency characteristic. LLSON The lock detect circuit continuously monitors the frequency difference between the reference clock and the divided VCO clock. If the reference clock and the divided VCO frequency differs by more than 500 ppm (or 2000 ppm, selectable), it switches the PFC into the PLL in order to pull the VCO back inside the lock-in range. This mode is called the acquisition mode. LLSOP Lock Detect Circuit The Bang-Bang phase detector is used in CDR mode as a true digital type detector, producing a binary output. It samples the incoming data twice each bit period: once in the transition of the (previous) bit period and once in the middle of the bit period. When a transition occurs between 2 consecutive bits - the value of the sample in the transition between the bits will show whether the VCO clock leads or lags the data. Hence the PLL is controlled by the bit transition point, thereby ensuring that data is sampled in the middle of the eye, once the system is in CDR mode. The external loop filter components control the characteristics of the PLL. LLB The schematic block diagram of GD16592A is shown in Figure 6. Bang Bang Phase Detector SIP OD0 DeMUX OD7 SIN SELPDH VCO VCTL Clock Gen. SELTCK Phase Adjust. CKOUT 0o/90o 180o/270o LSEL1 LSEL2 LOCK Divide by 4 Lock Detect VCC VCCA CKRF Divide by 1/2/4 The LOCK Signal The status of the lock-detection circuit is given by the LOCK signal. In CDR mode LOCK is steady high. In acquisition mode LOCK is alternating indicating the continuous shifts between the Bang-Bang Detector (high) and the PFC (low). The LOCK output may be used to generate a pseudo Loss Of Signal (LOS). The time for LOCK to assert is predictable and short, equal to the time to go into lock, but the time for LOCK to de-assert must be considered. When the line is down (i.e. no information received) the optical receiver circuit may produce random noise. It is possible that this random noise will keep the GD16592A within the 500 ppm (2000 ppm) range of the line frequency, hence LOCK will remain asserted for a non-deterministic time. This may be prevented by injecting a small current at the loop filter node, which actively pulls the PLL out of the lock range when the output of the phase detector acts randomly. The negligible penalty paid is a static phase error on the sampling time in the decision gate. However, due to the nature of the phase detector the error will be small (few degrees), forcing the loop to be at one edge of the error-function shaped transfer characteristic of the detector. Inputs SLSIP SLSIN 500 ppm (2000 ppm) limits, ensuring safe clocking of down stream circuitry. GND GNDA PFC The input amplifier (pin SIP / SIN) is designed as a limiting amplifier with a sensitivity of 10 mV (differential). Standard LVPECL levels may be applied as well. The inputs may be either AC or DC coupled. If the inputs are AC coupled the amplifier features an internal offset cancelling DC feedback. Notice that the offset cancellation will only work when the input is differential and AC-coupled as shown in the Figures 7 and 8 on page 5. The serial input SLSIP/SLSIN is selected when SLB is low. Outputs OUCHP RSEL1 RSEL1 Figure 6. The GD16592A Multifunction Receiver. Data Sheet Rev.: 14 GD16591A/GD16592A The CKOUT provides the necessary control for clocking the received data into the system ASIC. The phase can be adjusted with PSEL1-2 (0/90/180/270). Page 4 of 16 Practical Considerations 8k 100nF SIP 100nF SIN 50W 50W 100nF 100nF + LIA 8k The PCB must be designed with shortest possible conductors for the signals to the line interfaces. These connections should be designed as transmission lines. De-coupling capacitors should be applied to each power supply pin. Care should be taken to reduce ground bounce. The line loop signal and clock must be terminated close to the transmitter device (GD16591A). Figure 7. AC Coupled Input (using internal offset compensation). The system loop signal must be terminated close to the receiver device (GD16592A). 8k SIP SIN 50W 50W + LIA 8k VTT Figure 8. DC Coupled Input (ignoring internal offset compensation). VTT depends on the termination requirements of the previous stage, and the resulting amplitude on the input. Data Sheet Rev.: 14 GD16591A/GD16592A Page 5 of 16 Pin List, GD16591A - Transmitter Mnemonic: Pin No.: Pin Type: Description: 38, 40 LVTTL IN Reference clock inputs selectable by CSEL. Usable for forward clocking (co-directional timing), see AC-characteristics on page 12. The CKRx input must be noise free, since noise injected here passes onto the line. The frequency is determined by RSEL1-2. Maximum frequency is 78 MHz. CSEL=0 => CKR0; CSEL=1 =>CKR1 31, 29, 28, 22, 21, 19, 18, 17 LVTTL IN Data input port to MUX. See DSEL1-2 for bit use. ID0 is the first bit transmitted. See PSEL1-2 for timing. 27, 26 LVTTL IN DSEL1 0 0 1 1 1 LVTTL IN PDH(E4) mode select: 0 Line speeds 140 or 280 Mbit/s 1 Line speeds 155, 311, or 622 Mbit/s SELPDH is used as test clock input when SELTCK is low. RSEL1, RSEL2 35, 34 LVTTL IN Reference clock frequency select: RSEL1 RSEL2 CKREF (MHz) 0 0/1 77.76 1 0 38.88 1 1 19.44 PSEL1, PSEL2 42, 41 LVTTL IN IDx input phase versus CKOUT/CKRx select: (Note 2) PSEL2 PSEL1 0 0 TDEL = 0 0 1 TDEL = 90 1 0 TDEL = 180 1 1 TDEL = 270 SELTCK 47 LVTTL IN Connect to VCC. Used for test purpose (selects SELPDH as test clock when low). LLB 25 LVTTL IN Line Loop-Back, enabled when low. SLB 3 LVTTL IN System Loop-Back, enabled when low. LLSIP, LLSIN 16, 15 LVPECL IN Line Loop-back serial differential data. Connect to LLSOP/LLSON of GD16592A . LLCIP, LLCIN 14, 13 LVPECL IN Line Loop-back serial differential clock. Connect to LLCOP/LLCON of GD16592A. CKOUT 32 LVTTL OUT 77.76 MHz /19.44 MHz output clock. Usable for counter clocking (contradirectional timing) . SLSOP, SLSON 10, 9 LVPECL OUT System loop-back serial differential data. Connect and terminate close to SLSIP/SLSIN of GD16592A. SOP, SON 5, 4 LVPECL OUT Differential data output from MUX. SOP is true output, SON is inverted. COP, CON 8, 7 LVPECL OUT Differential clock output from MUX. VCTL 45 Analog IN OUCHP 43 Analog OUT 2, 11, 20, 23, 30, 37 PWR +3.3 V power for core and I/O. VCCA 44 PWR +3.3 V power for VCO. GND 6, 12, 24, 33, 36, 48 GND 0 V power for core and I/O. 46 GND 0 V power for VCO. CKR0, CKR1 CSEL 39 ID0..ID7 DSEL1, DSEL2 SELPDH VCC GNDA Heat sink Note 1: Note 2: DSEL2 0 1 0 1 Line speed 155 Mbit/s 155 Mbit/s 311 Mbit/s 622 Mbit/s System speed 78 Mbit/s 19 Mbit/s 78 Mbit/s 78 Mbit/s Used bit 0&1 0 .. 7 0 .. 3 0 .. 7 VCO control voltage input. Connect to OUCHP and terminate with 1 kW in series with 1 mF to VCCA. Charge pump output. Connected to GND. Only standard line speeds for SDH/SONET applications are indicated. For PDH (E4) usage, corresponding values apply, i.e. substitute 19 MHz clock with 17 MHz, 78 MHz with 70 MHz, 155 Mbit/s with 140 Mbit/s, 311 Mbit/s with 280 Mbit/s. When forward clocking, the frequency of the reference clock must be identical to the input data bit rate. Data Sheet Rev.: 14 GD16591A/GD16592A Page 6 of 16 Pin List, GD16592A - Receiver Mnemonic: Pin No.: Pin Type: Description: 32 LVTTL IN Reference clock input (19 / 39 / 78 MHz), determined by RSEL1, RSEL2. 39, 38 LVTTL IN DSEL1 0 0 1 1 1 LVTTL IN Active low, PDH(E4) mode select: 0 Line speeds 140 or 280 Mbit/s 1 Line speeds 155, 311, or 622 Mbit/s SELPDH is used as test clock input when SELTCK is low. RSEL1, RSEL2 3, 34 LVTTL IN RSEL1 0 1 1 RSEL2 0/1 0 1 Reference clock frequency select: CKRF = 78 MHz CKRF = 38 MHz CKRF = 19 MHz LSEL1, LSEL2 10, 9 LVTTL IN LSEL1 0 0 1 1 LSEL2 0 1 0 1 Lock Select inputs for clock and data recovery set-up. Manual, Phase Freq. Comp. (PFC) Manual, Phase Detect (BB) Auto lock, 2000 ppm Auto lock, 500 ppm (Default, when not connected) SELTCK 47 LVTTL IN Connect to VCC. Test purpose (selects SELPDH as test clock when low). LLB 41 LVTTL IN Line Loop-Back, enabled when low. SLB 40 LVTTL IN System Loop-Back, enabled when low. 25, 35 LVTTL IN PSEL2 0 0 1 1 SIP, SIN 4, 5 Analog IN Differential serial data input. SLSIP, SLSIN 7, 8 LVPECL IN System loop-back serial differential data. Connect to SLSOP/N of GD16591A. CKOUT 29 LVTTL OUT Regenerated output clock (77.76 / 19.44 MHz). Used for ODx timing. 28, 27, 26, 22, 21, 19, 18, 17 LVTTL OUT Re-timed data output from DeMUX. See DSEL1-2 for bit use. OD0 is the first bit received. See PSEL1-2 for timing. LLSOP, LLSON 13, 14 LVPECL OUT Line loop-back serial differential data. Connect and terminate close to LLSIP/LLSIN of GD16591A. LLCOP, LLCON 15, 16 LVPECL OUT Line loop-back serial differential clock. Connect and terminate close to LLCIP/LLCIN of GD16591A. LOCK 42 LVTTL OUT VCTL 45 Analog IN OUCHP 43 Analog OUT Charge Pump output for PLL. 2, 11, 20, 23, 30, 37 PWR +3.3 V power for core and I/O. VCCA 44 PWR +3.3 V power for VCO. GND 6, 12, 24, 33, 36, 48 GND 0 V power for core and I/O. GNDA 46 GND 0 V power for VCO. NC 31 NC CKRF DSEL1, DSEL2 SELPDH PSEL1, PSEL2 OD0...OD7 VCC Heat sink Note: DSEL2 0 1 0 1 PSEL1 0 1 0 1 Line speed 155 Mbit/s 155 Mbit/s 311 Mbit/s 622 Mbit/s System speed 78 Mbit/s 19 Mbit/s 78 Mbit/s 78 Mbit/s Used bit 0&1 0 .. 7 0 .. 3 0 .. 7 ODx output phase versus CKOUT select: TDEL = 0 TDEL = 90 TDEL = 180 TDEL = 270 High level indicates PLL locked to incoming data signal. Low level indicates PLL out of lock. VCO control voltage input. Connect to OUCHP and terminate with 22 W in series with 1 mF to VCCA. Not Connected. Connected to GND. Only standard line speeds for SDH/SONET applications are indicated. For PDH (E4) usage, corresponding values apply, i.e. substitute 19 MHz clock with 17 MHz, 78 MHz with 70 MHz, 155 Mbit/s with 140 Mbit/s, 311 Mbit/s with 280 Mbit/s. Data Sheet Rev.: 14 GD16591A/GD16592A Page 7 of 16 Package Pinouts GNDA VCTL VCCA OUCHP PSEL1 PSEL2 CKR1 CSEL CKR0 VCC 47 46 45 44 43 42 41 40 39 38 37 48 SELTCK GND SELPDH 1 36 GND VCC 2 35 RSEL1 SLB 3 34 RSEL2 SON 4 33 GND SOP 5 32 CKOUT GND 6 31 ID0 CON 7 30 VCC COP 8 29 ID1 SLSON 9 28 ID2 SLSOP 10 27 DSEL1 VCC 11 26 DSEL2 GND 12 25 LLB 24 GND DSEL2 VCC 38 37 VCC VCC 20 ID5 23 19 ID6 22 18 ID7 ID4 17 LLSIP ID3 16 LLSIN 21 14 15 LLCIN LLCIP 13 Figure 9. GD16591A, Package 48 pin TQFP - Top View. DSEL1 40 39 42 41 LOCK 43 LLB OUCHP 44 SLB VCCA 46 45 47 VCTL SELTCK 48 GNDA GND SELPDH 1 36 GND VCC 2 35 PSEL2 RSEL1 3 34 RSEL2 SIP 4 33 GND SIN 5 32 CKRF GND 6 31 NC SLSIP 7 30 VCC SLSIN 8 29 CKOUT LSEL2 9 28 OD0 LSEL1 10 27 OD1 VCC 11 26 OD2 GND 12 25 PSEL1 21 23 24 OD3 VCC GND OD5 22 19 OD6 VCC 18 OD7 OD4 17 LLCON 20 15 16 LLSON LLCOP LLSOP 14 13 Figure 10.GD16592A, Package 48 pin TQFP - Top View. Data Sheet Rev.: 14 GD16591A/GD16592A Page 8 of 16 Maximum Ratings These are the limits beyond which the component may be damaged. All voltages in the table are referred to GND. All currents in the table are defined positive out of the pin. Symbol: Characteristic: VCC, VCCA Supply Voltage V0 MAX Output Voltage I0 MAX, LVPECL MAX.: UNIT.: 0 6 V -0.5 VCC+0.5 V Output Current 30 mA I0 MAX, VCTL Output Current 0.5 mA IOO, LVTTL LVTTL Output Source Current 24 mA IOI, LVTTL LVTTL Output Sink Current -24 mA VI MAX Input Voltage -0.5 VCC+0.5 V II MAX Input Current -1.0 1.0 mA T0 Operating Temperature -55 125 C TS Storage Temperature -65 150 C VESD Electro Static Discharge Voltage Note1: Conditions: Junction Note 1 MIN.: TYP.: 500 V According to MIL std. 883, method 3015, Human Body Model. Thermal Characteristics The worst case thermal resistance from junction to ambient is QJA = 75 C/W in still air, using a low conductivity board (2 layers) according to JEDEC standard JESD51.3. When using a low conductivity board with no air flow it is recommended that the heat sink is soldered to the board, and that the board is a multilayer. Data Sheet Rev.: 14 GD16591A/GD16592A Page 9 of 16 DC Characteristics TAMBIENT = -25 oC to 85 oC. All voltages in the table are referred to GND . All input signal and power currents in the table are defined positive into the pin. All output signal currents are defined positive out of the pin. Symbol: Characteristic: MIN.: TYP.: MAX.: UNIT: VCC, VCCA Positive Supply Voltage 3.1 3.3 3.6 V ICC,GD16591A Positive Supply Current (GD16591A) Note 1 105 130 mA ICC,GD16592A Positive Supply Current (GD16592A) Note 1 135 160 mA VSIN,SIP Data Input Voltage Swing, Differential Note 5 10 1400 mVP-P VICM, LVPECL LVPECL Input Common Mode Voltage VCC -1.5 VCC -1.1 V VIDIFF, LVPECL LVPECL Input Differential Voltage 0.25 1.4 V II, LVPECL LVPECL Input Current -100 100 mA VOH, LVPECL LVPECL Output HI Voltage Note 2 VCC -1.2 VCC -0.6 V VOL, LVPECL LVPECL Output LO Voltage Note 2 VCC -2.0 VCC -1.6 V VODIFF, LVPECL LVPECL Output Differential Voltage Note 2 0.6 1.1 V VIH, LVTTL LVTTL Input HI Voltage Note 3, 4 2.0 VCC V VIL, LVTTL LVTTL Input LO Voltage Note 3, 4 0.0 0.8 V IIH, LVTTL LVTTL Input HI Current Note 3, 4 100 mA IIL, LVTTL LVTTL Input LO Current Note 3, 4 VOH, LVTTL LVTTL Output HI Voltage IOH = 3 mA, Note 4, 6 VOL, LVTTL LVTTL Output LO Voltage IOL = -1 mA, Note 4 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Conditions: 0.5 -500 mA VCC -1.1 V 0 0.5 V Power: 0.8 x PTYP < P < 1.2 x PTYP; add to this variations due to power supply voltage. It is noted that the AC power depends on the frequency and load at the outputs (LVTTL). RLOAD = 50 W to VCC -2.0 V All LVTTL inputs are provided with an internal pull-up resistor of 16 kW 20 %, room temperature. Thus, the default LVTTL input value is "1" when not connected. Under the condition of typical supply voltage (3.3 V). Standard LVPECL differential voltages may be applied to input SIP, SIN. If single-ended input is used, the minimum required peak to peak voltage is 25 mV. For IOH = 1 mA the minimum HI voltage is increased 100 mV (i.e. VCC -1 V). Data Sheet Rev.: 14 GD16591A/GD16592A Page 10 of 16 AC Characteristics - General TAMBIENT = -25 C to +85 C. Symbol: Characteristic: Conditions: FTRSDH SDH Tuning Range Relative to Center Frequency Note 1 FTRPDH PDH Tuning Range Relative to Center Frequency Note 1 TR-LVPECL LVPECL Output Rise Time Note 2 TF-LVPECL LVPECL Output Fall Time TR-LVTTL MAX.: UNIT: 98 102 % 97 101 % 270 500 ps Note 2 200 500 ps LVTTL Output Rise Time Note 3 0.8 1 ns TF-LVTTL LVTTL Output Fall Time Note 3 0.8 1 ns DCCKOUT Duty Cycle, CKOUT @ 78 MHz Note 4 50 60 % Note 1: Note 2: Note 3: Note 4: MIN.: 40 TYP.: The frequency tuning range may be larger. The minimum/maximum values define the worst case range of the VCO at temperature and power extremes. 20 - 80 %, 50 W to VCC -2.0 V. 20 - 80 %, 10 pF. The 20 - 80 % rise and fall times are 2 ns (maximum) with 20 pF load. Measured at VTH = 1.4 V, 10 pF. Data Sheet Rev.: 14 GD16591A/GD16592A Page 11 of 16 AC Characteristics - GD16591A TAMBIENT = -25 C to +85 C. CKRx (78 MHz) COP CKRx (39 MHz) SOP/SON CKRx (19 MHz) TCO SLSOP/N CKOUT (78 MHz) TSLCO CKOUT (19 MHz) TRC TRC19 Forward Clocking CKOUT (78 MHz) IDx(0o) TSA IDx(90o) THA IDx(270o) TSB GD16591A Frequency Range: TSC THC PDH E4 STM-1 / OC-3 (CMI) TSD THD STM-1 / OC-3 (optical) 100 Hz - 1.3 MHz 60 0.1 STM-4 / OC-12 1000 Hz - 5 MHz 60 0.05 THB IDx(180o) Intrinsic VCO Jitter Generation Period [s] Jitter: [UIp-p] 200 Hz - 3.5 MHz 10 0.05 500 Hz - 1.3 MHz 60 0.05 Maximum Allowed RMS Jitter on Reference Clocks Inputs Counter Clocking Line Rate Ref. Clk. Frq. CKOUT (19/78 MHz) IDx(90o) THE TSE IDx(180o) IDx(270o) Data Sheet Rev.: 14 TSF THF TSG THG 311 Mbit/s 155 Mbit/s 78 MHz 13 ps 26 ps 52 ps 39 MHz 9 ps 18 ps 36 ps 19 MHz IDx(0o) 622 Mbit/s 3 dB - PLL BW (Note 1) Note 1: Note 2: TSH THH GD16591A/GD16592A 5 ps 10 ps 20 ps 12 (R) 500 kHz 12 (R) 250 kHz 12 (R) 125 kHz Measure the RMS jitter on the reference clock within the 3 dB PLL bandwidth used for the actual line rate. Adding the maximum allowed jitter on the reference clock inputs the resulting output jitter will meet the standard recommendations (ITU-T G.751, G.813, G.952, and DE/TM-3017-4). Page 12 of 16 AC Characteristics - GD16591A - Continued TAMBIENT = -25 C to +85 C. Symbol: Characteristic: TCO Conditions: MIN.: TYP.: MAX.: UNIT: COP (falling edge) to SOP/SON Valid 100 200 400 ps TSLCO COP (falling edge) to SLSOP/N Valid 100 200 400 ps TSLL LLSIP/N Set-up Time before LLCIP falling edge 500 ps THLL LLSIP/N Hold Time after LLCIP falling edge 50 ps TSA IDx Set-up Time before CKRx rising edge Note 5 3.5 ns TSB IDx Set-up Time after CKRx rising edge Note 1, 5 T/4 - 3.5 ns TSC IDx Set-up Time after CKRx rising edge Note 1, 5 T/2 - 3.5 ns TSD IDx Set-up Time after CKRx rising edge Note 1, 5 3xT/4 - 3.5 ns THA IDx Hold Time after CKRx rising edge Note 5 THB IDx Hold Time after CKRx rising edge THC 2.5 ns Note 1, 5 T/4 + 2.5 ns IDx Hold Time after CKRx rising edge Note 1, 5 T/2 + 2.5 ns THD IDx Hold Time after CKRx rising edge Note 1, 5 3xT/4+2.5 ns TRC Delay from CKRx rising edge to CKOUT falling edge 78 MHz, 5 pF load 2.5 3.5 4.5 ns TRC19 Delay from CKRx rising edge to CKOUT falling edge 19 MHz, 5 pF load Note 6 12 13 14 ns PWHI, CKRx High Pulse Width, CKRx Inputs Note 2 3 ns TSE IDx Set-up Time before CKOUT falling edge Note 3 TRC + 3.5 ns TSF IDx Set-up Time after CKOUT falling edge Note 1, 3 T/4-TRC-3.5 ns TSG IDx Set-up Time after CKOUT falling edge Note 1, 3 T/2-TRC-3.5 ns TSH IDx Set-up Time after CKOUT falling edge Note 1, 3 3xT/4-TRC-3.5 ns THE IDx Hold Time before CKOUT falling edge Note 3 THD IDx Hold Time after CKOUT falling edge THF TRC-2.5 ns Note 1, 3 T/4-TRC+2.5 ns IDx Hold Time after CKOUT falling edge Note 1, 3 T/2-TRC+2.5 ns THG IDx Hold Time after CKOUT falling edge Note 1, 3 3xT/4-TRC+2.5 ns JT Jitter Transfer Note 4 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: 0.0 0.1 dB T equals the period time for CKOUT, which is the bit period for the parallel data; i.e. 12.9 ns for 78 Mbit/s or 51.4 ns for 19 Mbit/s. Measured at VTH = 1.4 V. It is the rising edge, which is used for the timing and frequency comparison. The 20% - 80% rise time should be less than 1 ns to minimise jitter at the reference clock inputs. Set-up and Hold times with respect to the delay TRC. PLL 3 dB bandwidth 12 kHz to N x 125 kHz for STM-N. Peaking and bandwidth depends on actual loop filter values. Valid for 78 MHz forward clocking. For 19 MHz forward clocking the setup and hold windows are delayed 9.6 ns. TRC19 is actually TRC + 9.6 ns. Data Sheet Rev.: 14 GD16591A/GD16592A Page 13 of 16 AC Characteristics - GD16592A TAMBIENT = -25 C to +85 C. CKOUT (19/78 MHz) ODx (0o) TA LLCOP ODx (90o) LLSOP/N TB ODx (180o) TLLCO TC ODx (270o) TD [UI] Jitter Tolerance A1 GD16592A f1 [Hz] f2 [Hz] f3 [Hz] f4 [Hz] A1 [UIp-p] A2 [UIp-p] PDH E4 200 500 10k 3.5M 2 0.15 STM-1 / OC-3 (CMI) 500 3.25k 65k 1.3M 2 0.15 STM-1 / OC-03 (optical) 500 6.5k 65k 1.3M 2 0.2 STM-4 / OC-12 300 25k 250k 2.5M 2 0.2 Note: A2 f1 f2 f3 f4 [Hz] The stated jitter tolerance of GD16592A exceeds the standard recommendations (ITU-T G.823, G.825, and DE/TM-03067). Symbol: Characteristic: MIN.: TYP.: MAX.: UNIT: TLLCO LLCOP to LLSOP/N Valid 100 200 400 ps TA CKOUT to ODx Valid Note 3 0 1 ns TB CKOUT to ODx Valid Note 1, 3 T/4 T/4+1 ns TC CKOUT to ODx Valid Note 1, 3 T/2 T/2+1 ns TD CKOUT to ODx Valid Note 1, 3 3xT/4 3xT/4+1 ns TACQUISITION Acquisition Time Transition density = 0.5 25 CID Consecutive Indentical Digits # bits without transition 250 DCKRF CKRF Frequency Deviation from Nominal Line Frequency JT Jitter Transfer Note 1: Note 2: Note 3: Conditions: ms ppm 200 Note 2 0.0 0.1 dB T equals the period time for CKOUT, which is the bit period for the parallel data; i.e. 12.9 ns for 78 Mbit/s or 51.4 ns for 19 Mbit/s. PLL 3 dB bandwidth 12 kHz to 500 kHz; N x 125 kHz for STM-N. Peaking and bandwidth depends on actual loop filter values. 10 pF load at CKOUT and ODx outputs. Data Sheet Rev.: 14 GD16591A/GD16592A Page 14 of 16 Package Outline Figure 11.Package 48 pin EDQUAD TQFPa (7 x 7 x 1.4 mm). External References GD90591/592 ITU-T G.751 (11/88) ITU-T G.813 (8/96) ITU-T G.823 (3/93) ITU-T G.825 (3/93) ITU-T G. 958 (11/94) DE/TM-3017-4 (Draft) DE/TM-03067 (Draft) MIL Std. 883 (3/89) JEDEC JESD51 (12/95) JEDEC JESD51.3 (8/96) Data Sheet Rev.: 14 : Data sheet for the evaluation board for the GD16591A/GD16592A chip set. : Digital multiplex equipments operating at the third order bit rate of 34368 kbit/s. : Timing characteristics of SDH equipment slave clocks. : The control of jitter and wander within digital networks based on the 2048 kbit/s hierarchy. : The control of jitter and wander within digital networks based on SDH. : Digital line system based on the SDH for use on optical fibre channels. : Transmission and multiplexing; generic requirements for synchronisation networks. : Transmission and multiplexing; the control of jitter and wander in transport networks. : Method 3015, Human Body Model. : Methology for the Thermal Measurement of Component Packages (Single Semiconductor Device) : Low effective Thermal Conductivity Test Boards for Leaded Surface Mount Packages. GD16591A/GD16592A Page 15 of 16 Device Marking GD16591A <Wafer ID>-<Wafer Lot#> <Assembly Lot#>-<YYWW> <Design ID> GD16592A <Wafer ID>-<Wafer Lot#> <Assembly Lot#>-<YYWW> <Design ID> Pin 1 - Mark Pin 1 - Mark Figure 12.Device Marking - GD16591A. Top View. Figure 13.Device Marking - GD16592A. Top View. Ordering Information To order, please specify as shown below: Product Name: Type: Package Type: Ambient Temperature Range: GD16591A-48BA GD16592A-48BA Transmitter EDQUAD TQFPa, 48 pin -25...85EC Receiver EDQUAD TQFPa, 48 pin -25...85EC GD16591A/GD16592A, Data Sheet Rev.: 14 - Date: 16 May 2001 an Intel company Mileparken 22, DK-2740 Skovlunde Denmark Phone : +45 7010 1062 Fax : +45 7010 1063 E-mail : sales@giga.dk Web site : http://www.giga.dk Please check our Internet web site for latest version of this data sheet. The information herein is assumed to be reliable. GIGA assumes no responsibility for the use of this information, and all such information shall be at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. GIGA does not authorise or warrant any GIGA Product for use in life support devices and/or systems. Distributor: Copyright (c) 2001 GIGA ApS An Intel company All rights reserved