FAGD16592A48BA835977 - Intel

General Description

The GD16591A and GD16592A is a

front-end transmitter/receiver chip set de-

signed for multiple line interfaces:

uSTM-4 / OC-12

uSTM-1 / OC-3

uPDH E4

This chip set is designed to interconnect

the high speed line interface to standard

CMOS ASICs providing low speed data

interface.

The GD16591A and GD16592A devices

are designed for use in both electrical

and optical line interface modules. The

devices support line speeds of:

u140/155 Mbit/s NRZ mode for E4/

OC-3/STM-1 for an optical line inter-

face.

u280/311 Mbit/s for E4/OC-3/STM-1 in

CMI mode for electrical line interface,

where en-/decoding is made at the

system site.

u622 Mbit/s NRZ mode line speed for

OC-12/STM-4 operation.

The on-chip VCO and PLL blocks for

clock generation eliminate the need for

an external high-speed clock signal.

The GD16592A comprises a Limiting In-

put Amplifier (LIA), Clock & Data Recov-

ery, and a configurable DeMUX circuit.

The LIA offers a differential input sensi-

tivity of 10 mV peak to peak for the high-

speed serial input. A Lock Detect output

monitors the PLL locked onto the re-

ceived serial data.

The low-speed interface I/O´s are

LVTTL-level, and the high-speed I/O´s

are differential LVPECL levels (The LIA

input is usable as LVPECL input).

System (local) Loop-back and Line (re-

mote) Loop-back functions offer simpli-

fied manufacturing and field testing.

Low power consumption is achieved by

the 3.3 V single power supply and by

omitting all circuitry, which can easily be

implemented in the low speed system

ASIC, thus reducing the overall power

consumption.

The devices are housed in 48 pin

EDQUAD TQFPäplastic packages.

an Intel company

Data Sheet Rev.: 14

Features

General

lLow jitter on-chip VCO and PLL.

lJitter performance exceeds the rec-

ommendations of ITU-T and Bellcore.

lThe chip set offers seven line and

system speed mode:

622 Mbit/s «78 Mbit/s, 8 bit

311 Mbit/s «78 Mbit/s, 4 bit

155 Mbit/s «78 Mbit/s, 2 bit

155 Mbit/s «19 Mbit/s, 8 bit

280 Mbit/s «70 Mbit/s, 4 bit

140 Mbit/s «70 Mbit/s, 2 bit

140 Mbit/s «17 Mbit/s, 8 bit

lFour phase selectable clock to data

timing at parallel interface.

lSelectable reference clock input fre-

quencies:

17.408/19.44MHz, 34.816/

38.88MHz, and 69.632/77.76MHz.

lLoop Back for System & Line test

modes.

l48 pin EDQUAD TQFPäpackages.

lSingle supply: 3.1 ... 3.6 V.

GD16591A (Transmitter)

l8:1 / 4:1 / 2:1 MUX.

lDifferential transmitted clock output.

lLVPECL data outputs.

lOptional forward/counter clocking

scheme.

lPower dissipation, typ.: 350 mW

GD16592A (Receiver)

l1:8 / 1:4 / 1:2 DeMUX.

STM-4/STM-1/E4

3.3 V Multifunction

Transmitter and

Receiver

GD16591A/GD16592A

GD16591A

MUX/

Retiming PLL

CMOS System ASIC

GD16592A

DeMUX/

CDR with PLL

Data

70/78 Mbit/s

17/19 Mbit/s

System / Line Loop Back

2/4/8bit

Data

70/78 Mbit/s

17/19 Mbit/s

Clock

Line Interface

140/155 Mbit/s (optical)

280/311 Mbit/s (electrical)

622 Mbit/s (STM-4 opt.)

Line Interface

140/155 Mbit/s (optical)

280/311 Mbit/s (electrical)

622 Mbit/s (STM-4 opt.)

Functional Details

General

The Transmitter and Receiver functional

blocks are split up into two devices in or-

der to reduce cross talk and pin count

per device.

The telecommunication system (line

speed group) is choosen by the select

pin (SELPDH):

uFor SDH/SONET

(622/311/155 Mbit/s) set SELPDH

High.

uFor PDH (280/140 Mbit/s)

set SELPDH Low.

The devices can operate in different line

and system speed modes; selected by

DSEL1, DSEL2 and SELPDH,

see Table 1.

The bit order on the low speed parallel

interface is defined with bit 0 as the first

bit transferred (ID0 for the transmitter

and OD0 for the receiver).

The bit rate per connection can be kept

at 78(70) Mbit/s regardless of the line

speed. In addition a separate low speed

1:8 mode support the transmission of

155(140) Mbit/s serial to 19(17) Mbit/s,

8 bit parallel. All data pins are used.

Both devices have a selectable clock di-

vider for the system reference clock,

which allows the circuits to be driven

from either 19 (17), 38(35), or

78(70) MHz reference, independantly of

the line and system speed. The refer-

ence clock frequency is selected by

RSEL1, RSEL2, and SELPDH,

see table 2.

Connecting the differential Line Loop Sig-

nals and Clocks (LLxxx) between

GD16591A and GD16592A allows clock

recovered loop-back of the received line

signal, when LLB on both devices is low.

Connecting the differential System Loop

Signals (SLSxx) between GD16591A and

GD16592A allows system loop-back,

when SLB on both devices is low.

Both circuits comprise fully integrated

PLL functions for re-timing data at the

transmit site, and for clock and data re-

covery at the receive site.

A passive loop filter (consisting of a re-

sistor and a capacitor) is used for both

devices. The external loop filter connect-

ing OUCHP to VCTL is shown in Figure 1

(for the transmitter GD16591A) and Fig-

ure 2 (for the receiver GD16592A).

The loop filter values are optimized at the

evaluation board GD90591/592.

The optimal values depends on the ac-

tual application. The suggested values in

Figures 1 and 2are optimized for best

jitter transfer at the evaluation board.

The loop filter values should be opti-

mized for the actual application.

Figure 1. Loop Filter for the Transmitter,

GD16591A.

Figure 2. Loop Filter for the Receiver,

GD16592A.

Data Sheet Rev.: 14 GD16591A/GD16592A Page 2 of 16

SELPDH DSEL1 DSEL2 Line Speed System Speed Used Bits

140 Mbit/s

280 Mbit/s

---

70 Mbit/s

17 Mbit/s

70 Mbit/s

---

0&1

0...7

0...3

---

155 Mbit/s

311 Mbit/s

622 Mbit/s

78 Mbit/s

19 Mbit/s

78 Mbit/s

0&1

0...7

0...3

0...7

Table 1. Line and system speed mode selection.

SELPDH RSEL1 RSEL2 Ref. Clock

0/1

69.632 MHz

34.816 MHz

17.408 MHz

0/1

77.76 MHz

38.88 MHz

19.44 MHz

Table 2. Reference clock frequency selection.

VCC

VCTL

VCCA

1.5kW1Fm

OUCHP

VCC

VCTL

VCCA

15W1Fm

OUCHP

The Transmitter - GD16591A

The schematic block diagram of

GD16591A is shown in Figure 3.

By the select signal (CSEL) two different

reference clock inputs can be selected

(CKR0/CKR1). This allows for line timing

in normal operation with a selection of a

separate reference when the received

line input data is flawed. Thus, allowing

forwarding alarm status in the event of a

loss of received data.

Forward Clocking

Co-directional timing for input data is pro-

vided. The phase can with the select pins

PSEL1-2 be set to 0°/90°/ 180°/ 270°dif-

ference between data input sampling and

reference clock (CKR0/CKR1).

When forward clocking, the frequency of

the reference clock must be identical to

the input data bit rate.

I.e. for 78(70) Mbit/s use 78(70) MHz ref-

erence clock, and for 19(17) Mbit/s use

19(17) MHz reference clock. Refer to AC

Characteristics on page 12.

Counter Clocking

In addition, contra directional timing is

provided. The phase between input and

CKOUT is adjustable with (0°/90°/180°/

270°). Refer to AC Characteristics on

page 12.

CKOUT is kept synchronous to the refer-

ence clock by the Phase Frequency

Comparator (PFC).

Outputs

The outputs from the multiplexer is fed to

differential LVPECL output stages. See

Figures 4 and 5for output temination.

The serial data output (SOP/SON) are

accompanied by a serial clock output

(COP/CON). See timing data on

page 12.

SLSOP/SLSON is enabled when SLB is

low. When SLB is high (e.g. by internal

pull-up resistor) SLSOP=0and

SLSON = 1; thus avoiding noise injection

at normal operation.

Figure 3. The GD16591A Multifunction Transmitter.

Figure 4. LVPECL Output Termination, AC-coupled.

Figure 5. LVPECL Output Termination, DC-coupled.

Data Sheet Rev.: 14 GD16591A/GD16592A Page 3 of 16

Phase

Adjust

0 /90

180 /270

Clock

Gen.

MUX

VCO

Divide

1/2/4

PFC

VUU

RDD

ID0

DSEL1

PSEL1

DSEL2

PSEL2

LLCIP

LLSIP

LLCIN

LLSIN

LLB

SLB

ID7

SELPDH

VCTL

SELTCK

RSEL1

CKR0

CKR1

CSEL

RSEL2

SOP

SLSOP

COP

SON

SLSON

CON

CKOUT

VCC

VCCA

GND

GNDA

OUCHP

180W50W

180W

100nF

(

GND

)

(

VCC -1.3V

)

50W

LVPECL

Output Input

LVPECL

50W

1.3V

(

VCC -2V

)

50W

LVPECL

Output Input

LVPECL

The Receiver - GD16592A

The schematic block diagram of

GD16592A is shown in Figure 6.

Lock Detect Circuit

The lock detect circuit continuously moni-

tors the frequency difference between

the reference clock and the divided VCO

clock. If the reference clock and the di-

vided VCO frequency differs by more

than 500 ppm (or 2000 ppm, selectable),

it switches the PFC into the PLL in order

to pull the VCO back inside the lock-in

range. This mode is called the acquisi-

tion mode.

The PFC is used to ensure predictable

lock up conditions for the GD16592A by

locking the VCO to an external reference

clock source. It is only used during acqui-

sition and pulls the VCO into the lock

range where the Bang-Bang phase de-

tector is capable of acquiring lock to in-

coming data. The PFC is made with

digital set/reset cells giving it a true

phase and frequency characteristic.

Once the VCO is inside the lock-range

the lock-detection circuit switches the

Bang-Bang phase detector into the PLL

in order to lock to the data signal. This

mode is called CDR mode.

Figure 6. The GD16592A Multifunction

Receiver.

Bang-Bang Phase Detector

The Bang-Bang phase detector is used

in CDR mode as a true digital type de-

tector, producing a binary output. It sam-

ples the incoming data twice each bit

period: once in the transition of the (pre-

vious) bit period and once in the middle

of the bit period. When a transition oc-

curs between 2 consecutive bits - the

value of the sample in the transition be-

tween the bits will show whether the

VCO clock leads or lags the data. Hence

the PLL is controlled by the bit transition

point, thereby ensuring that data is sam-

pled in the middle of the eye, once the

system is in CDR mode. The external

loop filter components control the chara-

cteristics of the PLL.

The binary output of either the PFC or

the Bang-Bang phase detector (depend-

ing of the mode of the lock-detection cir-

cuit) is fed to a charge pump capable of

sinking or sourcing current or tristating.

The output of the charge pump is filtered

through the loop filter and controls the

tuning-voltage of the VCO.

As a result of the continuous monitoring

lock-detect circuit the VCO frequency

never deviates more than 500 ppm

(2000 ppm) from the reference clock be-

fore the PLL is considered to be ’Out of

Lock’. Hence the acquisition time is pre-

dictable and short and the output clock

CKOUT is always kept within the

500 ppm (2000 ppm) limits, ensuring

safe clocking of down stream circuitry.

The LOCK Signal

The status of the lock-detection circuit is

given by the LOCK signal. In CDR mode

LOCK is steady high. In acquisition mode

LOCK is alternating indicating the con-

tinuous shifts between the Bang-Bang

Detector (high) and the PFC (low).

The LOCK output may be used to gener-

ate a pseudo Loss Of Signal (LOS). The

time for LOCK to assert is predictable

and short, equal to the time to go into

lock, but the time for LOCK to de-assert

must be considered. When the line is

down (i.e. no information received) the

optical receiver circuit may produce ran-

dom noise. It is possible that this random

noise will keep the GD16592A within the

500 ppm (2000 ppm) range of the line

frequency, hence LOCK will remain as-

serted for a non-deterministic time. This

may be prevented by injecting a small

current at the loop filter node, which ac-

tively pulls the PLL out of the lock range

when the output of the phase detector

acts randomly.

The negligible penalty paid is a static

phase error on the sampling time in the

decision gate. However, due to the na-

ture of the phase detector the error will

be small (few degrees), forcing the loop

to be at one edge of the error-function

shaped transfer characteristic of the de-

tector.

Inputs

The input amplifier (pin SIP / SIN) is de-

signed as a limiting amplifier with a sen-

sitivity of 10 mV (differential). Standard

LVPECL levels may be applied as well.

The inputs may be either AC or DC cou-

pled. If the inputs are AC coupled the

amplifier features an internal offset can-

celling DC feedback. Notice that the off-

set cancellation will only work when the

input is differential and AC-coupled as

shown in the Figures 7 and 8on page 5.

The serial input SLSIP/SLSIN is selected

when SLB is low.

Outputs

The CKOUT provides the necessary con-

trol for clocking the received data into the

system ASIC. The phase can be ad-

justed with PSEL1-2 (0°/90°/180°/270°).

Data Sheet Rev.: 14 GD16591A/GD16592A Page 4 of 16

DeMUX

Bang

Phase

Detector

VCO

Divide

1/2/4

PFC

DSEL1

PSEL1

RSEL1

SLB

DSEL2

PSEL2

LLB

LLSOP

LLCOP

LLSON

LLCON

SELPDH

SIN

SLSIN

SIP

SLSIP

VCTL

SELTCK

CKRF

OUCHP

VCCA

VCC

GNDA

GND

LOCK

LSEL2

LSEL1

CKOUT

OD7

OD0

Divide

Lock

Detect

Clock

Gen.

Phase

Adjust.

0 /90

180 /270

Figure 7. AC Coupled Input (using internal offset compensation).

Figure 8. DC Coupled Input (ignoring internal offset compensation). VTT depends on

the termination requirements of the previous stage, and the resulting ampli-

tude on the input.

Practical Considerations

The PCB must be designed with shortest

possible conductors for the signals to the

line interfaces. These connections should

be designed as transmission lines.

De-coupling capacitors should be applied

to each power supply pin. Care should

be taken to reduce ground bounce.

The line loop signal and clock must be

terminated close to the transmitter device

(GD16591A).

The system loop signal must be termi-

nated close to the receiver device

(GD16592A).

Data Sheet Rev.: 14 GD16591A/GD16592A Page 5 of 16

50W50W

100nF

100nF100nF

SIP

SIN

LIA

VTT

50W50W

SIP

SIN

LIA

Pin List, GD16591A - Transmitter

Mnemonic: Pin No.: Pin Type:Description:

CKR0, CKR1

CSEL

38, 40

LVTTL IN Reference clock inputs selectable by CSEL. Usable for forward clocking

(co-directional timing), see AC-characteristics on page 12. The CKRx input

must be noise free, since noise injected here passes onto the line. The fre-

quency is determined by RSEL1-2. Maximum frequency is 78 MHz.

CSEL=0 => CKR0; CSEL=1 =>CKR1

ID0..ID7 31, 29, 28, 22,

21, 19, 18, 17

LVTTL IN Data input port to MUX. See DSEL1-2 for bit use. ID0 is the first bit transmit-

ted. See PSEL1-2 for timing.

DSEL1, DSEL2 27, 26 LVTTL IN DSEL1 DSEL2 Line speed System speed Used bit

0 0 155 Mbit/s 78 Mbit/s 0 & 1

0 1 155 Mbit/s 19 Mbit/s 0 .. 7

1 0 311 Mbit/s 78 Mbit/s 0 .. 3

1 1 622 Mbit/s 78 Mbit/s 0 .. 7

SELPDH 1 LVTTL IN PDH(E4) mode select:

0 Line speeds 140 or 280 Mbit/s

1 Line speeds 155, 311, or 622 Mbit/s

SELPDH is used as test clock input when SELTCK is low.

RSEL1, RSEL2 35, 34 LVTTL IN Reference clock frequency select:

RSEL1 RSEL2 CKREF (MHz)

0 0/1 77.76

1 0 38.88

1 1 19.44

PSEL1, PSEL2 42, 41 LVTTL IN IDx input phase versus CKOUT/CKRx select: (Note 2)

PSEL2 PSEL1

00 T

DEL =0°

01 T

DEL =90°

10 T

DEL = 180°

11 T

DEL = 270°

SELTCK 47 LVTTL IN Connect to VCC. Used for test purpose (selects SELPDH as test clock

when low).

LLB 25 LVTTL IN Line Loop-Back, enabled when low.

SLB 3 LVTTL IN System Loop-Back, enabled when low.

LLSIP, LLSIN 16, 15 LVPECL IN Line Loop-back serial differential data. Connect to LLSOP/LLSON of

GD16592A .

LLCIP, LLCIN 14, 13 LVPECL IN Line Loop-back serial differential clock. Connect to LLCOP/LLCON of

GD16592A.

CKOUT 32 LVTTL OUT 77.76 MHz /19.44 MHz output clock. Usable for counter clocking (contra-

directional timing) .

SLSOP,

SLSON

10, 9 LVPECL OUT System loop-back serial differential data. Connect and terminate close to

SLSIP/SLSIN of GD16592A.

SOP, SON 5, 4 LVPECL OUT Differential data output from MUX. SOP is true output, SON is inverted.

COP, CON 8, 7 LVPECL OUT Differential clock output from MUX.

VCTL 45 Analog IN VCO control voltage input. Connect to OUCHP and terminate with 1 kWin

series with 1 mF to VCCA.

OUCHP 43 Analog OUT Charge pump output.

VCC 2, 11, 20, 23,

30, 37

PWR +3.3 V power for core and I/O.

VCCA 44 PWR +3.3 V power for VCO.

GND 6, 12, 24, 33,

36, 48

GND 0 V power for core and I/O.

GNDA 46 GND 0 V power for VCO.

Heat sink Connected to GND.

Note 1: Only standard line speeds for SDH/SONET applications are indicated. For PDH (E4) usage, corresponding values apply,

i.e. substitute 19 MHz clock with 17 MHz, 78 MHz with 70 MHz, 155 Mbit/s with 140 Mbit/s, 311 Mbit/s with 280 Mbit/s.

Note 2: When forward clocking, the frequency of the reference clock must be identical to the input data bit rate.

Data Sheet Rev.: 14 GD16591A/GD16592A Page 6 of 16

Pin List, GD16592A - Receiver

Mnemonic: Pin No.: Pin Type: Description:

CKRF 32 LVTTL IN Reference clock input (19 / 39 / 78 MHz), determined by RSEL1, RSEL2.

DSEL1, DSEL2 39, 38 LVTTL IN DSEL1 DSEL2 Line speed System speed Used bit

0 0 155 Mbit/s 78 Mbit/s 0 & 1

0 1 155 Mbit/s 19 Mbit/s 0 .. 7

1 0 311 Mbit/s 78 Mbit/s 0 .. 3

1 1 622 Mbit/s 78 Mbit/s 0 .. 7

SELPDH 1 LVTTL IN Active low, PDH(E4) mode select:

0 Line speeds 140 or 280 Mbit/s

1 Line speeds 155, 311, or 622 Mbit/s

SELPDH is used as test clock input when SELTCK is low.

RSEL1, RSEL2 3, 34 LVTTL IN RSEL1 RSEL2 Reference clock frequency select:

0 0/1 CKRF = 78 MHz

1 0 CKRF = 38 MHz

1 1 CKRF = 19 MHz

LSEL1, LSEL2 10, 9 LVTTL IN LSEL1 LSEL2 Lock Select inputs for clock and data recovery set-up.

0 0 Manual, Phase Freq. Comp. (PFC)

0 1 Manual, Phase Detect (BB)

1 0 Auto lock, 2000 ppm

1 1 Auto lock, 500 ppm (Default, when not connected)

SELTCK 47 LVTTL IN Connect to VCC. Test purpose (selects SELPDH as test clock when low).

LLB 41 LVTTL IN Line Loop-Back, enabled when low.

SLB 40 LVTTL IN System Loop-Back, enabled when low.

PSEL1, PSEL2 25, 35 LVTTL IN PSEL2 PSEL1 ODx output phase versus CKOUT select:

00 T

DEL =0°

01 T

DEL =90°

10 T

DEL = 180°

11 T

DEL = 270°

SIP, SIN 4, 5 Analog IN Differential serial data input.

SLSIP, SLSIN 7, 8 LVPECL IN System loop-back serial differential data. Connect to SLSOP/N of

GD16591A.

CKOUT 29 LVTTL OUT Regenerated output clock (77.76 / 19.44 MHz). Used for ODx timing.

OD0...OD7 28, 27, 26, 22,

21, 19, 18, 17

LVTTL OUT Re-timed data output from DeMUX. See DSEL1-2 for bit use. OD0 is the first

bit received. See PSEL1-2 for timing.

LLSOP, LLSON 13, 14 LVPECL OUT Line loop-back serial differential data. Connect and terminate close to

LLSIP/LLSIN of GD16591A.

LLCOP, LLCON 15, 16 LVPECL OUT Line loop-back serial differential clock. Connect and terminate close to

LLCIP/LLCIN of GD16591A.

LOCK 42 LVTTL OUT High level indicates PLL locked to incoming data signal. Low level indicates

PLL out of lock.

VCTL 45 Analog IN VCO control voltage input. Connect to OUCHP and terminate with 22 Win

series with 1 mF to VCCA.

OUCHP 43 Analog OUT Charge Pump output for PLL.

VCC 2, 11, 20, 23,

30, 37

PWR +3.3 V power for core and I/O.

VCCA 44 PWR +3.3 V power for VCO.

GND 6, 12, 24, 33,

36, 48

GND 0 V power for core and I/O.

GNDA 46 GND 0 V power for VCO.

NC 31 NC Not Connected.

Heat sink Connected to GND.

Note: Only standard line speeds for SDH/SONET applications are indicated. For PDH (E4) usage, corresponding values apply,

i.e. substitute 19 MHz clock with 17 MHz, 78 MHz with 70 MHz, 155 Mbit/s with 140 Mbit/s, 311 Mbit/s with 280 Mbit/s.

Data Sheet Rev.: 14 GD16591A/GD16592A Page 7 of 16

Package Pinouts

Figure 9. GD16591A, Package 48 pin TQFP - Top View.

Figure 10.GD16592A, Package 48 pin TQFP - Top View.

Data Sheet Rev.: 14 GD16591A/GD16592A Page 8 of 16

GND

SELTCK

GNDA

VCTL

VCCA

OUCHP

PSEL1

PSEL2

CKR1

CSEL

CKR0

VCC

GND

RSEL1

RSEL2

GND

CKOUT

ID0

VCC

ID1

ID2

DSEL1

DSEL2

LLB

VCC

GND

ID3

ID4

VCC

ID5

ID6

ID7

LLSIP

LLSIN

LLCIP

LLCIN

GND

VCC

SLSOP

SLSON

COP

CON

GND

SOP

SON

SLB

VCC

SELPDH

GND

SELTCK

GNDA

VCTL

VCCA

OUCHP

LOCK

LLB

SLB

DSEL1

DSEL2

VCC

GND

PSEL2

RSEL2

GND

CKRF

VCC

CKOUT

OD0

OD1

OD2

PSEL1

VCC

GND

OD3

OD4

VCC

OD5

OD6

OD7

LLCON

LLCOP

LLSON

LLSOP

GND

VCC

LSEL1

LSEL2

SLSIN

SLSIP

GND

SIN

SIP

RSEL1

VCC

SELPDH

Maximum Ratings

These are the limits beyond which the component may be damaged.

All voltages in the table are referred to GND.

All currents in the table are defined positive out of the pin.

Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT.:

VCC, VCCA Supply Voltage 0 6 V

V0MAX Output Voltage -0.5 VCC+0.5 V

I0MAX, LVPECL Output Current 30 mA

I0MAX, VCTL Output Current 0.5 mA

IOO, LVTTL LVTTL Output Source Current 24 mA

IOI, LVTTL LVTTL Output Sink Current -24 mA

VIMAX Input Voltage -0.5 VCC+0.5 V

IIMAX Input Current -1.0 1.0 mA

T0Operating Temperature Junction -55 125 °C

TSStorage Temperature -65 150 °C

VESD Electro Static Discharge Voltage Note 1 500 V

Note1: According to MIL std. 883, method 3015, Human Body Model.

Thermal Characteristics

The worst case thermal resistance from junction to ambient is QJA =75°C/W in still air, using a low conductivity board (2 layers)

according to JEDEC standard JESD51.3.

When using a low conductivity board with no air flow it is recommended that the heat sink is soldered to the board, and that the

board is a multilayer.

Data Sheet Rev.: 14 GD16591A/GD16592A Page 9 of 16

DC Characteristics

TAMBIENT = -25 oCto85oC.

All voltages in the table are referred to GND .

All input signal and power currents in the table are defined positive into the pin.

All output signal currents are defined positive out of the pin.

Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:

VCC,V

CCA Positive Supply Voltage 3.1 3.3 3.6 V

ICC,GD16591A Positive Supply Current (GD16591A) Note 1 105 130 mA

ICC,GD16592A Positive Supply Current (GD16592A) Note 1 135 160 mA

VSIN,SIP Data Input Voltage Swing, Differential Note 5 10 1400 mVP-P

VICM, LVPECL LVPECL Input Common Mode Voltage VCC -1.5 VCC -1.1 V

VIDIFF, LVPECL LVPECL Input Differential Voltage 0.25 0.5 1.4 V

II, LVPECL LVPECL Input Current -100 100 mA

VOH, LVPECL LVPECL Output HI Voltage Note 2 VCC -1.2 VCC -0.6 V

VOL, LVPECL LVPECL Output LO Voltage Note 2 VCC -2.0 VCC -1.6 V

VODIFF, LVPECL LVPECL Output Differential Voltage Note 2 0.6 1.1 V

VIH, LVTTL LVTTL Input HI Voltage Note 3, 4 2.0 VCC V

VIL, LVTTL LVTTL Input LO Voltage Note 3, 4 0.0 0.8 V

IIH, LVTTL LVTTL Input HI Current Note 3, 4 100 mA

IIL, LVTTL LVTTL Input LO Current Note 3, 4 -500 mA

VOH, LVTTL LVTTL Output HI Voltage IOH = 3 mA,

Note 4, 6

VCC -1.1 V

VOL, LVTTL LVTTL Output LO Voltage IOL = -1 mA, Note 4 0 0.5 V

Note 1: Power: 0.8 x PTYP <P<1.2xP

TYP; add to this variations due to power supply voltage. It is noted that the AC power de-

pends on the frequency and load at the outputs (LVTTL).

Note 2: RLOAD =50Wto VCC -2.0 V

Note 3: All LVTTL inputs are provided with an internal pull-up resistor of 16 kW±20 %, room temperature. Thus, the default

LVTTL input value is “1”when not connected.

Note 4: Under the condition of typical supply voltage (3.3 V).

Note 5: Standard LVPECL differential voltages may be applied to input SIP, SIN. If single-ended input is used, the minimum re-

quired peak to peak voltage is 25 mV.

Note 6: For IOH = 1 mA the minimum HI voltage is increased 100 mV (i.e. VCC -1 V).

Data Sheet Rev.: 14 GD16591A/GD16592A Page 10 of 16

AC Characteristics - General

TAMBIENT = -25 °Cto+85°C.

Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:

FTRSDH SDH Tuning Range Relative to Center Frequency Note 1 98 102 %

FTRPDH PDH Tuning Range Relative to Center Frequency Note 1 97 101 %

TR-LVPECL LVPECL Output Rise Time Note 2 270 500 ps

TF-LVPECL LVPECL Output Fall Time Note 2 200 500 ps

TR-LVTTL LVTTL Output Rise Time Note 3 0.8 1 ns

TF-LVTTL LVTTL Output Fall Time Note 3 0.8 1 ns

DCCKOUT Duty Cycle, CKOUT @ 78 MHz Note 4 40 50 60 %

Note 1: The frequency tuning range may be larger. The minimum/maximum values define the worst case range of the VCO at

temperature and power extremes.

Note 2: 20-80%,50Wto VCC -2.0 V.

Note 3: 20 - 80 %, 10 pF. The 20 - 80 % rise and fall times are 2 ns (maximum) with 20 pF load.

Note 4: Measured at VTH = 1.4 V, 10 pF.

Data Sheet Rev.: 14 GD16591A/GD16592A Page 11 of 16

AC Characteristics - GD16591A

TAMBIENT = -25 °Cto+85°C.

Forward Clocking

Counter Clocking

Data Sheet Rev.: 14 GD16591A/GD16592A Page 12 of 16

CKRx (78 MHz)

CKRx (39 MHz)

CKRx (19 MHz)

CKOUT (19 MHz)

TRC

TRC19

CKOUT (78 MHz)

CKOUT

(78 MHz)

IDx(0 )

TSA

TSB

TSC

THC

TSD

THA

THB

THD

IDx(90 )

IDx(180 )

IDx(270 )

COP

SOP/SON

SLSOP/N

TCO

TSLCO

Intrinsic VCO Jitter Generation

GD16591A Frequency Range: Period

[s]

Jitter:

[UIp-p]

PDH E4 200 Hz - 3.5 MHz 10 0.05

STM-1 / OC-3 (CMI) 500 Hz - 1.3 MHz 60 0.05

STM-1 / OC-3 (optical) 100 Hz - 1.3 MHz 60 0.1

STM-4 / OC-12 1000 Hz - 5 MHz 60 0.05

Maximum Allowed RMS Jitter on Reference Clocks Inputs

Line Rate

Ref. Clk. Frq.

622 Mbit/s 311 Mbit/s 155 Mbit/s

78 MHz 13 ps 26 ps 52 ps

39MHz 9ps 18ps 36ps

19MHz 5ps 10ps 20ps

3 dB - PLL BW

(Note 1)

12 ®500 kHz 12 ®250 kHz 12 ®125 kHz

Note 1: Measure the RMS jitter on the reference clock within

the 3 dB PLL bandwidth used for the actual line rate.

Note 2: Adding the maximum allowed jitter on the reference

clock inputs the resulting output jitter will meet the

standard recommendations (ITU-T G.751, G.813,

G.952, and DE/TM-3017-4).

TSE

TSF

TSG

THG

TSH

THE

THF

THH

CKOUT

(19/78 MHz)

IDx(0 )

IDx(90 )

IDx(180 )

IDx(270 )

AC Characteristics - GD16591A - Continued

TAMBIENT = -25 °Cto+85°C.

Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:

TCO COP (falling edge) to SOP/SON Valid 100 200 400 ps

TSLCO COP (falling edge) to SLSOP/N Valid 100 200 400 ps

TSLL LLSIP/N Set-up Time before LLCIP

falling edge

500 ps

THLL LLSIP/N Hold Time after LLCIP falling edge 50 ps

TSA IDx Set-up Time before CKRx rising edge Note 5 3.5 ns

TSB IDx Set-up Time after CKRx rising edge Note 1, 5 T/4 - 3.5 ns

TSC IDx Set-up Time after CKRx rising edge Note 1, 5 T/2 - 3.5 ns

TSD IDx Set-up Time after CKRx rising edge Note 1, 5 3×T/4 - 3.5 ns

THA IDx Hold Time after CKRx rising edge Note 5 2.5 ns

THB IDx Hold Time after CKRx rising edge Note 1, 5 T/4 + 2.5 ns

THC IDx Hold Time after CKRx rising edge Note 1, 5 T/2 + 2.5 ns

THD IDx Hold Time after CKRx rising edge Note 1, 5 3×T/4+2.5 ns

TRC Delay from CKRx rising edge to CKOUT

falling edge

78 MHz,

5 pF load

2.5 3.5 4.5 ns

TRC19 Delay from CKRx rising edge to CKOUT

falling edge

19 MHz,

5 pF load

Note 6

12 13 14 ns

PWHI, CKRx High Pulse Width, CKRx Inputs Note 2 3 ns

TSE IDx Set-up Time before CKOUT falling edge Note 3 TRC + 3.5 ns

TSF IDx Set-up Time after CKOUT falling edge Note 1, 3 T/4-TRC-3.5 ns

TSG IDx Set-up Time after CKOUT falling edge Note 1, 3 T/2-TRC-3.5 ns

TSH IDx Set-up Time after CKOUT falling edge Note 1, 3 3×T/4-TRC-3.5 ns

THE IDx Hold Time before CKOUT falling edge Note 3 TRC-2.5 ns

THD IDx Hold Time after CKOUT falling edge Note 1, 3 T/4-TRC+2.5 ns

THF IDx Hold Time after CKOUT falling edge Note 1, 3 T/2-TRC+2.5 ns

THG IDx Hold Time after CKOUT falling edge Note 1, 3 3×T/4-TRC+2.5 ns

JT Jitter Transfer Note 4 0.0 0.1 dB

Note 1: T equals the period time for CKOUT, which is the bit period for the parallel data; i.e. 12.9 ns for 78 Mbit/s or 51.4 ns for

19 Mbit/s.

Note 2: Measured at VTH = 1.4 V. It is the rising edge, which is used for the timing and frequency comparison. The 20% - 80%

rise time should be less than 1 ns to minimise jitter at the reference clock inputs.

Note 3: Set-up and Hold times with respect to the delay TRC.

Note 4: PLL 3 dB bandwidth 12 kHz to N ×125 kHz for STM-N. Peaking and bandwidth depends on actual loop filter values.

Note 5: Valid for 78 MHz forward clocking. For 19 MHz forward clocking the setup and hold windows are delayed 9.6 ns.

Note 6: TRC19 is actually TRC + 9.6 ns.

Data Sheet Rev.: 14 GD16591A/GD16592A Page 13 of 16

AC Characteristics - GD16592A

TAMBIENT = -25 °Cto+85°C.

Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT:

TLLCO LLCOP to LLSOP/N Valid 100 200 400 ps

TACKOUT to ODx Valid Note 3 0 1 ns

TBCKOUT to ODx Valid Note 1, 3 T/4 T/4+1 ns

TCCKOUT to ODx Valid Note 1, 3 T/2 T/2+1 ns

TDCKOUT to ODx Valid Note 1, 3 3×T/4 3×T/4+1 ns

TACQUISITION Acquisition Time Transition density = 0.5 25 ms

CID Consecutive Indentical Digits # bits without transition 250

DCKRF CKRF Frequency Deviation from

Nominal Line Frequency

±200 ppm

JT Jitter Transfer Note 2 0.0 0.1 dB

Note 1: T equals the period time for CKOUT, which is the bit period for the parallel data; i.e. 12.9 ns for 78 Mbit/s or 51.4 ns for

19 Mbit/s.

Note 2: PLL 3 dB bandwidth 12 kHz to 500 kHz; N ×125 kHz for STM-N. Peaking and bandwidth depends on actual loop filter

values.

Note 3: 10 pF load at CKOUT and ODx outputs.

Data Sheet Rev.: 14 GD16591A/GD16592A Page 14 of 16

[UI]

f2 f3 f4 [Hz]f1

Jitter Tolerance

GD16592A f1

[Hz]

[UIp-p]

PDH E4 200 500 10k 3.5M 2 0.15

STM-1 / OC-3 (CMI) 500 3.25k 65k 1.3M 2 0.15

STM-1 / OC-03 (optical) 500 6.5k 65k 1.3M 2 0.2

STM-4 / OC-12 300 25k 250k 2.5M 2 0.2

Note: The stated jitter tolerance of GD16592A exceeds the stan-

dard recommendations (ITU-T G.823, G.825, and

DE/TM-03067).

(19/78 MHz)

(0 )

(90 )

(180 )

(270 )

ODx

LLCOP

LLSOP/N

TLLCO

Package Outline

Figure 11.Package 48 pin EDQUAD TQFPä(7x7x1.4mm).

External References

GD90591/592 : Data sheet for the evaluation board for the GD16591A/GD16592A chip set.

ITU-T G.751 (11/88) : Digital multiplex equipments operating at the third order bit rate of 34368 kbit/s.

ITU-T G.813 (8/96) : Timing characteristics of SDH equipment slave clocks.

ITU-T G.823 (3/93) : The control of jitter and wander within digital networks based on the 2048 kbit/s hierarchy.

ITU-T G.825 (3/93) : The control of jitter and wander within digital networks based on SDH.

ITU-T G. 958 (11/94) : Digital line system based on the SDH for use on optical fibre channels.

DE/TM-3017-4 (Draft) : Transmission and multiplexing; generic requirements for synchronisation networks.

DE/TM-03067 (Draft) : Transmission and multiplexing; the control of jitter and wander in transport networks.

MIL Std. 883 (3/89) : Method 3015, Human Body Model.

JEDEC JESD51 (12/95) : Methology for the Thermal Measurement of Component Packages (Single Semiconductor Device)

JEDEC JESD51.3 (8/96) : Low effective Thermal Conductivity Test Boards for Leaded Surface Mount Packages.

Data Sheet Rev.: 14 GD16591A/GD16592A Page 15 of 16

Device Marking

Figure 12.Device Marking - GD16591A. Top View. Figure 13.Device Marking - GD16592A. Top View.

GD16591A/GD16592A, Data Sheet Rev.: 14 - Date: 16 May 2001

The information herein is assumed to be

reliable. GIGA assumes no responsibility

for the use of this information, and all such

information shall be at the users own risk.

Prices and specifications are subject to

change without notice. No patent rights or

licenses to any of the circuits described

herein are implied or granted to any third

party. GIGA does not authorise or warrant

any GIGA Product for use in life support

devices and/or systems.

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Please check our Internet web site

for latest version of this data sheet.

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Ordering Information

To order, please specify as shown below:

Product Name: Type: Package Type: Ambient Temperature Range:

GD16591A-48BA Transmitter EDQUAD TQFPä, 48 pin -25...85EC

GD16592A-48BA Receiver EDQUAD TQFPä, 48 pin -25...85EC

GD16591A

Pin 1 - Mark

GD16592A

Pin 1 - Mark